Journal articles on the topic 'MULTIPLIER CIRCUIT'
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1
Ganjikunta, Ganesh Kumar, Sibghatullah I. Khan, and M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics." Journal of Low Power Electronics 15, no. 3 (September 1, 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
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A high speed N × N bit multiplier architecture that supports signed and unsigned multiplication operations is proposed in this paper. This architecture incorporates the modified two's complement circuits and also N × N bit unsigned multiplier circuit. This unsigned multiplier circuit is based on decomposing the multiplier circuit into smaller-precision independent multipliers using Vedic Mathematics. These individual multipliers generate the partial products in parallel for high speed operation, which are combined by using high speed adders and parallel adder to generate the product output. The proposed architecture has regular-shape for the partial product tree that makes easy to implement. Finally, this multiplier architecture is implemented in UMC 65 nm technology for N = 8, 16 and 32 bits. The synthesis results shows that the proposed multiplier architecture improves in terms of speed and also reduces power-delay product (PDP), compared to the architectures in the literature.
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Leela, S. Naga, Boppa Manisha, Palle Bharath, and Erram Praneeth. "Design of Wallace tree multiplier circuit using high performance and low power full adder." E3S Web of Conferences 391 (2023): 01025. http://dx.doi.org/10.1051/e3sconf/202339101025.
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The act of multiplying includes adding partial products repeatedly, and conventional multipliers call for many adders to perform partial product addition in higher order multiplication. A multiplier’s effectiveness and efficiency are evaluated using parameters such as speed, time delay, area, Power Delay Product (PDP), accuracy, and power consumption. In order to choose the optimum multiplier, this project is to evaluate various multipliers their performance metrics. Then, suggests employing a hybrid technology-based adder to improve the performance of the selected multiplier. The power consumption of the multiplier can be significantly reduced while maintaining the required accuracy by using a hybrid technology-based adder and low power full adders. This will allow multipliers to be used in low-power applications where power consumption is a major concern. To summarize, the goal of this project is to design and compare different multipliers using H-spice coding, as well as to improve the performance of the chosen. This project used 4x4 multiplier evaluation using 32nm technology.
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Senthil Kumar, K. K., R. Vignesh, V. R. Vivek, Jagdish Prasad Ahirwar, Khamdamova Makhzuna, and R. Ram kumar. "Approximate Multiplier based on Low power and reduced latency with Modified LSB design." E3S Web of Conferences 399 (2023): 01009. http://dx.doi.org/10.1051/e3sconf/202339901009.
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The devised approximation multiplier can adapt the precision and processing power needed formul triplication sat run-time based on the needs of the user. To decrease error distance, we also suggest a straight forward error compensation circuit. There are two types of approximate multi pliers. Dynamic voltages caling can be used for the first kind, which controls the timing route of the multiplier. If the voltage is lower, the critical path will take longer to complete. As a result, when the time path is violated, errors occurs and approximated results are produced. These cond types involves redesigning precise multiplier circuits like the Wallace Tree Multiplier and Dadda Tree Multiplier in order to change the functional behaviors of multipliers. Most of the earlier research on rebuilding multipliers suggested erroneous m-n compressors, which have m inputs and producen outputs. It dynamically reduces the area covered under the multiplier LSB which enables the MSB in accurate manner and LSB in approximate manner. This convolution al system approach is regarded to sequential cover up more than 32 bit multiplier. Since the accompanied circuit reduce then tire area by10times lesser than original multiplier, this conventional unit is regarded as abled circuit in the segment. Since the process of compressing partial products absorbed the majority of the multiplier energy and resulted in a consider able route delay, these incorrect compressors were utilized to compress the partial products within multiplication. These functionality are over come through our experimental setup.
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Yang, Zhixi, Xianbin Li, and Jun Yang. "Power Efficient and High-Accuracy Approximate Multiplier with Error Correction." Journal of Circuits, Systems and Computers 29, no. 15 (June 30, 2020): 2050241. http://dx.doi.org/10.1142/s0218126620502412.
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Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.
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HAGHPARAST, MAJID, MAJID MOHAMMADI, KEIVAN NAVI, and MOHAMMAD ESHGHI. "OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 311–23. http://dx.doi.org/10.1142/s0218126609005083.
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Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.
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Subbaiah, Madaka Venkata, and Galiveeti Umamaheswara Reddy. "Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (April 1, 2023): 1367. http://dx.doi.org/10.11591/ijece.v13i2.pp1367-1378.
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<span lang="EN-US">In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and synthesized by targeting the device ‘xc7s50fgga484-1’ of Spartan 7 family. Further, in terms of lookup table (LUT) count, critical path delay (CPD), total on-chip power, and power-delay-product (PDP), the performance of the proposed multiplier circuit is compared with the existing multipliers.</span>
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Rashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier." International Journal of Quantum Information 18, no. 03 (April 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
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In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.
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Aaron D’costa, Mr, Dr Abdul Razak, and Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters." International Journal of Engineering & Technology 7, no. 3 (June 26, 2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.
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Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so as to reduce the delay of whole circuit. The main purpose is to deal with high speed and lower power consumption even after decreasing the silicon area. This makes them well-suited for numerous complex and convenient VLSI circuit implementations. The fact however, remains that area and speed are two contradictory performance restrictions. Hence, increase in speed always results in the use of more and complex hardware. Different arithmetic techniques can be used to implement different multiplier circuits. The focus of this paper is to implement various multiplier circuit and compare them. The timing signals can be observed using software such as Modelsim and Xilinx.
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Abdulbaqia, Alaa Ghazi, and Yasir Hashim. "Design and Implementation of General Hardware Binary Multiplier (2n x 2n) Bits." Journal of Physics: Conference Series 2312, no. 1 (August 1, 2022): 012084. http://dx.doi.org/10.1088/1742-6596/2312/1/012084.
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Abstract In this paper, a new general 2n x 2n bits hardware multiplier based on combinatorial has been designed, implemented and analysed. First, a new design for circuit to multiply two binary numbers with 2n bits length, this new design starts with basic 2x2 bits circuit multiplier, n here equal to 1. Then based on this circuit, the 4x4 bits circuit multiplier has been designed. And based on 4x4, the 8x8 bits multiplier has been designed and continually the 16x16 bits multiplier. The final design for general 2nx2n bits multiplier has been presented. All these circuits have been mathematically proved and tested to get the final results.
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CHEN, YUAN-HO, CHIH-WEN LU, SHIAN-SHING SHYU, CHUNG-LIN LEE, and TING-CHIA OU. "A MULTI-STAGE FAULT-TOLERANT MULTIPLIER WITH TRIPLE MODULE REDUNDANCY (TMR) TECHNIQUE." Journal of Circuits, Systems and Computers 23, no. 05 (May 8, 2014): 1450074. http://dx.doi.org/10.1142/s0218126614500741.
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In this study, a multistage fault-tolerant (MSFT) scheme for two fixed-width array multipliers is proposed. To tolerate the fault that occurs in an integrated circuit, an architecture by using three redundant triple module redundancy (TMR) processing elements (PEs) (TMR-PE) is proposed. The proposed Type-I MSFT multipliers divide the array multiplier into multiple stages, and implement a single PE by considering multiple computation cycles to achieve a low area design. Thus, the MSFT multiplier employs the TMR-PEs to achieve a low-cost fault-tolerant design. The TMR-PEs were designed using compressors with multiple operands, such as 4-2 compressors or other compressors with additional operands, to reduce the number of computation cycles and expedite the execution process. To improve the fault-correction capability, Type-II MSFT multipliers that follow the multistage structure, which was designed as a TMR technique, were proposed. Because of implementation using a 0.18-μm CMOS process, the long word-length MSFT multiplier saves a substantial amount of the circuit area. The proposed 64 × 64 Type-I MSFT multiplier has only 13% of the circuit area and 3% of the delay overhead of the original multiplier. Based on the measurements of the area-delay product (AT) metric, the value of the 64 × 64 Type-I MSFT multiplier is only 0.21-fold of the value of the original multiplier. Regarding the fault-correction capability, the 64 × 64 Type-II MSFT multiplier achieves an area-delay-fault efficiency (ATF) that is 11-fold of the value of the original TMR multiplier.
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Weikle, R. M., T. W. Crowe, and E. L. Kollberg. "Multiplier and Harmonic Generator Technologies for Terahertz Applications." International Journal of High Speed Electronics and Systems 13, no. 02 (June 2003): 429–56. http://dx.doi.org/10.1142/s012915640300179x.
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Harmonic generation based on frequency multipliers has proven to be the most successful and widely used solid-state technology for generating power at submillimeter wavelengths. Over the last several years, the development of new device technologies, implementation of innovative circuits, and application of advanced integrated-circuit processing techniques to frequency multiplier design have resulted in unprecedented levels of performance throughout the submillimeter-wave frequency band. This paper reviews the technological innovations, device options, circuit architectures, and fabrication technologies that have made harmonic generation such a successful approach to source development in the submillimeter spectrum.
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Loganayaki, J., and M. Vasanthi. "Image Multiplier Based on Low Power Approximate Unsigned Multiplier." International Journal of Advance Research and Innovation 7, no. 2 (2019): 50–56. http://dx.doi.org/10.51976/ijari.721907.
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Approximate circuits have been considered for applications that can tolerate some loss of accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic circuits in many of these applications including digital signal processing (DSP). This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbours for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery circuit. The approximate multipliers using these two error reduction strategies are referred to as AM1 and AM2, respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Wallace multiplier optimized for speed, an 8×8 AM1 using four most significant bits for error reduction shows a 60% reduction in delay (when optimized for delay) and a 42% reduction in power dissipation (when optimized for area). In a 16×16 design, half of the least significant partial products are truncated for AM1 and AM2, which are thus denoted as TAM1 and TAM2, respectively. Compared with the Wallace multiplier, TAM1 and TAM2 save from 50% to 66% in power, when optimized for area. Compared with existing approximate multipliers, AM1, AM2, TAM1, and TAM2 show significant advantages in accuracy with a low power-delay product. AM2 has a better accuracy compared with AM1 but with a longer delay and higher power consumption. Image processing applications, including image sharpening and smoothing, are considered to show the quality of the approximate multipliers in error-tolerant applications. By utilizing an appropriate error recovery scheme, the proposed approximate multipliers achieve similar processing accuracy as exact multipliers, but with significant improvements in power.
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Reis, Cecília, J. A. Tenreiro Machado, and J. Boaventura Cunha. "Evolutionary Design of Combinational Logic Circuits." Journal of Advanced Computational Intelligence and Intelligent Informatics 8, no. 5 (September 20, 2004): 507–13. http://dx.doi.org/10.20965/jaciii.2004.p0507.
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This paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: 2-to-1 multiplexer, one-bit full adder, four-bit parity checker and a two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates.
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Suvarna, S., K. Rajesh, and T. Radhu. "A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic." International Journal of Students' Research in Technology & Management 4, no. 1 (March 10, 2016): 01–05. http://dx.doi.org/10.18510/ijsrtm.2016.411.
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High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.
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Monfared, Asma Taheri, and Majid Haghparast. "Quantum Ternary Multiplication Gate (QTMG): Toward Quantum Ternary Multiplier and a New Realization for Ternary Toffoli Gate." Journal of Circuits, Systems and Computers 29, no. 05 (July 3, 2019): 2050071. http://dx.doi.org/10.1142/s0218126620500711.
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The designs using ternary logic exploit its logarithmic reduction in the number of qudits compared with the binary circuits. In this paper, we propose quantum ternary multiplication gate. We term it as QTMG. Then we present the symbol and the realization of QTMG. Researchers will be able to use this gate as well as its symbol and realizations in their future studies. We also present a new realization of ternary Toffoli gate in specific state. Moreover, in this paper, we propose 1-qutrit multiplier circuit. The symbol and the realization of the proposed 1-qutrit multiplier circuit are also provided. Afterward, we proposed ternary partial products generation circuit (TPPG) and summation network circuit in order to design quantum ternary 2-qutrit multiplier circuit. Overall, the proposed design of QTMG in this paper is suggested for the first time. In addition, the proposed realization of ternary Toffoli gate, TPPG, summation network and 2-qutrit multiplier circuits are compared with the existing designs and the improvements are reported. The proposed gate and circuits are realized using macro-level ternary gates which are built on the top of the ion-trap realizable 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.
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Jagadeeswara Rao, E., K. Jayaram Kumar, and Dr T. V. Prasad. "Design of high speed Wallace tree multiplier using 8-2 and 4-2 adder compressors." International Journal of Engineering & Technology 7, no. 4 (September 17, 2018): 2386. http://dx.doi.org/10.14419/ijet.v7i4.12261.
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Multiplication is one of the most common arithmetic operations employed in digital systems such as FIR filters and DSP processors but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improv-ing the efficiency of the circuit. High-speed multiplier which uses the high-speed adder is designed based on the Wallace tree concept in this paper. In this paper first we present an approach towards the reduction of delay in Wallace tree multipliers by using 8:2 and 4:2 adder com-pressors, in the partial product reduction stage. The proposed design is also compared to the Wallace Tree multiplier which uses 4:2 and 8:2 adder compressors in terms of propagation delay. The proposed design enhances speed of the system by 74.1% compared to the conven-tional Wallace Tree multiplier, while 24.1 % reduction was achieved in the delay of the system relative to Wallace tree multiplier with 16-bit adder with one of the 8-2 adder compressors.
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Chen, Wei Ping, Tian Yang Wang, Hong Lei Xu, and Xiao Wei Liu. "A Four-Quadrant Analog Multiplier Based on CMOS Source Coupled Pair." Key Engineering Materials 483 (June 2011): 487–91. http://dx.doi.org/10.4028/www.scientific.net/kem.483.487.
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A novel structure for CMOS four-quadrant analog multiplier is presented. The multiplier is based on the square law of MOSFET. To enlarge the input impedance and improve the linearity, CMOS source coupled pair was employed. Also active attenuator was used to enhance the input range. Compared with the traditional multipliers based on Gilbert cell, the proposed circuit features high linearity, high input range. Circuit simulation using HSPICE with 0.5μm CMOS technology shows that under ±2.5V supply the proposed multiplier provides linear range of more than 50% of the voltage supply, THD is 0.3% at 100kHz and 0.8% at 1MHz, -3dB bandwidth is 2.5MHz, and the power consumption is 5mW.
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Maheswari, K., M. L. Ravi Chandra, D. Srinivasulu Reddy, and V. Vijaya Kishore. "Design of Three-valued Logic Based Adder and Multiplier Circuits using Pseudo N-type CNTFETs." International Journal of Electrical and Electronics Research 11, no. 2 (June 30, 2023): 518–22. http://dx.doi.org/10.37391/ijeer.110238.
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This work presents a novel technique to develop the three-valued logic (TVL) circuit schematics for very large-scale integration (VLSI) applications. The TVL is better alternative technology over the two-valued logic because it provides decreased interconnect connections, fast computation speed and decreases the chip complexity. The TVL based complicated designs such as half-adder and multiplier circuits are designed utilizing the Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The proposed TVL half adder multiplier schematics are developed in HSPICE tool. Additionally, the delay and circuit area for the half- adder and multiplier circuits are investigated and compared to the complementary circuits. The memory usage and CPU time for the proposed circuits are also analyzed. It is observed that the proposed circuit designs show the improved performance up to 43.03% on an average over the complementary designs.
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Eissa, M. H., A. Malignaggi, M. Ko, K. Schmalz, J. Borngräber, A. C. Ulusoy, and D. Kissinger. "A 216–256 GHz fully differential frequency multiplier-by-8 chain with 0 dBm output power." International Journal of Microwave and Wireless Technologies 10, no. 5-6 (March 5, 2018): 562–69. http://dx.doi.org/10.1017/s1759078718000235.
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AbstractThis work presents a fully differential wideband and low power 240 GHz multiplier-by-8 chain, manufactured in IHP's 130 nm SiGe:C BiCMOS technology with fT/fmax = 300/500 GHz. A single ended 30 GHz input signal is multiplied by 8 using Gilbert cell-based quadrupler and doubler, and then amplified with a wideband differential 3-stage cascode amplifier. To achieve wide bandwidth and optimize for power consumption, the power budget has been designed in order to operate the frequency multipliers and the output amplifier in saturation. With this architecture the presented circuit achieves a 3 dB bandwidth of 40 GHz, meaning a relative 3 dB bandwidth of 17%, and a peak saturated output power of 0 dBm. Harmonic rejections better than 25 dB were measured for the 5th, 6th, and 7th harmonics. It dissipates 255 mW from 3 V supply which results in drain efficiency of 0.4%, while occupying 1.2 mm2. With these characteristics the presented circuit suits very well as a frequency multiplier chain for driving balanced mixers in 240 GHz transceivers for radar, communication, and sensing applications.
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SAKUL, CHAIWAT, and KOBCHAI DEJHAN. "FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS." Journal of Circuits, Systems and Computers 21, no. 03 (May 2012): 1250024. http://dx.doi.org/10.1142/s0218126612500247.
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This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.
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Osta, Mario, Ali Ibrahim, and Maurizio Valle. "Approximate Computing Circuits for Embedded Tactile Data Processing." Electronics 11, no. 2 (January 8, 2022): 190. http://dx.doi.org/10.3390/electronics11020190.
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In this paper, we demonstrate the feasibility and efficiency of approximate computing techniques (ACTs) in the embedded Support Vector Machine (SVM) tensorial kernel circuit implementation in tactile sensing systems. Improving the performance of the embedded SVM in terms of power, area, and delay can be achieved by implementing approximate multipliers in the SVD. Singular Value Decomposition (SVD) is the main computational bottleneck of the tensorial kernel approach; since digital multipliers are extensively used in SVD implementation, we aim to optimize the implementation of the multiplier circuit. We present the implementation of the approximate SVD circuit based on the Approximate Baugh-Wooley (Approx-BW) multiplier. The approximate SVD achieves an energy consumption reduction of up to 16% at the cost of a Mean Relative Error decrease (MRE) of less than 5%. We assess the impact of the approximate SVD on the accuracy of the classification; showing that approximate SVD increases the Error rate (Err) within a range of one to eight percent. Besides, we propose a hybrid evaluation test approach that consists of implementing three different approximate SVD circuits having different numbers of approximated Least Significant Bits (LSBs). The results show that energy consumption is reduced by more than five percent with the same accuracy loss.
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Bhusare, Saroja S., and V. S. Kanchana Bhaaskaran. "Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique." Journal of Circuits, Systems and Computers 26, no. 05 (February 8, 2017): 1750079. http://dx.doi.org/10.1142/s0218126617500797.
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In many Multimedia and DSP applications, the fixed-width multipliers are used to avoid infinite growth in the word size. Fixed-width multiplier produces an [Formula: see text]-bit product with two [Formula: see text]-bit inputs. This paper presents probabilistic estimation technique applied for the fixed-width radix-8 Booth multiplier for the generation of the compensation bias circuit. The probabilistic estimation circuit for the fixed-width radix-8 Booth multiplier is derived systematically from theoretical computation in preference to time-consuming exhaustive simulations. Results show that the radix-8 direct truncated multiplier reduces the maximum absolute error by 33%, the average error by 22% and the mean square error by 39% for a 12-bit multiplier compared with the radix-4 direct truncated multiplier. Results also demonstrate that, with the probabilistic estimation technique applied to the fixed-width radix-8 Booth multiplier, there is a reduction of 25% in the maximum absolute error, 13.4% reduction in the average error, and 25.13% reduction in the mean square error have been realized compared with the existing fixed-width radix-4 Booth multiplier with probabilistic estimation technique. Standard EDA design tools are used for simulations.
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Rayudu, Kurada Verra Bhoga Vasantha, Dhananjay Ramachandra Jahagirdar, and Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes." Computer Science and Information Technologies 3, no. 1 (March 1, 2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.p1-9.
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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.
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Perisic, D. M., A. C. Zoric, and Z. Gavric. "A Frequency Multiplier Based on Time Recursive Processing." Engineering, Technology & Applied Science Research 7, no. 6 (December 18, 2017): 2104–8. http://dx.doi.org/10.48084/etasr.1499.
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This paper describes a digital frequency multiplier for a pulse rate. The multiplier is based on the recursive processing of the input and output periods and their time differences. Special emphasis is devoted to the techniques which provide the development of multipliers based on this principle. The circuit is defined by two system parameters. One is the ratio of two clock frequencies and the other is a division factor of a binary counter. The realization of the circuit is described. The region of the system parameters for the stable circuit is presented. The different aspects of applications and limitations in realization of the circuit are considered. All mathematical analyses are made using a Z transform approach. It is shown that the circuit can be also used in tracking and prediction applications. Computer simulations are performed to prove the correctness of the math and the whole approach.
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Sadeghi, Mohsen, Mahya Zahedi, and Maaruf Ali. "The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications." Annals of Emerging Technologies in Computing 3, no. 3 (July 1, 2019): 19–27. http://dx.doi.org/10.33166/aetic.2019.03.003.
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This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.
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Dattatraya, Kore Sagar, Belgudri Ritesh Appasaheb, Ramdas Bhanudas Khaladkar, and V. S. Kanchana Bhaaskaran. "Low Power, High Speed and Area Efficient Binary Count Multiplier." Journal of Circuits, Systems and Computers 25, no. 04 (February 2, 2016): 1650027. http://dx.doi.org/10.1142/s0218126616500274.
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Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.
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Durgam, Veena, and Dr K. Ragini. "Design of 32x32 Reversible Unsigned Multiplier Using Dadda Tree Algorithm." ECS Transactions 107, no. 1 (April 24, 2022): 16251–58. http://dx.doi.org/10.1149/10701.16251ecst.
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Multipliers are essential parts of every processor or computer. Microcontrollers and digital signal processors typically measure their performance on how many multiplications they can execute in a given amount of time. As a result, better multiplier designs are sure to increase system efficiency. A reversible Dadda multiplier is one such possible approach. The Dadda tree technique is used to construct two 32x32 reversible unsigned multipliers in this paper. The TG and FG gates are accustomed to create the partial product circuit in the first design. The PG and TG are utilized to create a partial product circuit in the second design. For adding partial products, the PG and reversible full adder gates are used. The design is implemented using Xilinx ISE 14.7 design suite.
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Wang, Yong Xi, and Mei Hu. "Analog Circuit Parameters Measurement System Based on Multiplier." Advanced Materials Research 989-994 (July 2014): 3041–44. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.3041.
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For the more complicated principles and the lower accuracy for the existing methods of the measurement of the analog circuit parameters, the paper constructs a measurement system for the analog circuits parameters based on the multiplier. The signal source generates two orthogonal sinusoidal analog signals with same frequency, and then one of the signals goes through the analog circuits. Then the multiplication and filtering are completed with the two DC signals. At last the phase and amplitude of the analog circuit are obtained through the DAQ and LabVIEW software. The amplitude and phase errors are less than 3%. The results show that the system has simple circuit, fast speed and high accuracy. So it is a feasible plan for the measurement system of the analog circuit parameters at present.
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Bibilo, P. N. "Synthesis of Modular Multipliers." Programmnaya Ingeneria 14, no. 8 (August 14, 2023): 377–87. http://dx.doi.org/10.17587/prin.14.377-387.
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The results of experiments on the circuit implementation of modular multipliers in the design library of ASIC (Application-Specific Integrated Circuits) and FPGA (Field-Programmable Gate Array) are presented. The initial descriptions of modular multiplier projects were given by systems of not fully defined (partial) Boolean functions and algorithmic VHDL descriptions. Logical optimization was carried out in the class of disjunctive normal forms (DNF) and representations of Boolean function systems by BDD (Binary Decision Diagrams). The synthesized circuits were evaluated by area and time delay. It is established that the use of partial Boolean function models and preliminary logical BDD optimization allows one to improve the parameters of synthesized ASIC and FPGA blocks for small module values, however, the best solutions for large module values can be obtained using algorithmic VHDL descriptions of modular multipliers. In the synthesis of modular multiplier circuits as part of an FPGA and the use of ISE and Vivado design systems it is advisable to use synthesized VHDL operations (a*b) mod p.
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Wasaki, H., Y. Horio, and S. Nakamura. "Current multiplier/divider circuit." Electronics Letters 27, no. 6 (1991): 504. http://dx.doi.org/10.1049/el:19910317.
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PERRI, STEFANIA, MARIA ANTONIA IACHINO, and PASQUALE CORSONELLO. "SIMD MULTIPLIERS FOR ACCELERATING EMBEDDED PROCESSORS IN FPGAs." Journal of Circuits, Systems and Computers 15, no. 04 (August 2006): 537–50. http://dx.doi.org/10.1142/s0218126606003210.
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This paper describes a new efficient 32×32 Single Instruction Multiple Data (SIMD) multiplier suitable for the multimedia extension of FPGA-based processors. The proposed circuit can adapt itself to 32-, 16-, and 8-bit operands widths avoiding time and power consuming reconfiguration. When implemented in an XCV400 device, the multiplier here described reaches a running frequency of about 97 MHz with an energy dissipation of just 20 mW/MHz. Comparisons with previously proposed SIMD multipliers for FPGA-based designs demonstrate that the new circuit allows the best area-time-power trade-off to be obtained.
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Melnyk, Oleksandr, Maksym Kravets, and Valerii Kravets. "Comparative Computer Design of Four-bits Nanomultiplier." Electronics and Control Systems 3, no. 73 (November 24, 2022): 59–64. http://dx.doi.org/10.18372/1990-5548.73.17014.
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This paper presents a simulation circuit of a 4x4 Baugh–Wooley multiplier on a proposed one-bit full adder. The results included a comparison with other adders, an analysis of energy dissipation depending on temperature and dissipated power of the existing and proposed multipliers in mW. As a result, it was found that the proposed adder has better properties compared to similar ones. As a result of the work, the simulation circuit of the Baugh–Wooley multiplier 4x4 was performed, and the simulation result was obtained. Computer-edit simulate and design is performed in QCA DESIGNER software.
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Reaungepattanawiwat, Chalermpol, and Yutthana Kanthaphayao. "Voltage Multiplier Circuits with Coupled-Inductor Applied to a High Step-Up DC-DC Converter." Applied Mechanics and Materials 781 (August 2015): 418–21. http://dx.doi.org/10.4028/www.scientific.net/amm.781.418.
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This paper presents a high voltage gain of a DC-DC converter. The proposed system consists of voltage multiplier circuits and a coupled inductor of a boost DC-DC converter. The input voltage of the voltage multiplier circuit is the induced voltage of inductor at a boost DC-DC converter. The field programmable gate array (FGPA) is used for generating the control signal of the proposed system. To verify the proposed circuit, an experiment was conducted from the prototype circuit. The proposed circuit can step-up the voltage with high voltage gain. Moreover, the voltage across the switch is very low.
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Al-Khaleel, Osama, Zakaria Al-Qudah, Mohammad Al-Khaleel, Raed Bani-Hani, Christos Papachristou, and Francis Wolff. "Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication." Journal of Circuits, Systems and Computers 24, no. 02 (November 27, 2014): 1550019. http://dx.doi.org/10.1142/s021812661550019x.
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This paper proposes two high performance binary-to-binary coded decimal (BCD) conversion algorithms for use in BCD multiplication. These algorithms are based on splitting the 7-bit binary partial product of two BCD digits into two groups, computing the contribution of each group to the equivalent BCD partial product, and adding these contributions to compute the final BCD partial product. Designs for the proposed architectures and their implementations targeting both ASIC and FPGA are compared with others. Implementations of BCD array multipliers using both our conversion circuits and existing conversion circuits have been performed. The synthesis results for both ASIC and FPGA show that the proposed designs are faster and occupying less area than the state-of-the-art conversion circuits. Furthermore, the results obtained from comparing BCD multipliers of various sizes show that the enhancement in the area of the conversion circuit grows into a sizable area improvement in the multiplier circuit.
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Kaufmann, Daniela, Armin Biere, and Manuel Kauers. "Incremental column-wise verification of arithmetic circuits using computer algebra." Formal Methods in System Design 56, no. 1-3 (February 26, 2019): 22–54. http://dx.doi.org/10.1007/s10703-018-00329-2.
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AbstractVerifying arithmetic circuits and most prominently multiplier circuits is an important problem which in practice still requires substantial manual effort. The currently most effective approach uses polynomial reasoning over pseudo boolean polynomials. In this approach a word-level specification is reduced by a Gröbner basis which is implied by the gate-level representation of the circuit. This reduction returns zero if and only if the circuit is correct. We give a rigorous formalization of this approach including soundness and completeness arguments. Furthermore we present a novel incremental column-wise technique to verify gate-level multipliers. This approach is further improved by extracting full- and half-adder constraints in the circuit which allows to rewrite and reduce the Gröbner basis. We also present a new technical theorem which allows to rewrite local parts of the Gröbner basis. Optimizing the Gröbner basis reduces computation time substantially. In addition we extend these algebraic techniques to verify the equivalence of bit-level multipliers without using a word-level specification. Our experiments show that regular multipliers can be verified efficiently by using off-the-shelf computer algebra tools, while more complex and optimized multipliers require more sophisticated techniques. We discuss in detail our complete verification approach including all optimizations.
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Saini, Jitendra Kumar, Avireni Srinivasulu, and Renu Kumawat. "High-Performance Low-Power 5:2 Compressor With 30 CNTFETs Using 32 nm Technology." International Journal of Sensors, Wireless Communications and Control 9, no. 4 (September 17, 2019): 462–67. http://dx.doi.org/10.2174/2210327909666190206144601.
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Background: The advent of High Performance Computing (HPC) applications and big data applications has made it imparitive to develop hardware that can match the computing demands. In such high performance systems, the high speed multipliers are the most sought after components. A compressor is an important part of the multiplier; it plays a vital role in the performance of multiplier, also it contributes to the efficiency enhancement of an arithmetic circuit. The 5:2 compressor circuit design proposed here improves overall performance and efficiency of the arithmetic circuits in terms of power consumption, delay and power delay product. The proposed 5:2 compressor circuit was implemented using both CMOS and Carbon Nano Tube Field Effect Transistor (CNTFET) technologies and it was observed that the proposed circuit has yielded better results with CNTFETs as compared to MOSFETs. Methods/Results: The proposed 5:2 compressor circuit was designed with CMOS technology simulated at 45 nm with voltage supply 1.0 V and compared it with the existing 5:2 compressor designes to validate the improvements. Thereafter, the proposed design was implemented with CNTFET technology at 32 nm and simulated with voltage supply 0.6 V. The comparision results of proposed 5:2 compressor with existing designs implemented using CMOS. The results also compare the proposed design on CMOS and CNTFET technologies for parameters like power, delay, power delay product. Conclusion: It can be concluded that the proposed 5:2 compressor gives better results as compared to the existing 5:2 compressor designs implemeted using CMOS. The improvement in power, delay and power delay product is approx 30%, 15% and 40% respectively. The proposed circuit of 5:2 compressor is also implemented using CNTFET technology and compared, which further enhances the results by 30% (power consumption and PDP). Hence, the proposed circuit implemented using CNTFET gives substantial improvements over the existing circuits.
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Lakshmi, Mutyala Sri Anantha. "Design and Implementation of Radix 8 Booth Encoding Multiplier for Low Area and High-Speed Applications." International Journal for Research in Applied Science and Engineering Technology 9, no. 12 (December 31, 2021): 862–64. http://dx.doi.org/10.22214/ijraset.2021.39398.
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Abstract: In this paper, we present the design and implementation of the Radix 8 Booth Encoding Multiplier. There are many multipliers in existence in which Radix 8 Booth Encoding Multiplier offers a decrease in area and provides high speed due to its diminution in the number of partial products. This project is designed and simulated on Xilinx ISE 14.7 version software using VHDL (Very High Speed Integrated Circuit Hardware Description Language). Simulation results show area reduction by 33.4% and delay reduction by 45.9% as compared to the conventional method. Keywords: Booth Multiplier, Radix 8, Partial Product
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A V, Arun. "Column Bypassing Multiplier Implementation on FPGA." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (June 30, 2022): 3427–41. http://dx.doi.org/10.22214/ijraset.2022.44628.
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Abstract: It is very important for modern DSP systems to develop low-power multipliers to reduce the power dissipation. This paper presents a new multiplier design in which switching activities are reduced through architecture optimization. The power consumption can be reduced if one can reduce the switching activity of a given logic circuit without changing its function. An obvious method to reduce the switching activity is to shut down the idle part of the circuit, Which is not in operating condition. In this the low powers Column bypasses multiplier design methodology that inserts more number of zeros in the multiplicand thereby reducing the number of switching activities as well as power consumption. The switching activity of the component used in the design depends on the input bit coefficient. This means if the input bit coefficient is zero, corresponding row or column of adders need not be activated. If multiplicand contains more zeros, higher power reduction can be achieved. To reduce the switching activity is to shut down the idle part of the circuit, which is not in operating condition.
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Lin, Jin-Fa, Cheng-Yu Chan, and Shao-Wei Yu. "Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications." Electronics 8, no. 12 (November 30, 2019): 1429. http://dx.doi.org/10.3390/electronics8121429.
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In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.
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Dündar, G., F.-C. Hsu, and K. Rose. "Effects of Nonlinear Synapses on the Performance of Multilayer Neural Networks." Neural Computation 8, no. 5 (July 1996): 939–49. http://dx.doi.org/10.1162/neco.1996.8.5.939.
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The problems arising from the use of nonlinear multipliers in multilayer neural network synapse structures are discussed. The errors arising from the neglect of nonlinearities are shown and the effect of training in eliminating these errors is discussed. A method for predicting the final errors resulting from nonlinearities is described. Our approximate results are compared with the results from circuit simulations of an actual multiplier circuit.
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Glushechenko, E. N. "Microstrip doubler microwave with non-traditional implementation." Технология и конструирование в электронной аппаратуре, no. 1-2 (2019): 20–26. http://dx.doi.org/10.15222/tkea2019.1-2.20.
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Frequency multipliers are used in electronic devices to generate spectrally pure sinusoidal signals in the frequency range from a few to tens of GHz. The multipliers are used to multiply the frequency of highly stable but more low-frequency devices with the subsequent extraction of the necessary harmonics from the frequency spectrum of the received microwave range. The frequencies selected after multiplication (set) have significantly higher energy, spectral and range characteristics, which allows them to be used as local oscillators and synthesizers in receiving and transmitting systems. The authors of this paper theoretically substantiate and practically demonstrate the possibility of an unconventional implementation of a microstrip multiplier of the microwave range based on a directional traveling wave filter. The proposed implementation does not require the use of active semiconductor elements. The well-known circuit and technological principles for the creation of microstrip microwave multipliers are considered in the paper. The features, problems and shortcomings arising from their implementation are analyzed. The effectiveness of using the balanced circuit for frequency multiplication is confirmed. A list of mandatory requirements and conditions necessary for the implementation of the microwave multipliers is given. It is demonstrated that the features of the microstrip travelling-wave filter are identical to the conditions and requirements for the implementation of balanced multipliers. It is shown and substantiated how an unconventional implementation of a passive microwave multiplier is possible due to the electromagnetic interaction of the input and output nodes of such a filter with an annular travelling-wave resonator. Using the example of modifying a block diagram of a directional filter into a multiplier circuit, the possibility of creating a microwave doubler is confirmed by separating a given frequency from the frequency spectrum of a traveling-wave ring resonator.
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Vozna, Natalia, Yaroslav Nykolaychuk, and Alina Davletova. "Multi-bit structure improvement methods for multiplier devices of matrix type." Physico-mathematical modelling and informational technologies, no. 32 (July 7, 2021): 80–85. http://dx.doi.org/10.15407/fmmit2021.32.080.
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The article proposes methods for improving the structures of matrix multipliers of multi-digit numbers. Advanced single-bit total adders with paraphrase switched inputs and paraphrase outputs are used, intended as components of high-speed matrix multipliers. Based on the use of such single-bit adders, the structures of matrix multipliers are proposed, characterized by 2 times increased speed, 5 times reduced structural complexity compared to known multipliers based on classical single-bit adders. Optimization of structures of multi-bit matrix multipliers is offered. Comparative estimates of structural and temporal complexities of their circuit implementations depending on the bit size of multiplied binary numbers are given. The use of optimized circuit solutions of matrix multipliers can significantly improve the system characteristics of complex computing devices with many such components in the crystals of microelectronic technologies.
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Upadhyay, Shipra, R. K. Nagaria, and R. A. Mishra. "Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic." VLSI Design 2013 (November 7, 2013): 1–9. http://dx.doi.org/10.1155/2013/726324.
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Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL) circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL) family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL)) is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In our proposed (IQSERL) inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.
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Keote, Minal, and P. T. Karule. "Design and Implementation of Low Power Multiplier Using Proposed Two Phase Clocked Adiabatic Static CMOS Logic Circuit." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (December 1, 2018): 4959. http://dx.doi.org/10.11591/ijece.v8i6.pp4959-4971.
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<p class="Abstract">This paper presents a design and implementation of 2*2 array and 4*4 array multiplier using proposed Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed 2PASCL circuit is based on adiabatic energy recovery principle which consumes less power. The proposed 2PASCL uses two sinusoidal power clocks which are 1800 phase shifted with each other. The measurement result of 2*2 array proposed 2PASCL multiplier gives 80.16 % and 97.67 %power reduction relative to reported 2PASCL and conventional CMOS logic and the measurement result of 4*4 array proposed 2PASCL multiplier demonstrate 32.88 % and 82.02 %power reduction compared to reported 2PASCL and conventional CMOS logic . Another advantage of the proposed circuit is that it gives less power though the number of transistor in proposed and reported 2PASCL circuit is same. From the result we conclude that proposed 2PASCL technology is advantageous to application in low power digital systems, pacemakers and sensors. The circuits are simulated at 180nm technology mode.</p>
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Zhou, Duo. "The Design of Multiplier in Integrated Circuit Based on Low-Power Algorithm." Applied Mechanics and Materials 624 (August 2014): 385–88. http://dx.doi.org/10.4028/www.scientific.net/amm.624.385.
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With rapid development of integrated circuit technologies, power consumption has been a key factor for long time, beside speed and area. Currently, in order to obtain the optimal low power result, we try to reduce system power consumption in each stage of integrated circuit design. Base on the traditional methodologies, a dual optimization methodology is developed, which reduces not only the number of addition operations, but also the width of one multiplier. From implementation point of view, the result of first optimization can be used for the second one, such implementation save the computation effort of second optimization, and promote operation speed and efficiency of whole methodology. The dissertation develop the low power technique for multipliers in different stages, it has reference value to integrated circuit front-end low power design for fixed coefficient multipliers.
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Li, Yin, Yu Zhang, and Xiaoli Guo. "Efficient Nonrecursive Bit-Parallel Karatsuba Multiplier for a Special Class of Trinomials." VLSI Design 2018 (January 11, 2018): 1–7. http://dx.doi.org/10.1155/2018/9269157.
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Recently, we present a novel Mastrovito form of nonrecursive Karatsuba multiplier for all trinomials. Specifically, we found that related Mastrovito matrix is very simple for equally spaced trinomial (EST) combined with classic Karatsuba algorithm (KA), which leads to a highly efficient Karatsuba multiplier. In this paper, we consider a new special class of irreducible trinomial, namely, xm+xm/3+1. Based on a three-term KA and shifted polynomial basis (SPB), a novel bit-parallel multiplier is derived with better space and time complexity. As a main contribution, the proposed multiplier costs about 2/3 circuit gates of the fastest multipliers, while its time delay matches our former result. To the best of our knowledge, this is the first time that the space complexity bound is reached without increasing the gate delay.
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Yan, Aibin, Xuehua Li, Runqi Liu, Zhengfeng Huang, Patrick Girard, and Xiaoqing Wen. "Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata." Electronics 12, no. 14 (July 23, 2023): 3189. http://dx.doi.org/10.3390/electronics12143189.
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Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions.
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Safoev, Nuriddin, and Jun-Cheol Jeon. "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata." Electronics 9, no. 6 (June 23, 2020): 1036. http://dx.doi.org/10.3390/electronics9061036.
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A multiplier is one of the main units for digital signal processing and communication systems. In this paper, a high speed and low complexity multiplier is designed on the basis of quantum-dot cellular automata (QCA), which is considered promising nanotechnology. We focus on Vedic multiplier architectures according to Vedic mathematics from ancient Indian sculptures. In fact, an adder is an important block in the design of almost all types of multipliers and a ripple carry adder is used to design simple multiplier implementations. However, a high-speed multi-bit multiplier requires high-speed adder owing to carry propagation. Cell-interaction-based QCA adders have better improvements over conventional majority-gate-based adders. Therefore, a two-bit Vedic multiplier is proposed in QCA and it is used to implement a four-bit form of the multiplier. The proposed architecture has a lower cell count and area compared to other existing structures. Moreover, simulation results demonstrate that the proposed design is sustainable and can be used to realize complex circuit designs for QCA communication networks.
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Swathi, Panchadi, and Gudla Bhanu Gupta. "Implementation of 2-bit Multiplier Circuit Using Pass Transistor Logic." International Journal for Research in Applied Science and Engineering Technology 10, no. 7 (July 31, 2022): 5013–22. http://dx.doi.org/10.22214/ijraset.2022.46100.
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Abstract: In this paper, we implemented 2-bit Multiplier Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The proposed Multiplier circuit is implemented in 2x2 bit multiplier to achieve high speed, low area and less power dissipation. VLSI schematic tool and the analysis is done by using the LT Spice simulator. This paper aims at an optimization of power area and voltages of multiplier to show the better performance. The design is implemented in 0.18um CMOS technology and its functional parameters are compared and the best result is incorporated. Simulation results have been performed on LT Spice tool simulator at 1.8v and 2v supply voltage and simulations are carried out indicate the functionality of the proposed multiplier circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.
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Zhu, R., Y. Zhang, J. Luo, S. Chang, Hao Wang, Q. Huang, and Jin He. "Graphene Field Effect Transistor’s Circuit Modeling and Radio Frequency Application Study." Key Engineering Materials 645-646 (May 2015): 139–44. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.139.
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In this paper, a large signal circuit model of graphene field effect transistor (GFET) is described accurately by Verilog-A language, which is suitable for radio frequency circuit design and can be applied in HSPICE and ADS directly. Then two typical radio frequency (RF) circuits, frequency multiplier and mixer, are based on this GFET circuit model. The proposed circuits’ performance are analyzed respectively in 10GHz, 15GHz and 20GHz, and GFET’s application foreground in radio frequency area is discussed.