Relevant bibliographies by topics / MULTIPLIER CIRCUIT

Academic literature on the topic 'MULTIPLIER CIRCUIT'

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Published: 11 September 2023

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Journal articles on the topic "MULTIPLIER CIRCUIT"

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Ganjikunta, Ganesh Kumar, Sibghatullah I. Khan, and M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics." Journal of Low Power Electronics 15, no. 3 (September 1, 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.

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A high speed N × N bit multiplier architecture that supports signed and unsigned multiplication operations is proposed in this paper. This architecture incorporates the modified two's complement circuits and also N × N bit unsigned multiplier circuit. This unsigned multiplier circuit is based on decomposing the multiplier circuit into smaller-precision independent multipliers using Vedic Mathematics. These individual multipliers generate the partial products in parallel for high speed operation, which are combined by using high speed adders and parallel adder to generate the product output. The proposed architecture has regular-shape for the partial product tree that makes easy to implement. Finally, this multiplier architecture is implemented in UMC 65 nm technology for N = 8, 16 and 32 bits. The synthesis results shows that the proposed multiplier architecture improves in terms of speed and also reduces power-delay product (PDP), compared to the architectures in the literature.
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Leela, S. Naga, Boppa Manisha, Palle Bharath, and Erram Praneeth. "Design of Wallace tree multiplier circuit using high performance and low power full adder." E3S Web of Conferences 391 (2023): 01025. http://dx.doi.org/10.1051/e3sconf/202339101025.

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The act of multiplying includes adding partial products repeatedly, and conventional multipliers call for many adders to perform partial product addition in higher order multiplication. A multiplier’s effectiveness and efficiency are evaluated using parameters such as speed, time delay, area, Power Delay Product (PDP), accuracy, and power consumption. In order to choose the optimum multiplier, this project is to evaluate various multipliers their performance metrics. Then, suggests employing a hybrid technology-based adder to improve the performance of the selected multiplier. The power consumption of the multiplier can be significantly reduced while maintaining the required accuracy by using a hybrid technology-based adder and low power full adders. This will allow multipliers to be used in low-power applications where power consumption is a major concern. To summarize, the goal of this project is to design and compare different multipliers using H-spice coding, as well as to improve the performance of the chosen. This project used 4x4 multiplier evaluation using 32nm technology.
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Senthil Kumar, K. K., R. Vignesh, V. R. Vivek, Jagdish Prasad Ahirwar, Khamdamova Makhzuna, and R. Ram kumar. "Approximate Multiplier based on Low power and reduced latency with Modified LSB design." E3S Web of Conferences 399 (2023): 01009. http://dx.doi.org/10.1051/e3sconf/202339901009.

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The devised approximation multiplier can adapt the precision and processing power needed formul triplication sat run-time based on the needs of the user. To decrease error distance, we also suggest a straight forward error compensation circuit. There are two types of approximate multi pliers. Dynamic voltages caling can be used for the first kind, which controls the timing route of the multiplier. If the voltage is lower, the critical path will take longer to complete. As a result, when the time path is violated, errors occurs and approximated results are produced. These cond types involves redesigning precise multiplier circuits like the Wallace Tree Multiplier and Dadda Tree Multiplier in order to change the functional behaviors of multipliers. Most of the earlier research on rebuilding multipliers suggested erroneous m-n compressors, which have m inputs and producen outputs. It dynamically reduces the area covered under the multiplier LSB which enables the MSB in accurate manner and LSB in approximate manner. This convolution al system approach is regarded to sequential cover up more than 32 bit multiplier. Since the accompanied circuit reduce then tire area by10times lesser than original multiplier, this conventional unit is regarded as abled circuit in the segment. Since the process of compressing partial products absorbed the majority of the multiplier energy and resulted in a consider able route delay, these incorrect compressors were utilized to compress the partial products within multiplication. These functionality are over come through our experimental setup.
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Yang, Zhixi, Xianbin Li, and Jun Yang. "Power Efficient and High-Accuracy Approximate Multiplier with Error Correction." Journal of Circuits, Systems and Computers 29, no. 15 (June 30, 2020): 2050241. http://dx.doi.org/10.1142/s0218126620502412.

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Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.
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HAGHPARAST, MAJID, MAJID MOHAMMADI, KEIVAN NAVI, and MOHAMMAD ESHGHI. "OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 311–23. http://dx.doi.org/10.1142/s0218126609005083.

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Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.
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Subbaiah, Madaka Venkata, and Galiveeti Umamaheswara Reddy. "Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (April 1, 2023): 1367. http://dx.doi.org/10.11591/ijece.v13i2.pp1367-1378.

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<span lang="EN-US">In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and synthesized by targeting the device ‘xc7s50fgga484-1’ of Spartan 7 family. Further, in terms of lookup table (LUT) count, critical path delay (CPD), total on-chip power, and power-delay-product (PDP), the performance of the proposed multiplier circuit is compared with the existing multipliers.</span>
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Rashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier." International Journal of Quantum Information 18, no. 03 (April 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.

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In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.
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Aaron D’costa, Mr, Dr Abdul Razak, and Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters." International Journal of Engineering & Technology 7, no. 3 (June 26, 2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.

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Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so as to reduce the delay of whole circuit. The main purpose is to deal with high speed and lower power consumption even after decreasing the silicon area. This makes them well-suited for numerous complex and convenient VLSI circuit implementations. The fact however, remains that area and speed are two contradictory performance restrictions. Hence, increase in speed always results in the use of more and complex hardware. Different arithmetic techniques can be used to implement different multiplier circuits. The focus of this paper is to implement various multiplier circuit and compare them. The timing signals can be observed using software such as Modelsim and Xilinx.
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Abdulbaqia, Alaa Ghazi, and Yasir Hashim. "Design and Implementation of General Hardware Binary Multiplier (2n x 2n) Bits." Journal of Physics: Conference Series 2312, no. 1 (August 1, 2022): 012084. http://dx.doi.org/10.1088/1742-6596/2312/1/012084.

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Abstract In this paper, a new general 2n x 2n bits hardware multiplier based on combinatorial has been designed, implemented and analysed. First, a new design for circuit to multiply two binary numbers with 2n bits length, this new design starts with basic 2x2 bits circuit multiplier, n here equal to 1. Then based on this circuit, the 4x4 bits circuit multiplier has been designed. And based on 4x4, the 8x8 bits multiplier has been designed and continually the 16x16 bits multiplier. The final design for general 2nx2n bits multiplier has been presented. All these circuits have been mathematically proved and tested to get the final results.
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CHEN, YUAN-HO, CHIH-WEN LU, SHIAN-SHING SHYU, CHUNG-LIN LEE, and TING-CHIA OU. "A MULTI-STAGE FAULT-TOLERANT MULTIPLIER WITH TRIPLE MODULE REDUNDANCY (TMR) TECHNIQUE." Journal of Circuits, Systems and Computers 23, no. 05 (May 8, 2014): 1450074. http://dx.doi.org/10.1142/s0218126614500741.

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In this study, a multistage fault-tolerant (MSFT) scheme for two fixed-width array multipliers is proposed. To tolerate the fault that occurs in an integrated circuit, an architecture by using three redundant triple module redundancy (TMR) processing elements (PEs) (TMR-PE) is proposed. The proposed Type-I MSFT multipliers divide the array multiplier into multiple stages, and implement a single PE by considering multiple computation cycles to achieve a low area design. Thus, the MSFT multiplier employs the TMR-PEs to achieve a low-cost fault-tolerant design. The TMR-PEs were designed using compressors with multiple operands, such as 4-2 compressors or other compressors with additional operands, to reduce the number of computation cycles and expedite the execution process. To improve the fault-correction capability, Type-II MSFT multipliers that follow the multistage structure, which was designed as a TMR technique, were proposed. Because of implementation using a 0.18-μm CMOS process, the long word-length MSFT multiplier saves a substantial amount of the circuit area. The proposed 64 × 64 Type-I MSFT multiplier has only 13% of the circuit area and 3% of the delay overhead of the original multiplier. Based on the measurements of the area-delay product (AT) metric, the value of the 64 × 64 Type-I MSFT multiplier is only 0.21-fold of the value of the original multiplier. Regarding the fault-correction capability, the 64 × 64 Type-II MSFT multiplier achieves an area-delay-fault efficiency (ATF) that is 11-fold of the value of the original TMR multiplier.
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Dissertations / Theses on the topic "MULTIPLIER CIRCUIT"

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Tang, Wing Ho Aaron. "Optimum MESFET frequency multiplier design." Thesis, Queen's University Belfast, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239221.

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Comerma, Montells Albert. "Development of a multichannel integrated circuit for Silicon Photo-Multiplier arrays readout." Doctoral thesis, Universitat de Barcelona, 2014. http://hdl.handle.net/10803/134876.

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The aim of this thesis is to present a solution for the readout of Silicon Photo-Multipliers (SiPMs) arrays improving currently implemented systems. Using as a starting point previous designs with similar objectives a novel current mode input stage has been designed and tested. To start with the design a valid model has been used to generate realistic output from the SiPMs depending on light input. Design has been performed in first place focusing in general applications for medical imaging Positron Emission Tomography (PET) and then using the same topology for a more constrained design in particle detectors (upgrade of Tracker detector at LHCb experiment). A 16 channel ASIC for PET applications including the novel input stage has demonstrated an excellent timing measurement with good energy resolution measurement and pile-up detection. This document starts with the analysis of the requirements needed to fit such a system, followed by a detailed description of the input stage and analog processing. Signal is divided in the input stage into three different signal paths: timing, energy and pileup. Every channel performs different signal analysis to deliver; a fast time signal output (digital edge), energy output (a linear time over threshold digital output) and a digital bit to signal pile-up. The time information is then ORed between all channels to generate a single timing output. All the pile-up bits are combined in a digital word ready to be readout for the 16 channels. Design has been optimized for reduced power consumption and no components needed to interface inputs and outputs. Digital slow control to tune the circuit behaviour is also included. The prototype measurements have proved to be a valid option for integration in a full system scanner. An adapted prototype of the input stage using different technology and adapted to the different constraints from a particle detector is also presented. Only simulation results are available since device is still under production. An analysis of the different requirements needed by the SciFi tracker design is summarized. Current specifications are still evolving since final sensor is still not defined, but other requirements and some tunable elements permits to design such prototypes.
L’objectiu d’aquesta tesi és presentar una solució per a la lectura de matrius de fotomultiplicadors de silici (SiPM) millorant les característiques de sistemes actuals. Amb aquesta finalitat s’ha dissenyat i provat el circuit d’una nova etapa d’entrada. En primer lloc s’ha dissenyat pensant en aplicacions genèriques i per a imatge mèdica, concretament per a escàners PET (Positron Emission Tomography). Però més endavant s’aplica la mateixa topologia per a una aplicació més concreta i específica com és un detector de partícules (l’actualització del Tracker a l’experiment LHCb). Els SiPM són uns dispositius electrònics relativament nous amb la possibilitat de comptar fotons i millorant algunes característiques dels sensors actuals, com serien la tensió d’operació més baixa, més guany o immunitat a camps magn`etics, mentre manté unes prestacions excel•lents respecte el guany, resolució temporal i rang dinàmic. Aquest tipus de dispositius es troben en constant evolució encara i una gran varietat de fabricants intenten millorar les prestacions, sobretot respecte la eficiència en la detecció de llum, reduir el corrent d’obscuritat, construir matrius més grans i augmentar l’espectre al qual són sensibles. En aquest document es presenta el disseny d’un circuit integrat específic amb les següents característiques: gran rang dinàmic, alta velocitat, multicanal, amb entrada en corrent i baixa impedància d’entrada, baix consum, control de la tensió de polarització del SiPM i amb les sortides de; temps, càrrega i apilament.
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Srinivasan, Venkataramanujam. "Gigahertz-Range Multiplier Architectures Using MOS Current Mode Logic (MCML)." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9643.

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The tremendous advancement in VLSI technologies in the past decade has fueled the need for intricate tradeoffs among speed, power dissipation and area. With gigahertz range microprocessors becoming commonplace, it is a typical design requirement to push the speed to its extreme while minimizing power dissipation and die area. Multipliers are critical components of many computational intensive circuits such as real time signal processing and arithmetic systems. The increasing demand in speed for floating-point co-processors, graphic processing units, CDMA systems and DSP chips has shaped the need for high-speed multipliers. The focus of our research for modern digital systems is two fold. The first one is to analyze a relatively unexplored logic style called MOS Current Mode Logic (MCML), which is a promising logic technique for the design of high performance arithmetic circuits with minimal power dissipation. The second one is to design high-speed arithmetic circuits, in particular, gigahertz-range multipliers that exploit the many attractive features of the MCML logic style. A small library of MCML gates that form the core components of the multiplier were designed and optimized for high-speed operation. The three 8-bit MCML multiplier architectures designed and simulated in TSMC 0.18 mm CMOS technology are: 3-2-tree architecture with ripple carry adder (Architecture I), 4-2-tree design with ripple carry adder (Architecture II) and 4-2-tree architecture with carry look-ahead adders (Architecture III). Architecture I operates with a maximum throughput of 4.76 GHz (4.76 Billion multiplications per second) and a latency of 3.78 ns. Architecture II has a maximum throughput of 3.3 GHz and a latency of 3 ns and Architecture III has a maximum throughput of 2 GHz and a latency of 3 ns. Architecture I achieves the highest throughput among the three multipliers, but it incurs the largest area and latency, in terms of clock cycle count as well as absolute delay. Although it is difficult to compare the speed of our multipliers with existing ones, due to the use of different technologies and different optimization goals, we believe our multipliers are among the fastest found in contemporary literature.
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Ramasamy, Lakshminarayanan. "First Order Mobility Independent ASIC for a Point-of-Care In-Vitro Diagnostic Device." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1326296847.

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El, Hassan Bachar. "Architecture VLSI asynchrone utilisant la logique différentielle à précharge : application aux opérateurs arithmétiques." Grenoble INPG, 1995. http://www.theses.fr/1995INPG0099.

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La complexite et la vitesse de fonctionnement des circuits integres, atteignent un seuil ou les systemes asynchrones deviennent une laternative interessante pour resoudre certains problemes des systemes synchrones. Apres une etude generale sur les differents types de systemes asynchrones nous sommes passes a l'etude de la circuiterie asynchrone: differentes logiques ont ete etudiees et nous avons choisi la logique dcvs (differential cascode voltage switch logic) pour la suite de l'etude. Nous sommes ensuite passes a l'etude et la conception des operateurs arithmetiques asynchrones, premiere experience d'utilisation de la logique dcvs. Nous avons etudie quatre architectures d'additionneurs-soustracteurs et plusieurs types de multiplieurs parallele-parallele. Puis nous avons concu et fabrique un multiplieur-accumulateur 18 12 + 30 bits, utilisant un arbre a retenue bloquee (carry-save) et un additionneur rapide, capable de fonctionner en modes synchrone et asynchrone. L'etude des pipelines asynchrones a ete ensuite abordee. Nous avons etudie plusieurs methodes pour realiser ces pipelines et nous avons propose quelques modifications a certaines d'entre elles. Ces modifications ont permis a ces pipelines de devenir plus rapides. L'etude des operateurs et du pipeline asynchrone nous a fait sentir le besoin d'une bibliotheque de cellules standards asynchrone et nous a donne les grandes lignes pour concevoir cette bibliotheque, en logique dcvs. La derniere partie de notre travail a ete consacree a l'etude des anneaux autosequences (self timed rings). Apres une etude general de ces anneaux nous y avons introduit la meme modification introduite au pipeline asynchrone. Ceci a permis de diminuer les nombres d'etages minimal et optimal de ces anneaux. La conception de la multiplication parallele-serie ainsi que la division en anneau a ensuite ete etudiee. Quatre diviseurs implementes en anneaux ont finalement ete concus en utilisant les cellules de la bibliotheque asynchrone
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Remund, Craig Timothy. "Design of CMOS Four-Quadrant Gilbert Cell Multiplier Circuits in Weak and Moderate Inversion." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd611.pdf.

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Ozalevli, Erhan. "Exploiting Floating-Gate Transistor Properties in Analog and Mixed-Signal Circuit Design." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14048.

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With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment. Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques. These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic architecture.
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Normand, Guy. "Les circuits translineaires : contribution a leur etude et a leur mise en oeuvre dans les domaines analogique et logique." Nantes, 1987. http://www.theses.fr/1987NANT2056.

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Les circuits translineaires sont des circuits constitues d'un certain nombre de jonctions bipolaires, organisees en mailles translineaires. Le processus translineaires conduit a la realisation de nombreuses fonctions electroniques lineaires ou non lineaires, analogiques ou logiques. Les structures translineaires sont destinees a commander electroniquement le facteur transfert des reseaux lineaires
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Choudens, Philippe de. "Test intégré de processeur facilement testable." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00319265.

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Un test permet d'assurer la sécurité de fonctionnement des circuits VLSI. La première partie montre l'intérêt dans un tel contexte d'un processeur facilement testable; la deuxième partie développe pour de tels microprocesseurs une stratégie de test. Dans la troisième partie est traité le problème de la définition des vecteurs de test des circuits logiques programmables. Développement d'un test pour multiplieur itératif
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Tang, Guang-ming. "Studies on Datapath Circuits for Superconductor Bit-Slice Microprocessors." 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/217208.

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Books on the topic "MULTIPLIER CIRCUIT"

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Kursun, Volkan. Multiple-voltage CMOS circuit design. Chichester, UK: John Wiley, 2006.

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Kursun, Volkan. Multiple supply and threshold voltage CMOS circuits. Chichester, England: John Wiley, 2006.

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T, Butler Jon, ed. Multiple-valued logic in VLSI design. Los Alamitos, Calif: IEEE Computer Society Press, 1991.

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Chedid, Andrée. L'enfant multiple. [Paris]: Flammarion, 1991.

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United States. Bureau of Mines, ed. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. [Washington, D.C.?]: U.S. Dept. of the Interior, Bureau of Mines, 1995.

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Hanson, David R. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. [Washington, D.C.?]: U.S. Dept. of the Interior, Bureau of Mines, 1995.

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Hanson, David R. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. [Washington, D.C.?]: U.S. Dept. of the Interior, Bureau of Mines, 1995.

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Hanson, David R. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. [Washington, D.C.?]: U.S. Dept. of the Interior, Bureau of Mines, 1995.

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Hanson, David R. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. Washington, DC: U.S. Dept. of the Interior, Bureau of Mines, 1995.

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Hanson, David R. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. [Washington, D.C.?]: U.S. Dept. of the Interior, Bureau of Mines, 1995.

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Book chapters on the topic "MULTIPLIER CIRCUIT"

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Selvam, K. C. "Circuit Simulation." In Multiplier-Cum-Divider Circuits, 197–202. New York: CRC Press, 2021. http://dx.doi.org/10.1201/9781003168515-14.

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Saas, C., A. Schlaffer, and J. A. Nossek. "An Adiabatic Multiplier." In Integrated Circuit Design, 276–84. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45373-3_29.

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Kaufmann, Daniela, and Armin Biere. "AMulet 2.0 for Verifying Multiplier Circuits." In Tools and Algorithms for the Construction and Analysis of Systems, 357–64. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-72013-1_19.

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AbstractAMulet 2.0 is a fully automatic tool for the verification of integer multipliers using computer algebra. Our tool models multiplier circuits given as and-inverter graphs as a set of polynomials and applies preprocessing techniques based on elimination theory of Gröbner bases. Finally it uses a polynomial reduction algorithm to verify the correctness of the given circuit. AMulet 2.0 is a re-factorization and improved re-implementation of our previous multiplier verification tool AMulet 1.0.
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Selvam, K. C. "Peak Responding Multiplier cum Dividers—Switching." In Design of Function Circuits with 555 Timer Integrated Circuit, 137–53. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003362968-8.

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Selvam, K. C. "Peak Responding Multiplier cum Dividers—Multiplexing." In Design of Function Circuits with 555 Timer Integrated Circuit, 119–35. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003362968-7.

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Selvam, K. C. "Time Division Multiplier cum Divider—Switching." In Design of Function Circuits with 555 Timer Integrated Circuit, 93–117. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003362968-6.

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Selsiya, M. James, M. Kalaiarasi, S. Rajaram, and V. R. Venkatasubramani. "Efficient Quantum Circuit for Karatsuba Multiplier." In Studies in Computational Intelligence, 79–96. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-9530-9_5.

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Babu, Hafiz Md Hasan. "LUT-Based Matrix Multiplier Circuit Using Pigeonhole Principle." In VLSI Circuits and Embedded Systems, 233–86. Boca Raton: CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-22.

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Mandal, Sumana, Dhoumendra Mandal, Mrinal Kanti Mandal, and Sisir Kumar Garai. "Design of Optical Quaternary Multiplier Circuit Using Polarization Switch." In Lecture Notes in Electrical Engineering, 111–19. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-6159-3_13.

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Wu, Ying, Chuangtao Chen, Chenyi Wen, Weikang Qian, Xunzhao Yin, and Cheng Zhuo. "Approximate Multiplier Design for Energy Efficiency: From Circuit to Algorithm." In Approximate Computing, 51–76. Cham: Springer International Publishing, 2012. http://dx.doi.org/10.1007/978-3-030-98347-5_3.

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Conference papers on the topic "MULTIPLIER CIRCUIT"

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Banerjee, A., and A. Pathak. "Reversible Multiplier Circuit." In Third International Conference on Emerging Trends in Engineering and Technology (ICETET 2010). IEEE, 2010. http://dx.doi.org/10.1109/icetet.2010.70.

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Zhu, Binxin, Yao Chen, Han Wang, and Mahinda Vilathgamuwa. "Multiple Input-Terminal Voltage Multiplier Circuit." In 2019 4th International Conference on Intelligent Green Building and Smart Grid (IGBSG). IEEE, 2019. http://dx.doi.org/10.1109/igbsg.2019.8886172.

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Hatkar, A. P., A. A. Hatkar, and N. P. Narkhede. "ASIC Design of Reversible Multiplier Circuit." In 2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies (ICESC). IEEE, 2014. http://dx.doi.org/10.1109/icesc.2014.16.

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Mongkolwai, Pratya, and Worapong Tangsrirat. "CFTA-based current multiplier/divider circuit." In 2011 International Symposium on Intelligent Signal Processing and Communications Systems (ISPACS 2011). IEEE, 2011. http://dx.doi.org/10.1109/ispacs.2011.6146074.

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El-Slehdar, A. A., and Ahmed G. Radwan. "Memristor-MOS hybrid circuit redundant multiplier." In 2014 26th International Conference on Microelectronics (ICM). IEEE, 2014. http://dx.doi.org/10.1109/icm.2014.7071836.

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Kwang-Jow Gan, Ping-Feng Wu, Wu-Yan Shie, Cher-Shiung Tsai, Dong-Shong Liang, Cheng-Hsiung Tsai, and Wen-Kuan Yeh. "Frequency multiplier design using BiCMOS-based multiple-peak NDR circuit." In 2010 IEEE International Conference of Electron Devices and Solid- State Circuits (EDSSC). IEEE, 2010. http://dx.doi.org/10.1109/edssc.2010.5713683.

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Ozenli, Deniz, Ersin Alaybeyoglu, and Hakan Kuntman. "A Grounded Capacitance Multiplier Circuit Employing VDTA." In 2021 13th International Conference on Electrical and Electronics Engineering (ELECO). IEEE, 2021. http://dx.doi.org/10.23919/eleco54474.2021.9677731.

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Hussain, Inamul, Chandan Kumar Pandey, and Saurabh Chaudhury. "Design and Analysis of High Performance Multiplier Circuit." In 2019 Devices for Integrated Circuit (DevIC). IEEE, 2019. http://dx.doi.org/10.1109/devic.2019.8783322.

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Sarker, Ankur, Mohd Istiaq Sharif, S. M. Mahbubur Rashid, and Hafiz Md Hasan Babu. "Implementation of reversible multiplier circuit using Deoxyribonucleic acid." In 2013 IEEE 13th International Conference on Bioinformatics and Bioengineering (BIBE). IEEE, 2013. http://dx.doi.org/10.1109/bibe.2013.6701637.

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Akhter, Shamim, and Saurabh Chaturvedi. "Modified Binary Multiplier Circuit Based on Vedic Mathematics." In 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN). IEEE, 2019. http://dx.doi.org/10.1109/spin.2019.8711583.

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Reports on the topic "MULTIPLIER CIRCUIT"

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Butler, Jon T., and Tsutomu Sasao. Multiple-Valued Combinational Circuits with Feedback. Fort Belvoir, VA: Defense Technical Information Center, January 1994. http://dx.doi.org/10.21236/ada599933.

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Chang, Young-hoon, and Jon T. Butler. The Design of Current Mode CMOS Multiple-Valued Circuits. Fort Belvoir, VA: Defense Technical Information Center, January 1991. http://dx.doi.org/10.21236/ada608087.

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Schueller, Kriss A., and Jon T. Butler. Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits. Fort Belvoir, VA: Defense Technical Information Center, October 1995. http://dx.doi.org/10.21236/ada605390.

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Nestleroth. L52298 Augmenting MFL Tools With Sensors that Assess Coating Condition. Chantilly, Virginia: Pipeline Research Council International, Inc. (PRCI), March 2009. http://dx.doi.org/10.55274/r0010396.

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Abstract:
External coatings are routinely used to protect transmission pipelines from corrosion; however, coatings may degrade or disbond over time enabling corrosion to occur. Transmission pipeline operators often use magnetic flux leakage (MFL) in-line inspection tools to detect metal loss corrosion defects. Rather than finding the cause of a problem, failure of the coating within a corrosive environment, MFL corrosion surveys only find the result of the problem, corrosion defects that may permanently alter the pressure carrying capacity of the pipeline. Stress corrosion cracking (SCC) can be detected using in-line inspection (ILI) technology, but the availability of tools is limited and the cost of inspection is high compared to MFL inspection. SCC almost always occurs at coating faults; direct coating assessment could indicate future problems that could degrade the serviceability of the pipeline. In this project, a new sensor was developed to assess external coating that could work with currently available ILI tools for minimal additional cost to perform the inspection. The sensors, electromagnetic acoustic transducers (EMATs), generate ultrasonic waves that are guided by the pipe material around the circumference of the pipe. The coating material and adherence can influence the propagation of the ultrasonic waves; changes in ultrasonic signal features were attributed to coating faults. This development used modeling and experiments to establish a more optimal configuration for coating assessment. A multiple feature approach was used. A commonly used feature, signal amplitude, provided good sensitivity to coating condition but was influenced by inspection variables. One unique feature identified in this development is arrival time of the ultrasonic wave. For the wave type and frequency selected, the wave velocity was different for bare and coated pipe. Therefore, disbonded or missing coating can be detected by monitoring arrival time of the ultrasonic wave, a feature that is amplitude independent. Another feature for assessing coating, absorption of selective frequencies, was also demonstrated. Coating assessment capability was experimentally demonstrated using a prototype EMAT ILI tool. All three detection features were shown to perform well in an ILI environment as demonstrated at Battelle"s Pipeline Simulation Facility and BJ Inspection Services pull rigs. Improvement to the prototype occurred between each test; the most significant improvement was the design and construction of a novel set of thick-trace transmitting and receiving Printed Circuit Board (PCB) EMAT coils. Implementation variables such as moisture and soil loading were shown to have a minimal influence on results.
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