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Journal articles on the topic 'Multiple-Input Floating Gate MOS'

Author: Grafiati

Published: 6 September 2023

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1

Rodríguez-Villegas, Esther O., Alberto Yúfera, and Adoración Rueda. "A Low-Voltage Floating-Gate MOS Biquad." VLSI Design 12, no. 3 (January 1, 2001): 407–14. http://dx.doi.org/10.1155/2001/16935.

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A second-order gm-C filter based on the Floating-Gate MOS (FGMOS) technique is presented. It uses a new fully differential transconductor and works at 2 V of voltage supply with a full differential input linear range and a THD below 1%. Programming and tuning are performed by means of a single voltage signal. The transconductor incorporates a novel Common-Mode Feedback Circuit (CMFB) based also on FGMOS transistors.

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2

Gupta, Maneesha, Richa Srivastava, and Urvashi Singh. "Low Voltage Floating Gate MOS Transistor Based Differential Voltage Squarer." ISRN Electronics 2014 (February 9, 2014): 1–6. http://dx.doi.org/10.1155/2014/357184.

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This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics in saturation region. The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator. The squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellation so as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate the differential signals. The proposed circuit provides a current output proportional to the square of the difference of two input voltages. The second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such as low supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ±0.75 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

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3

Mehrvarz, H. R., and Chee Yee Kwok. "A novel multi-input floating-gate MOS four-quadrant analog multiplier." IEEE Journal of Solid-State Circuits 31, no. 8 (1996): 1123–31. http://dx.doi.org/10.1109/4.508259.

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4

Khateb, Fabian, Tomasz Kulej, Harikrishna Veldandi, and Winai Jaikla. "Multiple-input bulk-driven quasi-floating-gate MOS transistor for low-voltage low-power integrated circuits." AEU - International Journal of Electronics and Communications 100 (February 2019): 32–38. http://dx.doi.org/10.1016/j.aeue.2018.12.023.

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5

Srivastava, Richa, Maneesha Gupta, and Urvashi Singh. "Fully Programmable Gaussian Function Generator Using Floating Gate MOS Transistor." ISRN Electronics 2012 (November 20, 2012): 1–5. http://dx.doi.org/10.5402/2012/148492.

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Floating gate MOS (FGMOS) based fully programmable Gaussian function generator is presented. The circuit combines the tunable property of FGMOS transistor, exponential characteristics of MOS transistor in weak inversion, and its square law characteristic in strong inversion region to implement the function. Two-quadrant current mode squarer is the core subcircuit of Gaussian function generator that helps to implement full Gaussian function for positive as well as negative input current. FGMOS implementation of the circuit reduces the current mismatching error and increases the tunability of the circuit. The performance of circuit is verified at 1.8 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

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6

Khateb, Fabian, Tomasz Kulej, Montree Kumngern, and Vilém Kledrowetz. "Low-Voltage Diode-Less Rectifier Based on Fully Differential Difference Transconductance Amplifier." Journal of Circuits, Systems and Computers 26, no. 11 (March 17, 2017): 1750172. http://dx.doi.org/10.1142/s0218126617501729.

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This paper presents a voltage-mode low-voltage low-power diode-less rectifier with only one active element, the fully differential difference transconductance amplifier (FDDTA). The multiple-input floating-gate MOS (FG-MOS) transistor is used to build the differential pairs of the FDDTA resulting in the reduced count of transistors, circuit simplicity and the capability to work under low-voltage supply with extended input voltage range. The rectifier was designed with 0.9[Formula: see text]V voltage supply and 8[Formula: see text][Formula: see text]W power consumption, hence it is suitable for wearable electronics and biomedical applications. The simulation results obtained from the Cadence platform using 0.18[Formula: see text][Formula: see text]m TSMC CMOS technology show good performances for the designed circuit.

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7

Sharroush, Sherif, and Sherif Nafea. "A Novel Domino Logic Based on Floating-Gate MOS Transistors." Jordan Journal of Electrical Engineering 9, no. 3 (2023): 410. http://dx.doi.org/10.5455/jjee.204-1672498383.

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Domino logic finds a wide variety of applications in both static and dynamic random-access memories and in high-speed microprocessors. However, the main limitation of the domino logic-circuit family is the trade-off between the noise immunity and speed. In order to resolve such a trade-off, this paper proposes a domino logic that is based on floating-gate MOS (FGMOS) transistors. Compact-form expressions are derived for the noise margins for the low and high inputs as well as the propagation delays. The proposed scheme is verified by simulation adopting the 45 nm CMOS predictive technology model (PTM) with a power-supply voltage of 1 V. The obtained results unveil that the proposed domino logic outperforms the conventional domino logic in terms of the power-delay product and the energy-delay product when realizing wide fan-in OR gates. The realized, with the proposed scheme, 16-input OR gate has an average power consumption of 3.7 µW and a propagation delay of 51 ps.

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8

Plascencia Jauregui, Francisco Javier, Agustín Santiago Medina Vazquez, Edwin Christian Becerra Alvarez, José Manuel Arce Zavala, and Sandra Fabiola Flores Ruiz. "On the methodology of calculating volume charge density in a MIFGMOS substrate using Poisson’s equation." Microelectronics International 38, no. 4 (October 14, 2021): 206–15. http://dx.doi.org/10.1108/mi-01-2021-0004.

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Purpose This study aims to present a mathematical method based on Poisson’s equation to calculate the voltage and volume charge density formed in the substrate under the floating gate area of a multiple-input floating-gate metal-oxide semiconductor metal-oxide semiconductor (MOS) transistor. Design/methodology/approach Based on this method, the authors calculate electric fields and electric potentials from the charges generated when voltages are applied to the control gates (CG). This technique allows us to consider cases when the floating gate has any trapped charge generated during the manufacturing process. Moreover, the authors introduce a mathematical function to describe the potential behavior through the substrate. From the resultant electric field, the authors compute the volume charge density at different depths. Findings The authors generate some three-dimensional graphics to show the volume charge density behavior, which allows us to predict regions in which the volume charge density tends to increase. This will be determined by the voltages on terminals, which reveal the relationship between CG and volume charge density and will allow us to analyze some superior-order phenomena. Originality/value The procedure presented here and based on coordinates has not been reported before, and it is an aid to generate a model of the device and to build simulation tools in an analog design environment.

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9

Luck, A., S. Jung, R. Brederlow, R. Thewes, K. Goser, and W. Weber. "On the design robustness of threshold logic gates using multi-input floating gate MOS transistors." IEEE Transactions on Electron Devices 47, no. 6 (June 2000): 1231–40. http://dx.doi.org/10.1109/16.842967.

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10

Rajesh, Durgam, Subramanian Tamil, Nikhil Raj, and Bharti Chourasia. "Low-voltage bulk-driven flipped voltage follower-based transconductance amplifier." Bulletin of Electrical Engineering and Informatics 11, no. 2 (April 1, 2022): 765–71. http://dx.doi.org/10.11591/eei.v11i2.3306.

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A low voltage high performance design of operational transconductance amplifier is proposed in this paper. The proposed architecture is based on bulk driven quasi-floating gate metal oxide semiconductor field effect transistor (MOSFET) which supports low voltage operation and improves the gain of the amplifier. Besides to this the tail current source requirement of operational transconductance amplifier (OTA) is removed by using the flipped voltage follower structure at the input pair along with bulk driven quasi-floating gate MOSFET. The proposed operational transconductance amplifier shows a five-fold increase in direct current (DC) gain and 3-fold increase in unity gain bandwidth when compared with its conventional bulk driven architecture. The metal oxide semiconductor (MOS) model used for amplifier design is of 0.18 um complementary metal oxide semiconductor (CMOS) technology at supply of 0.5 V.

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11

Yoon, Jong-Hwan. "Fabrication of Sn@Al2O3 Core-shell Nanoparticles for Stable Nonvolatile Memory Applications." Materials 12, no. 19 (September 24, 2019): 3111. http://dx.doi.org/10.3390/ma12193111.

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Sn@Al2O3 core-shell nanoparticles (NPs) with narrow spatial distributions were synthesized in silicon dioxide (SiO2). These Sn@Al2O3 core-shell NPs were self-assembled by thermally annealing a stacked structure of SiOx/Al/Sn/Al/SiOx sandwiched between two SiO2 layers at low temperatures. The resultant structure provided a well-defined Sn NP floating gate with a SiO2/Al2O3 dielectric stacked tunneling barrier. Capacitance-voltage (C-V) measurements on a metal-oxide-semiconductor (MOS) capacitor with a Sn@Al2O3 core-shell NP floating gate confirmed an ultra-high charge storage stability, and the multiple trapping of electron at the NPs, as expected from low-k/high-k dielectric stacked tunneling layers and metallic NPs, respectively.

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12

Durgam, Rajesh, S. Tamil, and Nikhil Raj. "Design of Low Voltage Low Power High Gain Operational Transconductance Amplifier." U.Porto Journal of Engineering 7, no. 4 (November 26, 2021): 103–10. http://dx.doi.org/10.24840/2183-6493_007.004_0008.

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In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.

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13

Bui, Trong-Tu, and Tadashi Shibata. "A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique." Journal of Engineering 2013 (2013): 1–8. http://dx.doi.org/10.1155/2013/759761.

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We present a compact and low-power rank-order searching (ROS) circuit that can be used for building associative memories and rank-order filters (ROFs) by employing time-domain computation and floating-gate MOS techniques. The architecture inherits the accuracy and programmability of digital implementations as well as the compactness and low-power consumption of analog ones. We aim to implement identification function as the first priority objective. Filtering function would be implemented once the location identification function has been carried out. The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology. It consumes only 132.3 μW for an eight-input demonstration case.

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14

CRISTOLOVEANU, SORIN, ROMAIN RITZENTHALER, AKIKO OHATA, and OLIVIER FAYNOT. "3D Size Effects in Advanced SOI Devices." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 9–30. http://dx.doi.org/10.1142/s0129156406003515.

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Recent results on state-of-the-art SOI MOS transistors reveal the impact of the device miniaturization. The role of each dimension (length, width, thickness) is examined sequentially, by emphasizing the link with the other MOSFET dimensions. Ultra-thin gate oxide and silicon film enable, respectively, Gate-Induced Floating Body Effects (GIFBE) and super-coupling. In ultra-thin SOI films, the interface coupling effects are amplified leading to interesting consequences for carrier transport and multiple-gate operation. The self-heating problem in SOI MOSFETs can be alleviated by replacing the buried oxide with a different dielectric that offers improved thermal conductivity, without degrading the electrostatic behavior of the device. We describe the operation and scaling principles of transistors with double, triple or quadruple gates, which are governed by strong 3-D coupling effects.

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15

Carrillo, Juan M., and Carlos A. de la Cruz-Blas. "0.6-V 1.65-μW Second-Order Gm-C Bandpass Filter for Multi-Frequency Bioimpedance Analysis Based on a Bootstrapped Bulk-Driven Voltage Buffer." Journal of Low Power Electronics and Applications 12, no. 4 (November 30, 2022): 62. http://dx.doi.org/10.3390/jlpea12040062.

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A bootstrapping technique used to increase the intrinsic voltage gain of a bulk-driven MOS transistor is described in this paper. The proposed circuit incorporates a capacitor and a cutoff transistor to be connected to the gate terminal of a bulk-driven MOS device, thus achieving a quasi-floating-gate structure. As a result, the contribution of the gate transconductance is cancelled out and the voltage gain of the device is correspondingly increased. The technique allows for implementing a voltage follower with a voltage gain much closer to unity as compared to the conventional bulk-driven case. This voltage buffer, along with a pseudo-resistor, is used to design a linearized transconductor. The proposed transconductance cell includes an economic continuous tuning mechanism that permits programming the effective transconductance in a range sufficiently wide to counteract the typical variations that process parameters suffer during fabrication. The transconductor has been used to implement a second-order Gm-C bandpass filter with a relatively high selectivity factor, suited for multi-frequency bioimpedance analysis in a very low-voltage environment. All the circuits have been designed in 180 nm CMOS technology to operate with a 0.6-V single-supply voltage. Simulated results show that the proposed technique allows for increasing the linearity and reducing the input-referred noise of the bootstrapped bulk-driven MOS transistor, which results in an improvement of the overall performance of the transconductor. The center frequency of the bandpass filter designed can be programmed in the frequency range from 6.5 kHz to 37.5 kHz with a power consumption ranging between 1.34 μW and 2.19 μW. The circuit presents an in-band integrated noise of 190.5 μVrms and is able to process signals of 110 mVpp with a THD below −40 dB, thus leading to a dynamic range of 47.4 dB.

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16

Shi, Yong, Zhong-Yuan Ma, Kun-Ji Chen, Xiao-Fan Jiang, Wei Li, Xin-Fan Huang, Ling Xu, Jun Xu, and Duan Feng. "The Effect of Multiple Interface States and nc-Si Dots in a Nc-Si Floating Gate MOS Structure Measured by their G — V Characteristics." Chinese Physics Letters 30, no. 7 (July 2013): 077307. http://dx.doi.org/10.1088/0256-307x/30/7/077307.

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17

Kim, Y. S., K. S. Sohn, K. J. Baek, N. S. Kim, S. F. Al-Sarawi, and D. Abbott. "Input common-mode adapter using multiple-input floating-gate devices." Electronics Letters 46, no. 19 (2010): 1318. http://dx.doi.org/10.1049/el.2010.1775.

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18

Ramirez-Angulo, J., S. C. Choi, D. Zrilic, and A. de Luca. "Charge-Mode Defuzzifiers using Multiple Input Floating-Gate Transistors." Intelligent Automation & Soft Computing 3, no. 1 (January 1997): 5–12. http://dx.doi.org/10.1080/10798587.1997.10750688.

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19

Cisneros-Sinencio, Luis Fortino, Alejandro Diaz-Sanchez, Jaime Ramirez-Angulo, and Hector Vazquez-Leal. "Realistic model for the multiple-input floating-gate transistor." IEEJ Transactions on Electrical and Electronic Engineering 9, no. 6 (September 2, 2014): 692–94. http://dx.doi.org/10.1002/tee.22027.

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20

Ramirez-Angulo, J., S. C. Choi, and G. Gonzalez-Altamirano. "Low-voltage circuits building blocks using multiple-input floating-gate transistors." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 42, no. 11 (1995): 971–74. http://dx.doi.org/10.1109/81.477210.

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21

Khateb, Fabian, Tomasz Kulej, Montree Kumngern, Winai Jaikla, and Rajeev Kumar Ranjan. "Comparative performance study of multiple-input bulk-driven and multiple-input bulk-driven quasi-floating-gate DDCCs." AEU - International Journal of Electronics and Communications 108 (August 2019): 19–28. http://dx.doi.org/10.1016/j.aeue.2019.06.003.

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22

Yang, Kewei, and Andreas G. Andreou. "A multiple input differential amplifier based on charge sharing on a floating-gate MOSFET." Analog Integrated Circuits and Signal Processing 6, no. 3 (November 1994): 197–208. http://dx.doi.org/10.1007/bf01238888.

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23

Srivastava, A., and H. N. Venkata. "Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETS." Integration 36, no. 3 (October 2003): 87–101. http://dx.doi.org/10.1016/s0167-9260(03)00049-x.

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24

Zhao, Zhou, Ashok Srivastava, Lu Peng, and Saraju P. Mohanty. "A Multiple Input Floating Gate Based Arithmetic Logic Unit with a Feedback Loop for Digital Calibration." Journal of Low Power Electronics 14, no. 4 (December 1, 2018): 535–47. http://dx.doi.org/10.1166/jolpe.2018.1585.

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25

Gu, Xiaofeng, Rao Che, Yating Dong, and Zhiguo Yu. "A Novel Word Line Driver Circuit for Compute-in-Memory Based on the Floating Gate Devices." Electronics 12, no. 5 (March 1, 2023): 1185. http://dx.doi.org/10.3390/electronics12051185.

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In floating gate compute-in-memory (CIM) chips, due to the gate equivalent capacitance of the large-scale array and the parasitic capacitance of the long-distance transmission wire, it is difficult to balance the switching speed and area of the word line driver circuit (WLDC). The difference among multiple voltage domains required for floating gate CIM devices has also far exceeded the withstand voltage range of a single transistor in the WLDC. This paper proposes a novel WLDC based on the working principle of the CIM array. A multi-level pre-processing voltage control method is adopted to carry out an optional hierarchical transmission of multiple high voltages, significantly reducing the propagation delay. The proposed WLDC is based on the Wilson current mirror structure, which substantially reduces the physical design area. The simulation results show that the circuit can convert a 1.2 V low-voltage domain input signal with a frequency of 10 MHz into a high-voltage domain output voltage, and the output voltage range of a single WLDC can reach −10 V to 10 V. With a capacitive load within 5 pF, the transmission delay is less than 10 ns. The layout area is 594.88 µm2, which is suitable for a large-scale CIM array.

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26

Ramirez-Angulo, J., R. G. Carvajal, J. Tombs, and A. Torralba. "Low-voltage CMOS op-amp with rail-to-rail input and output signal swing for continuous-time signal processing using multiple-input floating-gate transistors." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 48, no. 1 (2001): 111–16. http://dx.doi.org/10.1109/82.913195.

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27

Jaikla, Winai, Sirigul Bunrueangsak, Fabian Khateb, Tomasz Kulej, Peerawut Suwanjan, and Piya Supavarasuwat. "Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs." Electronics 10, no. 6 (March 15, 2021): 684. http://dx.doi.org/10.3390/electronics10060684.

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This paper presents inductance simulators using the voltage differencing differential input buffered amplifier (VD-DIBA) as an active building block. Three types of inductance simulators, including floating lossless inductance, series inductance-resistance, and parallel inductance-resistance simulators, are proposed, in addition to their application to the 4th order elliptic lowpass ladder filter. The simple design procedures of these inductance simulators using a circuit block diagram are also given. The proposed inductance simulators employ two VD-DIBAs and two passive elements. The complementary metal oxide semiconductor (CMOS) VD-DIBA used in this design utilizes the multiple-input metal oxide semiconductor (MOS) transistor technique in order to achieve a compact and simple structure with a minimum count of transistors. Thanks to this technique, the VD-DIBA offers high performances compared to the other CMOS structures presented in the literature. The CMOS VD-DIBAs and their applications are designed and simulated in the Cadence environment using a 0.18 µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). Using a supply voltage of ±0.9 V, the linear operation of VD-DIBA is obtained over a differential input range of −0.5 V to 0.5 V. The lowpass (LP) ladder filter realized with the proposed inductance simulators shows a dynamic range (DR) of 80 dB for a total harmonic distortion (THD) of 2% at 1 kHz and a 1.8 V peak-to-peak output. In addition, the experimental results of the floating inductance simulators and their applications are obtained by using VD-DIBA constructed from the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental ones, confirming the advantages of the inductance simulators and their application.

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28

Cho, Seongpil, Jongseo Park, and Minjoo Choi. "Fault Classification of a Blade Pitch System in a Floating Wind Turbine Based on a Recurrent Neural Network." Journal of Ocean Engineering and Technology 35, no. 4 (August 31, 2021): 287–95. http://dx.doi.org/10.26748/ksoe.2021.018.

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This paper describes a recurrent neural network (RNN) for the fault classification of a blade pitch system of a spar-type floating wind turbine. An artificial neural network (ANN) can effectively recognize multiple faults of a system and build a training model with training data for decision-making. The ANN comprises an encoder and a decoder. The encoder uses a gated recurrent unit, which is a recurrent neural network, for dimensionality reduction of the input data. The decoder uses a multilayer perceptron (MLP) for diagnosis decision-making. To create data, we use a wind turbine simulator that enables fully coupled nonlinear time-domain numerical simulations of offshore wind turbines considering six fault types including biases and fixed outputs in pitch sensors and excessive friction, slit lock, incorrect voltage, and short circuits in actuators. The input data are time-series data collected by two sensors and two control inputs under the condition that of one fault of the six types occurs. A gated recurrent unit (GRU) that is one of the RNNs classifies the suggested faults of the blade pitch system. The performance of fault classification based on the gate recurrent unit is evaluated by a test procedure, and the results indicate that the proposed scheme works effectively. The proposed ANN shows a 1.4% improvement in its performance compared to an MLP-based approach.

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29

Banchuin, Rawid, and Roungsan Chaisrichaoren. "The Completed Probabilistic Modelling of Nanometer MIFGMOSFET." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 14, no. 2 (September 11, 2020): 201–12. http://dx.doi.org/10.37936/ecti-cit.2020142.123097.

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A completed model of the probabilistic distribution of the drain current’s random variation of the nanometer multiple input floating gate MOSFET (MIFGMOSFET) is proposed in this work. The modelling process has taken the dominant physical level causes of the drain current’s variations into account. Unlike its predecessor, the proposed model considers both N-type and P-type nanometer MIFGMOSFET. Moreover, the formerly neglected parasitic coupling capacitances have also been taken into account. The obtained modelling results, which are based on the derived drain current’s equations of nanometer MIFGMOSFET, are very accurate. They can predict the probabilistic distributions of the candidate N-type and P-type nanometer MIFGMOSFETs obtained by using Monte-Carlo simulations with 99% confidence and higher accuracy than that of the previous work. We also perform a comparative robustness study of the nanometer MIFGMOSFET of both types and demonstrate various interesting applications of our modelling results

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30

Gudlavalleti, R. H., B. Saman, R. Mays, H. Salama, Evan Heller, J. Chandy, and F. Jain. "A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array." International Journal of High Speed Electronics and Systems 29, no. 01n04 (March 2020): 2040009. http://dx.doi.org/10.1142/s0129156420400091.

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Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

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Miyazaki, Seiichi. "Formation and Characterization of Hybrid Nanodots Floating Gate for Optoelectronic Application." MRS Proceedings 1510 (2013). http://dx.doi.org/10.1557/opl.2013.272.

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ABSTRACTWe have fabricated a hybrid nanodots floating gate (FG) in which Si quantum dots (QDs) and silicide nanodots (NDs) are stacked with a very thin SiO2 interlayer in order to satisfy both multiple valued capability and charge storage capacity for a sufficient memory window and to open up novel functionality for optoelectronic application. In electron charging and discharging characteristics measured with application of pulsed gate biases to MOS capacitors with a hybrid NDs FG, stepwise changes in the rates for electron injection and emission were revealed with increasing pulse width at room temperature. Also, nMOSFETs with a hybrid NDs FG show unique hysteresis with stepwise changes in the drain current - gate voltage characteristics. The observed characteristics can be interpreted in terms that the electron injection and storage into silicide-NDs proceed through the discrete charged states of Si-QDs. For MOS capacitors with a triple-stacked hybrid NDs FG fabricated by adding another Si-QDs, by subgap light irradiation from the back side of the Si substrate, a distinct infrared optical response in C-V characteristics was detected at room temperature. The result is attributable to the shift of charge centroid in the hybrid NDs FG as a result of transfer of photoexcited electrons from silicide NDs to Si-QDs.

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