Relevant bibliographies by topics / Multi-Processor System-on-Chip

Academic literature on the topic 'Multi-Processor System-on-Chip'

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Published: 14 March 2023

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Journal articles on the topic "Multi-Processor System-on-Chip"

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Nurmi, Jari. "International Symposium on System-on-Chip 2010." International Journal of Embedded and Real-Time Communication Systems 2, no. 4 (October 2011): 38–45. http://dx.doi.org/10.4018/ijertcs.2011100103.

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International Symposium on System-on-Chip 2010 was the 12th SoC event in Tampere, Finland. The theme of this symposium was Embedded Multi-processor/multi-core Computation Platforms. That was reflecting the increasing interest in multicore and many core implementations on System-on-Chip. This paper discusses briefly the history of the event which is technically co-sponsored by IEEE Circuits and Systems Society. The main focus is in an overview of the year 2010 contents, and in particular in its tutorial and invited talks.
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Lee, Seung Eun. "Reusing existing resources for testing a multi-processor system-on-chip." International Journal of Electronics 100, no. 3 (March 2013): 355–70. http://dx.doi.org/10.1080/00207217.2012.713011.

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Cui, Yuan, and Bo Nian Li. "A Multimedia System Based on OMAP3530." Applied Mechanics and Materials 40-41 (November 2010): 506–9. http://dx.doi.org/10.4028/www.scientific.net/amm.40-41.506.

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JPEG images decoded and encoded rapidly and effectively based on OMAP3530 chip. USB camera deployed as images’ acquisition equipment, and used the ARM + DSP multi-core OMAP3530 processor as image decode-encode processing chip. The results sent to the user interface ultimately. System’s development was based on DVSDK. The result proved system fast than others.
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Liu, Lin, and Yuanyuan Yang. "Energy-aware routing in hybrid optical network-on-chip for future multi-processor system-on-chip." Journal of Parallel and Distributed Computing 73, no. 2 (February 2013): 189–97. http://dx.doi.org/10.1016/j.jpdc.2012.09.018.

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Lafi, Walid, Didier Lattard, and Ahmed Jerrya. "An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip." Software: Practice and Experience 42, no. 7 (February 7, 2012): 877–90. http://dx.doi.org/10.1002/spe.1150.

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AMAMIYA, MAKOTO, HIDEO TANIGUCHI, and TAKANORI MATSUZAKI. "AN ARCHITECTURE OF FUSING COMMUNICATION AND EXECUTION FOR GLOBAL DISTRIBUTED PROCESSING." Parallel Processing Letters 11, no. 01 (March 2001): 7–24. http://dx.doi.org/10.1142/s0129626401000397.

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We are pursuing the FUCE architecture project at Kyushu University. FUCE means FUsion of Communication and Execution. The main objective of our research is, as the name shows, to develop a new architecture that truly fuses communication and computation. The FUCE project develops a new on-chip-multi-processor and kernel software on it. We name the processor FUCE processor, and the kernel software as CEFOS (Communication and Execution Fusion OS). The FUCE processor is designed as a network node processor to perform mainly switching/transmitting of messages/transaction and handling its contents. FUCE processor architecture is designed as a multiprocessor-on-chip to support the fine-grain multi-threading. The kernel software CEFOS is also developed on the concept of multithreading. User and system processes are constructed as a set of threads, which are executed concurrently according to thread dependences.
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Li, Shuo, Gao Chao Xu, Yu Shuang Dong, and Feng Wu. "The Review of Cache Partitioning in Multi-Core Processor." Key Engineering Materials 439-440 (June 2010): 1223–29. http://dx.doi.org/10.4028/www.scientific.net/kem.439-440.1223.

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With the development of microelectronics technology, Chip Multi-Processor (CMP) or multi-core design has become a mainstream choice for major microprocessor vendors. But in a chip-multiprocessor with a shared cache structure , the competing accesses from different applications degrade the system performance , resulting in non-optimal performance and non-predicting executing time. Cache partitioning techniques can exclusively partition the shared cache among multiple competing applications. In this paper, we first introduce the problems caused by Cache pollution in multicore processor structure; then present the different methods of Cache partitioning in multicore processor structure¬ －－categorizing them based on the different metrics. And finally, we discuss some possible directions for future research in the area.
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SLIMANI, Hayet, Abderrazak JEMAIU, and Ahmed Chiheb AMMARI. "Multi-Processor System-on-Chip Power Estimation Model At the CABA Level." IFAC Proceedings Volumes 45, no. 7 (2012): 341–46. http://dx.doi.org/10.3182/20120523-3-cz-3015.00065.

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Tang, Lin, and Jin Zhao Wu. "The Status and Challenges of Multi-Processor System-on-Chip’s Formal Verification." Applied Mechanics and Materials 602-605 (August 2014): 2926–29. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2926.

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With the continuous advancement of processor manufacturing process as well as the exposed limitations of single-core Processors, Multi-Processor System-on-Chip (MPSoC) has become the inevitable outcome of the technological development and practical application needs. It is used to meet the requirements of multitasking, multifunctional and high performance computing. With the improvement of chip complexity, verification module also increases exponentially. Verification of MPSoC is becoming Bottleneck in the process of chip’s design. So this paper first introduces the origin of MPSoC, and analyzes developing tendency of its verification. And then, the theory and main challenges to the formal verification of MPSoC are discussed. This paper will provide support for building the verified theory method and technology that can meet the demand of MPSoC design, and Developing MPSoC high-level architecture design verification technology.
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BAGHERZADEH, NADER, and MASARU MATSUURA. "PERFORMANCE IMPACT OF TASK-TO-TASK COMMUNICATION PROTOCOL IN NETWORK-ON-CHIP." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 283–94. http://dx.doi.org/10.1142/s021812660900506x.

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Network-on-Chip (NoC) is a strong candidate for scalable interconnect design of Multi-Processor System-on-Chip (MPSoC). Software tasks of MPSoC require a certain protocol to communicate with each other. In NoC such a communication protocol should be handled at Network Interface and/or Processor Element level and it is expected that different protocols show their trade-offs. In consideration of the above, we employed two types of basic protocol and investigated their performance impact. The contribution of this work is to quantitatively evaluate effectiveness of using separate communication protocols depending on the task structure.
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Dissertations / Theses on the topic "Multi-Processor System-on-Chip"

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Ghaeini, Bentolhoda. "A Fault-Aware Resource Manager for Multi-Processor System-on-Chip." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101010.

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The semiconductor technology development empowers fabrication of extremelycomplex integrated circuits (ICs) that may contain billions of transistors. Suchhigh integration density enables designing an entire system onto a single chip,commonly referred to as a System-on-Chip (SoC). In order to boost performance,it is increasingly common to design SoCs that contain a number of processors, socalled multi-processor system-on-chips (MPSoCs).While on one hand, recent semiconductor technologies enable fabrication ofdevices such as MPSoCs which provide high performance, on the other hand thereis a drawback that these devices are becoming increasingly susceptible to faults.These faults may occur due to escapes from manufacturing test, aging effects orenvironmental impacts. When present in a system, faults may disrupt functionalityand can cause incorrect system operation. Therefore, it is very importantwhen designing systems to consider methods to tolerate potential faults. To copewith faults, there is a need of fault handling which implies automatic detection,identification and recovery from faults which may occur during the system’s operation.This work is about the design and implementation of a fault handling methodsfor an MPSoC. A fault aware Resource Manager (RM) is designed and implementedto obtain correct system operation and maximize the system’s throughputin the presence of faults. The RM has the responsibility of scheduling jobs to availableresources, collecting fault states from resources in the system and performingfault handling tasks, based on fault states. The RM is also employed in multipleexperiments in order to study its behavior in different situations.
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Hegde, Sridhar. "FUNCTIONAL ENHANCEMENT AND APPLICATIONS DEVELOPMENT FOR A HYBRID, HETEROGENEOUS SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE." UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/252.

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Reconfigurable and dynamic computer architecture is an exciting area of research that is rapidly expanding to meet the requirements of compute intense real and non-real time applications in key areas such as cryptography, signal/radar processing and other areas. To meet the demands of such applications, a parallel single-chip heterogeneous Hybrid Data/Command Architecture (HDCA) has been proposed. This single-chip multiprocessor architecture system is reconfigurable at three levels: application, node and processor level. It is currently being developed and experimentally verified via a three phase prototyping process. A first phase prototype with very limited functionality has been developed. This initial prototype was used as a base to make further enhancements to improve functionality and performance resulting in a second phase virtual prototype, which is the subject of this thesis. In the work reported here, major contributions are in further enhancing the functionality of the system by adding additional processors, by making the system reconfigurable at the node level, by enhancing the ability of the system to fork to more than two processes and by designing some more complex real/non-real time applications which make use of and can be used to test and evaluate enhanced and new functionality added to the architecture. A working proof of concept of the architecture is achieved by Hardware Description Language (HDL) based development and use of a Virtual Prototype of the architecture. The Virtual Prototype was used to evaluate the architecture functionality and performance in executing several newly developed example applications. Recommendations are made to further improve the system functionality.
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Ryu, Kyeong Keol. "Automated Bus Generation for Multi-processor SoC Design." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5076.

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In the design of a multi-processor System-on-a-Chip (SoC), the bus architecture typically comes to the forefront because the system performance is not dependent only on the speed of the Processing Elements (PEs) but also on the bus architecture in the system. An efficient bus architecture with effective arbitration for reducing contention on the bus plays an important role in maximizing performance. Therefore, among many issues of multi-processor SoC research, we focus on two issues related to the bus architecture in this dissertation. One issue is how to quickly and easily design an efficient bus architecture for an SoC. The second issue is how to quickly explore the design space across performance influencing factors to achieve a high performance bus system. The objective of this research is to provide a Computer-Aided Design (CAD) tool with which the user can quickly explore System-on-a-Chip (SoC) bus design space in search of a high performance SoC bus system. From a straightforward description of the numbers and types of Processing Elements (PEs), non-PEs, memories and buses (including, for example, the address and data bus widths of the buses and memories), our Bus Synthesis tool, called BusSynth, generates a Register-Transfer Level (RTL) Verilog Hardware Description Language (HDL) description of the specified bus system. The user can utilize this RTL Verilog in bus-accurate simulations to more quickly arrive at an efficient bus architecture for a multi-processor SoC. The methodology we propose gives designers a great benefit in fast design space exploration of bus systems across a variety of performance influencing factors such as bus types, PE types and software programming styles (e.g., pipelined parallel fashion or functional parallel fashion). We also show that BusSynth can efficiently generate bus systems in a matter of seconds as opposed to weeks of design effort to integrate together each system component by hand. Moreover, unlike the previous related work, BusSynth can support a wide variety of PEs, memory types and bus architectures (including a hybrid bus architecture) in search of a high performance SoC.
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Kliem, Daniel [Verfasser]. "A Flexible Multi-Processor System-on-a-Chip Architecture for Safety- and Security-Critical Applications / Daniel Kliem." Aachen : Shaker, 2013. http://d-nb.info/1050342682/34.

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Poletti, Francesco <1977&gt. "Multi processor system on chip platform and studying of the best architecture and software solution for an application." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/407/1/Tesi_pol.pdf.

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Poletti, Francesco <1977&gt. "Multi processor system on chip platform and studying of the best architecture and software solution for an application." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/407/.

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Wang, Zheng [Verfasser], Anupam [Akademischer Betreuer] Chattopadhyay, and Tobias G. [Akademischer Betreuer] Noll. "High-level estimation and exploration of reliability for multi-processor system-on-chip / Zheng Wang ; Anupam Chattopadhyay, Tobias G. Noll." Aachen : Universitätsbibliothek der RWTH Aachen, 2015. http://d-nb.info/1125910704/34.

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Druyer, Rémy. "Réseau sur puce sécurisé pour applications cryptographiques sur FPGA." Thesis, Montpellier, 2017. http://www.theses.fr/2017MONTS023/document.

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Que ce soit au travers des smartphones, des consoles de jeux portables ou bientôt des supercalculateurs, les systèmes sur puce (System-on-chip (SoC)) ont vu leur utilisation largement se répandre durant ces deux dernières décennies. Ce phénomène s’explique notamment par leur faible consommation de puissance au regard des performances qu’ils sont capables de délivrer, et du large panel de fonctions qu’ils peuvent intégrer. Les SoC s’améliorant de jour en jour, ils requièrent de la part des systèmes d’interconnexions qui supportent leurs communications, des performances de plus en plus élevées. Pour répondre à cette problématique les réseaux sur puce (Network-on-Chip (NoC)) ont fait leur apparition.En plus des ASIC, les circuit reconfigurables FPGA sont un des choix possibles lors de la réalisation d’un SoC. Notre première contribution a donc été de réaliser et d’étudier les performances du portage du réseau sur puce générique Hermes initialement conçu pour ASIC, sur circuit reconfigurable. Cela nous a permis de confirmer que l’architecture du système d’interconnexions doit être adaptée à celle du circuit pour pouvoir atteindre les meilleures performances possibles. Par conséquent, notre deuxième contribution a été la conception de l’architecture de TrustNoC, un réseau sur puce optimisé pour FPGA à hautes performances en latence, en fréquence de fonctionnement, et en quantité de ressources logiques occupées.Un autre aspect primordial qui concerne les systèmes sur puce, et plus généralement de tous les systèmes numériques est la sécurité. Notre dernière principale contribution a été d’étudier les menaces qui s’exercent sur les SoC durant toutes les phases de leur vie, puis de développer à partir d’un modèle de menaces, des mécanismes matériels de sécurité permettant de lutter contre des détournements d’IP, et des attaques logicielles. Nous avons également veillé à limiter au maximum le surcoût qu’engendre les mécanismes de sécurité sur les performances sur réseau sur puce
Whether through smartphones, portable game consoles, or high performances computing, Systems-on-Chip (SoC) have seen their use widely spread over the last two decades. This can be explained by the low power consumption of these circuits with the regard of the performances they are able to deliver, and the numerous function they can integrate. Since SoC are improving every day, they require better performances from interconnects that support their communications. In order to address this issue Network-on-Chip have emerged.In addition to ASICs, FPGA circuits are one of the possible choices when conceiving a SoC. Our first contribution was therefore to perform and study the performance of Hermes NoC initially designed for ASIC, on reconfigurable circuit. This allowed us to confirm that the architecture of the interconnection system must be adapted to that of the circuit in order to achieve the best possible performances. Thus, our second contribution was to design TrustNoC, an optimized NoC for FPGA platform, with low latency, high operating frequency, and a moderate quantity of logical resources required for implementation.Security is also a primordial aspect of systems-on-chip, and more generally, of all digital systems. Our latest contribution was to study the threats that target SoCs during all their life cycle, then to develop and integrate hardware security mechanisms to TrustNoC in order to counter IP hijacking, and software attacks. During the design of security mechanisms, we tried to limit as much as possible the overhead on NoC performances
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Faure, Etienne. "Communications matérielles / logicielles dans les systèmes sur puces multi-processeurs orientés télécommunications." Paris 6, 2007. http://www.theses.fr/2007PA066201.

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Cette thèse présente un intergiciel de communication dans le contexte des systèmes embarqués sur puce. L'application est décrite sous la forme d'un graphe de tâches communicantes. Dans ce graphe, les tâches productrices et les tâches consommatrices associés à chaque canal sont en nombres quelconques. On représente donc explicitement les communications dans ce graphe pour aboutir à un graphe bi-partite. Dans ce graphe, les tâches peuvent être implantées sous la forme de threads logiciels, ou de coprocesseurs spécialisés. On souhaite cependant conserver un mécanisme de communication uniforme, quelle que soit la nature matérielle ou logicielle des tâches. Ces contraintes nous ont conduit à spécifier des canaux de communication par mémoire partagée et un protocole de communication en 5 étapes pour y accéder. Ce protocole est implanté sous la forme d'une bibliothèque de fonctions logicielles et d'un contrôleur matériel permettant à un coprocesseur d'utiliser ces canaux de communication.
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Belhadj, Amor Hela. "Hiérarchie mémoire dans les systèmes intégrés multiprocesseurs construits autour de réseaux sur puce." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAM049/document.

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Les systèmes parallèles de type multi/pluri-cœurs permettant d'obtenir une grande puissance de calcul à bas coût énergétique sont de nos jours une réalité. Néanmoins, l'exploitation des performances de ces architectures dépend de l'efficacité du système à gérer les accès aux données. Le but de nos travaux est d'améliorer l'efficacité de ces accès en exploitant les caractéristiques de l'architecture matérielle.Dans une première partie, nous proposons une nouvelle organisation de la hiérarchie des mémoires caches qui maximise l'utilisation de l'espace de stockage disponible à chaque niveau. Cette solution, basée sur les architectures à accès non uniforme au cache (NUCA), supporte les transferts inter et intra-niveau de la hiérarchie. Elle requiert un protocole de cohérence de cache qui s'adapte à ses spécifications.Certes, le transfert des données au niveau de la hiérarchie est aussi un déterminant de la performance du système. Dans une seconde partie, nous prenons en compte les besoins de communication spécifiques du protocole. Nous proposons un réseau virtualisé comme support de communication ad-hoc afin de gérer le trafic de cohérence à moindre coût. Ce dernier relie les caches d'un même niveau pour supporter les transferts intra-niveaux, qui sont une spécificité de notre protocole, en vue de réduire la latence moyenne d'accès
Multi/many-cores parallel systems for high-power computing at low energy costs are nowadays a reality. However, exploiting the performance of these architectures depends on the efficiency of the system in managing data accesses. The aim of our work is to improve the efficiency of these accesses by exploiting the hardware architecture characteristics.In a first part, we propose a new cache hierarchy organization that aims at maximizing the use of the available storage space at each level. This solution, based on non-uniform cache access architectures (NUCA), supports inter and intra-level transfers of the hierarchy. It requires a cache coherency protocol that suits its specifications.Obviously, the transfer of data in the hierarchy is also a determinant of the system performance. In a second part, we consider the specific communication needs of the protocol. We suggest the use of a virtualized network as an ad-hoc communication medium to manage consistency traffic at a lower cost. It links the caches of the same level to support intra-level transfers, which are a specificity of our protocol, in order to reduce the average access latency
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Books on the topic "Multi-Processor System-on-Chip"

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Wieferink, Andreas. Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms. Dordrecht: Springer Science+Business Media B.V., 2008.

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Wang, Zheng, and Anupam Chattopadhyay. High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-1073-6.

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Rousseau, Frédéric, and Liliana Andrade. Multi-Processor System-On-Chip 1: Architectures. Wiley & Sons, Incorporated, John, 2021.

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Rousseau, Frédéric, and Liliana Andrade. Multi-Processor System-On-Chip 1: Architectures. Wiley & Sons, Incorporated, John, 2021.

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Rousseau, Frédéric, and Liliana Andrade. Multi-Processor System-On-Chip 2: Applications. Wiley & Sons, Incorporated, John, 2021.

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Rousseau, Frédéric, and Liliana Andrade. Multi-Processor System-On-Chip 2: Applications. Wiley & Sons, Incorporated, John, 2021.

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Rousseau, Frédéric, and Liliana Andrade. Multi-Processor System-On-Chip 1: Architectures. Wiley & Sons, Incorporated, John, 2021.

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Rousseau, Frédéric, and Liliana Andrade. Multi-Processor System-On-Chip 2: Applications. Wiley & Sons, Incorporated, John, 2021.

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Rousseau, Frédéric, and Liliana Andrade. Multi-Processor System-On-Chip 2: Applications. Wiley & Sons, Incorporated, John, 2021.

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Rousseau, Frédéric, and Liliana Andrade. Multi-Processor System-On-Chip 1: Architectures. Wiley & Sons, Incorporated, John, 2021.

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Book chapters on the topic "Multi-Processor System-on-Chip"

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Wagner, Philipp, Thomas Wild, and Andreas Herkersdorf. "DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip." In Architecture of Computing Systems – ARCS 2016, 197–209. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30695-7_15.

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Pétrot, Frédéric, Luc Michel, and Clément Deschamps. "Multi-Processor System-on-Chip Prototyping Using Dynamic Binary Translation." In Handbook of Hardware/Software Codesign, 1–27. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-7358-4_20-1.

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Ferreira, Rubem Euzébio, Luiza de Macedo Mourelle, and Nadia Nedjah. "A Parallel Genetic Algorithm on a Multi-Processor System-on-Chip." In Trends in Applied Intelligent Systems, 164–72. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-13025-0_18.

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Biedermann, Alexander, Marc Stöttinger, Lijing Chen, and Sorin A. Huss. "Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture." In Lecture Notes in Computer Science, 385–96. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19475-7_40.

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Wang, Zheng, and Anupam Chattopadhyay. "System-Level Reliability Exploration." In High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip, 155–76. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-1073-6_7.

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Amaricai, Alexandru, Alin Dobre, Oana Boncalo, Andrei Tanase, and Camelia Valuch. "Using Cycle-Approximate Simulation for Bus Based Multi-Processor System-On Chip Analysis." In Applied Computational Intelligence in Engineering and Information Technology, 213–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-28305-5_17.

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Wang, Zheng, and Anupam Chattopadhyay. "Introduction." In High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip, 1–4. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-1073-6_1.

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Wang, Zheng, and Anupam Chattopadhyay. "Background." In High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip, 5–10. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-1073-6_2.

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Wang, Zheng, and Anupam Chattopadhyay. "State-of-the-Art." In High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip, 11–28. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-1073-6_3.

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Wang, Zheng, and Anupam Chattopadhyay. "High-Level Fault Injection and Simulation." In High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip, 29–80. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-1073-6_4.

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Conference papers on the topic "Multi-Processor System-on-Chip"

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Gohringer, Diana, Michael Hubner, Volker Schatz, and Jurgen Becker. "Runtime adaptive multi-processor system-on-chip: RAMPSoC." In Distributed Processing Symposium (IPDPS). IEEE, 2008. http://dx.doi.org/10.1109/ipdps.2008.4536503.

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Holma, Kalle, Tero Arpinen, Erno Salminen, Marko Hannikainen, and Timo D. Hamalainen. "Real-time execution monitoring on multi-processor system-on-chip." In 2008 International Symposium on System-on-Chip (SOC). IEEE, 2008. http://dx.doi.org/10.1109/issoc.2008.4694872.

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Rossi, D., F. Campi, A. Deledda, C. Mucci, S. Pucillo, S. Whitty, R. Ernst, et al. "A multi-core signal processor for heterogeneous reconfigurable computing." In 2009 International Symposium on System-on-Chip - SOC 2009. IEEE, 2009. http://dx.doi.org/10.1109/socc.2009.5335668.

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Kakoee, Mohammad Reza, Vladimir Petrovic, and Luca Benini. "A multi-banked shared-l1 cache architecture for tightly coupled processor clusters." In 2012 International Symposium on System-on-Chip - SOC. IEEE, 2012. http://dx.doi.org/10.1109/issoc.2012.6376362.

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Goossens, Gert, Dirk Lanneer, Werner Geurts, and Johan Van Praet. "Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite." In 2006 International Symposium on System-on-Chip. IEEE, 2006. http://dx.doi.org/10.1109/issoc.2006.321968.

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Zhang, Qiwei, Andre B. J. Kokkeler, and Gerard J. M. Smit. "A System-level Design Method for Cognitive Radio on a Reconfigurable Multi-processor Architecture." In 2007 International Symposium on System-on-Chip. IEEE, 2007. http://dx.doi.org/10.1109/issoc.2007.4427419.

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Halim, Dareen Kusuma, S. W. Lee, M. S. Ng, Z. N. Lim, and C. M. Tang. "Exploring software-defined radio on Multi-Processor System-on-Chip." In 2015 3rd International Conference on New Media (CONMEDIA). IEEE, 2015. http://dx.doi.org/10.1109/conmedia.2015.7449149.

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Hau, Yuan Wen, M. N. Marsono, Chia Yee Ooi, and M. Khalil-Hani. "A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip." In 2011 IEEE 9th International Conference on ASIC (ASICON 2011). IEEE, 2011. http://dx.doi.org/10.1109/asicon.2011.6157150.

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Airoldi, Roberto, Piia Saastamoinen, and Jari Nurmi. "Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression." In 2012 International Symposium on System-on-Chip - SOC. IEEE, 2012. http://dx.doi.org/10.1109/issoc.2012.6376371.

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Zadrija, Valentina, and Vlado Sruk. "Component-based specification for Multi-Processor System-on-Chip design." In Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference. IEEE, 2010. http://dx.doi.org/10.1109/melcon.2010.5475898.

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