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Journal articles on the topic 'Multi-Gate Transistors'

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Author: Grafiati

Published: 14 March 2023

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1

Lin, Jinhan. "Advancement and Challenges of Field Effect Transistors based on Multi-gate Transistor." Journal of Physics: Conference Series 2370, no. 1 (November 1, 2022): 012004. http://dx.doi.org/10.1088/1742-6596/2370/1/012004.

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The advancement and challenges of field effect transistors are based on multi-gate transistors from the perspective of structure and material. Multi-gate field-effect transistors (Multi-gate FET) have steeper sub-threshold slopes, which can reduce the short channel effect and improve mobility and drive current. A fin field-effect transistor (FinFET) and gate-all-around field-effect transistor (GAAFET) are attractive multi-gate structures most compatible with today’s standard machining technologies. As the future moves towards smaller processes, FinFET and GAAFET processes limit the spacing between n-to-p devices. In order to increase the possibility of transistor miniaturization, innovative structures such as Forksheet FET and Complementary-FET (CFET) have been proposed.

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2

Sporea, Radu Alexandru. "(Invited) Multi-Gate Contact-Controlled Transistors." ECS Meeting Abstracts MA2021-01, no. 32 (May 30, 2021): 1058. http://dx.doi.org/10.1149/ma2021-01321058mtgabs.

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3

Seon, Kim, Kim, and Jeon. "Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel." Electronics 8, no. 9 (September 4, 2019): 988. http://dx.doi.org/10.3390/electronics8090988.

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Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physics at the same time. In this work, we derived new analytical current-voltage model for GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain boundary effect. Based on the derived formula, the compact I-V model for various operating regions and threshold voltage was proposed for the first time. The proposed model was compared with the measured data and good agreements were observed.

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4

ZHANG, WEIQIANG, LI SU, YU ZHANG, LINFENG LI, and JIANPING HU. "LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 147–62. http://dx.doi.org/10.1142/s0218126611007128.

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The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.

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5

Mo, Zening, Zhidi Jiang, and Jianping Hu. "A Novel Three-Input Field Effect Transistor with Parallel Switching Function Using T-Shaped Channel." Journal of Electrical and Computer Engineering 2022 (April 11, 2022): 1–12. http://dx.doi.org/10.1155/2022/1432545.

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In this article, a novel three-input field effect transistor with parallel switching function (PSF-TiFET) is proposed. The channels of the new device consist of a vertical subchannel and two horizontal subchannels. The two horizontal subchannels are manufactured over the vertical subchannel by using smart-cut process. The top gate is located above the two horizontal subchannels. The front gate and back gate below the two horizontal subchannels are located on the two sides of the vertical subchannel, respectively. Each of the all three gates has roughly the same control area on the channel, and thus, the all three gates have roughly the same effect on the device channel. Due to its special structure, the new device is logically equivalent to three conventional single-input transistors in parallel. Compared with the traditional field effect transistors with a single-input terminal, the new device can be used to simplify the circuit with the reduced transistor number. The impacts of body thickness, gate oxide thickness, and work function on device performance are investigated, and then the device optimizations are carried out. The current characteristic of the device is theoretically analyzed. Silvaco TCAD simulations show that the theoretical analysis agrees well with the TCAD simulation results. This work explores the feasibility of multi-input devices, which would facilitate its development.

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6

Yang, Maolong, Yao Lu, Qiancui Zhang, Zhao Han, Yichi Zhang, Maliang Liu, Ningning Zhang, Huiyong Hu, and Liming Wang. "Charge transport behaviors in a multi-gated WSe₂/MoS₂ heterojunction." Applied Physics Letters 121, no. 4 (July 25, 2022): 043501. http://dx.doi.org/10.1063/5.0097390.

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Heterojunctions and multi-gated structures facilitate the fabrication of high-performance and multifunctional transistors. Here, a WSe2/MoS2 heterojunction structure transistor with a back gate and two top gates is proposed. The back gate controls the carrier transport of the entire heterojunction channel, and the top gates independently control the carrier transports of MoS2 or WSe2 channels. The rectification direction of the heterojunction device could be reversed, and the rectification ratio could be modulated from 10−4 to 104 by changing the back-gate voltage. In addition, an evident negative-differential transconductance phenomenon with a current peak and a current valley are observed in the back-gate transfer characteristic curve, which results from the different control ability of the same gate voltage to the Fermi levels in MoS2 and WSe2. The current peak can be obviously modulated and eliminated by the MoS2 top gate, while the WSe2 top gate can control the position of the current valley from −8 to +12 V, which clearly supports the heterostructure energy band model. Moreover, the diversity of output states under multi-gate modulation makes applications in logic circuits possible. These results demonstrate the potential of this approach for the development of next-generation electronic functional devices.

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7

Chu, Shunan. "Comparative Analysis of Optimization Schemes of Carry Look-ahead Adder." Journal of Physics: Conference Series 2290, no. 1 (June 1, 2022): 012008. http://dx.doi.org/10.1088/1742-6596/2290/1/012008.

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Abstract Conventional CLA adder has has a large number of transistors and high input impedance, which affects various performance aspects, resulting in high delay and power consumption. Therefore, to increase the performance and reduce delay, several optimized structures of CLA are proposed. From the perspective of structure and power, this paper selects four different design schemes and uses Cadence Virtuoso 90nm technology to compare and analyze the optimization results in aspects of circuit area, delay and power consumption. The analysis results show that the conventional 4-bit adder structure can be improved by designing the carry term Field Effect Transistor (FET) network and replacing the existing gate circuit with a hybrid Gate diffusion technology (GDI) gate, which can reduce the number of transistors and the design circuit area. They also contribute to improving the power consumption, delay, power delay product (PDP) and other performance parameters. Pipeline technology and multi-layer CLA block technology are suitable for carry look-ahead adder with more bits and longer carry chain, which can shorten carry propagation time, further optimize processor performance and improve CPU computing efficiency.

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8

Kondo, Jun, Murali Lingalugari, Pik-Yiu Chan, Evan Heller, and Faquir Jain. "Modeling and Fabrication of Quantum Dot Channel Field Effect Transistors Incorporating Quantum Dot Gate." MRS Proceedings 1551 (2013): 149–54. http://dx.doi.org/10.1557/opl.2013.899.

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ABSTRACTQuantum dot gate (QDG) field-effect transistors (FET) have shown three-state transfer characteristics. Quantum dot channel (QDC) field-effect transistors (FET) have exhibited fourstate ID-VG characteristics. This project aims at studying the effect of incorporating cladded quantum dot layers in the gate region of QDC-FET. Four-state characteristics are explained by carrier transport in narrow energy mini-bands which are manifested in a quantum dot superlattice (QDSL) channel. QDSL is formed by an array of cladded quantum dots (such as SiOx-Si and GeOx-Ge). Multi-state FETs are needed in multi-valued logic (MVL) that can reduce the number of gates and transistors in digital circuits. The fabricated device showed the four-state characteristic (OFF, ‘I1’, ‘I2’, ON).

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9

Boampong, Amos Amoako, Jae-Hyeok Cho, Yoonseuk Choi, and Min-Hoi Kim. "Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure." Journal of Nanoscience and Nanotechnology 21, no. 3 (March 1, 2021): 1766–71. http://dx.doi.org/10.1166/jnn.2021.18923.

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We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO. The voltage applied to the counter bottom-gate electrode causes variations in the turn-on voltage position, which controlled the memory on- and off-current in retention characteristics. Specifically, due to the full depletion of semiconductor by the high negative counter gate bias, the memory off-current in reading operation is dramatically reduced by 104. The application of a high negative counter field to the dual-gate solution-processed ferroelectric memory gives a high memory on- and off-current ratio useful for the production of high performance multi-bit memory devices.

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10

Bhadra, Debabrata. "USING PERCOLATIVE CRYSTALLINE 0.3 CUO/PVDF NANOCOMPOSITE GATE DIELECTRIC FOR FABRICATING HIGH-EFFECT MOBILITY THIN FILM TRANSISTOR OPERATING AT LOW VOLTAGE." International Journal of Advanced Research 9, no. 11 (November 30, 2021): 1095–101. http://dx.doi.org/10.21474/ijar01/13846.

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Thin-film transistor (TFT) with various layers of crystalline Poly-vinylidene fluoride (PVDF)/CuO percolative nanocomposites based on Anthracene as a gate dielectric insulator have been fabricated. A device with excellent electrical characteristics at low operating voltages (<1V) has been designed. Different layers (L) of the film were also prepared to achieve the best optimization of ideal gate insulator with various static dielectric constants (Îµr). Capacitance density, leakage current at 1V gate voltage and electrical characteristics of OFETs with a single and multi layer films have been investigated. This device was showed highest field effect mobility of 2.27 cm2/Vs, a threshold voltage of -1.6V, an exceptionally low sub threshold slope of 380 mV/decade and an on/off ratio of 106. Such a High-Îµ three layered (3L) PVDF/CuO gate dielectric appears to be highly promising candidates for organic non-volatile memory, sensor and field-effect transistors (FETs).

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11

Mirdha, Pial, Murali Lingalugari, Evan K. Heller, John A. Chandy, and Faquir C. Jain. "Novel Multiplexer Design Using Multi-State Spatial Wavefunction-Switched (SWS) FETs." International Journal of High Speed Electronics and Systems 24, no. 03n04 (September 2015): 1520011. http://dx.doi.org/10.1142/s0129156415200116.

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In this paper, we propose a multiplexer design based on use of a twin channel and twin drain spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFET comprises of vertically stacked coupled quantum wells devices, which are the channels, where depending on the gate voltage only one of the channels is in conduction mode. Using SWSFET in multi-channel and single drain configuration operates as a multi-valued logic device. 2:1 and 4:2 multiplexer designs are proposed which are compatible with current CMOS technology and with all SWSFET. Both designs lead to greater than 4X reduction in transistor count. Ngspice simulation of circuits is also presented.

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12

Jeong, Moon-Young, Yoon-Ha Jeong, Sung-Woo Hwang, and Dae M. Kim. "Performance of Single-Electron Transistor Logic Composed of Multi-gate Single-Electron Transistors." Japanese Journal of Applied Physics 36, Part 1, No. 11 (November 15, 1997): 6706–10. http://dx.doi.org/10.1143/jjap.36.6706.

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13

Doucet, Jean-Christophe, Aimad Saib, Christian Mourad, François Piette, Etienne Vanzieleghem, and Pierre Delatte. "HADES®: a High-Temperature Isolated Gate Driver Solution for SiC-based Multi-kW Converters." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000145–51. http://dx.doi.org/10.4071/hiten-paper3-jcdoucet.

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This paper presents HADES® Gate Driver, a new solution that efficiently drives Silicon-Carbide (SiC) devices in multi-kW converters. It discusses how it allows taking full advantage of SiC technology by placing the gate driver circuits very close to the power transistors: The resulting lower parasitic inductances enable faster switching times and subsequently higher efficiency. Higher operating temperature for both the gate driver and the power transistors also translate into considerable reduction of complexity, size and weight of the system, in particular of the cooling systems. Finally, the paper describes how HADES® reference design is built from a new chipset especially developed for this purpose and designed to operate up to 225°C: THEMIS, ATLAS and RHEA.

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14

Wan, Haoji, Xianyun Liu, Xin Su, Xincheng Ren, Shengting Luo, and Qi Zhou. "Characteristics of a Novel FinFET with Multi-Enhanced Operation Gates (MEOG FinFET)." Applied Sciences 12, no. 21 (November 7, 2022): 11279. http://dx.doi.org/10.3390/app122111279.

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This study illustrates a type of novel device. Integrating fin field-effect transistors (FinFETs) with current silicon-on-insulator (SOI) wafers provides an excellent platform to fabricate advanced specific devices. An SOI FinFET device consists of three independent gates. By connecting the various gates, multiple working modes are obtained. Compared with traditional FinFETs, the multi-enhanced operation gate fin field-effect transistor in this study combines independent gates by connecting the selection modes; thus, a possible operation can be performed to attain a FinFET with five equivalent working states in only one device. This novel function can enable the device to work with multiple specific voltages and currents by connecting the corresponding gate combinations, augmenting the integrated degrees and shifting the working modes, thereby meeting the different needs of high-speed, low-power, and other potential applications. Further, the potential applications are highlighted.

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15

Qian, Chuan, Ling-an Kong, Junliang Yang, Yongli Gao, and Jia Sun. "Multi-gate organic neuron transistors for spatiotemporal information processing." Applied Physics Letters 110, no. 8 (February 20, 2017): 083302. http://dx.doi.org/10.1063/1.4977069.

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16

Zhu, Li Qiang, Hui Xiao, Yang Hui Liu, Chang Jin Wan, Yi Shi, and Qing Wan. "Multi-gate synergic modulation in laterally coupled synaptic transistors." Applied Physics Letters 107, no. 14 (October 5, 2015): 143502. http://dx.doi.org/10.1063/1.4932568.

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17

Colinge, Jean-Pierre, Dimitri Lederer, Aryan Afzalian, Ran Yan, Chi-Woo Lee, Nima Dehdashti Akhavan, and Weize Xiong. "Properties of Accumulation-Mode Multi-Gate Field-Effect Transistors." Japanese Journal of Applied Physics 48, no. 3 (March 23, 2009): 034502. http://dx.doi.org/10.1143/jjap.48.034502.

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18

Lin, Yu-Ru, Yi-Yun Yang, Yu-Husien Lin, Erry Dwi Kurniawan, Mu-Shih Yeh, Lun-Chun Chen, and Yug-Chun Wu. "Performance of Stacked Nanosheets Gate-All-Around and Multi-Gate Thin-Film-Transistors." IEEE Journal of the Electron Devices Society 6 (2018): 1187–91. http://dx.doi.org/10.1109/jeds.2018.2873008.

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19

Samuel, T. S. Arun, and M. Karthigai Pandian. "Comparative Performance Analysis of Multi Gate Tunnel Field Effect Transistors." Journal of Nano Research 41 (May 2016): 1–8. http://dx.doi.org/10.4028/www.scientific.net/jnanor.41.1.

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In this paper, analytical modelling and performance analysis of novel device structures such as single gate SOI Tunnel Field Effect transistor (SG SOI TFET), Dual-Material Gate TFET (DMG TFET) and Dual Material Double Gate TFET (DMDG TFET) are proposed. The performance of the three devices is studied and compared in terms of surface potential, electric field and drain current. The DMDG TFET shows better performance in suppressing leakage current and enhancing ION current than the SG SOI TFET and DMG TFET. The analytical models of the devices are found to be in good agreement with the results obtained using two-dimensional TCAD device simulator.

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20

Abdul Tahrim, ‘Aqilah binti, Huei Chaeng Chin, Cheng Siong Lim, and Michael Loong Peng Tan. "Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology." Journal of Nanomaterials 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/726175.

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The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.

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21

Maisurah Mohd Hassan, Siti, Yusman M. Yusof, Arjuna Marzuki, Nazif Emran Farid, Siti Amalina Enche Ab Rahim, and Mohd Hafis M. Ali. "RF characteristics of 0.13-μm NMOS transistors for millimeter-wave application." Microelectronics International 31, no. 2 (April 29, 2014): 116–20. http://dx.doi.org/10.1108/mi-09-2013-0044.

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Purpose – The purpose of this paper is to present the high-frequency performance of 0.13-μm n-type metal-oxide-semiconductor (NMOS) transistors with various multi-finger configurations for implementation in millimeter-wave (mm-wave) frequency. Design/methodology/approach – A folded-like double-gate transistor layout is designed to enable the transistor to work in the mm-wave region. Different sizes of transistors with variation in finger width (WF ) and number of fingers (NF ) were fabricated to determine the optimum size of the transistor. The extrinsic parasitic elements of selected transistors were extracted and investigated. The radio frequency (RF) performance of these samples were then analyzed and compared. Findings – The proposed layout performed well with the highest maximum oscillation frequency (fmax ) achieved at 122 GHz. Based on the comparison done, the optimum WF obtained for the layout is at 2.0 μm. It is found that the extrinsic parasitic capacitance is more dominant than the parasitic resistance in affecting the fmax . In s-parameter analysis, it is observed that the transistor with the least NF has smaller variance in small-signal gain throughout the measurement frequency. The maximum stable gain for the samples is also found to be roughly similar and independent of NF . Originality/value – A new layout structure for an NMOS transistor that works in mm-wave frequency is proposed. Experimental analyses presented here cover for both NF and WF , unlike others which focus on either NF or WF only.

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22

Kwon, Hyunah, Hocheon Yoo, Masahiro Nakano, Kazuo Takimiya, Jae-Joon Kim, and Jong Kyu Kim. "Gate-tunable gas sensing behaviors in air-stable ambipolar organic thin-film transistors." RSC Advances 10, no. 4 (2020): 1910–16. http://dx.doi.org/10.1039/c9ra09195e.

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23

Wessely, F., T. Krauss, and U. Schwalke. "CMOS without doping: Multi-gate silicon-nanowire field-effect-transistors." Solid-State Electronics 70 (April 2012): 33–38. http://dx.doi.org/10.1016/j.sse.2011.11.011.

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24

Erine, Catherine, Jun Ma, Giovanni Santoruvo, and Elison Matioli. "Multi-Channel AlGaN/GaN In-Plane-Gate Field-Effect Transistors." IEEE Electron Device Letters 41, no. 3 (March 2020): 321–24. http://dx.doi.org/10.1109/led.2020.2967458.

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25

Wang, Xiangjing, Li Zhu, Chunsheng Chen, Huiwu Mao, Yixin Zhu, Ying Zhu, Yang Yang, Changjin Wan, and Qing Wan. "Freestanding multi-gate IZO-based neuromorphic transistors on composite electrolyte membranes." Flexible and Printed Electronics 6, no. 4 (December 1, 2021): 044008. http://dx.doi.org/10.1088/2058-8585/ac4203.

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Abstract Brain-inspired neuromorphic computing would bring a breakthrough to the classical computing paradigm through its massive parallelism and potential low power consumption advantages. Introduction of flexibility may bring vitality to this area by expanding its application areas to such as wearable and implantable electronics. At present, the development of flexible neuromorphic devices makes it a choice with wide prospect for next-generation wearable artificial neuromorphic computing. In this study, a freestanding graphene oxide/polyvinyl alcohol composite solid electrolyte membrane is utilized as the gate dielectric and support material, and indium-zinc-oxide (IZO) neuromorphic transistors are fabricated on such membrane. Based on the in-plane gate modulation, many key synaptic plasticity behaviors have been successfully emulated, including excitatory postsynaptic current, paired-pulse facilitation, high-pass filtering, and spatiotemporal signal processing. Moreover, transition of the spiking logic and the superlinear and sublinear dendritic integration function are realized. Our results indicate that these freestanding IZO-based neuromorphic transistors may of great significance for future flexible anthropomorphic robots, wearable bionic perception.

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26

Yu, Ji-Man, Chungryeol Lee, Joon-Kyu Han, Seong-Joo Han, Geon-Beom Lee, Sung Gap Im, and Yang-Kyu Choi. "Multi-functional logic circuits composed of ultra-thin electrolyte-gated transistors with wafer-scale integration." Journal of Materials Chemistry C 9, no. 22 (2021): 7222–27. http://dx.doi.org/10.1039/d1tc01486b.

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Wafer-scale integration of electrolyte gated transistors is demonstrated by using iCVD. A solid-state pEGDMA was used as a gate electrolyte, and it configures multi-functional logic circuits, such as inverter, NAND, and NOR with high performance.

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Kondo, Jun, Pial Mirdha, Barath Parthasarathy, Pik-Yiu Chan, Bander Saman, Faquir Jain, and Evan Heller. "Modeling and Fabrication of GeOx-Ge Cladded Quantum Dot Channel (QDC) FETs on Poly-Silicon." International Journal of High Speed Electronics and Systems 27, no. 01n02 (March 2018): 1840005. http://dx.doi.org/10.1142/s0129156418400050.

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Quantum dot channel (QDC) and Quantum dot gate (QDG) field effect transistors (FETs) have been fabricated on crystalline Si using cladded Si and Ge quantum dots. This paper presents fabrication and modeling of quantum dot channel field effect transistors (QDC-FETs) using cladded Ge quantum dots on poly-Si thin films grown on silicon-on-insulator (SOI) substrates. HfAlO2 high-k dielectric layers are used for the gate dielectric. QDC-FETs exhibit multi-state I-V characteristics which enable two-bit processing, and reduce FET count and power dissipation. QDC-FETs using germanium quantum dots provide higher electron mobility than conventional poly-silicon FETs, and mobility values comparable to conventional FETs using single crystalline silicon.

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28

Kwon, Hyuk-Min, Dae-Hyun Kim, and Tae-Woo Kim. "Instability in In0.7Ga0.3As Quantum-Well MOSFETs with Single-Layer Al2O3 and Bi-Layer Al2O3/HfO2 Gate Stacks Caused by Charge Trapping under Positive Bias Temperature (PBT) Stress." Electronics 9, no. 12 (December 1, 2020): 2039. http://dx.doi.org/10.3390/electronics9122039.

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The instability of transistor characteristics caused by charge trapping under positive bias temperature (PBT) stress in In0.7Ga0.3As metal oxide semiconductor field-effect transistors (MOSFETs) with single-layer Al2O3 and bi-layer Al2O3/HfO2 gate stacks was investigated. The equivalent field across the multi-gate stacks was compared with a single layer used to compare the instability of electrical characteristics. The observed threshold voltage degradation (ΔVT) was consistent with the phenomenon of fast transient trapping of injected electrons at pre-existing shallow defects in the high-κ dielectric of HfO2, in which this charging was recovered by applying a relaxation voltage. Excluding the fast-transient charging components, the power law exponent (n), with respect to the time-dependent threshold voltage degradation, ranged from 0.3 to 0.35 for both single-layer Al2O3 and bi-layer Al2O3/HfO2 gate stacks. This long-term (slow) VT shift, which was strongly correlated with transconductance (Gm) degradation, was attributed to significant charge trapping in the border trap or/and defect sites within the high-κ dielectric.

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29

Wang, Ding, Ping Wang, Minming He, Jiangnan Liu, Shubham Mondal, Mingtao Hu, Danhao Wang, Yuanpeng Wu, Tao Ma, and Zetian Mi. "Fully epitaxial, monolithic ScAlN/AlGaN/GaN ferroelectric HEMT." Applied Physics Letters 122, no. 9 (February 27, 2023): 090601. http://dx.doi.org/10.1063/5.0143645.

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In this Letter, we demonstrated fully epitaxial ScAlN/AlGaN/GaN based ferroelectric high electron mobility transistors (HEMTs). Clean and atomically sharp heterostructure interfaces were obtained by utilizing molecular beam epitaxy. The fabricated ferroelectric gate HEMTs showed counterclockwise hysteretic transfer curves with a wide threshold voltage tuning range of 3.8 V, a large ON/OFF ratio of 3 × 107, and reconfigurable output characteristics depending on the poling conditions. The high quality ferroelectric gate stack and effective ferroelectric polarization coupling lead to improved subthreshold performance, with subthreshold swing values approaching 110 and 30 mV/dec under forward and backward gate sweeps, respectively. The results provide fundamental insight into the ferroelectric polarization coupling and threshold tuning processes in ferroelectric nitride heterostructures and are promising for nitride-based nonvolatile, multi-functional, reconfigurable power, and radio frequency devices as well as memory devices and negative capacitance transistors for next-generation electronics.

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30

Chang, P. C., K. H. Lee, Z. H. Wang, and S. J. Chang. "AlGaN/GaN High Electron Mobility Transistors with Multi-MgxNy/GaN Buffer." Journal of Nanomaterials 2014 (2014): 1–4. http://dx.doi.org/10.1155/2014/623043.

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We report the fabrication of AlGaN/GaN high electron mobility transistors with multi-MgxNy/GaN buffer. Compared with conventional HEMT devices with a low-temperature GaN buffer, smaller gate and source-drain leakage current could be achieved with this new buffer design. Consequently, the electron mobility was larger for the proposed device due to the reduction of defect density and the corresponding improvement of crystalline quality as result of using the multi-MgxNy/GaN buffer.

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Zhao, Yuhang, and Jie Jiang. "Recent Progress on Neuromorphic Synapse Electronics: From Emerging Materials, Devices, to Neural Networks." Journal of Nanoscience and Nanotechnology 18, no. 12 (December 1, 2018): 8003–15. http://dx.doi.org/10.1166/jnn.2018.16428.

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To realize intelligent functions in electronic devices like a human brain, it is important to develop the electronic devices that can imitate biological neurons and synapses (synaptic electronics). In this paper, we review the critical learning mechanisms for synaptic plasticity. Different electronic devices were developed to mimic biological synapses, such as atomic switch, phase change memory, ferroelectric memory, and electric-double-layer transistors. More importantly, several groups have realized the artificial neuromorphic network using multi-gate transistor architecture. The leap from synapse to neuron to neural network, thus, has been systematically realized using thin films and nanomaterials. The emerging synaptic electronics can have a broader applications and brighter future in the next-generation intelligent nano-electronics.

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Nagy, Daniel, Manuel Aldegunde, Muhammad A. Elmessary, Antonio J. García-Loureiro, Natalia Seoane, and Karol Kalna. "Modelling of nanoscale multi-gate transistors affected by atomistic interface roughness." Journal of Physics: Condensed Matter 30, no. 14 (March 15, 2018): 144006. http://dx.doi.org/10.1088/1361-648x/aab10f.

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Malik, Gul Faroz Ahmad, Mubashir Ahmad Kharadi, and Farooq Ahmad Khanday. "Electrically reconfigurable logic design using multi-gate spin Field Effect Transistors." Microelectronics Journal 90 (August 2019): 278–84. http://dx.doi.org/10.1016/j.mejo.2019.07.003.

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Deng, Guoqing, and Chunhong Chen. "Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 9 (September 2013): 1573–82. http://dx.doi.org/10.1109/tvlsi.2012.2217993.

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Liu, Kai, Yuan Liu, Yu-Rong Liu, Yun-Fei En, and Bin Li. "Comparative study of mobility extraction methods in p-type polycrystalline silicon thin film transistors." Modern Physics Letters B 31, no. 19-21 (July 27, 2017): 1740007. http://dx.doi.org/10.1142/s0217984917400073.

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Channel mobility in the p-type polycrystalline silicon thin film transistors (poly-Si TFTs) is extracted using Hoffman method, linear region transconductance method and multi-frequency C-V method. Due to the non-negligible errors when neglecting the dependence of gate-source voltage on the effective mobility, the extracted mobility results are overestimated using linear region transconductance method and Hoffman method, especially in the lower gate-source voltage region. By considering of the distribution of localized states in the band-gap, the frequency independent capacitance due to localized charges in the sub-gap states and due to channel free electron charges in the conduction band were extracted using multi-frequency C-V method. Therefore, channel mobility was extracted accurately based on the charge transport theory. In addition, the effect of electrical field dependent mobility degradation was also considered in the higher gate-source voltage region. In the end, the extracted mobility results in the poly-Si TFTs using these three methods are compared and analyzed.

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Yang, Hsin-Chia, Sung-Ching Chi, and Wen-Shiang Liao. "Comparison of Fitting Current–Voltage Characteristics Curves of FinFET Transistors with Various Fixed Parameters." Applied Sciences 12, no. 20 (October 18, 2022): 10519. http://dx.doi.org/10.3390/app122010519.

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In the deep submicron regime, FinFET successfully suppresses the leakage current using a 3D fin-like channel substrate, which gets depleted and blocks possible leakage as the gate is applied with a bias wholly wrapping the channel. Fortunately, a scanning photo-lithography using extensive ultraviolet (EUV) and multi-mask task carefully resolves critical dimension issues. The ensuing anisotropic plasma dry etching is somehow a subsequent challenging process, which consumes the edge of original ‘I’-shape epitaxial silicon and causes dimension loss, and thus produces fin-like bodies as prepared channels. In order to protect the transistors from malfunction due to dimension over-etching, fin width is taken to be 120 nanometers, while the channel lengths vary. The prepared transistors are measured and characteristic curves are fitted for analysis. Measured current versus voltage characteristic curves are fitted with three parameters (transistor geometry constant, threshold voltage, and Early voltage) in the conventional current-voltage formula , which are allowed to vary as the short channel effects or process-related issues are taken into account. In this paper, one of the three is deliberately set to be fixed for a transistor, and the others are freely chosen and determined to reach minimum variation. Various conclusions through comparisons and analysis may give important feasible applications in the future.

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Chatterjee, A., S. W. Aur, T. Niuya, P. Yang, and J. A. Seitchik. "Failure in CMOS circuits induced by hot carriers in multi-gate transistors." IEEE Electron Device Letters 9, no. 11 (November 1988): 564–66. http://dx.doi.org/10.1109/55.9277.

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Nitayama, A., F. Horiguchi, H. Takato, N. Okabe, K. Sunouchi, K. Hieda, and F. Masuoka. "High speed and compact CMOS circuits with multi-pillar surrounding gate transistors." IEEE Transactions on Electron Devices 36, no. 11 (November 1989): 2605–6. http://dx.doi.org/10.1109/16.43705.

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39

Jian, Jhang-Jie, Hsin-Ying Lee, Edward-Yi Chang, and Ching-Ting Lee. "Investigation of Multi-Mesa-Channel-Structured AlGaN/GaN MOSHEMTs with SiO2 Gate Oxide Layer." Coatings 11, no. 12 (December 3, 2021): 1494. http://dx.doi.org/10.3390/coatings11121494.

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In this study, an electron-beam lithography system was employed to pattern 80-nm-wide and 980-nm-spaced multi-mesa-channel for fabricating AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs). Since the structure of multi-mesa-channel could enhance gate control capabilities and reduce the self-heating effect in the channel, the performance of the MOSHEMTs could be obviously improved. The direct current performance metrics of the multi-mesa-channel-structured MOSHEMTs, such as a saturation drain-source current of 929 mA/mm, maximum extrinsic transconductance of 223 mS/mm, and on-resistance of 2.1 Ω-mm, were much better than those of the planar-structured MOSHEMTs. Moreover, the threshold voltage of the multi-mesa-channel-structured MOSHEMTs shifted toward positive voltage from −2.6 to −0.6 V, which was attributed to the better gate control capability. Moreover, the multi-mesa-channel-structured MOSHEMTs also had superior high-frequency and low-frequency noise performance. A low Hooge’s coefficient of 1.17 × 10−6 was obtained.

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Toral-Lopez, A., F. Pasadas, E. G. Marin, A. Medina-Rull, J. M. Gonzalez-Medina, F. G. Ruiz, D. Jiménez, and A. Godoy. "Multi-scale analysis of radio-frequency performance of 2D-material based field-effect transistors." Nanoscale Advances 3, no. 8 (2021): 2377–82. http://dx.doi.org/10.1039/d0na00953a.

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This multi-scale approach combines small-signal modeling with numerical simulations to study 2D-FETs. It is introduced in the context of performance protection of MoS₂ devices with different gate lengths and low contact resistances.

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Yang, Ling, Hao Lu, Xuerui Niu, Meng Zhang, Chunzhou Shi, Longge Deng, Bin Hou, et al. "Investigation of contact mechanism and gate electrostatic control in multi-channel AlGaN/GaN high electron mobility transistors with deep recessed ohmic contact." Journal of Applied Physics 132, no. 16 (October 28, 2022): 165703. http://dx.doi.org/10.1063/5.0106827.

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In this paper, the ohmic contact mechanism and gate electrostatic control of a deep-recessed ohmic contact structure for multi-channel Al0.3Ga0.7N/GaN high electron mobility transistors (HEMTs) is investigated. A transmission electron microscope and an energy dispersive spectrum are utilized to investigate the ohmic contact interface mechanism. Due to a reduction of source/drain parasitic resistances and simultaneous connection of five channels by using deep-recessed ohmic contact, a large maximum drain current density and a distinct five hump feature of ultra-wider trans-conductance are achieved. More importantly, it is revealed that the downward expansion of the gate potential for the deep-recessed ohmic contact structure is much deeper than that for conventional devices. This characteristic leads to a remarkable reduction in subthreshold swing (SS) and off-state leakage, indicating an ultra-wide and high trans-conductance profile. The fabricated devices show a lower off-state drain leakage, a lower SS, and a wider gate voltage swing (40 V). Due to an enhancement of gate electrostatic control, the current collapse and electrical reliability characteristics of multi-channel Al0.3Ga0.7N/GaN HEMTs with deep-recessed ohmic contact also improve. The results presented here indicate that the multi-channel device has great potential for high current and wide bandwidth applications.

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Sehgal, Amit, Tina Mangla, Mridula Gupta, and R. S. Gupta. "Multi-material gate poly-crystalline thin film transistors: Modeling and simulation for an improved gate transport efficiency." Thin Solid Films 516, no. 8 (February 2008): 2162–70. http://dx.doi.org/10.1016/j.tsf.2007.06.119.

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43

Liu, Bo-Ying, Gao-Sheng Wang, Ming-Lang Tseng, Zhi-Gang Li, and Kuo-Jui Wu. "New Energy Empowerment Using Kernel Principal Component Analysis in Insulated Gate Bipolar Transistors Module Monitoring." Sustainability 10, no. 10 (October 11, 2018): 3644. http://dx.doi.org/10.3390/su10103644.

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At present, energy exhausted and environmental pollution are important issues, vigorously promoting new energy and improving the utilization efficiency and management level of new energy is an important way to achieve sustainable social development. Insulated gate bipolar transistors are important components in power converters and are widely used in new energy generation, new energy vehicles, high-speed rail and industrial production. However, the power module’s age is related to all aspects of its performance change, precluding the use of a single parameter to fully and accurately express the aging state. To monitor this state and evaluate the aging state, this study presents a method to analyze and process the state data of Insulated gate bipolar transistors power module aging tests using kernel principal component analysis and establishes a multi-dimensional grey model to evaluate the power module aging state. Using the temperature cycle aging test platform, the 7000 temperature cycling tests are implemented to accelerate the age of the power module to failure, the dynamic parameters of the power modules are measured after every 1000 cycles. During the accelerated aging process, the case temperature change rate, collector-emitter voltage drop Vce(SAT) and Miller platform of the gate signal of Vge are found to exhibit different variation trends at different aging stages. The result showed that multiple parameters are combined into integrated attributes to enable more accurate implementation of the state monitoring of power modules using the proposed method, which improves the status monitoring level of Insulated gate bipolar transistors modules. The proposed method is beneficial to improve the utilization efficiency and new energy source management level.

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Kushwah, Preeti, Saurabh Khandelwal, and Shyam Akashe. "Multi-Threshold Voltage CMOS Design for Low-Power Half Adder Circuit." International Journal of Nanoscience 14, no. 05n06 (October 2015): 1550022. http://dx.doi.org/10.1142/s0219581x15500222.

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The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than conventional half adder. In CMOS technology, transistors used have small area and low power consumption. It is used in various applications like adder, subtract or, multiplexer, ALU and microprocessors digital VLSI systems. As the scaling technology reduces, the leakage power increases. In this paper, multi threshold complementary metal oxide semiconductor (MTCMOS) technique is proposed to reduce the leakage current and leakage power. MTCMOS is an effective circuit level technique that increases the performance of a cell by using both low- and high-threshold voltage transistors. Leakage current is reduced by 85.37% and leakage power is reduced by 87.45% using MTCMOS technique as compared to standard CMOS technique. The half adder design simulation work was performed by cadence simulation tool at 45-nm technology.

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Opoku, C., K. F. Hoettges, M. P. Hughes, V. Stolojan, S. R. P. Silva, and M. Shkunov. "Solution processable multi-channel ZnO nanowire field-effect transistors with organic gate dielectric." Nanotechnology 24, no. 40 (September 12, 2013): 405203. http://dx.doi.org/10.1088/0957-4484/24/40/405203.

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Cho, Kyungjune, Tae-Young Kim, Woanseo Park, Juhun Park, Dongku Kim, Jingon Jang, Hyunhak Jeong, Seunghun Hong, and Takhee Lee. "Gate-bias stress-dependent photoconductive characteristics of multi-layer MoS2 field-effect transistors." Nanotechnology 25, no. 15 (March 18, 2014): 155201. http://dx.doi.org/10.1088/0957-4484/25/15/155201.

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Park, Mingyo, and Byung-Wook Min. "X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors." Solid-State Electronics 141 (March 2018): 69–73. http://dx.doi.org/10.1016/j.sse.2017.12.009.

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48

Conde, J., I. Mejia, F. S. Aguirre-Tostado, C. Young, and M. A. Quevedo-Lopez. "Design considerations for II–VI multi-gate transistors: the case of cadmium sulfide." Semiconductor Science and Technology 29, no. 4 (February 20, 2014): 045006. http://dx.doi.org/10.1088/0268-1242/29/4/045006.

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49

Lima, Vitor Gonçalves, Guilherme Paim, Rodrigo Wuerdig, Leandro Mateus Giacomini Rocha, Leomar Da Rosa Júnior, Felipe Marques, Vinicius Valduga, Eduardo Costa, Rafael Soares, and Sergio Bampi. "Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing." Journal of Integrated Circuits and Systems 15, no. 1 (May 26, 2020): 1–11. http://dx.doi.org/10.29292/jics.v15i1.100.

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Differential power analysis (DPA) exploits the difference between the instantaneous power of the circuit arches transitions to stole the state as information aiming to unveil the cryptographic key. Secure triple track logic (STTL) is a circuit-level countermeasure to DPA attacks based on dual-rail precharge logic (DPL). STTL is robust to attacks due to the delay in an insensitive feature that mitigates the logic glitches generated by the different path delays that lead to the logic gate inputs until they stabilize. The main STTL drawback, however, is the asymmetry of the transistor topology. Asymmetry causes unbalanced internal capacitances and different internal paths for the current flow, and DPA exploits it as a source of information leakage. Our work proposes three circuit topologies, combining multi-Vt transistors with a circuit counterbalancing strategy, aiming to improve the STTL DPA attack-resistance. Data encryption standard substitution-box circuit, designed in a TSMC 40 nm CMOS process, is our application case study to evaluate the DPA attack-resistance. Results gathered at the application-level show that our proposals outperform DPA attack-resistance of the prior work.

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Tsai, Meng-Ju, Kang-Hui Peng, Chong-Jhe Sun, Siao-Cheng Yan, Chieng-Chung Hsu, Yu-Ru Lin, Yu-Hsien Lin, and Yung-Chun Wu. "Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors." IEEE Journal of the Electron Devices Society 7 (2019): 1133–39. http://dx.doi.org/10.1109/jeds.2019.2952150.

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