Dissertations / Theses on the topic 'Multi-Gate Transistors'

L’escalat dels transistors MOSFET convencionals ha portat a aquests dispositius a la nanoescala per incrementar tant les seves prestacions com el nombre de components per xip. En aquest process d’escalat, els coneguts “Short Channel Effects” representen una forta limitació. La forma més efectiva de suprimir aquests efectes i aixi estendre l’ús del MOSFET convencional, és la reducció del gruix de l’òxid de porta i l’augment de la concentració de dopants al canal. Quan el gruix d’òxid de porta es redueix a unes quantes capes atòmiques, apareix l’efecte túnel mecano-quàntic d’electrons, produint un gran augment en els corrents de fuita, perjudicant la normal operació dels MOSFETs. Això ha fet obligatori l’ús de materials d’alta permitivitat o materials high-κ en els dielèctrics de porta. Tot i les solucions proposades, la reducció de les dimensiones físiques del MOSFET convencional no pot ser mantinguda de forma indefinida i per mantenir la tendència tecnològica s’han suggerit noves estructures com ara MOSFETs multi-porta de cos ultra-prim. En particular, el MOSFET de doble porta és considerat com una estructura multi-porta prometedora per les seves diverses qualitats i avantatges en l’escalat. Aquesta tesi s’enfoca en la modelització de dispositius MOSFET de doble porta i, en particular, en la modelització del corrent túnel de porta que afecta críticamente al consum de potència del transistor. Primerament desenvolupem un model quàntic compacte tant per al potencial electrostàtic com per a la càrrega elèctrica en el transistor de doble-porta simètric amb cos no dopat. Després, aquest model quàntic s’utilitza per proposar un model analític compacte per al corrent túnel directe amb SiO2 com dielèctric de porta, primerament, i després amb una doble capa composta de SiO2 com a capa interfacial i un material “high-κ”. Finalment se desenvolupa un mètode precís per calcular el corrent túnel de porta. El mètode es basa en l’aplicació de condicions de frontera absorbents i, més especificament, en el mètode PML. Aquesta tesi està motivada per les recomanacions fetes pel “International Technology Roadmap of Semiconductors” (ITRS) sobre la necessitat existent de modelatge i simulació d’estructures semiconductores multi-porta.
The scaling of the conventional MOSFETs has led these devices to the nanoscale to increase both the performance and the number of components per chip. In this process, the so-called “Short Channel Effects” have arisen as a limiting factor. To extend the use of the bulk MOSFETs, the most effective ways of suppressing such effects are the reduction of the gate oxide thickness and increasing of the channel doping concentration. When the gate oxide thickness is reduced to a few atomic layers, quantum mechanical tunneling is responsible of a huge increase in the gate leakage current impairing the normal operation of MOSFETs. This has made mandatory the use of high permittivity materials or high-κ as gate dielectrics. Despite the proposed solutions, reduction of the physical dimensions of the conventional MOSFETs cannot be maintained. To keep the technological trend, new MOSFET structures have been suggested such as ultra-thin body Multi-Gate MOSFETs. In particular, the Double-Gate MOSFETs is considered as a promising MG structure for its several qualities and advantages in scaling. This thesis focuses on the modeling of Double-Gate MOSFET and, in particular, on the modeling of the gate leakage current critically affecting the power consumption. First we develop a compact quantum model for both the electrostatic potential and the electric charge in symmetric double-gate MOSFET with undoped thin body. Then, this quantum model is used to propose an analytical compact model for the direct tunnelling current with SiO2 as gate dielectric, firstly, and later assuming a dual layer consisting of a SiO2 interfacial layer and a high-κ material. Finally, an accurate method for the calculation of the gate tunnelling current is developed. It is based on Absorbing Boundary Conditions techniques and, more specifically, on the Perfectly Mached Layer (PML) method. This thesis is motivated by the recommendations given by the “International Technology Roadmap of Semiconductors” (ITRS) about the need for the modeling and simulation of multi-gate semiconductor structures.

As the formation of nearly abrupt p-n junctions in aggressively scaled transistors has become a complex task, a novel type of device in which there are no junctions has recently been suggested (J. P. Colinge et al., Nature 2010). The device of interest is referred to as the junctionless transistor, and it has demonstrated excellent functionality, with the advantage of a simpler fabrication process than conventional FETs. Despite the remarkable performances exhibited by the junctionless transistor, this device has to be tested against variability before it may be produced in large scale. Hence, the study of how the fluctuations in the number and in the position of the dopant atoms affects a large number of devices has been developed in this work. Such variability source is referred to as Random Dopant Fluctuations (RDF) and it is among the most critical ones for conventional MOSFETs. Our view is that RDF ought to largely affect the junctionless transistors. Hence, in this work we mainly aim at investigating the impact of RDF in these type of devices. Firstly, we provide a detailed analysis on the performance of an ideal junctionless transistor with a uniform non-random doping concentration, by mean of simulations developed using a TCAD software. Secondly, we investigate the effects of RDF in the junctionless transistor, as the principal aim of our study. Here, we determine how the I-V characteristics are affected by the random dopants and we illustrate fundamental the causes of the variations. A first estimation of the impact of RDF is provided by the illustration of the threshold voltage and beta [1] distributions, and by the computation of the fundamental statistical quantities relating to the two parameters. A further and last estimation is provided by the comparison obtained studying RDF on the inversion mode FET.

La diminution de la taille des transistors actuellement utilisés en microélectronique ainsi que l’augmentation de leurs performances demeure encore au centre de toutes les attentions. Cette thèse propose d’étudier et de fabriquer des transistors à base de nanofils empilés. Cette architecture avec des grilles enrobantes est l’ultime solution pour concentrer toujours plus de courant électrique dans un encombrement minimal. Les simulations ont par ailleurs révélé le potentiel des nanofeuillets de silicium qui permettent à la fois d’optimiser l’espace occupé tout en proposant des performances supérieures aux dispositifs actuels. L’importance de l’ajout de certaines étapes de fabrication a également été soulignée. En ce sens, deux séries d’étapes de fabrication ont été proposées : la première option vise à minimiser le nombre de variations par rapport à ce qui est aujourd’hui en production tandis que la deuxième alternative offre potentiellement de meilleures performances au prix de développements plus importants. Les transistors ainsi fabriqués proposent des performances prometteuses supérieures à ce qui a pu être fabriqué dans le passé notamment grâce à l’introduction de contraintes mécaniques importantes favorables au transport du courant électrique
The future of the transistors currently used in Microelectronics is still uncertain: shrinking these devices while increasing their performances always remains a challenge. In this thesis, stacked nanowire transistors are studied, fabricated and optimized. This architecture embeds gate all around which is the ultimate solution for concentrating always more current within a smaller device. Simulations have shown that silicon nanosheets provide an optimal utilization of the space with providing increased performances over the other technologies. Crucial process steps have also been identified. Subsequently, two process flows have been suggested for the fabrication of SNWFETs. The first approach consists in minimizing the number of variations from processes already in mass production. The second alternative has potentially better performances but its development is more challenging. Finally, the fabricated transistors have shown improved performances over state-of-the-art especially due to mechanical stress induced for improving electric transport

Ce travail de thèse étudie de nouvelles configurations d'alimentation de commande rapprochée et un nouveau concept de packaging afin d'améliorer les performances des MOSFETs SiC connectés en série. Les nouvelles configurations de commande rapprochée sont proposées afin de réduire les courants de bruit qui circulent dans la partie commande du système électrique. De plus, une nouvelle alimentation de commande de grille est proposée pour augmenter le dv / dt de la cellule de commutation. Ces améliorations, c'est-à-dire la réduction du courant de bruit et l'amplification du dv/dt, sont obtenues en modifiant l'impédance des circuits de commande de grille. Le nouveau concept de packaging est proposé afin d'améliorer les performances d’équilibrage de tension. Les nouvelles configurations de commande rapprochée et les concepts de packaging sont introduits et analysés grâce à des modèles analytique et des simulations. Ensuite, des essayes expérimentales sont effectuées pour confirmer que les concepts proposés sont meilleurs que les concepts traditionnels en termes d'équilibrage de tension, de vitesse de commutation et de réduction EMI conduite
This work investigates new gate drive power supply configurations and a novel multi-steppackaging concept in order to improve the performance of series-connected SiC-MOSFETs. The new gate drive configurations are proposed in order to reduce noise currents that circulate in the control part of the electrical system. Furthermore, a new gate drive power supply is proposed to increase the dv/dt of the switching cell. These improvements, i.e., noise current reduction and dv/dt boosting, are achieved by modifying the impedance of the gate drive circuitry. The novel multi-step packaging concept is proposed in order to improve the voltage sharing performance. The proposed package geometry considers optimal dielectric isolation for each device leading to a multi-step geometry. It has a significant impact on the parasitic capacitances introduced by the packaging structure that are responsible for voltageunbalances. The new gate driver configurations and the proposed multi-step packaging concepts are introduced and analysed thanks to equivalent models and time domain simulations. Then, experimental set-ups are performed to confirm that the proposed concepts are better than traditional ones in terms of voltage balancing, switching speed and conducted EMI reduction

Afin de dépasser la limite d'échelle, il existe une solution innovante qui permet de fabriquer des structures multi-grilles. Ainsi, un NMOSFET composé de trois grilles indépendantes fabriquées dans la technologie CMOS. En dehors de leur forme, géométrique, le transistor multi-grille est similaire à une structure classique. Une multi-grille NMOSFET peut être fabriquée par l'intégration de tranchées de polysilicium. Ces tranchées sont utilisées dans diverses applications telles que les mémoires DRAM, électronique de puissance ou de capteurs d'image. Les capteurs d'image présentent le problème des charges parasites entre les pixels, appelées diaphonie. Les tranchées sont l'une des solutions qui réduisent ce phénomène. Ces tranchées assurent l'isolation électrique sur toute la matrice des pixels. Nous avons étudié ses caractéristiques en utilisant des mesures I-V, méthode du split C-V et de pompage de charge à deux et à trois niveaux. Son multi-seuil caractéristique a été vérifié. Nous n'avons observé aucune dégradation significative de ces caractéristiques grâce à l'intégration des tranchées. La structure a été simulée par la méthode des éléments finis en 3D via le logiciel TCAD. Ses caractéristiques électriques ont été simulées et confrontées avec les résultats obtenus à partir de mesures électriques. La tension de seuil et la longueur de canal effective ont été extraites. Sa mobilité effective et les pièges de l'interface Si/SiO2 ont également été simulés ou calculés. En raison des performances électriques satisfaisantes et d'un bon rendement, nous avons remarqué que ce dispositif est une solution adéquate pour les applications analogiques grâce aux niveaux de tension multi-seuil
One of the recent solutions to overcome the scaling limit issue are multi-gate structures. One cost-effective approach is a three-independent-gate NMOSFET fabricated in a standard bulk CMOS process. Apart from their shape, which takes advantage of the three-dimensional space, multi gate transistors are similar to the conventional one. A multi-gate NMOSFET in bulk CMOS process can be fabricated by integration of polysilicon-filled trenches. This trenches are variety of the applications for instance in DRAM memories, power electronics and in image sensors. The image sensors suffer from the parasitic charges between the pixels, called crosstalk. The polysilicon - filled trenches are one of the solution to reduce this phenomenon. These trenches ensure the electrical insulation on the whole matrix pixels. We have investigated its characteristics using l-V measurements, C-V split method and both two- and three-level charge pumping techniques. Tts tunable-threshold and multi-threshold features were verified. Tts surface- channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. We observed no significant degradation of these characteristics due to integration of polysilicon-filled trenches in the CMOS process. The structure has been simulated by using 3D TCAD tool. Tts electrical characteristics has been evaluated and compared with results obtained from electrical measurements. The threshold voltage and the effective channel length were extracted. Tts surface-channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. Owing to the good electrical performances and cost-effective production, we noticed that this device is a good aspirant for analog applications thanks to the multi-threshold voltages

Silicon Nanowires (SiNWs) are considered the fundamental component blocks of future nanoelectronics. Many interesting properties have gained them such a prominent position in the investigation in recent decades. Large surface-to-volume ratio, bio-compatibility, band-gap tuning are among the most appealing features of SiNWs. More importantly, in the ongoing process of dimension miniaturization, SiNWs compatibility with the existing and reliable silicon technology stands as a fundamental advantage. Consequently, the employment of SiNWs spred in several application fields: from computational logic where SiNWs are used to realize transistors, to bio-chemical sensing and nanophotonic applications. In this thesis work we concentrate our attention on the employment of SiNWs in computational logic and bio-chemical sensing. In particular, we aim at giving a contribution in the modelling and simulation of SiNW-based electron devices. Given the current intense investigation of new devices, the modelling of their electrical behaviour is strongly required. On one side, modelling procedures could give an insight on the physical phenomena of transport in nanometer scale systems where quantum effects are dominant. On the other side, the availability of compact models for actual devices can be of undeniable help in the future design process. This work is divided into two parts. After a brief introduction on Silicon Nanowires, the main fabrication techniques and their properties, the first part is dedicated to the modelling of Multiple-Independent Gate Transistors, a new generation of devices arisen from the composition of Gate-All-Around Transistors, finFETs and Double-Gate Transistors. Interesting applications resulting from their employment are Vertically-stacked Silicon Nanowire FETs, known to have an ambipolar behaviour, and Silicon Nanowire Arrays. We will present a compact numerical model for composite Multiple-Independent Gate Transistors which allows to compute current and voltages in complex structures. Validation of the model through simulation proves the accuracy and the computational efficiency of the resulting model. The second part of the thesis work is instead devoted to Silicon Nanowires for bio-chemical sensing. In this respect, major attention is given to Porous Silicon (PS), a non-crystalline material which demonstrated peculiar features apt for sensing. Given its not regular microscopic morphology made of a complex network of crystalline and non-crystalline regions, PS has large surface-to-volume ratio and a relevant chemical reactivity at room temperature. In this work we start from the fabrication of PS nanowires at Istituto Nazionale di Ricerca Metrologica in Torino (I.N.Ri.M.) to devise two main models for PSNWs which can be used to understand the effects of porosity on electron transport in these structures. The two modelling procedures have different validity regimes and efficiently take into account quantum effects. Their description and results are presented. The last part of the thesis is devoted to the impact of surface interaction of molecular compounds and dielectric materials on the transport properties of SiNWs. Knowing how molecules interact with silicon atoms and how the conductance of the wire is affected is indeed the core of SiNWs used for bio-chemical sensing. In order to study the phenomena involved, we performed ab-initio simulations of silicon surface interacting with SO2 and NO2 via the SIESTA package, implementing DFT code. The calculations were performed at Institut de Ciencia De Materials de Barcelona (ICMAB-CSIC) using their computational resources. The results of this simulation step are then exploited to perform simulation of systems made of an enormous quantity of atoms. Due to their large dimensions, atomistic simulations are not affordable and other approaches are necessary. Consequently, calculations with physics-based softwares on a larger spatial scale were adopted. The description of the obtained results occupies the last part of the work together with the discussion of the main theoretical insight gained with the conducted study.

Die kontinuierliche Skalierung der planaren MOSFETs war in den vergangenen 40 Jahren der Schlüssel, um die Bauelemente immer kleiner und leistungsfähiger zu gestalten. Hinzu kamen Techniken zur mechanischen Verspannung, Verfahren zur Kurzzeitausheilung, die in-situ-dotierte Epitaxie und neue Materialien, wie das High-k-Gateoxid in Verbindung mit Titannitrid als Gatemetall. Jedoch erschwerten Kurzkanaleffekte und eine zunehmende Streuung der elektrischen Eigenschaften die Verkleinerung der planaren Transistoren erheblich. Somit gelangten die planaren MOSFETs mit der aktuellen 28 nm-Technologie teilweise an die Grenzen ihrer Funktionalität. Diese Arbeit beschäftigt sich daher mit der Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie, welche eine bessere Steuerfähigkeit des Gatekontaktes aufweisen und somit die Fortführung der Skalierung ermöglichen. Zudem standen die Anforderungen eines stabilen und kostengünstigen Herstellungsprozesses als Grundvoraussetzung zur Übernahme in die Volumenproduktion stets mit im Vordergrund. Die Simulationen der Tri-Gate-Transistoren stellten dabei den ersten Schritt hin zu einer Multi-Gate-Technologie dar. Ihre Prozessabfolge unterscheidet sich von den planaren Transistoren nur durch die Formierung der Finnen und bietet damit die Möglichkeit eines hybriden 22 nm-Prozesses. Am Beispiel der Tri-Gate-Transistoren wurden zudem die Auswirkungen der Kristallorientierung, der mechanischen Verspannung und der Überlagerungseffekte es elektrischen Feldes auf die Leistungsfähigkeit von Multi-Gate-Strukturen analysiert. Im nächsten Schritt wurden Transistoren mit vollständig verarmten Kanalgebieten untersucht. Sie weisen aufgrund einer niedrigen Kanaldotierung eine Volumeninversion, eine höhere Ladungsträgerbeweglichkeit und eine geringere Anfälligkeit gegenüber der zufälligen Dotierungsfluktuation auf, welche für leistungsfähige Multi-Gate-Transistoren entscheidende Kriterien sind. Zu den betrachteten Varianten zählen die planaren ultradünnen SOI-MOSFETs, die klassischen FinFETs mit schmalen hohen Finnen und die vertikalen Nanowire-Transistoren. Anschließend wurden die Vor- und Nachteile der verschiedenen Transistorstrukturen für eine mittel- bis langfristige industrielle Nutzung betrachtet. Dazu erfolgte eine Analyse der statistischen Schwankungen und eine Skalierung hin zur 14 nm-Technologie. Eine Zusammenfassung aller Ergebnisse und ein Ausblick auf die mögliche Übernahme der Konzepte in die Volumenproduktion schließen die Arbeit ab
Within the past 40 years the continuous scaling of planar MOSFETs was key to shrink the devices and to improve their performance. Techniques like mechanical stressing, rapid thermal annealing and in-situ doped epitaxial growing as well as novel materials, such as high-k-gate-oxide in combination with titanium nitride as metal-gate, has been introduced. However, short-channel-effects and increased scattering of electrical proper-ties significantly complicate the scaling of planar transistors. Thus, the planar MOSFETs gradually reached their limits of functionality with the current 28 nm technology node. For that reason, this work focuses on integration of multi-gate transistors based on a 22 nm technology, which show an improved gate control and allow a continuous scaling. Furthermore, the requirements of a stable and cost-efficient process as decisive condition for mass fabrication were always taken into account. The simulations of the tri-gate transistors present the first step toward a multi-gate technology. The process sequence differs from the planar one solely by a fin formation and offers the possibility of a hybrid 22 nm process. Also, the impact of crystal orientation, mechanical stress and superposition of electrical fields on the efficiency of multi-gate structures were analyzed for the tri-gate transistors. In a second step transistors with fully depleted channel regions were studied. Due to low channel doping they are showing a volume inversion, a higher carrier mobility and a lower sensitivity to random doping fluctuations, which are essential criteria for powerful multi-gate transistors. Reviewed structure variants include planar ultra-thin-body-SOI-MOSFETs, classic FinFETs with a tall, narrow fins and vertical nanowire transistors. Then advantages and disadvantages of the considered transistor structures have been observed for a medium to long term industrial use. For this purpose, an analysis of statistical fluctuations and the scaling-down to 14 nm technology was carried out. A summary of all results and an outlook to the transfer of concepts into mass fabrication complete this work

Ce travail concerne les transistors bipolaires à hétérogène TBH SiGe. En particulier, l'auto-échauffement des transistors unitaires et le couplage thermique avec leurs plus proches voisins périphériques sont caractérisés et modélisés. La rétroaction électrothermique intra- et inter-transistor est largement étudiée. En outre, l’impact des effets thermiques sur la performance de deux circuits analogiques est évalué. L'effet d'autoéchauffement est évalué par des mesures à basse fréquence et des mesures impulsionnelles DC et AC. L'auto-échauffement est diminué de manière significative en utilisant des petites largeurs d'impulsion. Ainsi la dépendance fréquentielle de l’autoéchauffementa été étudiée en utilisant les paramètres H et Y. De nouvelles structures de test ont été fabriqués pour mesurer l'effet de couplage. Les facteurs de couplage thermique ont été extraits à partir de mesures ainsi que par simulations thermiques 3D. Les résultats montrent que le couplage des dispositifs intra est très prononcé. Un nouvel élément du modèle de résistance thermique récursive ainsi que le modèle de couplage thermique a été inclus dans un simulateur de circuit commercial. Une simulation transitoire entièrement couplée d'un oscillateur en anneau de 218 transistors a été effectuée. Ainsi, un retard de porte record de 1.65ps est démontré. À la connaissance des auteurs, c'est le résultat le plus rapide pour une technologie bipolaire. Le rendement thermique d'un amplificateur de puissance à 60GHz réalisé avec un réseau multi-transistor ou avec un transistor à plusieurs doigts est évalué. La performance électrique du transistor multidoigt est dégradée en raison de l'effet de couplage thermique important entre les doigts de l'émetteur. Un bon accord est constaté entre les mesures et les simulations des circuits en utilisant des modèles de transistors avec le réseau de couplage thermique. Enfin, les perspectives sur l'utilisation des résultats sont données
The power generate by modern silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) can produce large thermal gradients across the silicon substrate. The device opering temperature modifies model parameters and can significantly affect circuit operation. This work characterizes and models self-heating and thermal coupling in SiGe HBTs. The self-heating effect is evaluated with low frequency and pulsed measurements. A novel pulse measurement system is presented that allows isothermal DC and RF measurements with 100ns pulses. Electrothermal intra- and inter-device feedback is extensively studied and the impact on the performance of two analog circuits is evaluated. Novel test structures are designed and fabricated to measure thermal coupling between single transistors (inter-device) as well as between the emitter stripes of a multi-finger transistor (intra-device). Thermal coupling factors are extracted from measurements and from 3D thermal simulations. Thermally coupled simulations of a ring oscillator (RO) with 218 transistors and of a 60GHz power amplifier (PA) are carried out. Current mode logic (CML) ROs are designed and measured. Layout optimizations lead to record gate delay of 1.65ps. The thermal performance of a 60GHz power amplifier is compared when realized with a multi-transistor array (MTA) and with a multi-finger trasistor (MFT). Finally, perspectives of this work within a CAD based circuit design environment are discussed

Les capteurs d'images CMOS ont connu au cours des six dernières années une réduction de la taille des pixels d'un facteur quatre. Néanmoins, cette miniaturisation se heurte à la diminution rapide du signal maximal de chaque pixel et à l'échange parasite entre pixels (diaphotie). C'est dans ce contexte qu'a été développé le Pixel à Tranchées Profondes Capacitives et Grille de Transfert verticale (pixel CDTI+VTG). Basé sur la structure d'un pixel « 4T », il intègre une isolation électrique par tranchées, une photodiode profonde plus volumineuse et une grille verticale permettant le stockage profond et le transfert des électrons. Des procédés de fabrication permettant cette intégration spécifique ont tout d'abord été développés. Parallèlement, une étude détaillée des transistors du pixel, également isolés par CDTI a été menée. Ces tranchées capacitives d'isolation actionnées en tant que grilles supplémentaires ouvrent de nombreuses applications pour un transistor multi-grille compatible avec un substrat massif. Un démonstrateur de 3MPixels intégrant des pixels d'une taille de 1.75*1.75 μm² a été réalisé dans une technologie CMOS 120 nm. Les performances de ce capteur ont pu être déterminées, en particulier en fonction de la tension appliquée aux CDTI. Un bas niveau de courant d'obscurité a tout particulièrement été obtenu grâce à la polarisation électrostatique des tranchées d'isolation
CMOS image sensors showed in the last few years a dramatic reduction of pixel pitch. However pitch shrinking is increasingly facing crosstalk and reduction of pixel signal, and new architectures are now needed to overcome those limitations. Our pixel with Capacitive Deep Trench Isolation and Vertical Transfer Gate (CDTI+VTG) has been developed in this context. Innovative integration of polysilicon-filled deep trenches allows high-quality pixel isolation, vertically extended photodiode and deep vertical transfer ability. First, specific process steps have been developed. In parallel, a thorough study of pixel MOS transistors has been carried out. We showed that capacitive trenches can be also operated as extra lateral gates, which opens promising applications for a multi-gate transistor compatible with CMOS-bulk technology. Finally, a 3MPixel demonstrator integrating 1.75*1.75 μm² pixels has been realized in a CMOS 120 nm technology. Pixel performances could be measured and exploited. In particular, a low dark current level could be obtained thanks to electrostatic effect of capacitive isolation trenches

abstract: Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate field-effect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation. In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and SGFET are developed. Despite the complex device structure and boundary conditions for the Poisson-Boltzmann equation, the core structure of the DG-FinFET and SGFET models, are maintained similar to the surface potential based compact models for planar MOSFETs such as SP and PSP. TCAD simulations show differences between the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This effect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the Poisson-Boltzmann equation. An accurate implicit input voltage equation valid in all regions of operation is proposed for common-gate symmetric DG-FinFETs with intrinsic or lightly doped bodies. A closed-form algorithm is developed for solving the new input voltage equation including ambipolar effects. The algorithm is verified for both the surface potential and its derivatives and includes a previously published analytical approximation for surface potential as a special case when ambipolar effects can be neglected. The symmetric linearization method for common-gate symmetric DG-FinFETs is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFETs. The accuracy of the proposed technique is verified by comparison with exact results. An alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson-Boltzmann equation for the independent-gate asymmetric DG-FinFET is developed in terms of the Lambert W function. Efficient numerical algorithm is proposed for solving the input voltage equation. Analytical expressions for terminal charges of an independent-gate asymmetric DG-FinFET are derived. The new charge model is C-infinity continuous, valid for weak as well as for strong inversion condition of both the channels and does not involve the charge-sheet approximation. This is accomplished by developing the symmetric linearization method in a form that does not require identical boundary conditions at the two Si-SiO2 interfaces and allows for volume inversion in the DG-FinFET. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The model is implemented in a standard circuit simulator through Verilog-A code. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric DG-FinFETs.
Dissertation/Thesis
Ph.D. Electrical Engineering 2012

Silicon nanowire based multiple gate metal oxide field effect transistors(MG-MOSFET) appear as replacements for conventional bulk transistors in post 45nm technology nodes. In such transistors the short channel effect(SCE) is controlled by the device geometry, and hence an undoped (or, lightly doped) ultra-thin body silicon nanowire is used to sustain the channel. The use of undoped body also solves several issues in bulk MOSFETs e.g., random dopant fluctuations, mobility degradation and compatibility with midgap metal gates. The electrostatic integrity of such devices increases with the scaling down of the body thickness. Since the quantization of electron energy cannot be ignored in such ultra-thin body devices, it is extremely important to consider quantum effects in their threshold voltage models. Most of the models reported so far are valid for long channel double gate devices. Only Munteanu et al. [Journal of non-crystalline solids vol 351 pp 1911-1918 2005] have reported threshold voltage model for short channel symmetric double gate MOSFET, however it involves unphysical fitting parameters. Only Munteanu et al.[Molecular simulation vol 31 pp 839-845 2005] reported threshold voltage model for quad gate transistor which is implicit in nature. On the other hand no modeling work has been reported for other types of MG-MOSFETs (e.g., tri gate, cylindrical body)apart from numerical simulation results. In this work we report physically based closed form quantum threshold voltage models for short channel symmetric double gate, quad gate and cylindrical body gate-all-around MOSFETs. In these devices quantum effects aries mainly due to the structural confinement of electron energy. Proposed models are based on the analytical solution of two or three-dimensional Poisson equation and one or two-dimensional Schrodinger equation depending on the device geometries. Judicial approximations have been taken to simplify the models in order to make them closed form and efficient for large scale circuit simulation. Effort has also been put to model the quantum threshold voltage of tri gate MOSFET. However it is found that the energy quantization in tri gate devices are mainly due to electronic confinement and hence it is very difficult to develop closed form analytical equations for the threshold voltage. Thus in this work the modeling of tri gate devices have been limited to long channel cases. All the models are validated against the professional numerical simulator.

Undoped body multi gate (MG) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are appearing as replacements for single gate bulk MOSFET in forthcoming sub-45nm technology nodes. It is therefore extremely necessary to develop compact models for MG transistors in order to use them in nano-scale integrated circuit design and simulation. There is however a sharp distinction between the electrostatics of traditional bulk transistors and undoped body devices. In bulk transistor, where the substrate is sufficiently doped, the inversion charges are located close to the surface and hence the surface potential solely controls the electrostatic integrity of the device. However, in undoped body devices, gate electric field penetrates the body center, and inversion charge exists throughout the body. In contrast to the bulk transistors, depending on device geometry, the potential of the body center of undoped body devices could be higher than the surface in weak inversion regime and the current flows through the center-part of the device instead of surface. Several crucial parameters (e.g. Sub-threshold slope) sometimes become more dependable on the potential of body center rather than the surface. Hence the body-center potential should also be modeled correctly along with the surface-potential for accurate calculation of inversion charge, threshold voltage and other related parameters of undoped body multi-gate transistors. Although several potential models for MG transistors have been proposed to capture the short channel behavior in the subthreshold regime but most of them are based on the crucial approximation of coverting the 2D Poisson’s equation into Laplace equation. This approximation holds good only at surface but breaks down at body center and in the moderate inversion regime. As a result all the previous models fail to capture the potential of body center Correctly and remain valid only in weak-inversion regime. In this work we have developed semiclassical compact models for potential distribution for double gate (DG) and cylindrical Gate-All-Around (GAA) transistors. The models are based on the analytical solution of 2D Poisson’s equation in the channel region and valid for both: a) weak and strong inversion regimes, b) long channel and short channel transistors, and, c) body surface and center. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body thicknesses pass through a single common point (termed as crossover point). Using the concept of “crossover point” the effect of body thickness on the threshold voltage of undoped body multi-gate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. Some other parameters e.g. inversion charge, threshold voltage roll-off etc are also studied to demonstrate the impact of body center potential on the electrostatics of multi gate transistor. All the models are validated against professional numerical device simulator.

碩士
國立交通大學
電子工程學系 電子研究所
103
In this thesis, we presented electrical characteristics of trapezoidal shaped channel for the junctionless (JL) bulk and silicon-on-insulator (SOI) FinFET are numerically explored by using 3D quantum-corrected device simulation. The dependence of device performances, including subthreshold slope, drain-induced barrier lowering, off-current and threshold voltage roll-off, on the various fin angle and fin height are investigated. The JL bulk FinFET exhibits excellent short channel characteristics, gate controllability over trapezoidal shaped channel and less sensitivity of the fin angle to electrical performances by reducing effective channel thickness that is caused by the channel/ substrate junction. Hence, the JL bulk FinFET is highly recommended in sub-10-nm nodes. Additionally, this work demonstrates for the first time the fabrication of a proposed hybrid P/N poly-Si channel junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structure. The novel hybrid P/N JL-TFTs showed excellent electrical performances in terms of a steep subthreshold swing of 64mV/dec, a high Ion/Ioff current ratio (>107), a low drain-induced barrier lowering value of 3 mV/V, small series resistance and temperature stability were investigated, indicating greater gate electrostatic controllability and less current crowding than in conventional JL-TFTs. Furthermore, simulated results and a quantum model physical model were discussed initially but not detailed enough for future work support experimental data. Hence, the proposed hybrid P/N JL-TFT is highly promising for future further sub-10-nm scaling and 3D stacked ICs applications.

碩士
國立清華大學
工程與系統科學系
105
In recreant years, the electronic products pursue not only the higher speed and better performance, but also less power consumption and lower cost. The Semiconductor ICs manufacturing companies still follow Moore's law to scaling. In addition to processing technology feasibility limits, it is important to develop a target that suffices high performance and scalability. Information processing technology is driving the semiconductor into a broadening spectrum of new applications according to 2015 ITRS 2.0 report. A significant part of the research to further improve device performance is presently concentrated on III-V materials and Ge. These materials promise higher mobility than Si devices. The combination of 3D device architecture and low power device will usher the Era of Scaling, identified in short as “3D Power Scaling”. In order to increase transistor density for continuing Moore’s law, we implement the stacked nanosheert (NS) vertically inversion-mode field-effect-transistors(VM-FET) in 3D stacked integrated circuit (IC) applications. This research which focus on is showing the following: (1) device process, (2).basic device characteristics analysis, (3) device simulation. There are three kinds device structure. The first one is stacked Fin-FET, The second is stacked Gate all around VM-FET, The third is p-Channel Silicon/Germanium Quantum Well Multi-Gate Field-Effect-Transistor, we adopt the oxidation trimming method to form thin active layer and exhibit quasi-crystal channel due to the reduction of grain boundaries and defects. It is beneficial for excellent electrical performance. In the basic device characteristics analysis. First part will show the comparison of stacked Fin-FET and conventional stacked planar Fin-FET. The stacked Fin-FET exhibits the better performance. After that comparison of stacked Fin-FET and stacked GAA-FET. The stacked GAA-FET achieves lowing subthreshold swing (S.S.) and Off current. Second part will discuss about the change of width dimension for I-V characteristics with stacked structure. However, in the device simulation, we use Sentaurus TCAD to analyze and confirm the measured basic electrical characteristics. In our proposed the stacked NS VM-FET has better electrical characteristics. Moreover, it may provide a probable next-generation CMOS device solution and be utilized in advanced 3D stacked IC applications.

碩士
國立聯合大學
電子工程學系碩士班
106
With the continuous miniaturization of electronic components in the semiconductor companies, in addition to processing technology feasibility limits, it is important to develop a target that suffices high performance and scalability. Conventional inversion-mode Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) face a lot of challenges such as Short channel effects (SCEs), device process technologies, and physical limits in the scaling process. JL-FET is a novel device, which has heavily doping channel with the same type to that of source and drain. Therefore, JL-FET has a slight SCEs and less thermal budget in process of fabrication. In this thesis, we succeed demonstrated the double stacked nanosheet (NS) channels with multi-gate junctionless field effect transistors (MG-JLFET) applied in the future three-dimensional stacked integrated circuit , which includes the component process and the analysis of the electrical characteristics. There are two kinds device structure. The first one is double stacked nanosheet channels with multi-gate junctionless field effect transistors, the second is double stacked nanosheet channels with gate all around junctionless field effect transistors (GAA-JLFET). In the stacked device, we adopt the oxidation trimmed method to form thin active layer and exhibit quasi-crystal channel due to the reduction of grain boundaries and defects. In the basic device characteristics analysis. First part will compare MG JL-FET used different etch methods when definite the contact window, increased on current due to increased metal contact area and reduced Total Resistance, it has better electrical characteristics. The second part compares GAA-JLFET, because the use of GAA process, the transistor has better gate control, and discuss about the change of width dimension for electrical characteristics with stacked structure. In our proposed the stacked JL-FET has better electrical characteristics. Moreover, it may provide a probable next-generation CMOS device solution and be utilized in advanced 3D stacked IC applications.

碩士
國立清華大學
工程與系統科學系
100
As electronic products with each passing day, IC design must be toward the high density development to meet market demand, the size of the components themselves must also be constantly scaling to respond. However, conventional transistors because of structural problems led to encounter considerable difficulties in miniature on the SCE (Short Channel Effect) and random dopant fluctuation. In this study adopted a novel junctionless structure, the characteristics of such a structure, channel and source and drain of the same doping type, doping concentration is also quite, so the channel to the source electrode and the channel to the drain electrode have no junctions. And it has no Charge Sharing Effect in scaling, because there is no junction to avoid short-channel effect. And doped with the same type, a considerable concentration, the doping process will be easy. There have no energy level difference between gate to channel so that can be avoided DIBL (Drain Induce Barrier Lowing) effect. However, the off state characteristic of junctionless transistor depend on the energy level difference between gate to channel, therefore to shut down the junctionless transistor is not an easy thing, so in this study adopted the multi gate to improve the gate control ability. That achieved better subthreshold characteristics in the off state, and more suitable for scaling, to become the next generation of mainstream transistor.

碩士
華梵大學
電子工程學系碩士班
107
The power loss has always been a problem that humans continue to explore, especially in this high-performance era. In which how to reduce the power loss of electronic products is an important issue. Improving power loss on power devices is a common goal for developers. In recent years, a new structure, called "Split-Gate Metal Oxide Semiconductor Field Effect Transistor (Split-Gate MOSFET)", has been developed, which power loss has been improved, and can be operated in high frequency environments. In this thesis, SILVACO simulation software was used to simulate a 100-volt Split-Gate MOSFET and to study its characteristics. The Split-Gate MOSFETs were optimized by simulation for the purpose of reducing their on-resistance. First the size of the Split-Gate MOSFET was scaled. The purpose is to reduce the specific on-resistance (Ron,sp). Finally, we changed the structure of the device and proposed the Multi-Split-Gate MOSFET including 2 Split-Gate, 4 Split-Gate and 6 Split-Gate. The characteristics of 4 Split-Gate is better than others. Therefore, this structure had been further optimized for the miniature size finally. After a series optimization, compared with 2.5 um cell pitch Split-Gate, Ron,sp had reduced about 55% for new structure with 2.0 um cell pitch and 4 Split-Gate in this paper.

博士
國立交通大學
電子工程學系 電子研究所
102
In this work, we comprehensively study the physics, device operation, and applications of the multi-gate junctionless (JL) metal-oxide-semiconductor field- effect-transistor (MOSFET). In the first part of this work, we discuss the physics difference between JL transistors and conventional inversion-mode (IM) multi-gate transistors. The bulk conduction of the current in JL transistors has been addressed by the band-diagram and distributions of carrier density. Such conduction mechanism prevents the carrier mobility suffering from high field degradation and surface scattering, but shows a weak dependence on the gate bias. In JL transistor, since the dominating scattering mechanism is the impurity scattering due to heavily doped channel is used, the temperature dependency of the drain current is differ from IM transistor, the zero temperature coefficient point is not observed. Owing to the doping concentration gradient between source/drain and channel is zero, the depletion charge is control by the gate alone, the effective channel length is larger than gate length when JL transistor is turned off, resulting in the better short channel effect control and smaller total gate capacitance due to the reduction of gate to source/drain overlap capacitance. The JL transistor usually operate at flat-band condition when device is turned on, the total gate capacitance is smaller than that in IM transistor, but it also obtain a larger variation with the change of temperature. In the second part of this work, we compare the performance of JL transistor with bulk and silicon-on-insulator (SOI) substrate and study their advantages and limitations. In JL bulk transistor, the carriers concentrate on the top side of the channel due to the channel/substrate junction reduces the effective channel thickness. Such phenomenon improves the control of short channel effect but degrades the on-current simultaneously, and results in a better output conductance but a worse transconductance than those of JL SOI transistor. The JL bulk transistor performs less sensitivity to the device process variation, and provides an additional design parameter, substrate doping concentration, to tune the device performance. For analog and radio frequency characteristics, JL bulk transistor shows worse performance than in JL SOI transistor because of the parasitic substrate capacitance. The JL SOI transistors performs a shorter delay time, a smaller power consumption, and a larger static noise margin than those of the JL bulk transistor in the analysis of inverter and static random access memory (SRAM) circuits, and the JL SOI SRAM can operate at a very low supply voltage, which is benefit to the digital circuit application. In the last part of this work, we successfully fabricate a JL thin-film-transistor (TFT) with 2nm-thick channel; the measurement results demonstrate a 108 on/off current and a 61mV/dec subthrshold swing and are robust to process variation. We also measure the breakdown voltage of such device and compare it to IM TFT and laterally-diffused-metal-oxide-semiconductor (LDMOS). Our JL TFT obtains much higher breakdown voltage because the electric field in the device is uniformly distributed liked a resistor, indicating the potential of high-voltage application.

碩士
中原大學
醫學工程研究所
91
Abstract The concentrations of potassium and sodium ion in blood can response the condition of kidney. In addition, acidosis is an important factor in the setting of myocardial ischemia. The inhibition of potassium ion current was decreased during acidosis. Therefore, the concentrations of potassium and sodium ion are the index of health and an significant parameter in clinical diagnosis In this study, the extended-gate field effect transistor (EGFET), with was the SnO2/ITO glass structure, was applied to fabricate the potassium and sodium ion selective electrodes. The valinomycin and Bis[(12-crown-4) methyl]dodecyl- methylmalonate(B12C4) with two kinds of polymer (polyurethane and PVC) based on the EGFET were used for potassium and sodium ion selective electrodes. The polyurethane (Hydro-aliphatic urethane diacrylate,EB2001) membrane can improve the valinomycin and B12C4 to detect the potassium and sodium ions and its selectivity was about 40~50 mV/decade. Then , the potentiometric selectivity coefficient of SnO2 potassium and sodium electrodes will be obtained.

碩士
中華大學
電機工程學系碩士班
101
To improve the performance of complementary metal-oxide-semiconductor (CMOS) devices, it is necessary to use a pair of metals with work functions that are near the conduction-band and valence-band edges of silicon to replace conventional n+/p+ poly-Si gate materials. According to ITRS, metal gate can evade high sheet resistance and poly depletion effect as compared with conventional poly-Si gate. Gate-last process has been adopted to eliminate work function shift, which occurs from the band-edge to the mid-gap, and high-k dielectric degradation after high temperature thermal process for dopant activation in source/drain (S/D) regions. However, these complex processes lead to restrictions on circuit design and process window. If gate-first process efficiently suppresses work function shift of metal gate electrodes and decreases equivalent oxide thickness (EOT) of gate dielectrics after dopant activation process, it will become a ponderable and promising candidate to simplify and reduce cost of nowadays CMOS fabrication process. The first part in this thesis investigated the dopant activation process by means of microwave annealing (MWA) and rapid thermal annealing (RTA) respectively. The results of experiments demonstrated suppressed diffusion profile of dopant which activated by MWA in comparison with conventional RTA process. The second and the third parts in this thesis compared MOSFETs with different gate stacks, which comprised TiN/HfO2/Si and TiN/TaN/HfO2/Si, proceeded post-deposition annealing (PDA) and post-metallization annealing (PMA) by MWA and RTA respectively. The results revealed the devices with post-treatment by MWA were possessed of lower interface trap density (Dit) and thinner EOT. The analysis by transmission electron microscopy (TEM) further explained the variation of EOT. The fourth part in this thesis demonstrated the electrical characteristics of MOSFETs after thermal process proceeded by MWA and RTA respectively. The result turned out that MWA was beneficial for suppressing short channel effect (SCE) in nanoscale MOSFETs. In contrast with MWA process, conventional RTA activated devices performed worse short-channel behavior due to inherent high temperature thermal process.

Die kontinuierliche Skalierung der planaren MOSFETs war in den vergangenen 40 Jahren der Schlüssel, um die Bauelemente immer kleiner und leistungsfähiger zu gestalten. Hinzu kamen Techniken zur mechanischen Verspannung, Verfahren zur Kurzzeitausheilung, die in-situ-dotierte Epitaxie und neue Materialien, wie das High-k-Gateoxid in Verbindung mit Titannitrid als Gatemetall. Jedoch erschwerten Kurzkanaleffekte und eine zunehmende Streuung der elektrischen Eigenschaften die Verkleinerung der planaren Transistoren erheblich. Somit gelangten die planaren MOSFETs mit der aktuellen 28 nm-Technologie teilweise an die Grenzen ihrer Funktionalität. Diese Arbeit beschäftigt sich daher mit der Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie, welche eine bessere Steuerfähigkeit des Gatekontaktes aufweisen und somit die Fortführung der Skalierung ermöglichen. Zudem standen die Anforderungen eines stabilen und kostengünstigen Herstellungsprozesses als Grundvoraussetzung zur Übernahme in die Volumenproduktion stets mit im Vordergrund. Die Simulationen der Tri-Gate-Transistoren stellten dabei den ersten Schritt hin zu einer Multi-Gate-Technologie dar. Ihre Prozessabfolge unterscheidet sich von den planaren Transistoren nur durch die Formierung der Finnen und bietet damit die Möglichkeit eines hybriden 22 nm-Prozesses. Am Beispiel der Tri-Gate-Transistoren wurden zudem die Auswirkungen der Kristallorientierung, der mechanischen Verspannung und der Überlagerungseffekte es elektrischen Feldes auf die Leistungsfähigkeit von Multi-Gate-Strukturen analysiert. Im nächsten Schritt wurden Transistoren mit vollständig verarmten Kanalgebieten untersucht. Sie weisen aufgrund einer niedrigen Kanaldotierung eine Volumeninversion, eine höhere Ladungsträgerbeweglichkeit und eine geringere Anfälligkeit gegenüber der zufälligen Dotierungsfluktuation auf, welche für leistungsfähige Multi-Gate-Transistoren entscheidende Kriterien sind. Zu den betrachteten Varianten zählen die planaren ultradünnen SOI-MOSFETs, die klassischen FinFETs mit schmalen hohen Finnen und die vertikalen Nanowire-Transistoren. Anschließend wurden die Vor- und Nachteile der verschiedenen Transistorstrukturen für eine mittel- bis langfristige industrielle Nutzung betrachtet. Dazu erfolgte eine Analyse der statistischen Schwankungen und eine Skalierung hin zur 14 nm-Technologie. Eine Zusammenfassung aller Ergebnisse und ein Ausblick auf die mögliche Übernahme der Konzepte in die Volumenproduktion schließen die Arbeit ab.:Symbol- und Abkürzungsverzeichnis 1 Einleitung 2 Grundlagen und Entwicklung der CMOS-Technologie 2.1 Planare Transistoren 2.1.1 Theoretische Grundlagen von MOSFETs 2.1.2 Skalierung und Kurzkanalverhalten planarer Transistoren 2.1.3 Mechanische Verspannung von Silizium 2.1.4 Techniken zur mechanischen Verspannung 2.2 Multi-Gate-Transistoren 2.2.1 Multi-Gate-Strukturen 2.2.2 Überlagerungseffekte 2.2.3 Quanteneffekte 2.3 Stand der Technik 3 Grundlagen der Simulation 3.1 Prozesssimulation 3.1.1 Abscheiden und Abtragen von Schichten 3.1.2 Implantation 3.1.3 Thermische Ausheilung mit Diffusion 3.2 Bauelementesimulation 3.2.1 Grundgleichungen und Ladungsträgertransport 3.2.2 Bandlückenverengung 3.2.3 Generation und Rekombination 3.2.4 Ladungsträgerbeweglichkeit 3.2.5 Effekte der mechanischen Verspannung 3.2.6 Ladungsträgerquantisierung 3.3 Kalibrierung der Modellparameter 3.3.1 Prozessparameter 3.3.2 Modellparameter 4 Planare Transistoren auf Basis einer 22 nm-Technologie 4.1 Transistoraufbau 4.1.1 Replacement-Gate-Prozess 4.1.2 In-situ-dotierte Source-Drain-Gebiete 4.1.3 Haloimplantation 4.1.4 Elemente der mechanischen Verspannung 4.2 Charakterisierung des elektrischen Verhaltens 4.2.1 Stationäres Verhalten 4.2.2 Gatesteuerung und Kurzkanaleffekte 4.2.3 Dynamisches Verhalten 5 Tri-Gate-Transistoren 5.1 Prozessintegration und Transistoraufbau 5.1.1 Anforderungen an hochintegrierte Schaltkreise 5.1.2 Hybride CMOS-Technologie 5.1.3 Strukturierung der Finne 5.1.4 Geometrieabhängiges Dotierungsprofil 5.2 Charakterisierung des elektrischen Verhaltens 5.2.1 Stationäres Verhalten 5.2.2 Kurzkanaleffekte und Gatesteuerung 5.2.3 Eckeneffekt 5.2.4 Eckenimplantation 5.2.5 Finnengeometrie 5.2.6 Dynamisches Verhalten 5.3 Optimierung der Tri-Gate-Struktur 5.3.1 Gestaltung der epitaktischen Source-Drain-Gebiete 5.3.2 Mechanisch verspanntes Isolationsoxid 5.3.3 Substratorientierung 6 Transistoren mit vollständig verarmtem Kanal 6.1 Ultra-Dünne-SOI-MOSFETs 6.1.1 Prozessintegration 6.1.2 Charakterisierung des elektrischen Verhaltens 6.2 FinFETs 6.2.1 Prozessintegration 6.2.2 Charakterisierung des elektrischen Verhaltens 6.3 Vertikale Nanowire-MOSFETs 6.3.1 Prozessintegration 6.3.2 Strukturierung des Aktivgebiets 6.3.3 Charakterisierung des elektrischen Verhaltens 6.3.4 Asymmetrisches Dotierungsprofil 6.3.5 Mechanische Verspannung 7 Skalierung und statistische Schwankungen der Strukturen 7.1 Skalierung zur 14 nm-Technologie 7.1.1 Leistungsfähigkeit 7.1.2 Kurzkanalverhalten und Steuerfähigkeit 7.2 Statistische Schwankungen 7.2.1 Impedanz-Feld-Methode 7.2.2 Zufällige Dotierungsfluktuation 7.2.3 Fixe Ladungen im Oxid 7.2.4 Metall-Gate-Granularität 7.2.5 Geometrische Variationen 7.2.6 Kombination der Störquellen 8 Zusammenfassung und Ausblick Anhang Literaturverzeichnis Danksagung Acknowledgement
Within the past 40 years the continuous scaling of planar MOSFETs was key to shrink the devices and to improve their performance. Techniques like mechanical stressing, rapid thermal annealing and in-situ doped epitaxial growing as well as novel materials, such as high-k-gate-oxide in combination with titanium nitride as metal-gate, has been introduced. However, short-channel-effects and increased scattering of electrical proper-ties significantly complicate the scaling of planar transistors. Thus, the planar MOSFETs gradually reached their limits of functionality with the current 28 nm technology node. For that reason, this work focuses on integration of multi-gate transistors based on a 22 nm technology, which show an improved gate control and allow a continuous scaling. Furthermore, the requirements of a stable and cost-efficient process as decisive condition for mass fabrication were always taken into account. The simulations of the tri-gate transistors present the first step toward a multi-gate technology. The process sequence differs from the planar one solely by a fin formation and offers the possibility of a hybrid 22 nm process. Also, the impact of crystal orientation, mechanical stress and superposition of electrical fields on the efficiency of multi-gate structures were analyzed for the tri-gate transistors. In a second step transistors with fully depleted channel regions were studied. Due to low channel doping they are showing a volume inversion, a higher carrier mobility and a lower sensitivity to random doping fluctuations, which are essential criteria for powerful multi-gate transistors. Reviewed structure variants include planar ultra-thin-body-SOI-MOSFETs, classic FinFETs with a tall, narrow fins and vertical nanowire transistors. Then advantages and disadvantages of the considered transistor structures have been observed for a medium to long term industrial use. For this purpose, an analysis of statistical fluctuations and the scaling-down to 14 nm technology was carried out. A summary of all results and an outlook to the transfer of concepts into mass fabrication complete this work.:Symbol- und Abkürzungsverzeichnis 1 Einleitung 2 Grundlagen und Entwicklung der CMOS-Technologie 2.1 Planare Transistoren 2.1.1 Theoretische Grundlagen von MOSFETs 2.1.2 Skalierung und Kurzkanalverhalten planarer Transistoren 2.1.3 Mechanische Verspannung von Silizium 2.1.4 Techniken zur mechanischen Verspannung 2.2 Multi-Gate-Transistoren 2.2.1 Multi-Gate-Strukturen 2.2.2 Überlagerungseffekte 2.2.3 Quanteneffekte 2.3 Stand der Technik 3 Grundlagen der Simulation 3.1 Prozesssimulation 3.1.1 Abscheiden und Abtragen von Schichten 3.1.2 Implantation 3.1.3 Thermische Ausheilung mit Diffusion 3.2 Bauelementesimulation 3.2.1 Grundgleichungen und Ladungsträgertransport 3.2.2 Bandlückenverengung 3.2.3 Generation und Rekombination 3.2.4 Ladungsträgerbeweglichkeit 3.2.5 Effekte der mechanischen Verspannung 3.2.6 Ladungsträgerquantisierung 3.3 Kalibrierung der Modellparameter 3.3.1 Prozessparameter 3.3.2 Modellparameter 4 Planare Transistoren auf Basis einer 22 nm-Technologie 4.1 Transistoraufbau 4.1.1 Replacement-Gate-Prozess 4.1.2 In-situ-dotierte Source-Drain-Gebiete 4.1.3 Haloimplantation 4.1.4 Elemente der mechanischen Verspannung 4.2 Charakterisierung des elektrischen Verhaltens 4.2.1 Stationäres Verhalten 4.2.2 Gatesteuerung und Kurzkanaleffekte 4.2.3 Dynamisches Verhalten 5 Tri-Gate-Transistoren 5.1 Prozessintegration und Transistoraufbau 5.1.1 Anforderungen an hochintegrierte Schaltkreise 5.1.2 Hybride CMOS-Technologie 5.1.3 Strukturierung der Finne 5.1.4 Geometrieabhängiges Dotierungsprofil 5.2 Charakterisierung des elektrischen Verhaltens 5.2.1 Stationäres Verhalten 5.2.2 Kurzkanaleffekte und Gatesteuerung 5.2.3 Eckeneffekt 5.2.4 Eckenimplantation 5.2.5 Finnengeometrie 5.2.6 Dynamisches Verhalten 5.3 Optimierung der Tri-Gate-Struktur 5.3.1 Gestaltung der epitaktischen Source-Drain-Gebiete 5.3.2 Mechanisch verspanntes Isolationsoxid 5.3.3 Substratorientierung 6 Transistoren mit vollständig verarmtem Kanal 6.1 Ultra-Dünne-SOI-MOSFETs 6.1.1 Prozessintegration 6.1.2 Charakterisierung des elektrischen Verhaltens 6.2 FinFETs 6.2.1 Prozessintegration 6.2.2 Charakterisierung des elektrischen Verhaltens 6.3 Vertikale Nanowire-MOSFETs 6.3.1 Prozessintegration 6.3.2 Strukturierung des Aktivgebiets 6.3.3 Charakterisierung des elektrischen Verhaltens 6.3.4 Asymmetrisches Dotierungsprofil 6.3.5 Mechanische Verspannung 7 Skalierung und statistische Schwankungen der Strukturen 7.1 Skalierung zur 14 nm-Technologie 7.1.1 Leistungsfähigkeit 7.1.2 Kurzkanalverhalten und Steuerfähigkeit 7.2 Statistische Schwankungen 7.2.1 Impedanz-Feld-Methode 7.2.2 Zufällige Dotierungsfluktuation 7.2.3 Fixe Ladungen im Oxid 7.2.4 Metall-Gate-Granularität 7.2.5 Geometrische Variationen 7.2.6 Kombination der Störquellen 8 Zusammenfassung und Ausblick Anhang Literaturverzeichnis Danksagung Acknowledgement

碩士
國立中山大學
電機工程學系研究所
103
In this thesis, we propose two novel capacitorless 1T-DRAMs, with the multi-gate and nano-pillar structures : The first type is a double-gate Nanowire TFT, with the fin-gate and pillar-body structure (FGPB). The second type is a vertical current bridge MOSFET, with the gate-all-around and nano-pillar structure (GAANP). We adopt the GIDL mechanism as 1T-DRAM programming method, and use the Sentaurus TCAD 12.0 simulation tool to confirm the memory performance. Compared with the conv. DG-NTFT, the FGPB device has nano-pillar structure, which can increase the pseudo neutral region without additional occupied area. This structure can improve the band-to-band tunneling, and keep the holes away from the P-N junction. The GIDL current is improved about 274.33 %. With fin-gate to control the excess hole efficiently, this structure can also overcome the SRH recombination influence indirectly. In terms of the low-power application, and the power consumption can maintained below 0.8 μW/μm. Compared with the lateral current bridge 1T-DRAMs, the GAANP SOI/Bulk-Silicon device has surrounding gate, which can enhance the excess hole control-ability; the vertical channel not only keeps the device in long-channel, but also maintains at a certain level of memory performance. In terms of the current bridge devices benchmark comparison, the GAANP SOI 1T-DRAM PW is improved at least about 238.54 %. The RT at 358 K is improved about 6.91 %. Two novel devices not only achieve low-power consumption, but also have sufficient operating endurance and disturbance immunity. We provide two excellent candidates for future 1T-DRAM applications.

To enable the advancement of Si based technology, necessary to increase computing power and the manufacture of more compact circuits, significant changes to the current MOS multi-gate transistor device are a necessity. Novel transistor architectures and materials are currently being researched vigorously. This thesis, on the electrical characterisation of multigate transistors displays detailed insight into the carrier transport and resulting performance limiting mechanisms. The results are composed of many parts. The impact of variations of the gate length, gate dielectric material, fin parameter, gate work function, doping concentration, and temperature on device characteristics are studied using ATLAS Silvaco device simulator. Simulation results for various gate lengths are reported and analyzed. As the quantum effects are pronounced in nanoscale devices, we have included these effects in our study and simulation. We have then compared the achieved results to classical simulations to assess their performance limits. Finally, a comparison of our results with recently published data is presented to confirm our study.

碩士
國立交通大學
電子工程系所
93
I have studied the effects of NH3 plasma passivation on the electrical characteristics of pattern-dependent metal-induced lateral crystallization (PDMILC) polysilicon thin-film transistors (poly-Si TFTs). These transistors have various numbers of multiple channels. PDMILC TFTs with NH3 plasma passivation outperform those without such passivation. This is because of the effective hydrogen passivation of the grain-boundary dangling bonds, and the pile-up of nitrogen at the SiO2/poly-Si interface. Additionally, the performance of such devices improves as the number of multi-channels increase. In particular, the electrical characteristics of a nano-scale TFT with ten 67 nm-wide split channels (M10) are superior to other TFTs. For example, the M10 TFT has a higher field effect mobility of 84.63 cm2/Vs, a higher ON/OFF current ratio (>106), a steeper subthreshold slope (SS) of 230 mV/decade, an absence of drain-induced barrier lowering (DIBL) and favorable output characteristics. We have found that the active channels of the M10 TFT have exhibit for the best NH3 plasma passivation, due to its split nanowire channels structure. We have also studied for the pattern-dependent nickel (Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels and multi-gate. Experiment results show that employing ten nanowire channels improves the Ni-MILC poly-Si TFT performance, including a higher ON/OFF ratio and a lower threshold voltage (Vth) than single-channel TFT. Furthermore, experimental results reveal that a combination the multi-gate structure and ten nanowire channels can further enhance the entire performance of Ni-MILC TFT, including a low leakage current, a high ON/OFF ratio, a low Vth, a steep subthreshold swing (SS), and a kink-free output characteristics. From our studies, we conclude that the performance of the PDMILC TFTs can be improved by NH3 plasma passivation. The lateral electrical field of a ten multiple nanowire channels TFT can be effectively reduced by additional multi-gate control. The PDMILC TFTs process is compatible with CMOS technology, and involves no extra mask. Such high performance PDMILC TFTs are thus promising for use in future high-performance poly-Si TFT applications, especially in AMLCD and 3D MOSFET stacked circuits.

碩士
中原大學
電子工程研究所
97
From recent years, people are becoming more and more conscious on health and environment protection issues. An instance in the field of research is real-time monitoring of water quality for safe human consumption having continued impact and significance. This study presents ion sensors that define chlorine concentration (pCl) of aqueous solutions. Chloride ion (Cl-) sensors were prepared using separate extended gate field effect transistor (SEGFET) structure. Two substrates were employed: indium tin oxide on slide glass (ITO/Glass) and aluminum nitride deposited on ITO/Glass (AlN/ITO/Glass). Membrane sensitive to chloride ions was deposited onto windows of these substrates. Such membrane was synthesized from PVC polymer, DOS plasticizer, ETH9033 ionophore, and THF additive. Afterwards, the ITO part in these sensor heads (PVC-DOS-ETH9033-THF/ITO/Glass, PVC-DOS-ETH9033-THF/AlN/ITO/Glass) were connected to commercially available MOSFET transistors (CD4007UB) to complete two kinds of SEGFET chloride ion sensors. The characterization of SEGFET chloride ion sensors utilized a semiconductor device analyzer (Agilent B1500A) and a constant voltage constant current (CVCC) interface circuitry. The sensitivity of sensors was evaluated using sodium chloride (NaCl) solutions with concentration from pCl 1 to pCl 5. Experiments on the sensitivity yielded: 51.8 mV/pCl of 98% linearity for the chloride ion sensor on ITO/Glass; and 54.3 mV/pCl of 97% linearity for the chloride ion sensor on AlN/ITO/Glass. The stability of sensors was also tested. After 8 hours in 1000 ppm NaCl solution, the time drift of sensors was determined: 0.915 V/hr for the chloride ion sensor on ITO/Glass; and 0.018 V/hr for the chloride ion sensor on AlN/ITO/Glass. Furthermore, the hysteresis of sensors was verified using NaCl solution with pCl level altered every 20 minutes in the direction of pCl 3, pCl 2, pCl 1, pCl 2, to pCl 3, pCl 4, pCl 5, pCl 4, and to pCl 3 again. The hysteresis of sensors measured at pCl 3: around 15 mV for the chloride ion sensor on ITO/Glass; and around 16 mV for the chloride ion sensor on AlN/ITO/Glass. Based on experimental results, the SEGFET chloride ion sensors using ITO/Glass and AlN/ITO/Glass both exhibited wide range of pCl detection, good linearity, stable performance and acceptable reproducibility. The CVCC interface of SEGFET chloride ion sensors was fabricated in integrated circuit using TSMC 2P4M 0.35 micron CMOS technology. The design, simulations and tests of this chip are also reported in this study. With the availability of chloride ion sensors suitable for pCl measurements of water, the low cost structure of SEGFET, together with the readout chip implementation, this study successfully showed that a portable chloride ion measurement system for real-time water monitoring application is very possible.

Among the multilevel (ML)-voltage source converters (VSCs) for medium voltage (MV) and high power (HP) applications, the most used power topology is the three level (3L)-neutral point clamped (NPC)-VSC, due to its features such as common direct current (DC)-bus capability with medium point, absence of switches in series-connection, low part count, and straightforward control. The use of MV-insulated gate bipolar transistor (IGBT) modules as power switches offers further advantages like inexpensive gate drivers and survival capability after short-circuit. However, the IGBT modules have a reduced life cycle due to thermal stress generated by load cycles. Despite the advantages of the 3L-NPC-VSC, its main drawback is the uneven power loss distribution among its power devices. To address this issue and to improve other characteristics, more advanced ML converters have been developed. The 3L-active neutral point clamped (ANPC)-VSC allows an improved power loss distribution thanks to its additional IGBTs, which increase the number of feasible zero-states, but needs a loss balancing scheme to choose the proper redundant zero-state and a more complex commutation sequence between states. The 3L-neutral point piloted (NPP)-VSC improves the power loss distribution thanks to the use of series-connected switches between the output terminal and the positive and negative DC-link terminals. Other advanced power topologies with higher amount of levels include the 5L-ANPC-VSC, which has a flying capacitor per phase to generate the additional levels; and the 5L-stacked multicell converter (SMC), which needs two flying capacitors per phase. The goal of this work is to is to evaluate the performance of the aforementioned NPC-type ML converters with common DC-link, included the ones with flying capacitors, in terms of the power loss distribution and the junction temperature of the most stressed devices, which define, along with the nominal output voltage, the maximum power the converter can deliver. A second objective of this work is to describe the commutations of a MV 3L-ANPC-VSC phase leg prototype with IGBT modules, including all the intermediate switching states to generate the desired commutations.:Figures and Tables V Glossary XIII 1. Introduction 1 2. State of the art of medium voltage source converters and power semiconductors 5 2.1. Overview of medium voltage source converters 5 2.1.1. Multilevel Voltage Source Converter topologies 6 2.1.2. Application oriented basic characteristic of IGCTs and IGBTs 10 2.1.3. Market overview of ML-VSCs 11 2.2. IGBT modules for MV applications 12 2.2.1. Structure and Function 12 2.2.2. Electrical characteristics of the IGBT modules 15 2.2.3. Power losses and junction temperatures estimation 17 2.2.4. Packaging 19 2.2.5. Reliability and Life cycle of IGBT modules 21 2.2.6. Market Overview 23 2.3. Summary of Chapter 2 23 3. Structure, function and characteristics of NPC-based VSCs 25 3.1. The 3L-NPC-VSC 25 3.1.1. Power Topology 25 3.1.2. Switching states, current paths and blocking voltage distribution 26 3.1.3. Modulation of three-level inverters 28 3.1.4. Power loss distribution 32 3.1.5. “Short” and “long” commutation paths 33 3.2. The 3L-NPP-VSC 34 3.2.1. Power Topology 34 3.2.2. Switching states, current paths and blocking voltage distribution 35 3.2.3. Power Loss distribution 36 3.3. The 3L-ANPC-VSC 37 3.3.1. Power Topology 37 3.3.2. Switching states, current paths and blocking voltage distribution 38 3.3.3. Commutations and power loss distribution 39 3.3.4. Loss balancing schemes 57 3.4. The 5L-ANPC-VSC 60 3.4.1. Power Topology 60 3.4.2. Switching states, current paths and blocking voltage distribution 61 3.4.3. Commutation sequences 62 3.4.4. Power Loss distribution 70 3.4.5. Modulation and balancing strategies of capacitor voltages 70 3.5. The 5L-SMC 74 3.5.1. Power Topology 74 3.5.2. Switching states, current paths and blocking voltage distribution 75 3.5.3. Commutations and power loss distribution 78 3.5.4. Modulation and balancing strategies of capacitor voltages 80 3.6. Summary of Chapter 3 81 4. Comparative evaluation and performance of NPC-based converters 83 4.1. Motivation and goal of the comparisons 83 4.2. Basis of the comparison 83 4.2.1. Simulation scheme 85 4.2.2. Losses and thermal models for (4.5 kV, 1.2 kA) IGBT modules 86 4.2.3. Operating points, modulation, controllers and general parameters 88 4.2.4. Life cycle estimation 94 4.3. Simulation results of the 3.3 kV 3L-VSCs 97 4.3.1. Loss distribution and temperature at equal phase current 97 4.3.2. Maximum phase current 109 4.3.3. Life cycle 111 4.4. Simulation results of the 6.6 kV 5L and 3L-VSCs 115 4.4.1. Loss distribution and temperature at equal phase current 115 4.4.2. Maximum phase current 120 4.4.3. Life cycle 128 4.5. Summary of Chapter 4 132 5. Experimental investigation of the 3L-ANPC-VSC with IGBT modules 135 5.1. Goal of the work 135 5.2. Description of the 3L-ANPC-VSC test bench 136 5.2.1. Medium voltage stage 136 5.2.2. Gate drivers and digital signal handling 138 5.2.3. Measurement equipment 139 5.3. Double-pulse test and commutation sequences 140 5.3.1. Description of the double-pulse test for the 3L-ANPC-VSC 140 5.3.2. Commutation sequences for the double-pulse test 142 5.4. Commutation measurements 142 5.4.1. Switching and transition times 144 5.4.2. Type I commutations 145 5.4.3. Type I-U commutations 150 5.4.4. Type II commutations 150 5.4.5. Type III commutations 157 5.4.6. Comparison of the commutation times 157 5.4.7. Stray inductances of the “short” and “long” commutations 163 5.5. Summary of Chapter 5 167 6. Conclusions 169 Appendices 173 A. Thermal model of IGBT modules 175 A.1. General “Y” model 175 A.2. “Foster” thermal circuit 177 A.3. “Cauer” thermal circuit 178 A.4. From “Foster” to “Cauer” 179 A.5. Temperature comparison using “Foster” and “Cauer” networks 181 B. The “Rainflow” cycle counting algorithm 183 C. Description of the wind generator example 187 C.1. Simulation models 188 C.1.1. Wind turbine 188 C.1.2. Synchronous generator, grid and choke filter 189 C.1.3. Converters 189 C.2. Controllers 190 C.2.1. MPPT scheme 190 C.2.2. Pitch angle controller 191 C.2.3. Generator side VSC 192 C.2.4. Grid side VSC 193 D. 3D-surfaces of the maximum load currents in NPC-based converters 195 Bibliography 201 Bibliography 201
Unter den Multilevel-Spannungsumrichtern für Mittelspannungs- und Hochleistungsanwendungen ist die am häufigsten verwendete Leistungstopologie der NPC-VSC, wegen seinen Merkmalen wie die Gleichstrom-Bus fähigkeit mit mittlerem Punkt, das Fehlen von Schaltern in Reihenschaltung, eine geringe Anzahl von Bauteilen und eine einfache Steuerung. Die Verwendung von Bipolartransistor Modulen mit isolierter Gate-Elektrode als Leistungsschalter bietet weitere Vorteile wie kostengünstige Gatetreiber und Überlebensfähigkeit nach einem Kurzschluss. Die IGBT-Module haben jedoch aufgrund der durch Lastzyklen erzeugten thermischen Belastung eine verkürzte Lebensdauer. Trotz der Vorteile des 3L-NPC-VSC ist der Hauptnachteil die ungleichmäßige Verteilung der Leistungsverluste zwischen den Leistungsgeräten. Um dieses Problem zu beheben und andere Eigenschaften zu verbessern, wurden fortgeschrittenere ML-Konverter entwickelt. Das 3L-ANPC-VSC ermöglicht dank seiner zusätzlichen IGBTs eine verbesserte Verlustleistungsverteilung, wodurch die Anzahl der möglichen Null-Zustände erhöht wird, es ist jedoch ein Verlustausgleichsschema erforderlich, um den richtigen redundanten Null-Zustand, und benötigt auszuwählende komplexere Kommutierungssequenz zwischen Zuständen. Das 3L-NPP-VSC verbessert die Verlustleistungsverteilung durch die Verwendung von in Reihe geschalteten Schaltern zwischen der Ausgangsklemme und den positiven und negativen Zwischenkreisklemmen. Andere fortgeschrittene Leistungstopologien mit einer höheren Anzahl von Stufen umfassen den 5L-ANPC-VSC, der pro Phase einen fliegenden Kondensator zur Erzeugung der zusätzlichen Stufen aufweist; und den 5L-SMC, der pro Phase zwei fliegende Kondensatoren benötigt. Das Ziel dieser Arbeit ist es, die Leistung der oben genannten NPC-VSC, einschließlich der mit fliegenden Kondensatoren, hinsichtlich der Verlustleistungsverteilung und der Sperrschichttemperatur der am stärksten beanspruchten Geräte zu bewerten. Diese definieren zusammen mit der Nennausgangsspannung die maximale Leistung, die der Umrichter liefern kann. Ein zweites Ziel dieser Arbeit ist die Beschreibung der Kommutierungen eines MV 3L-ANPC-VSC- Prototyps mit IGBT-Modulen einschließlich aller Zwischenschaltzustände, um die gewünschten Kommutierungen zu erzeugen.:Figures and Tables V Glossary XIII 1. Introduction 1 2. State of the art of medium voltage source converters and power semiconductors 5 2.1. Overview of medium voltage source converters 5 2.1.1. Multilevel Voltage Source Converter topologies 6 2.1.2. Application oriented basic characteristic of IGCTs and IGBTs 10 2.1.3. Market overview of ML-VSCs 11 2.2. IGBT modules for MV applications 12 2.2.1. Structure and Function 12 2.2.2. Electrical characteristics of the IGBT modules 15 2.2.3. Power losses and junction temperatures estimation 17 2.2.4. Packaging 19 2.2.5. Reliability and Life cycle of IGBT modules 21 2.2.6. Market Overview 23 2.3. Summary of Chapter 2 23 3. Structure, function and characteristics of NPC-based VSCs 25 3.1. The 3L-NPC-VSC 25 3.1.1. Power Topology 25 3.1.2. Switching states, current paths and blocking voltage distribution 26 3.1.3. Modulation of three-level inverters 28 3.1.4. Power loss distribution 32 3.1.5. “Short” and “long” commutation paths 33 3.2. The 3L-NPP-VSC 34 3.2.1. Power Topology 34 3.2.2. Switching states, current paths and blocking voltage distribution 35 3.2.3. Power Loss distribution 36 3.3. The 3L-ANPC-VSC 37 3.3.1. Power Topology 37 3.3.2. Switching states, current paths and blocking voltage distribution 38 3.3.3. Commutations and power loss distribution 39 3.3.4. Loss balancing schemes 57 3.4. The 5L-ANPC-VSC 60 3.4.1. Power Topology 60 3.4.2. Switching states, current paths and blocking voltage distribution 61 3.4.3. Commutation sequences 62 3.4.4. Power Loss distribution 70 3.4.5. Modulation and balancing strategies of capacitor voltages 70 3.5. The 5L-SMC 74 3.5.1. Power Topology 74 3.5.2. Switching states, current paths and blocking voltage distribution 75 3.5.3. Commutations and power loss distribution 78 3.5.4. Modulation and balancing strategies of capacitor voltages 80 3.6. Summary of Chapter 3 81 4. Comparative evaluation and performance of NPC-based converters 83 4.1. Motivation and goal of the comparisons 83 4.2. Basis of the comparison 83 4.2.1. Simulation scheme 85 4.2.2. Losses and thermal models for (4.5 kV, 1.2 kA) IGBT modules 86 4.2.3. Operating points, modulation, controllers and general parameters 88 4.2.4. Life cycle estimation 94 4.3. Simulation results of the 3.3 kV 3L-VSCs 97 4.3.1. Loss distribution and temperature at equal phase current 97 4.3.2. Maximum phase current 109 4.3.3. Life cycle 111 4.4. Simulation results of the 6.6 kV 5L and 3L-VSCs 115 4.4.1. Loss distribution and temperature at equal phase current 115 4.4.2. Maximum phase current 120 4.4.3. Life cycle 128 4.5. Summary of Chapter 4 132 5. Experimental investigation of the 3L-ANPC-VSC with IGBT modules 135 5.1. Goal of the work 135 5.2. Description of the 3L-ANPC-VSC test bench 136 5.2.1. Medium voltage stage 136 5.2.2. Gate drivers and digital signal handling 138 5.2.3. Measurement equipment 139 5.3. Double-pulse test and commutation sequences 140 5.3.1. Description of the double-pulse test for the 3L-ANPC-VSC 140 5.3.2. Commutation sequences for the double-pulse test 142 5.4. Commutation measurements 142 5.4.1. Switching and transition times 144 5.4.2. Type I commutations 145 5.4.3. Type I-U commutations 150 5.4.4. Type II commutations 150 5.4.5. Type III commutations 157 5.4.6. Comparison of the commutation times 157 5.4.7. Stray inductances of the “short” and “long” commutations 163 5.5. Summary of Chapter 5 167 6. Conclusions 169 Appendices 173 A. Thermal model of IGBT modules 175 A.1. General “Y” model 175 A.2. “Foster” thermal circuit 177 A.3. “Cauer” thermal circuit 178 A.4. From “Foster” to “Cauer” 179 A.5. Temperature comparison using “Foster” and “Cauer” networks 181 B. The “Rainflow” cycle counting algorithm 183 C. Description of the wind generator example 187 C.1. Simulation models 188 C.1.1. Wind turbine 188 C.1.2. Synchronous generator, grid and choke filter 189 C.1.3. Converters 189 C.2. Controllers 190 C.2.1. MPPT scheme 190 C.2.2. Pitch angle controller 191 C.2.3. Generator side VSC 192 C.2.4. Grid side VSC 193 D. 3D-surfaces of the maximum load currents in NPC-based converters 195 Bibliography 201 Bibliography 201