Academic literature on the topic 'Multi-FPGA Boards'

To reduce the cost of designing new specialized FPGA boards as direct-summation MOND (Modified Newtonian Dynamics) simulator, we propose a new heterogeneous architecture with existing FPGA boards, which is called RP-ring (reconfigurable processor ring). This design can be expanded conveniently with any available FPGA board and only requires quite low communication bandwidth between FPGA boards. The communication protocol is simple and can be implemented with limited hardware/software resources. In order to avoid overall performance loss caused by the slowest board, we build a mathematical model to decompose workload among FPGAs. The dividing of workload is based on the logic resource, memory access bandwidth, and communication bandwidth of each FPGA chip. Our accelerator can achieve two orders of magnitude speedup compared with CPU implementation.

Purpose – The purpose of this study was the use of embedded components technology and innovative concepts of the printed circuit board (PCB) for electronic modules containing field-programmable gate array (FPGA) devices with a large number of pins (e.g. Virtex 6, FF1156/RF1156 package, 1,156 pins). Design/methodology/approach – In the multi-layered boards, embedded passive components that support FPGA device input/output (I/O), such as blocking capacitors and pull-up resistors, were used. These modules can be used in rapid design of electronic devices. In the study, the MC16T FaradFlex material was used for the inner capacitive layer. The Ohmega-Ply RCM 25 Ω/sq material was used to manufacture pull-up resistors for high-frequency pins. The embedded components have been connected to pins of the FPGA component by using plated-through holes for capacitors and blind vias for resistors. Also, a technique for a board-to-board joining, by using castellated terminations, is described. Findings – The fully functional modules for assembly of the FPGA were manufactured. Achieved resistance of embedded micro resistors, as small as the smallest currently used surface-mount device components (01005), was below required tolerance of 10 per cent. Obtained tolerance of capacitors was less than 3 per cent. Use of embedded components allowed to replace the pull-up resistors and blocking capacitors and shortens the signal path from the I/O of the FPGA. Correct connection to the castellated terminations with a very small pitch was also obtained. This allows in further planned studies to create a full signal distribution system from the FPGA without the use of unreliable plug connectors in aviation and space technology. Originality/value – This study developed and manufactured several innovative concepts of signal distribution from printed circuit boards. The signal distribution solutions were integrated with embedded components, which allowed for significant reduction in the signal path. This study allows us to build the target object that is the module for rapid design of the FPGA device. Usage of a pre-designed module would lessen the time needed to develop a FPGA-based device, as a significant part of the necessary work (mainly designing the signal and power fan-out) will already be done during the module development.

Remote-sensing platforms, such as Unmanned Aerial Vehicles, are characterized by limited power budget and low-bandwidth downlinks. Therefore, handling hyperspectral data in this context can jeopardize the operational time of the system. FPGAs have been traditionally regarded as the most power-efficient computing platforms. However, there is little experimental evidence to support this claim, which is especially critical since the actual behavior of the solutions based on reconfigurable technology is highly dependent on the type of application. In this work, a highly optimized implementation of an FPGA accelerator of the novel HyperLCA algorithm has been developed and thoughtfully analyzed in terms of performance and power efficiency. In this regard, a modification of the aforementioned lossy compression solution has also been proposed to be efficiently executed into FPGA devices using fixed-point arithmetic. Single and multi-core versions of the reconfigurable computing platforms are compared with three GPU-based implementations of the algorithm on as many NVIDIA computing boards: Jetson Nano, Jetson TX2 and Jetson Xavier NX. Results show that the single-core version of our FPGA-based solution fulfils the real-time requirements of a real-life hyperspectral application using a mid-range Xilinx Zynq-7000 SoC chip (XC7Z020-CLG484). Performance levels of the custom hardware accelerator are above the figures obtained by the Jetson Nano and TX2 boards, and power efficiency is higher for smaller sizes of the image block to be processed. To close the performance gap between our proposal and the Jetson Xavier NX, a multi-core version is proposed. The results demonstrate that a solution based on the use of various instances of the FPGA hardware compressor core achieves similar levels of performance than the state-of-the-art GPU, with better efficiency in terms of processed frames by watt.

FPGA-based cards for data concentration and readout are often used in data acquisition (DAQ) systems for high-energy physics experiments. The DMA engines implemented in FPGA enable efficient data transfer to the processing system’s memory. This paper presents a versatile DMA engine. It may be used in systems with FPGA-equipped PCIe boards hosted in a server and MPSoC-based systems with programmable logic connected directly to the AXI system bus. The core part of the engine is implemented in HLS to simplify further development and modifications. The design is modular and may be easily integrated with the user’s DAQ logic, assuming it delivers the data via a standard AXI-Stream interface. The engine and accompanying software are designed with flexibility in mind. They offer a simple single-packet mode for debugging and a high-performance multi-packet mode fully utilizing the computational power of the processing system. The number of used DAQ cards and the amount of memory used for the DMA buffer may be modified in the runtime without rebooting the system. That is particularly useful in the development and test setups. This paper also presents the development and testing methodology. The whole design is open-source and available in public repositories.

In 2019, the ATLAS experiment at CERN is planning an upgrade in order to cope with the higher luminosity requirements. In this upgrade, the installation of the new muon chambers for the end-cap muon system will be carriedout. Muon track reconstruction performance can be improved, and fake triggers can be reduced. It is also necessary to develop readout system of trigger data for the Level-1 end-cap muon trigger. We have decided to develop software-based data acquisition system. There-fore, we have implemented SiTCP technology, which connects a FPGA with the network, on the FPGA of new trigger processor boards. Due to this implementation, the new DAQ system can take advantage of the latest developments in computing industry. This new readout system architec-ture is based on multi-process software, and can assemble events at a rate of 100 kHz. For data collection, the 10 Gbit Ethernet network switch is used. Moreover, we have optimized these processes to send data to the following sys-tem without any error. Therefore, the built events can be sent with an average throughput of approximately 211 Mbps. Our newly developed readout system is very generic and it is flexible for modi-fications, extensions and easyto debug. This paper will present the details of the new software-based DAQ system and report the development status for ATLAS Run-3.

Because of the denser active use of the spectrum, and because of radio telescopes higher sensitivity, radio frequency interference (RFI) mitigation has become a sensitive topic for current and future radio telescope designs. Even if quite sophisticated approaches have been proposed in the recent years, the majority of RFI mitigation operational procedures are based on post-correlation corrupted data flagging. Moreover, given the huge amount of data delivered by current and next generation radio telescopes, all these RFI detection procedures have to be at least automatic and, if possible, real-time. In this paper, the implementation of a real-time pre-correlation RFI detection and flagging procedure into generic high-performance computing platforms based on field programmable gate arrays (FPGA) is described, simulated and tested. One of these boards, UniBoard, developed under a Joint Research Activity in the RadioNet FP7 European programme is based on eight FPGAs interconnected by a high speed transceiver mesh. It provides up to 4 TMACs with ®Altera Stratix IV FPGA and 160 Gbps data rate for the input data stream. The proposed concept is to continuously monitor the data quality at different stages in the digital preprocessing pipeline between the antennas and the correlator, at the station level and the core level. In this way, the detectors are applied at stages where different time–frequency resolutions can be achieved and where the interference-to-noise ratio (INR) is maximum right before any dilution of RFI characteristics by subsequent channelizations or signal recombinations. The detection decisions could be linked to a RFI statistics database or could be attached to the data for later stage flagging. Considering the high in–out data rate in the pre-correlation stages, only real-time and go-through detectors (i.e. no iterative processing) can be implemented. In this paper, a real-time and adaptive detection scheme is described. An ongoing case study has been set up with the Electronic Multi-Beam Radio Astronomy Concept (EMBRACE) radio telescope facility at Nançay Observatory. The objective is to evaluate the performances of this concept in term of hardware complexity, detection efficiency and additional RFI metadata rate cost. The UniBoard implementation scheme is described.

This study shows the design, implementation, and test results of a low-cost portable radiation-detector system relies on a directionally designed multi detector probe that works in Geiger-Müller counting mode with a single chip solution. The proposed system can perform the functions of detecting the ionizing radiation source, counting gamma and showing the direction and angle of the gamma source relative to the position of the device. The radiation direction finding (RDF) system consists of a radiation probe and electronic sections that are mounted in a metal box. The probe has a has a cast housing made of lead material and it has 8 directional slots for placing the optically isolated PIN diode arrays where each array consists of 4 parallelly connected BPW 34 PIN model diode. The lead housing also blocks incident rays from unintended directions and provides a directional sensing for PIN diodes. The metal box contains 8 low noise amplifiers and pulse shaping detector boards that are assigned to each channel of PIN diode arrays, a signal inverter board, a step-up high voltage board, a 12 V battery and a parallel processing FPGA board with an embedded VHDL software that can process all 8 channels simultaneously and execute the direction estimation algorithm. The system also has an adjustable detector bias voltage and the applied voltage can be displayed on a seven-segment display located in front of the unit so that different models of PIN diodes can be used and tested with different bias voltage levels. It also has a HMI touch screen unit and user interface for displaying the Cpm or Cps values of each channel; a 360-degree scale showing the direction of the source with its pointer and an indicator showing the direction of the source numerically in degrees. The system works as a gamma detector and the source direction can also be detected within ±45° interval. The success of system within this interval is 99.22%. The detector was tested with low to high energy gamma sources (241Am, 9.761 μCi, 59.54 keV, 137Cs 661, 3.7 MBq, keV and 60Co, μCi, 1173 and 1332 keV) and showed good sensitivity performance level in gamma ray detection. The major outcome of this study and the major contribution of this work to the literature is therefore is the design and production details of a hand-held detector and source direction locator prototype; which is a light, portable and compact system.

Abstract A multichannel high-speed data acquisition system based on improved SPI communication is designed to meet the requirements of synchronous acquisition of current and voltage parameters by master and slave control boards. The main architecture of this system is a master-slave FPGA board and AD acquisition card, and the program is developed based on the Vivado platform. Based on traditional SPI communication, this paper puts forward an improved SPI communication. By increasing the number of MISO data lines, the data transmission rate between master and slave control boards is greatly increased, and the FPGA expansion port resources are fully utilized. In addition, a data conversion module is added to the system, which can observe the acquisition results more intuitively. At the same time as high-speed data acquisition, the measurement accuracy within the specified voltage input range is high. The experimental results show that the system can realize multichannel high-speed data acquisition.

Multi-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle. However, after partitioning the design on the multi-FPGA platform, the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowers the system frequency. The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set of constraints to be taken into account during the partitioning task. Then, the resulting inter-FPGA signals are routed with an iterative routing algorithm in order to obtain the best multiplexing ratio. Indeed, signals are grouped and then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8% compared to constructive routing algorithm.

This PhD work has been carried out at the Legnaro National Laboratories (LNL), one of the four national labs of the National Institute for Nuclear Physics (INFN). The mission of LNL is to perform research in the field of nuclear physics and nuclear astrophysics together with emerging technologies. Technological research and innovation are the key to promote excellence in science, to excite competitive industries and to establish a better society. The research activities concerning electronics and computer science are an essential base to develop the control system of the Selective Production of Exotic Species (SPES) project. Nowadays, SPES is the most important project commissioned at LNL and represents the future of the Lab. It is a second generation Isotope Separation On-Line (ISOL) radioactive ion beam facility intended for fundamental nuclear physics research as well as experimental applications in different fields of science, such as nuclear medicine; radio-pharmaceutical production for therapy and diagnostic. The design of the SPES control system demands innovative technologies to embed the control of several appliances with different requirements and performing different tasks spanning from data sharing and visualization, data acquisition and storage, networking, security and surveillance operations, beam transport and diagnostic. The real time applications and fast peripherals control commonly found in the distributed control network of particle accelerators are accompanied by the challenge of developing custom embedded systems. In this context, the proposed PhD work describes the design and development of a multi-purpose Input Output Controller (IOC) board capable of embedding the control of typical accelerator instrumentation involved in the automatic beam transport system foreseen for the SPES project. The idea behind this work is to extend the control reach to the single device level without losing in modularity and standardization. The outcome of the research work is a general purpose embedded computer that will be the base for standardizing the hardware layer of the frontend computers in the SPES distributed control system. The IOC board is a Computer-on-Module (COM) carrier board designed to host any COM Express type 6 module and is equipped with a Field Programmable Gate Array (FPGA) and user application specific I/O connection solutions not found in a desktop pc. All the generic pc functionalities are readily available in off-the-shelf modules and the result is a custom motherboard that bridges the gap between custom developments and commercial personal computers. The end user can deal with a general-purpose pc with a high level of hardware abstraction besides being able to exploit the on-board FPGA potentialities in terms of fast peripherals control and real time digital data processing. This document opens with an introductory chapter about the SPES project and its control system architecture and technology before to describe the IOC board design, prototyping, and characterization. The thesis ends describing the installation in the field of the IOC board which is the core of the new diagnostics data readout and signal processing system. The results of the tests performed under real beam conditions prove that the new hardware extends the current sensitivity to the pA range, addressing the SPES requirements, and prove that the IOC board is a reliable solution to standardize the control of several appliances in the SPES accelerators complex where it will be embedded into physical equipment, or in their proximity, and will control and monitor their operation replacing the legacy VME technology. The installation in the field of the IOC board represents a great personal reward and crowns these years of busy time during which I turned what was just an idea in 2014, into a working embedded computer today.
Questo lavoro di dottorato è stato svolto presso ai Laboratori Nazionali di Legnaro (LNL), uno dei quattro laboratori nazionali dell’Istituto Nazionale di Fisica Nucleare. La missione principale dei LNL è la ricerca di base nella fisica e astrofisica nucleare, sostenuta da un’importante ricerca relativa alle tecnologie emergenti. Le attività di ricerca nell’ambito dell’elettronica e dell’informatica sono essenziali per lo sviluppo del sistema di controllo del progetto SPES (produzione selettiva di specie esotiche). SPES è il progetto piú importante e rappresenta il futuro dei laboratori di Legnaro. Si tratta di una infrastruttura di tipo ISOL (separazione di isotopi in linea), di seconda generazione, il cui obiettivo è quello di generare e accelerare un fascio di ioni radioattivi dedicato alla ricerca nel campo della fisica nucleare, astrofisica nucleare, e ad applicazioni sperimentali in diversi campi della scienza come la produzione di particolari radionuclidi per la medicina nucleare che saranno utili per la diagnosi e la cura di patologie oncologiche. Il progetto del sistema di controllo di SPES sarà basato su tecnologie innovative che consentiranno di monitorare e controllare dispositivi tra loro molto diversi e che eseguono funzioni differenti che vanno dall’acquisizione e visualizzazione dei dati, condivisione dei dati in rete, memorizzazione delle informazioni, operazioni di sorveglianza, diagnostiche e trasporto del fascio. In questo contesto, il dottorato di ricerca proposto descrive il progetto e la realizzazione di una scheda elettronica di controllo (IOC) multifunzione capace di controllare quasi tutte le apparecchiature coinvolte nel trasporto del fascio di ioni radioattivi. L’idea di base di questo lavoro è quella di estendere il controllo a livello di singola apparecchiatura o piccoli gruppi di dispositivi senza rinunciare alla modularità e alla standardizzazione dell’elettronica. Il risultato del lavoro di dottorato è un computer embedded multifunzione progettato con tecnologie all’avanguardia che diventerà lo standard, a livello hardware, su cui si baserà il sistema di controllo distribuito di SPES. Questo controllore multifunzione integra tutte le funzionalità di un computer commerciale e in aggiunta è equipaggiato con un dispositivo programmabile sul campo (FPGA) e alcune periferiche non standard dedicate ad applicazioni di controllo specifiche. L’utente finale potrà sfruttare questa scheda elettronica come un qualunque pc commerciale, oppure, potrà sfruttare le potenzialità della FPGA per le elaborazioni digitali dei dati in tempo reale, per il trasferimento dei dati ad alta velocità su fibra ottica, per chiudere anelli di controllo a larga banda e per avere tempi di risposta agli stimoli in ingresso dal campo deterministici e molto brevi. Il documento apre con una introduzione sul progetto SPES prima di descrivere la progettazione, prototipizzazione e validazione della scheda IOC dando particolare risalto alle attività in cui il mio contributo è stato fondamentale. La tesi si chiude descrivendo l’integrazione della scheda IOC nel sistema di diagnostiche di fascio di SPES. Le misure del profilo di fascio eseguite sul campo e l’estensione della sensibilità di corrente a pochi pA confermano che la scheda elettronica progettata è una soluzione affidabile per standardizzare, a livello hardware, il controllo di diverse apparecchiature nel complesso degli acceleratori del progetto SPES. Questa scheda sostituirà la tecnologia VME in diverse applicazioni e sarà la base su cui implementare un sistema di trasporto di fascio automatico e di qualità, fondamentale per il successo delle attività di ricerca ai LNL. L’installazione in campo della scheda elettronica rappresenta una soddisfazione personale enorme e corona questi anni di duro lavoro durante ai quali ho trasformato quella che nel 2014 era solo un’idea, in un computer embedded pienamente funzionante.

To protect safety-critical systems from common-cause failures that can lead to potentially dangerous outcomes, special methods are applied, including multi-version technologies operating at different levels of diversity. A model representing different diversity types during the development of safety-critical systems is suggested. The model addresses diversity types that are the most expedient in providing required safety. The diversity of complex electronic components (FPGA, etc.), printed circuit boards, manufacturers, specification languages, design, and program languages, etc. are considered. The challenges addressed are related to factors of scale and dependencies among diversity types, since not all combinations of used diversity are feasible. Taking these dependencies into consideration, the model simplifies the choice of diversity options. This chapter presents a cost effective approach to selection of the most diverse NPP Reactor Trip System (RTS) under uncertainty. The selection of a pair of primary and secondary RTS is named a diversity strategy. All possible strategies are evaluated on an ordinal scale with linguistic values provided by experts. These values express the expert’s degree of confidence that evaluated variants of secondary RTS are different from primary. All diversity strategies are evaluated on a set of linguistic diversity criteria, which are included into a corresponding diversity attribute. The generic fuzzy diversity score is an aggregation of the linguistic values provided by the experts to obtain a collective assessment of the secondary RTS’s similarity (difference) with a primary one. This rational diversity strategy is found during the exploitation stage, taking into consideration the fuzzy diversity score and cost.

Reconfigurable computing, exploiting Field Programmable Gate Arrays (FPGA), has become of great interest for both academia and industry research thanks to the possibility to greatly accelerate a variety of applications. The interest has been further boosted by recent developments of FPGA programming frameworks which allows to design applications at a higher-level of abstraction, for example using directive based approaches. In this work we describe our first experiences in porting to FPGAs an HPC application, used to simulate Rayleigh-Taylor instability of fluids with different density and temperature using Lattice Boltzmann Methods. This activity is done in the context of the FET HPC H2020 EuroEXA project which is developing an energyefficient HPC system, at exa-scale level, based on Arm processors and FPGAs. In this work we use the OmpSs directive based programming model, one of the models available within the EuroEXA project. OmpSs is developed by the Barcelona Supercomputing Center (BSC) and allows to target FPGA devices as accelerators, but also commodity CPUs and GPUs, enabling code portability across different architectures. In particular, we describe the initial porting of this application, evaluating the programming efforts required, and assessing the preliminary performances on a Trenz development board hosting a Xilinx Zynq UltraScale+ MPSoC embedding a 16nm FinFET+ programmable logic and a multi-core Arm CPU.

This work targets the challenging issue to produce high throughput and low-cost configurable architecture of Discrete wavelet transforms (DWT). More specifically, it proposes a new hardware architecture of the first and second generation of DWT using a modified multi-resolution tree. This approach is based on serializations and interleaving of data between different stages. The designed architecture is massively parallelized and sharing hardware between low-pass and high-pass filters in the wavelet transformation algorithm. Consequently, to process data in high speed and decrease hardware usage. The different steps of the post/pre-synthesis configurable algorithm are detailed in this paper. A modulization in VHDL at RTL level and implementation of the designed architecture on FPGA technology in a NexysVideo board (Artix 7 FPGA) are done in this work, where the performance, the configurability and the generic of our architecture are highly enhanced. The implementation results indicate that our proposed architectures provide a very high-speed data processing with low needed resources. As an example, with the parameters depth order equal 2, filter order equal 2, order quantization equal 5 and a parallel degree P = 16, we reach a bit rate around 3160 Mega samples per second with low used of logic elements ( ≈ 400) and logic registers ( ≈ 700 ).

A comparative analysis of the functionality of stereo vision algorithms on various hardware architectures has been carried out. The quantitative results of stereo vision algorithms implementation are presented, taking into account the specifics of the applied hardware base. The description of the original algorithm for calculating the depth map using the summed-area table is given. The complexity of the algorithm does not depend on the size of the search window. The article presents the content and results of the implementation of the stereo vision method on standard architecture computers, including multi-threaded implementation, a single-board computer and FPGA. The proposed results may be of interest in the design of vision systems for applied applications.