Relevant bibliographies by topics / Multi-core execution

Academic literature on the topic 'Multi-core execution'

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Published: 14 March 2023

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Journal articles on the topic "Multi-core execution"

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Fang, Juan, and Hong Bo Zhang. "An Improved Architecture for Multi-Core Prefetching." Advanced Materials Research 505 (April 2012): 253–56. http://dx.doi.org/10.4028/www.scientific.net/amr.505.253.

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The “Memory Wall” problem has become a bottleneck for the performance of processor, and on-chip multiprocessor(CMP) aggravates the memory access latency. So many hardware prefetching techniques have been brought to solve this challenge, i.e. Future Execution. This paper introduces runahead execution(another hardware prefetching technique firstly used on single-core processor) and Future Execution, then it brings up some improvement for Future Execution and gives the result and analysis of data tested by SPEC2000 benchmark.
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Chen, Xiaowen. "Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips." Journal of Software 10, no. 2 (February 2015): 142–61. http://dx.doi.org/10.17706/jsw.10.2.142-161.

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Maity, Arka, Anuj Pathania, and Tulika Mitra. "PkMin: Peak Power Minimization for Multi-Threaded Many-Core Applications." Journal of Low Power Electronics and Applications 10, no. 4 (September 30, 2020): 31. http://dx.doi.org/10.3390/jlpea10040031.

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Multiple multi-threaded tasks constitute a modern many-core application. An accompanying generic Directed Acyclic Graph (DAG) represents the execution precedence relationship between the tasks. The application comes with a hard deadline and high peak power consumption. Parallel execution of multiple tasks on multiple cores results in a quicker execution, but higher peak power. Peak power single-handedly determines the involved cooling costs in many-cores, while its violations could induce performance-crippling execution uncertainties. Less task parallelization, on the other hand, results in lower peak power, but a more prolonged deadline violating execution. The problem of peak power minimization in many-cores is to determine task-to-core mapping configuration in the spatio-temporal domain that minimizes the peak power consumption of an application, but ensures application still meets the deadline. All previous works on peak power minimization for many-core applications (with or without DAG) assume only single-threaded tasks. We are the first to propose a framework, called PkMin, which minimizes the peak power of many-core applications with DAG that have multi-threaded tasks. PkMin leverages the inherent convexity in the execution characteristics of multi-threaded tasks to find a configuration that satisfies the deadline, as well as minimizes peak power. Evaluation on hundreds of applications shows PkMin on average results in 49.2% lower peak power than a similar state-of-the-art framework.
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Griffin, Thomas A. N., Kenneth Shankland, Jacco van de Streek, and Jason Cole. "MDASH: a multi-core-enabled program for structure solution from powder diffraction data." Journal of Applied Crystallography 42, no. 2 (March 5, 2009): 360–61. http://dx.doi.org/10.1107/s0021889809006852.

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The simulated annealing approach to structure solution from powder diffraction data, as implemented in theDASHprogram, is easily amenable to parallelization at the individual run level. Modest increases in speed of execution can therefore be achieved by executing individualDASHruns on the individual cores of CPUs.
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Chen, Gang, Kai Huang, Long Cheng, Biao Hu, and Alois Knoll. "Dynamic Partitioned Cache Memory for Real-Time MPSoCs with Mixed Criticality." Journal of Circuits, Systems and Computers 25, no. 06 (March 31, 2016): 1650062. http://dx.doi.org/10.1142/s0218126616500626.

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Shared cache interference in multi-core architectures has been recognized as one of major factors that degrade predictability of a mixed-critical real-time system. Due to the unpredictable cache interference, the behavior of shared cache is hard to predict and analyze statically in multi-core architectures executing mixed-critical tasks, which will not only result in difficulty of estimating the worst-case execution time (WCET) but also introduce significant worst-case timing penalties for critical tasks. Therefore, cache management in mixed-critical multi-core systems has become a challenging task. In this paper, we present a dynamic partitioned cache memory for mixed-critical real-time multi-core systems. In this architecture, critical tasks can dynamically allocate and release the cache resourse during the execution interval according to the real-time workload. This dynamic partitioned cache can, on the one hand, provide the predicable cache performance for critical tasks. On the other hand, the released cache can be dynamically used by non-critical tasks to improve their average performance. We demonstrate and prototype our system design on the embedded FPGA platform. Measurements from the prototype clearly demonstrate the benefits of the dynamic partitioned cache for mixed-critical real-time multi-core systems.
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Suleman, M. Aater, Onur Mutlu, Moinuddin K. Qureshi, and Yale N. Patt. "Accelerating critical section execution with asymmetric multi-core architectures." ACM SIGARCH Computer Architecture News 37, no. 1 (March 2009): 253–64. http://dx.doi.org/10.1145/2528521.1508274.

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Chen, Kuan-Chung, and Chung-Ho Chen. "Enabling SIMT Execution Model on Homogeneous Multi-Core System." ACM Transactions on Architecture and Code Optimization 15, no. 1 (April 2, 2018): 1–26. http://dx.doi.org/10.1145/3177960.

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Kulkarni, Abhishek, Latchesar Ionkov, Michael Lang, and Andrew Lumsdaine. "Optimizing process creation and execution on multi-core architectures." International Journal of High Performance Computing Applications 27, no. 2 (April 2, 2013): 147–61. http://dx.doi.org/10.1177/1094342013481483.

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Suleman, M. Aater, Onur Mutlu, Moinuddin K. Qureshi, and Yale N. Patt. "Accelerating critical section execution with asymmetric multi-core architectures." ACM SIGPLAN Notices 44, no. 3 (February 28, 2009): 253–64. http://dx.doi.org/10.1145/1508284.1508274.

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Huang, Shujuan, Yi'an Zhu, Bailin Liu, and Feng Xiao. "Research on Three Dimensional Scheduling Model for Embedded Multi-Core System." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 36, no. 5 (October 2018): 1020–25. http://dx.doi.org/10.1051/jnwpu/20183651020.

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This paper proposes a new three-dimensional scheduling model which can divide the tasks into harmonic tasks and non-harmonic tasks for the high demands of embedded mucticne plactorim. According to the characteristic parameters of the tasks and make the value of the rectangular area as the attribute of the execution region which is divided into executive region, interference region and free region with the characteristic of the area. By using these attributes of the different region, the tasks are allocated to different cores. Experimental results show that the proposed method is more fully optimizing the system utilization and throughput than PEDF.
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Dissertations / Theses on the topic "Multi-core execution"

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Faleiro, Jose Manuel. "High Performance Multi-core Transaction Processing via Deterministic Execution." Thesis, Yale University, 2019. http://pqdtopen.proquest.com/#viewpdf?dispub=13851858.

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The increasing democratization of server hardware with multi-core CPUs and large main memories has been one of the dominant hardware trends of the last decade. "Bare metal" servers with tens of CPU cores and over 100 gigabytes of main memory have been available for several years now. Recently, this large scale hardware has also been available via the cloud; for instance, Amazon EC2 now provides instances with 64 physical CPU cores. Database systems, with their roots in uniprocessors and paucity of main memory, have unsurprisingly been found wanting on modern hardware.

In addition to changes in hardware, database systems have had to contend with changing application requirements and deployment environments. Database systems have long provided applications with an interactive interface, in which an application can communicate with the database over several round-trips in the course of a single request. A large class of applications, however, does not require interactive interfaces, and is unwilling to pay the performance cost associated with overly flexible interfaces. Some of these applications have eschewed database systems altogether in favor of high-performance key-value stores.

Finally, modern applications are increasingly deployed at ever increasing scales, often serving hundreds of thousands to millions of simultaneous clients. These large scale deployments are more prone to errors due to consistency issues in their underlying database systems. Ever since their inception, database systems have provided applications to tradeoff consistency for performance, and often nudge applications towards weak consistency. When deployed at scale, weak consistency exposes latent consistency-related bugs, in the same way that failures are more likely to occur at scale. Nearly every widely deployed database system provides applications with weak consistency consistency by default, and its widespread use in practice significantly complicates application development, leading to latent Heisenbugs that are only exposed in production.

This dissertation proposes and explores the use of deterministic execution to address these concerns. Database systems have traditionally been non-deterministic; given an input list of transactions, the final state of the database, which corresponds to some totally ordered execution of transactions, is dependent on non-deterministic factors such as thread scheduling decisions made by the operating system and failures. Deterministic execution, on the other hand, ensures that the database's final state is always determined by its input list of transactions; in other words, the input list of transactions is the same as the total order of transactions that determines the database's state.

While non-deterministic database systems expend significant resources in determining valid total orders of transactions, we show that deterministic systems can exploit simple and low-cost up-front total ordering of transactions to execute and schedule transactions much more efficiently. We show that deterministic execution enables low-overhead, highly-parallel scheduling mechanisms, that can address the performance limitations of existing database systems on modern hardware. Deterministic database systems are designed based on the assumption that applications can submit their transactions in one-shot prepared transactions, instead of multiple round-trips. Finally, we attempt to understand the fundamental reason for the observed performance differences between various consistency levels in database systems, and based on this understanding, show that we can exploit deterministic execution to provide strong consistency at a cost that is competitive with that offered by weak consistency levels.

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Grosic, Hasan, and Emir Hasanovic. "Optimizing Inter-core Data-propagation Delays in Multi-core Embedded Systems." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-44770.

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The demand for computing power and performance in real-time embedded systems is continuously increasing since new customer requirements and more advanced features are appearing every day. To support these functionalities and handle them in a more efficient way, multi-core computing platforms are introduced. These platforms allow for parallel execution of tasks on multiple cores, which in addition to its benefits to the system's performance introduces a major problem regarding the timing predictability of the system. That problem is reflected in unpredictable inter-core interferences, which occur due to shared resources among the cores, such as the system bus. This thesis investigates the application of different optimization techniques for the offline scheduling of tasks on the individual cores, together with a global scheduling policy for the access to the shared bus. The main effort of this thesis focuses on optimizing the inter-core data propagation delays which can provide a new way of creating optimized schedules. For that purpose, Constraint Programming optimization techniques are employed and a Phased Execution Model of the tasks is assumed. Also, in order to enforce end-to-end timing constraints that are imposed on the system, job-level dependencies are generated prior and subsequently applied during the scheduling procedure. Finally, an experiment with a large number of test cases is conducted to evaluate the performance of the implemented scheduling approach. The obtained results show that the method is applicable for a wide spectrum of abstract systems with variable requirements, but also open for further improvement in several aspects.
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Li, Pei. "Unified system of code transformation and execution for heterogeneous multi-core architectures." Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0441/document.

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Architectures hétérogènes sont largement utilisées dans le domaine de calcul haute performance. Cependant, le développement d'applications sur des architectures hétérogènes est indéniablement fastidieuse et sujette à erreur pour un programmeur même expérimenté. Pour passer une application aux architectures multi-cœurs hétérogènes, les développeurs doivent décomposer les données de l'entrée, gérer les échanges de valeur intermédiaire au moment d’exécution et garantir l'équilibre de charge de système. L'objectif de cette thèse est de proposer une solution de programmation parallèle pour les programmeurs novices, qui permet de faciliter le processus de codage et garantir la qualité de code. Nous avons comparé et analysé les défauts de solutions existantes, puis nous proposons un nouvel outil de programmation STEPOCL avec un nouveau langage de domaine spécifique qui est conçu pour simplifier la programmation sur les architectures hétérogènes. Nous avons évalué la performance de STEPOCL sur trois cas d'application classiques : un stencil 2D, une multiplication de matrices et un problème à N corps. Le résultat montre que : (i) avec l'aide de STEPOCL, la performance d'application varie linéairement selon le nombre d'accélérateurs, (ii) la performance de code généré par STEPOCL est comparable à celle de la version manuscrite. (iii) les charges de travail, qui sont trop grandes pour la mémoire d'un seul accélérateur, peuvent être exécutées en utilisant plusieurs accélérateurs. (iv) grâce à STEPOCL, le nombre de lignes de code manuscrite est considérablement réduit
Heterogeneous architectures have been widely used in the domain of high performance computing. However developing applications on heterogeneous architectures is time consuming and error-prone because going from a single accelerator to multiple ones indeed requires to deal with potentially non-uniform domain decomposition, inter-accelerator data movements, and dynamic load balancing. The aim of this thesis is to propose a solution of parallel programming for novice developers, to ease the complex coding process and guarantee the quality of code. We lighted and analysed the shortcomings of existing solutions and proposed a new programming tool called STEPOCL along with a new domain specific language designed to simplify the development of an application for heterogeneous architectures. We evaluated both the performance and the usefulness of STEPOCL. The result show that: (i) the performance of an application written with STEPOCL scales linearly with the number of accelerators, (ii) the performance of an application written using STEPOCL competes with an handwritten version, (iii) larger workloads run on multiple devices that do not fit in the memory of a single device, (iv) thanks to STEPOCL, the number of lines of code required to write an application for multiple accelerators is roughly divided by ten
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Gustavsson, Andreas. "Static Execution Time Analysis of Parallel Systems." Doctoral thesis, Mälardalens högskola, Inbyggda system, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-31399.

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The past trend of increasing processor throughput by increasing the clock frequency and the instruction level parallelism is no longer feasible due to extensive power consumption and heat dissipation. Therefore, the current trend in computer hardware design is to expose explicit parallelism to the software level. This is most often done using multiple, relatively slow and simple, processing cores situated on a single processor chip. The cores usually share some resources on the chip, such as some level of cache memory (which means that they also share the interconnect, e.g., a bus, to that memory and also all higher levels of memory). To fully exploit this type of parallel processor chip, programs running on it will have to be concurrent. Since multi-core processors are the new standard, even embedded real-time systems will (and some already do) incorporate this kind of processor and concurrent code. A real-time system is any system whose correctness is dependent both on its functional and temporal behavior. For some real-time systems, a failure to meet the temporal requirements can have catastrophic consequences. Therefore, it is crucial that methods to derive safe estimations on the timing properties of parallel computer systems are developed, if at all possible. This thesis presents a method to derive safe (lower and upper) bounds on the execution time of a given parallel system, thus showing that such methods must exist. The interface to the method is a small concurrent programming language, based on communicating and synchronizing threads, that is formally (syntactically and semantically) defined in the thesis. The method is based on abstract execution, which is itself based on abstract interpretation techniques that have been commonly used within the field of timing analysis of single-core computer systems, to derive safe timing bounds in an efficient (although, over-approximative) way. The thesis also proves the soundness of the presented method (i.e., that the estimated timing bounds are indeed safe) and evaluates a prototype implementation of it.
Den strategi som historiskt sett använts för att öka processorers prestanda (genom ökad klockfrekvens och ökad instruktionsnivåparallellism) är inte längre hållbar på grund av den ökade energikonsumtion som krävs. Därför är den nuvarande trenden inom processordesign att låta mjukvaran påverka det parallella exekveringsbeteendet. Detta görs vanligtvis genom att placera multipla processorkärnor på ett och samma processorchip. Kärnorna delar vanligtvis på några av processorchipets resurser, såsom cache-minne (och därmed också det nätverk, till exempel en buss, som ansluter kärnorna till detta minne, samt alla minnen på högre nivåer). För att utnyttja all den prestanda som denna typ av processorer erbjuder så måste mjukvaran som körs på dem kunna delas upp över de tillgängliga kärnorna. Eftersom flerkärniga processorer är standard idag så måste även realtidssystem baseras på dessa och den nämnda typen av kod.  Ett realtidssystem är ett datorsystem som måste vara både funktionellt och tidsmässigt korrekt. För vissa typer av realtidssystem kan ett inkorrekt tidsmässigt beteende ha katastrofala följder. Därför är det ytterst viktigt att metoder för att analysera och beräkna säkra gränser för det tidsmässiga beteendet hos parallella datorsystem tas fram. Denna avhandling presenterar en metod för att beräkna säkra gränser för exekveringstiden hos ett givet parallellt system, och visar därmed att sådana metoder existerar. Gränssnittet till metoden är ett litet formellt definierat trådat programmeringsspråk där trådarna tillåts kommunicera och synkronisera med varandra. Metoden baseras på abstrakt exekvering för att effektivt beräkna de säkra (men ofta överskattade) gränserna för exekveringstiden. Abstrakt exekvering baseras i sin tur på abstrakta interpreteringstekniker som vida används inom tidsanalys av sekventiella datorsystem. Avhandlingen bevisar även korrektheten hos den presenterade metoden (det vill säga att de beräknade gränserna för det analyserade systemets exekveringstid är säkra) och utvärderar en prototypimplementation av den.
Worst-Case Execution Time Analysis of Parallel Systems
RALF3 - Software for Embedded High Performance Architectures
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Gustavsson, Andreas. "Static Timing Analysis of Parallel Systems Using Abstract Execution." Licentiate thesis, Mälardalens högskola, Inbyggda system, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-26125.

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The Power Wall has stopped the past trend of increasing processor throughput by increasing the clock frequency and the instruction level parallelism.Therefore, the current trend in computer hardware design is to expose explicit parallelism to the software level.This is most often done using multiple processing cores situated on a single processor chip.The cores usually share some resources on the chip, such as some level of cache memory (which means that they also share the interconnect, e.g. a bus, to that memory and also all higher levels of memory), and to fully exploit this type of parallel processor chip, programs running on it will have to be concurrent.Since multi-core processors are the new standard, even embedded real-time systems will (and some already do) incorporate this kind of processor and concurrent code. A real-time system is any system whose correctness is dependent both on its functional and temporal output. For some real-time systems, a failure to meet the temporal requirements can have catastrophic consequences. Therefore, it is of utmost importance that methods to analyze and derive safe estimations on the timing properties of parallel computer systems are developed. This thesis presents an analysis that derives safe (lower and upper) bounds on the execution time of a given parallel system.The interface to the analysis is a small concurrent programming language, based on communicating and synchronizing threads, that is formally (syntactically and semantically) defined in the thesis.The analysis is based on abstract execution, which is itself based on abstract interpretation techniques that have been commonly used within the field of timing analysis of single-core computer systems, to derive safe timing bounds in an efficient (although, over-approximative) way.Basically, abstract execution simulates the execution of several real executions of the analyzed program in one go.The thesis also proves the soundness of the presented analysis (i.e. that the estimated timing bounds are indeed safe) and includes some examples, each showing different features or characteristics of the analysis.
Worst-Case Execution Time Analysis of Parallel Systems
RALF3 - Software for Embedded High Performance Architectures
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Nowotsch, Jan [Verfasser], and Theo [Akademischer Betreuer] Ungerer. "Interference-sensitive Worst-case Execution Time Analysis for Multi-core Processors / Jan Nowotsch. Betreuer: Theo Ungerer." Augsburg : Universität Augsburg, 2014. http://d-nb.info/1077704410/34.

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Bin, Jingyi. "Controlling execution time variability using COTS for Safety-critical systems." Phd thesis, Université Paris Sud - Paris XI, 2014. http://tel.archives-ouvertes.fr/tel-01061936.

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While relying during the last decade on single-core Commercial Off-The-Shelf (COTS) architectures despite their inherent runtime variability, the safety critical industry is now considering a shift to multi-core COTS in order to match the increasing performance requirement. However, the shift to multi-core COTS worsens the runtime variability issue due to the contention on shared hardware resources. Standard techniques to handle this variability such as resource over-provisioning cannot be applied to multi-cores as additional safety margins will offset most if not all the multi-core performance gains. A possible solution would be to capture the behavior of potential contention mechanisms on shared hardware resources relatively to each application co-running on the system. However, the features on contention mechanisms are usually very poorly documented. In this thesis, we introduce measurement techniques based on a set of dedicated stressing benchmarks and architecture hardware monitors to characterize (1) the architecture, by identifying the shared hardware resources and revealing their associated contention mechanisms. (2) the applications, by learning how they behave relatively to shared resources. Based on such information, we propose a technique to estimate the WCET of an application in a pre-determined co-running context by simulating the worst case contention on shared resources produced by the application's co-runners.
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Kumar, Vijay Shiv. "Specification, Configuration and Execution of Data-intensive Scientific Applications." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1286570224.

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Haas, Florian [Verfasser], and Theo [Akademischer Betreuer] Ungerer. "Fault-tolerant Execution of Parallel Applications on x86 Multi-core Processors with Hardware Transactional Memory / Florian Haas ; Betreuer: Theo Ungerer." Augsburg : Universität Augsburg, 2019. http://d-nb.info/1194312942/34.

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Haur, Imane. "AUTOSAR compliant multi-core RTOS formal modeling and verification." Electronic Thesis or Diss., Ecole centrale de Nantes, 2022. http://www.theses.fr/2022ECDN0057.

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La vérification formelle est une solution pour augmenter la fiabilité de l’implémentation du système. Dans notre travail de thèse, nous nous intéressons à l’utilisation de ces méthodes pour la vérification des systèmes d’exploitation multi-coeurs temps réel. Nous proposons une approche de model-checking utilisant les réseaux de Petri temporels, étendus avec des transitions colorées et des fonctionnalités de haut niveau. Nous utilisons ce formalisme pour modéliser le système d’exploitation multi-coeur Trampoline, conforme aux standards OSEK/VDX etAUTOSAR. Nous définissons dans un premier temps ce formalisme et montrons son adéquation avec la modélisation de systèmes concurrents temps reel. Nous utilisons ensuite ce formalisme pour modéliser le système d’exploitation multi-coeur Trampoline et vérifions par model-checking sa conformité avec le standard AUTOSAR. À partir de ce modèle, nous pouvons vérifier des propriétés aussi bien sur l’OS que sur l’application telles que l’ordonnançabilité d’un système tempsréel ainsi que les mécanismes de synchronisation : accès concurrents aux structures de données du système d’exploitation, ordonnancement multi-coeur et traitement des interruptions inter-coeur. À titre d’illustration, cette méthode a permis l’identification automatique de deux erreurs possibles de l’OS Trampoline dans l’exécution concurrente, montrant une protection insuffisante des données et une synchronisation défectueuse
Formal verification is a solution to increase the system’s implementation reliability. In our thesis work, we are interestedin using these methods to verify multi-core RTOS. We propose a model-checking approach using time Petri nets extended with colored transitions and high-level features. We use this formalism to model the Trampoline multi-core OS, compliant with the OSEK/VDX and AUTOSAR standards. We first define this formalism and show its suitability for modeling real-time concurrent systems. We then use this formalism to model the Trampoline multi-core RTOS and verify by model-checkingits conformity with the AUTOSAR standard. From this model, we can verify properties of both the OS and the application, such as the schedulability of a real-time system and the synchronization mechanisms: concurrent access to the data structures of the OS, multicore scheduling, and inter-core interrupt handling. As an illustration, this method allowed the automatic identification of two possible errors of the Trampoline OS in concurrent execution, showing insufficient data protection andfaulty synchronization
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Book chapters on the topic "Multi-core execution"

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Muresano, Ronal, Dolores Rexachs, and Emilio Luque. "An Approach for Efficient Execution of SPMD Applications on Multicore Clusters." In Programming multi-core and many-core computing systems, 431–50. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2017. http://dx.doi.org/10.1002/9781119332015.ch21.

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Lee, Sungju, Heegon Kim, and Yongwha Chung. "Power-Time Tradeoff of Parallel Execution on Multi-core Platforms." In Lecture Notes in Electrical Engineering, 157–63. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-642-40675-1_25.

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Huang, Shiang, Jer-Min Jou, Cheng-Hung Hsieh, and Ding-Yuan Lin. "Design of a Dynamic Parallel Execution Architecture for Multi-core Systems." In Advances in Intelligent Systems and Applications - Volume 2, 731–40. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-35473-1_72.

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Grass, Thomas, Alejandro Rico, Marc Casas, Miquel Moreto, and Alex Ramirez. "Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors." In Lecture Notes in Computer Science, 218–29. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-14313-2_19.

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Seo, Dongyou, Myungsun Kim, Hyeonsang Eom, and Heon Y. Yeom. "Bubble Task: A Dynamic Execution Throttling Method for Multi-core Resource Management." In Job Scheduling Strategies for Parallel Processing, 1–16. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-15789-4_1.

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Suraj, R., P. Chitra, and S. Madumidha. "Evaluation of Worst-Case Execution Time of Tasks on Multi-core Processor." In Advances in Intelligent Systems and Computing, 441–48. New Delhi: Springer India, 2014. http://dx.doi.org/10.1007/978-81-322-2135-7_47.

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Chang, Wen-Hsien, Jer-Min Jou, Cheng-Hung Hsieh, and Ding-Yuan Lin. "A Distributed Run-Time Dynamic Data Manager for Multi-core System Parallel Execution." In Advances in Intelligent Systems and Applications - Volume 2, 741–50. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-35473-1_73.

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Haas, Florian, Sebastian Weis, Theo Ungerer, Gilles Pokam, and Youfeng Wu. "Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support." In Architecture of Computing Systems - ARCS 2017, 16–30. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-54999-6_2.

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Prabhakar, Raghu, R. Govindarajan, and Matthew J. Thazhuthaveetil. "CUDA-For-Clusters: A System for Efficient Execution of CUDA Kernels on Multi-core Clusters." In Euro-Par 2012 Parallel Processing, 415–26. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-32820-6_42.

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Li, Ying, Jianwei Niu, Jiong Zhang, Mohammed Atiquzzaman, and Xiang Long. "Real-Time Scheduling for Periodic Tasks in Homogeneous Multi-core System with Minimum Execution Time." In Collaborate Computing: Networking, Applications and Worksharing, 175–87. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59288-6_16.

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Conference papers on the topic "Multi-core execution"

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Yuan, Simon, Li Hsien Yoong, and Partha S. Roop. "Compiling Esterel for Multi-core Execution." In 2011 14th Euromicro Conference on Digital System Design (DSD). IEEE, 2011. http://dx.doi.org/10.1109/dsd.2011.97.

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Sgroi, Kevin J., and Scott E. Spetka. "Analysis of Multi-Threaded Code Execution on Small Multi-Core Architectures." In ASME 2010 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2010. http://dx.doi.org/10.1115/detc2010-29135.

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Abstract:
Utilizing threads and other parallel execution techniques efficiently to achieve concurrency on multiple processors/cores is becoming more difficult as the complexity of engineering applications increases. While hardware performance and scalability in this environment have been well-studied, software and operating system aspects of parallel code execution deserve additional attention. This is especially the case for smaller multi-core architectures such as those found in desktop computers. A matrix-multiply application has been customized to generate a multi-threaded load for testing, to address issues associated with mixing a multi-threaded load with available Linux benchmarking tools. This application was executed with the UNIXBENCH benchmark test suite in this study to conduct experiments designed to reveal problem areas that should be considered when implementing applications on modern parallel computing architectures. The analysis covers five types of operations: CPU intensive, Inter-process communication with pipes, shell script execution, file I/O and System call overhead. The results indicate that shell script execution, file I/O and system call overhead had the most degradation in performance as the multi-threaded load was increased. Pipe-based communication (directly between processes) and CPU intensive operations tended to scale well as the load increased.
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Inam, Rafia, Nesredin Mahmud, Moris Behnam, Thomas Nolte, and Mikael Sjodin. "The Multi-Resource Server for predictable execution on multi-core platforms." In 2014 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 2014. http://dx.doi.org/10.1109/rtas.2014.6925986.

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Suleman, M. Aater, Onur Mutlu, Moinuddin K. Qureshi, and Yale N. Patt. "Accelerating critical section execution with asymmetric multi-core architectures." In Proceeding of the 14th international conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1508244.1508274.

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hayakawa, Kiyoshi, and Ryusuke Yamano. "Multi-core FPGA Execution for Electromagnetic Simulation by FDTD." In 2015 2nd International Conference on Information Science and Control Engineering (ICISCE). IEEE, 2015. http://dx.doi.org/10.1109/icisce.2015.189.

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Camp, David, E. Wes Bethel, and Hank Childs. "Transitioning Data Flow-Based Visualization Software to Multi-core Hybrid Parallelism." In 2013 Data-Flow Execution Models for Extreme Scale Computing (DFM). IEEE, 2013. http://dx.doi.org/10.1109/dfm.2013.12.

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Schuele, T. "Efficient parallel execution of streaming applications on multi-core processors." In 19th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2011). IEEE, 2011. http://dx.doi.org/10.1109/pdp.2011.48.

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Dennis, Jack B. "On the Feasibility of a Codelet Based Multi-core Operating System." In 2014 Fourth Workshop on Data-Flow Execution Models for Extreme Scale Computing. IEEE, 2014. http://dx.doi.org/10.1109/dfm.2014.18.

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Salamat, Babak, Andreas Gal, Todd Jackson, Karthikeyan Manivannan, Gregor Wagner, and Michael Franz. "Multi-variant Program Execution: Using Multi-core Systems to Defuse Buffer-Overflow Vulnerabilities." In 2008 International Conference on Complex, Intelligent and Software Intensive Systems. IEEE, 2008. http://dx.doi.org/10.1109/cisis.2008.136.

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Ho, Nam, Andrea Mondelli, Alberto Scionti, Marco Solinas, Antoni Portero, and Roberto Giorgi. "Enhancing an x86_64 multi-core architecture with data-flow execution support." In CF'15: Computing Frontiers Conference. New York, NY, USA: ACM, 2015. http://dx.doi.org/10.1145/2742854.2742896.

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