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Relevant bibliographies by topics / Multi-core configuration

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Academic literature on the topic 'Multi-core configuration'

Author: Grafiati

Published: 30 May 2022

Last updated: 31 July 2025

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Journal articles on the topic "Multi-core configuration"

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Zhang, Sheng Wen, and Xuan Peng Wang. "Configuration of Multi-Tenant Applications." Advanced Materials Research 219-220 (March 2011): 1182–85. http://dx.doi.org/10.4028/www.scientific.net/amr.219-220.1182.

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SaaS (Software as a Service) application mode came into being along with the expansion and convenient of the network platform, and its core lies in Multi-Tenant (multi-tenant) application. Multi-Tenant Application under the SaaS model makes software applications efficient and convenient, more importantly, tenants can greatly reduce their software development costs, hardware acquisition costs, training costs, and upgrade and maintenance costs by using the application system, which virtually eased business cost pressures and makes more focus on business development. This paper elaborates the per

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Levieux, Sébastien, Frank Singhoff, Stéphane Rubini, et al. "An Iterative Benchmark Configuration Method forQuantifying Multi-core Interference." ACM SIGAda Ada Letters 44, no. 1 (2024): 78–84. https://doi.org/10.1145/3706601.3706615.

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Interference within a multi-core architecture may have several origins. Understanding where interference comes from is mandatory for verification and certification purposes. Unfortunately, the complexity of current architectures makes it difficult to quantify such interference. In this article, a new approach is introduced that enables benchmark configurations to isolate and quantify interference. An experiment with DMA interference is presented and shows a WCET overhead of up to 0.26% at 25 Mbit/s. This experiment was also able to discover and identify interference related to DMA, such as int

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Fan, Kaijie, Biagio Cosenza, and Ben Juurlink. "Accurate Energy and Performance Prediction for Frequency-Scaled GPU Kernels." Computation 8, no. 2 (2020): 37. http://dx.doi.org/10.3390/computation8020037.

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Energy optimization is an increasingly important aspect of today’s high-performance computing applications. In particular, dynamic voltage and frequency scaling (DVFS) has become a widely adopted solution to balance performance and energy consumption, and hardware vendors provide management libraries that allow the programmer to change both memory and core frequencies manually to minimize energy consumption while maximizing performance. This article focuses on modeling the energy consumption and speedup of GPU applications while using different frequency configurations. The task is not straigh

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Israr, Haris Ahmad, Teh Soo Chwen, Ainullotfi Abd Latif, et al. "Preliminary Structural Design of Coreless Spoiler by Topological Optimization." Processes 10, no. 10 (2022): 2076. http://dx.doi.org/10.3390/pr10102076.

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Most spoilers are made from a sandwich structure with a honeycomb component as its core. However, the honeycomb core is sensitive to water ingress, causing damage to the control surface due to its weak moisture-resistance behavior. This study aimed to conduct the design and analysis of an improved composite structure for a coreless spoiler. A spoiler design of an aircraft, the A320, was used for the case study. The weaknesses of a coreless spoiler were identified through finite element analysis via Abaqus software. Multi-spar and multi-rib designs were studied and compared for topological opti

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Sun, Jiang, Ju Long Lan, and Yu Feng Li. "Reseach and Implementation of Packet Capture Based on Multi-Core Binding Technology in Linux Environment." Applied Mechanics and Materials 48-49 (February 2011): 902–5. http://dx.doi.org/10.4028/www.scientific.net/amm.48-49.902.

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According to zero-copy idea and the application of multi-core binding to realize a high-performance packet capture platform based on multi-core binding(MCPCP).By modifying the memory management mode about sk_buff in kernel,realize the user space program to directly access the data packet, which is a kind of universal significance of the zero-copy scheme. And then through the multi-core binding technique, for each CPU core scheduling and control, with multi-threaded user programs can minimize the cache jitter to improve the efficiency of packet capture. Experiments show that in the case of low-

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Lorenti, Gianmarco, Carlo Stefano Ragusa, Maurizio Repetto, and Luigi Solimene. "Data-Driven Constraint Handling in Multi-Objective Inductor Design." Electronics 12, no. 4 (2023): 781. http://dx.doi.org/10.3390/electronics12040781.

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This paper analyses the multi-objective design of an inductor for a DC-DC buck converter. The core volume and total losses are the two competing objectives, which should be minimised while satisfying the design constraints on the required differential inductance profile and the maximum overheating. The multi-objective optimisation problem is solved by means of a population-based metaheuristic algorithm based on Artificial Immune Systems (AIS). Despite its effectiveness in finding the Pareto front, the algorithm requires the evaluation of many candidate solutions before converging. In the case

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Wang, Dong. "The Study of Multi-Tenant's Configurability." Modern Electronic Technology 1, no. 1 (2017): 24. http://dx.doi.org/10.26549/met.v1i1.326.

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SaaS (Software as a Service)the application mode occurs exactly along with the broadening and convenience of network platform, its core is the application of Multi-Tenant. The Multi-Tenant under SaaS not only makes Application Software more efficient and convenient, but also reduce the cost of software development, hardware purchase, training and upgrade maintenance, which can relieve the financial pressure of enterprises invisibly, so that enterprises can focus on the business development. Aiming at the personalized demand of Multi-Tenant's tenement, this thesis studies about personalized con

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Liang, Yu, Yihui Yan, and Huiyuan Guan. "Middle school classroom furniture evaluation model based on combinatorial weighting of game theory." BioResources 20, no. 2 (2025): 3971–95. https://doi.org/10.15376/biores.20.2.3971-3995.

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Within the context of educational innovation, diversified teaching models impose higher requirements on classroom furniture adaptability. However, conflicting multi-stakeholder demands and configuration imbalances constrain the upgrading of educational spaces. To address this, this study focuses on the “demand-configuration” contradiction and constructs a composite evaluation model integrating the “game theory combined weighting method – fuzzy comprehensive evaluation method – quadrant diagram model”. Through improved Analytic Hierarchy Process (AHP) and entropy method game weighting, this app

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Coutinho Demetrios, A. M., Daniele De Sensi, Arthur Francisco Lorenzon, et al. "Performance and Energy Trade-Offs for Parallel Applications on Heterogeneous Multi-Processing Systems." Energies 13, no. 9 (2020): 2409. http://dx.doi.org/10.3390/en13092409.

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This work proposes a methodology to find performance and energy trade-offs for parallel applications running on Heterogeneous Multi-Processing systems with a single instruction-set architecture. These offer flexibility in the form of different core types and voltage and frequency pairings, defining a vast design space to explore. Therefore, for a given application, choosing a configuration that optimizes the performance and energy consumption is not straightforward. Our method proposes novel analytical models for performance and power consumption whose parameters can be fitted using only a few

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Scharf, Oliver, and Gediminas Gaigalas. "Large scale multi-configuration Hartree-Fock calculation of the hyperfine structure of the ground state of vanadium." Open Physics 4, no. 1 (2006): 42–57. http://dx.doi.org/10.1007/s11534-005-0005-7.

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AbstractThe hyperfine structure of the ground state of vanadium, 51VI, is calculated in the nonrelativistic framework of the multi-configuration Hartree-Fock approximation. A configuration state function limiting algorithm is used to make the calculations feasible and to study the influence of core, valence and core-valence correlations in detail. The obtained configuration state function space captures the most important orbital correlations within 2%. Further correlations are included through configuration interaction calculation. The atomic state functions are used to evaluate the magnetic

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Dissertations / Theses on the topic "Multi-core configuration"

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Kumar, Vijay Shiv. "Specification, Configuration and Execution of Data-intensive Scientific Applications." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1286570224.

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Кочерга, Олександр Іванович. "Підвищення ефективності лінійних імпульсних електромеханічних перетворювачів за рахунок мультиякірних конфігурацій". Thesis, Національний технічний університет "Харківський політехнічний інститут", 2020. http://repository.kpi.kharkov.ua/handle/KhPI-Press/49201.

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Дисертація на здобуття наукового ступеня кандидата технічних наук за спеціальністю 05.09.01 "Електричні машини й апарати" (14 – Електрична інженерія) – Національний технічний університет "Харківський політехнічний інститут", м. Харків, 2020 р. Дисертаційна робота присвячена удосконаленню лінійних імпульсних електромеханічних перетворювачів силового та швидкісного призначення за рахунок використання декількох якорів, що взаємодіють з обмоткою індуктора. В дисертаційній роботі проведено аналіз конструкцій та сфер використання лінійних імпульсних електромеханічних перетворювачів індукційного, ел

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Book chapters on the topic "Multi-core configuration"

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Suárez, Daniel, Francisco Almeida, Vicente Blanco, and Pedro Toledo. "Containerization for Heterogeneous and Hybrid Parallelism." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-90200-0_36.

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Abstract This paper investigates the viability and efficiency of parameter search for machine learning (ML) pipelines through containerization in diverse computational environments. We leverage parallelization by executing each test in the grid search as an independent container, allowing for scalable and efficient parameter tuning. Our study encompasses a detailed comparison of energy efficiency, power consumption, and execution times between two distinct setups. The first setup comprises a cluster of eight Raspberry Pi Compute Module 4 units integrated into two Turing Pi boards, each housing

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Xiang, Yang, and Daxin Tian. "Multi-Core Supported Deep Packet Inspection." In Handbook of Research on Scalable Computing Technologies. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-661-7.ch037.

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Network security applications such as intrusion detection systems (IDSs), firewalls, anti-virus/spyware systems, anti-spam systems, and security visualisation applications are all computing-intensive applications. These applications all heavily rely on deep packet inspection, which is to examine the content of each network packet’s payload. Today these security applications cannot cope with the speed of broadband Internet that has already been deployed, that is, the processor power is much slower than the bandwidth power. Recently the development of multi-core processors brings more processing

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Allande César, Jorba Josep, Sikora Anna, and César Eduardo. "Performance model based on memory footprint for OpenMP memory bound applications." In Advances in Parallel Computing. IOS Press, 2016. https://doi.org/10.3233/978-1-61499-621-7-73.

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Performance of memory intensive applications executed on multi-core multi-socket environments is closely related to the utilization of shared resources in the memory hierarchy. Depending on the characteristics of the application, the shared resources utilization can lead to a significant performance degradation. The exploration of different thread affinity configurations allows the selection of a proper configuration that balances the performance improvement obtained by increasing parallelism with the performance degradation due to memory contention. However, as the number of cores per process

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"Topology-Aware Load-Balance Schemes for Heterogeneous Graph Processing." In Advances in Computer and Electrical Engineering. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-3799-1.ch005.

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Inspired by the insights presented in Chapters 2, 3, and 4, in this chapter the authors present the KCMAX (K-Core MAX) and the KCML (K-Core Multi-Level) frameworks: novel k-core-based graph partitioning approaches that produce unbalanced partitions of complex networks that are suitable for heterogeneous parallel processing. Then they use KCMAX and KCML to explore the configuration space for accelerating BFSs on large complex networks in the context of TOTEM, a BSP heterogeneous GPU + CPU HPC platform. They study the feasibility of the heterogeneous computing approach by systematically studying

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Pinto, Pedro, António Alberto Pinto, and Manuel Ricardo. "Reducing Simulation Runtime in Wireless Sensor Networks." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-8823-0.ch024.

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Wireless Sensor Networks (WSNs) can be deployed using available hardware and software. The Contiki is an operative system compatible with a wide range of WSN hardware. A Contiki development environment named InstantContiki is also available and includes the Cooja simulator, useful to test WSN simulation scenarios prior to their deployment. Cooja can provide realistic results since it uses the full Contiki's source code and some motes can be emulated at the hardware level. However this implies extending the simulation runtime, which is heightened since the Cooja is single threaded, i.e, it make

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Benkner Siegfried, Pllana Sabri, Larsson Träff Jesper, et al. "The PEPPHER Approach to Programmability and Performance Portability for Heterogeneous many-core Architectures." In Advances in Parallel Computing. IOS Press, 2012. https://doi.org/10.3233/978-1-61499-041-3-361.

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The European FP7 project PEPPHER is addressing programmability and performance portability for current and emerging heterogeneous many-core architectures. As its main idea, the project proposes a multi-level parallel execution model comprised of potentially parallelized components existing in variants suitable for different types of cores, memory configurations, input characteristics, optimization criteria, and couples this with dynamic and static resource and architecture aware scheduling mechanisms. Crucial to PEPPHER is that components can be made performance aware, allowing for more effici

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Mohanty, Ram Prasad, Ashok Kumar Turuk, and Bibhudatta Sahoo. "Designing of High Performance Multicore Processor with Improved Cache Configuration and Interconnect." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-8853-7.ch009.

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The growing number of cores increases the demand for a powerful memory subsystem which leads to enhancement in the size of caches in multicore processors. Caches are responsible for giving processing elements a faster, higher bandwidth local memory to work with. In this chapter, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN) referenced from NIAGRA architecture. As the number of core's increases, traditional on-chip interconnects like bus and crossbar pro

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LeDonne, John P. "Client States and Societies." In The Grand Strategy of the Russian Empire, 1650-1831. Oxford University PressNew York, NY, 2003. http://dx.doi.org/10.1093/oso/9780195161007.003.0004.

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Abstract Russian grand strategy was an essentially political concept, recognizing no dis-continuity between peace and wartime. The decisions that shaped it proceeded from a consensus worked out among the ruling elite not only on military and economic policy but also on diplomatic relations with neighboring territories. Most of those territories were found within the Heartland. Some were core areas, others were frontiers between them and Russia. Russia’s diplomatic vision was largely confined to the Heartland. Muscovy and the empire—even if the term empire did not come into official use until P

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Venkatesha, Shashikiran, and Ranjani Parthasarathi. "Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core Systems." In Fault Tolerance [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.102823.

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Billions of transistors on a chip have led to integration of many cores leading to many challenges such as increased power dissipation, thermal dissipation, occurrence of faults in the circuits, and reliability issues. Existing approaches explore the usage of redundancy-based solutions for fault tolerance at core level, thread level, micro-architectural level, and software level. Core-level techniques improve the lifetime reliability of multi-core systems with asymmetric cores (large and small cores), which have gained momentum and focus among a large number of researchers. Based on the above

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Isaac, Bikash Ranjan, Prayash Mallick, and Vijayamohanan K. Pillai. "Multifunctional Electrocatalysis: Fundamentals and Future Directions." In Multi-functional Electrocatalysts. Royal Society of Chemistry, 2024. http://dx.doi.org/10.1039/9781837674497-00001.

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Electrocatalysis is a vibrant field of chemistry, materials science, and energy technology since electrochemical processes promote the enhanced efficiency of various applications, ranging from electrolysers and fuel cells for energy storage devices to the electro-organic synthesis of many important drugs and intermediates. This chapter provides a comprehensive overview of core electrochemical concepts in electrocatalysis, elucidating the interplay of various multifunctional sites and intermediates. Furthermore, the role of the electrocatalyst is explained in terms of the reaction kinetics and

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Conference papers on the topic "Multi-core configuration"

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Lin, Guoying, Lai Zhou, Hangchen Liu, and Guan Chen. "Multi-Core Module Configuration Model Considering “Cloud-Edge-End-Core” Collaborative Efficiency Optimization." In 2024 China International Conference on Electricity Distribution (CICED). IEEE, 2024. http://dx.doi.org/10.1109/ciced63421.2024.10753880.

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Lee, Younghyun, Hyejun Kim, Yongseung Yu, Myeongjin Cho, Jiwon Seo, and Yongjun Park. "Discovering Efficient Fused Layer Configurations for Executing Multi-Workloads on Multi-Core NPUs." In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2024. http://dx.doi.org/10.23919/date58400.2024.10546719.

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Littell, Justin, Michael Seal, Edwin Fasanella, Karen Jackson, and Martin Annett. "The Development of Two Composite Energy Absorbers for Use in a Transport Rotorcraft Airframe Crash Testbed (TRACT 2) Full-Scale Crash Test." In Vertical Flight Society 71st Annual Forum & Technology Display. The Vertical Flight Society, 2015. http://dx.doi.org/10.4050/f-0071-2015-10141.

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Two composite energy absorbers were developed and evaluated at NASA Langley Research Center through multi-level testing and simulation performed under the Transport Rotorcraft Airframe Crash Testbed (TRACT) research program. A conical-shaped energy absorber, designated the conusoid, was evaluated that consisted of four layers of hybrid carbon-Kevlar® plain weave fabric oriented at [+45°°/-45°/-45°/+45°] with respect to the vertical direction. A sinusoidal-shaped energy absorber, designated the sinusoid, was developed that consisted of hybrid carbon-Kevlar® plain weave fabric face sheets, two l

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Kim, Sung Hoon, Jung Su Kim, Dian Nugraha, Vincent Wan, and Il Hong Suh. "Automotive ADAS Camera System Configuration Using Multi-Core Microcontroller." In 18th Asia Pacific Automotive Engineering Conference. SAE International, 2015. http://dx.doi.org/10.4271/2015-01-0023.

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Aldoumani, M., T. Meydan, and Williams P. I. Wolfson. "A planar coil fluxgate magnetometer using multi-core configuration." In 2015 IEEE Sensors. IEEE, 2015. http://dx.doi.org/10.1109/icsens.2015.7370196.

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Gharajeh, Mohammad Samadi, Tiago Carvalho, and Luis Miguel Pinho. "Configuration of Parallel Real-Time Applications on Multi-Core Processors." In 2022 IEEE 20th International Conference on Industrial Informatics (INDIN). IEEE, 2022. http://dx.doi.org/10.1109/indin51773.2022.9976163.

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Shota, Oe, Haisong Jiang, and Kiichi Hamamoto. "Proposal of 128ch coupled multi-core fiber configuration using coil-shape (MCF)." In 2015 20th Microoptics Conference (MOC). IEEE, 2015. http://dx.doi.org/10.1109/moc.2015.7416520.

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Ichikawa, Shuichi, and Shoichiro Takagi. "Estimating the Optimal Configuration of a Multi-Core Cluster: A Preliminary Study." In 2009 International Conference on Complex, Intelligent and Software Intensive Systems (CISIS). IEEE, 2009. http://dx.doi.org/10.1109/cisis.2009.108.

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Sun Jing and Sun Jian. "Implementation of Volume Rendering Technique Based on VTK Parallelism in Multi-core Configuration." In Third International Conference on Information and Computing Science (ICIC 2010). IEEE, 2010. http://dx.doi.org/10.1109/icic.2010.87.

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Wen-Yen Tsai, Nen-Fu Huang, and Hsien-Wei Hung. "A port-configuration assisted NIC IRQ affinitization scheme for multi-core packet forwarding applications." In GLOBECOM 2012 - 2012 IEEE Global Communications Conference. IEEE, 2012. http://dx.doi.org/10.1109/glocom.2012.6503500.

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