Journal articles: 'MOSFETs'

1

Funaki, Tsuyoshi, Yuki Nakano, and Takashi Nakamura. "Comparative Study of SiC MOSFETs in High Voltage Switching Operation." Materials Science Forum 717-720 (May 2012): 1081–84. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1081.

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SiC power device is expected to have high breakdown voltage with low on resistance, which cannot be attainable for conventional Si device. This study evaluates the switching performance of high voltage SiC MOSFETs with comparing to that of conventional Si power MOSFET having equivalent breakdown voltage. To this end, turn-on and turn-off switching operation of MOSFETs are assessed with resistive load for same conduction current density. Though the on resistance of SiC MOSFETs are quite lower than Si MOSFET, especially for trench gate type. But, SiC MOSFETs have larger terminal capacitance. Therefore, SiC MOSFETs show slower switching speed than Si MOSFETs for same current density condition.

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Yoshioka, Hironori, Junji Senzaki, Atsushi Shimozato, Yasunori Tanaka, and Hajime Okumura. "Characterization of Interface State Density from Subthreshold Slope of MOSFETs at Low Temperatures (≥ 10 K)." Materials Science Forum 821-823 (June 2015): 745–48. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.745.

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We have evaluated interface state density (DIT) for EC−ET > 0.00 eV from the subthreshold slope deterioration of MOSFETs at low temperatures. We have compared two n-channel MOSFETs on the C- and a-faces with the gate oxide formed by pyrogenic oxidation followed by annealing in H2. The peak field-effect mobility (µFE,peak) for the C-face MOSFET was 57 cm2V-1s-1 at 300 K, which is lower than the half of 135 cm2V-1s-1 for the a-face MOSFET. We have shown that DIT very close to EC can well explain why µFE for C-face MOSFETs is lower than that for a-face MOSFETs. The value of DIT at 0.00 eV corresponding to the subthreshold slope at 11 K was 1.6×1014 cm-2eV-1 for the C-face MOSFET, which is more than the double of 6.4×1013 cm-2eV-1 for the a-face MOSFET.

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Albrecht, Matthaeus, Tobias Erlbacher, Anton J. Bauer, and Lothar Frey. "Potential of 4H-SiC CMOS for High Temperature Applications Using Advanced Lateral p-MOSFETs." Materials Science Forum 858 (May 2016): 821–24. http://dx.doi.org/10.4028/www.scientific.net/msf.858.821.

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In this work, the impact of the n-well doping concentration on the channel mobility and threshold voltage of p-MOSFETs and their applications in CMOS-devices is evaluated. For this purpose lateral p-channel MOSFETs with different channel lengths (L = 800 μm, 10 μm, 5 μm, and 3 μm) and doping concentrations (ND = 1015 cm-3 and 8·1015 cm-3) were fabricated and the respective field-effect mobility was extracted from the transfer-characteristics. Comparable to n-MOSFETs the mobility of p-MOSFETs was found to be the highest for the lowest doping concentration in the channel and the absolute value of the threshold voltage increases with increasing doping concentration [4]. To investigate its suitability for CMOS applications, inverters with different doping concentrations for n-MOSFET (NA = 1015 cm-3 and 1017 cm-3) und p-MOSFET (ND = 1015 cm-3 and 8·1015 cm-3) were built. For logic levels of 0 V and 10 V, the voltage transfer characteristic with the highest input ranges was obtained for a low p-MOSFET and a high n-MOSFET doping concentration. The lowest propagation delay time could be achieved with a low p-MOSFET and a low n-MOSFET doping concentration. At room temperature as well as at high temperatures T = 573 K the drain current of p-MOSFETs with channel lengths below 3 μm is hampered by the series resistance of the source and drain region which limits the performance of CMOS devices.

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Chaudhry, Amit, and Nath Roy. "A comparative study of hole and electron inversion layer quantization in MOS structures." Serbian Journal of Electrical Engineering 7, no. 2 (2010): 185–93. http://dx.doi.org/10.2298/sjee1002185c.

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In this paper, an analytical model has been developed to study inversion layer quantization in nanoscale Metal Oxide Semiconductor Field Effect Oxide p-(MOSFET). n-MOSFETs have been studied using the variation approach and the p-MOSFETs have been studied using the triangular well approach. The inversion charge density and gate capacitance analysis for both types of transistors has been done. There is a marked decrease in the inversion charge density and the capacitance of the p-MOSFET as compared to n-MOSFETs. The results are compared with the numerical results showing good agreement.

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Lichtenwalner, Daniel J., Brett Hull, Vipindas Pala, Edward Van Brunt, Sei-Hyung Ryu, Joe J. Sumakeris, Michael J. O’Loughlin, Albert A. Burk, Scott T. Allen, and John W. Palmour. "Performance and Reliability of SiC Power MOSFETs." MRS Advances 1, no. 2 (2016): 81–89. http://dx.doi.org/10.1557/adv.2015.57.

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ABSTRACTDue to the wide bandgap and other key materials properties of 4H-SiC, SiC MOSFETs offer performance advantages over competing Si-based power devices. For example, SiC can more easily be used to fabricate MOSFETs with very high voltage ratings, and with lower switching losses. Silicon carbide power MOSFET development has progressed rapidly since the market release of Cree’s 1200V 4H-SiC power MOSFET in 2011. This is due to continued advancements in SiC substrate quality, epitaxial growth capabilities, and device processing. For example, high-quality epitaxial growth of thick, low-doped SiC has enabled the fabrication of SiC MOSFETs capable of blocking extremely high voltages (up to 15kV); while dopant control for thin highly-doped epitaxial layers has helped enable low on-resistance 900V SiC MOSFET production. Device design and processing improvements have resulted in lower MOSFET specific on-resistance for each successive device generation. SiC MOSFETs have been shown to have a long device lifetime, based on the results of accelerated lifetime testing, such as high-temperature reverse-bias (HTRB) stress and time-dependent dielectric breakdown (TDDB).

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Choi, Cheol-Woong, Jae-Hyeon So, Jae-Sub Ko, and Dae-Kyong Kim. "Influence Analysis of SiC MOSFET’s Parasitic Capacitance on DAB Converter Output." Electronics 12, no. 1 (December 30, 2022): 182. http://dx.doi.org/10.3390/electronics12010182.

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This paper proposes the influence analysis of silicon carbide (SiC) MOSFET’s parasitic output capacitance on a dual active bridge (DAB) converter. Power converters are required for DC grids and energy storage. Because SiC metal-oxide-semiconductor FETs (MOSFETs) have lower on-state resistance and faster reverse recovery time than Si MOSFETs, they can be controlled with lower losses and higher frequencies. MOSFETs have a parasitic capacitance. Because of the output parasitic capacitance, the switch voltage does not rise instantaneously during switching but has a delay. The output parasitic capacitance of the switch depends on its drain-to-source voltage, and this parasitic capacitance affects the output of the DAB converter by delaying the switch voltage. In this paper, in order to analyze the effect of the parasitic capacitance on the DAB converter output, the delay time was calculated through a formula, and this value was compared with a simulated value. In addition, the effect of the parasitic capacitance of the SiC MOSFET on the output of the DAB converter was presented by comparing the actual output voltage with the ideal output voltage and analyzing the effect of the output voltage according to the delay.

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Huang, W., T. Khan, and T. P. Chow. "Geometry and Short Channel Effects on Enhancement-Mode n-Channel GaN MOSFETs on p and n-GaN/Sapphire Substrates." International Journal of High Speed Electronics and Systems 17, no. 01 (March 2007): 49–53. http://dx.doi.org/10.1142/s0129156407004230.

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In this paper, we have fabricated and compared the performance of lateral enhancement-mode GaN MOSFETs with linear and circular geometries. Circular MOSFETs show 2 to 4 orders of magnitude lower leakage current than that of linear MOSFETs. We also studied short channel behaviors and found that they are similar to those previously reported Si MOSFET.

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Allen, Scott, Vipindas Pala, E. VanBrunt, Brett Hull, Lin Cheng, S. Ryu, Jim Richmond, M. O’Loughlin, Al Burk, and J. Palmour. "Next-Generation Planar SiC MOSFETs from 900 V to 15 kV." Materials Science Forum 821-823 (June 2015): 701–4. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.701.

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A family of planar MOSFETs with voltage ratings from 900 V to 15 kV are demonstrated. This family of planar MOSFETs represents Cree’s next generation MOSFET design and process, in which we continue to refine and evolve device design and processing to further shrink die sizes and enhance device performance. At voltage ratings of 3.3 kV and above, the specific on-resistance of the MOSFETs is approaching the theoretical limit. MOSFET switching performance in a clamped inductive switching circuit for the full range of voltage ratings is also demonstrated. Finally, improved threshold voltage and body diode stability under long-term stresses are presented.

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9

Bradford, T., and S. P. McAlister. "The use of multiple-gated MOSFETs in a simple application." Canadian Journal of Physics 74, S1 (December 1, 1996): 182–85. http://dx.doi.org/10.1139/p96-855.

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We describe the design and simulation of the use of neuron MOSFETs in a simple application — that of a parallel-carry adder circuit. The neuron MOSFETs are multigated MOSFETs where the multiple coupling to a MOSFET's gate is made capacitatively. By using such devices a multilevel logic is achieved that allows functions in a circuit to be achieved with fewer transistors than in a conventional CMOS design.

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Ahn, Tae Jun, and Yun Seop Yu. "Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter." Journal of Nanoscience and Nanotechnology 21, no. 8 (August 1, 2021): 4252–57. http://dx.doi.org/10.1166/jnn.2021.19388.

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We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

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11

Hino, Shiro, Naruhisa Miura, Akihiko Furukawa, Shoyu Watanabe, Yukiyasu Nakao, Shuhei Nakata, Masayuki Imaizumi, Hiroaki Sumitani, and Tatsuo Oomori. "SiC-MOSFET Structure Enabling Fast Turn-On and -Off Switching." Materials Science Forum 717-720 (May 2012): 1097–100. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1097.

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High speed switching is desired to reduce switching losses of SiC-MOSFETs. In order to realize SiC-MOSFETs capable of high speed switching, we numerically evaluated the electric field induced in SiC-MOSFETs during switching using an equivalent circuit model. Based on the evaluation, we designed a SiC-MOSFET, which successfully demonstrated high speed switching with a dV/dt of over 70 V/ns.

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12

Hatta, Hideyuki, Takaaki Tominaga, Shiro Hino, Naruhisa Miura, Shingo Tomohisa, and Satoshi Yamakawa. "Suppression of Short-Circuit Current with Embedded Source Resistance in SiC-MOSFET." Materials Science Forum 924 (June 2018): 727–30. http://dx.doi.org/10.4028/www.scientific.net/msf.924.727.

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This work reports an SiC-MOSFET which replaces a part of the channel resistance with an additional embedded resistance, called a source resistance (Rs). MOSFETs with Rs have higher resistance during short circuit compared with MOSFETs without Rs and suppress short-circuit currents. An improvement of the trade-off relationship between short-circuit capability and on-resistance was obtained with MOSFETs including embedded Rs.

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13

Naik, Harsh, and T. Paul Chow. "Study of Mobility Limiting Mechanisms in (0001) 4H and 6H-SiC MOSFETs." Materials Science Forum 679-680 (March 2011): 595–98. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.595.

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To study the mobility limiting mechanisms in (0001) 4H-SiC and 6H-SiC MOSFETs, physics based modeling of the inversion mobility of has been done. Two very different limiting mechanisms have been found for 4H-SiC and 6H-SiC MOSFETs. The mobility in 6H-SiC MOSFETs is limited by phonon scattering while the 4H-SiC MOSFET mobility is limited by Coulombic at low electric fields and surface roughness scattering at high electric fields.

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14

Albrecht, Matthaeus, Tobias Erlbacher, Anton Bauer, and Lothar Frey. "Improving 5V Digital 4H-SiC CMOS ICs for Operating at 400°C Using PMOS Channel Implantation." Materials Science Forum 963 (July 2019): 827–31. http://dx.doi.org/10.4028/www.scientific.net/msf.963.827.

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In this work, the impact of a shallow aluminum channel implantation on the channel properties of SiC p-MOSFETs and digital SiC CMOS devices is investigated. For this purpose, p-MOSFETs, CMOS inverters and ring oscillators with different channel implantation doses were fabricated and electrically characterized. The threshold voltage of the resulting p-MOSFETs was shifted from-5 V to-3.6 V whereas the effective channel mobility was slightly decreased from 11.8 cm2/Vs to 10.2 cm2/Vs for a p-MOSFET channel implantation dose of 2∙1013 cm-2 compared to the non-implanted channel. The resulting p-MOSFETs enable SiC CMOS logic circuits to operate with a 5 V power supply and to satisfy 5 V TTL input level specification over the whole temperature range of 25°C to 400°C. Furthermore the propagation delay time of inverters was reduced by 80% at 25°C and 40% at 400°C compared to inverters without p-MOSFET channel implantation.

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15

Nepomnyaschiy, O. V., Yu V. Krasnobaev, I. E. Sazonov, and A. P. Yablonskiy. "A software-based method for energy losses decreasing in cascaded buck + boost DC-DC converter." Journal of Physics: Conference Series 2388, no. 1 (December 1, 2022): 012025. http://dx.doi.org/10.1088/1742-6596/2388/1/012025.

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Abstract A MOSFETs switching times calculation method for the known modulation strategy for bidirectional buck + boost DC-DC converter is presented. A former low-loss, constant-frequency modulation strategy based on a negative inductor offset current takes place at the beginning of each conversion period which provides the ability to turn on converter’s MOSFET switches under zero-voltage and zero current switching (ZVS/ZCS) condition. Time interval between switching times of half-bridge MOSFETs is needed to provide the ability to turn on the MOSFET under ZVS/ZCS due to its antiparallel diode takes over an inductor current. Described method based on a switching delay time estimation for the worst case of converter’s circuit components spread which allows to calculate proper MOSFETs switching times by Digital Control Unit (DCU). The article describes in detail the switching of the input half-bridge MOSFETs at first switching time. The clarified offset current calculation method, based on an estimated switching delay and converter’s input voltage is presented.

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Singh, Ajay Kumar. "Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 2 (March 4, 2019): 815–28. http://dx.doi.org/10.1108/compel-08-2018-0327.

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Purpose This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs. Design/methodology/approach This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach. Findings It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement. Originality/value Compact Analytical models for undoped symmetric double gate MOSFETs.

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Petrosyants, Konstantin O., Igor A. Kharitonov, and Lev M. Sambursky. "Hardware-Software Subsystem for MOSFETs Characteristic Measurement and Parameter Extraction with Account for Radiation Effects." Advanced Materials Research 718-720 (July 2013): 750–55. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.750.

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Hardware-software subsystem designed for MOSFETs characteristic measurement and SPICE model parameter extraction taking into account radiation effects is presented. Parts of the system are described. The macromodel approach is used to account for radiation effects in MOSFET modeling. Particularities of the account for radiation effects in MOSFETs within the measurement and model parameter extraction procedures are emphasized. Application of the subsystem is illustrated on the example of radiation hardened 0.25 μm SOI MOSFET test structures.

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Gowthaman, Naveenbalaji, and Viranjay Srivastava. "Analysis of InN/La2O3 Twosome for Double-Gate MOSFETs for Radio Frequency Applications." Materials Science Forum 1048 (January 4, 2022): 147–57. http://dx.doi.org/10.4028/www.scientific.net/msf.1048.147.

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The channel material of a gate describes the operating condition of the MOSFET. A suitable operating condition prevails in MOSFETs if the transistors are quite enough to observe and control at the nanometer regime. An efficient gate and channel material have been proposed in this work which is based on the electrical properties they exhibit at the temperature of 300K. The doping concentration for the electrons and holes is maintained to be 1Χ1019cm-3 for the entire electronic simulator. The simulation results show that using La2O3 along with Indium Nitride (InN) material for the designing of Double-Gate (DG) MOSFETs provides better controllability over the transistor at a channel length of 50nm. This proposed DG-MOSFET is more compliant than the conventional coplanar MOSFETs based on Silicon.

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Matocha, Kevin, Peter A. Losee, Arun Gowda, Eladio Delgado, Greg Dunne, Richard Beaupre, and Ljubisa Stevanovic. "Performance and Reliability of SiC MOSFETs for High-Current Power Modules." Materials Science Forum 645-648 (April 2010): 1123–26. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1123.

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We address the two critical challenges that currently limit the applicability of SiC MOSFETs in commercial power conversion systems: high-temperature gate oxide reliability and high total current rating. We demonstrate SiC MOSFETs with predicted gate oxide reliability of >106 hours (100 years) operating at a gate oxide electric field of 4 MV/cm at 250°C. To scale to high total currents, we develop the Power Overlay planar packaging technique to demonstrate SiC MOSFET power modules with total on-resistance as low as 7.5 m. We scale single die SiC MOSFETs to high currents, demonstrating a large area SiC MOSFET (4.5mm x 4.5 mm) with a total on-resistance of 30 m, specific on-resistance of 5 m-cm2 and blocking voltage of 1400V.

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Ejury, Jens. "Advanced Thermal Simulation Model for Power MOSFETs." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000598–603. http://dx.doi.org/10.4071/isom-2013-wa64.

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Modern Power MOSFETs are widely used for high efficiency SMPS applications. Also, they provide very low on-resistance which reduces conduction losses in Oring or eFuse applications. These applications as well as others have transition states in which they drive the MOSFET in linear mode operation during turn-on and turn-off events respectively. The high cell density in modern Power MOSFETs provokes uneven current distribution in linear mode operation which locally stresses certain cell areas more than others. To prevent destruction, the SOA of these MOSFETs has a thermal limit line boundary imposed. With existing L3 MOSFET models it is possible to simulate temperature rise and power loss of the entire MOSFET. However, the local heating effect is not represented in this model. Here, a wrapper is being introduced. It converts a standard L3-model into a model that incorporates a dynamic representation of the entire SOA diagram. The temperature rise follows the hottest cell so that simulations in linear mode become a valid way to predict the highest junction temperature. The limitations of this approach will be outlined.

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Kawahara, Koutarou, Shiro Hino, Koji Sadamatsu, Yukiyasu Nakao, Toshiaki Iwamatsu, Shuhei Nakata, Shingo Tomohisa, and Satoshi Yamakawa. "Impact of Embedding Schottky Barrier Diodes into 3.3 kV and 6.5 kV SiC MOSFETs." Materials Science Forum 924 (June 2018): 663–66. http://dx.doi.org/10.4028/www.scientific.net/msf.924.663.

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External Schottky barrier diodes (SBDs) used as free-wheel diodes should be larger in higher voltage devices to avoid bipolar degradation consequent on current conduction of body diodes in SiC MOSFETs. By embedding an external SBD into an SiC MOSFET, we achieved compact 3.3 kV and 6.5 kV SiC MOSFETs that are free from bipolar degradation. The active area of the 3.3 kV/6.5 kV samples is only about a half/quarter of the total active area of a conventional MOSFET and a coupled external SBD.

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Noborio, Masato, Yuki Negoro, Jun Suda, and Tsunenobu Kimoto. "Reduction of On-Resistance in 4H-SiC Multi-RESURF MOSFETs." Materials Science Forum 527-529 (October 2006): 1305–8. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1305.

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SiC lateral MOSFETs with multi-RESURF structures have been fabricated by a self-aligned process. The “multi-RESURF” means “double RESURF” and “buried-p RESURF” structures, which have the buried-p region at the top and at the middle of RESURF region, respectively. The increase of net RESURF dose and the decrease of channel length lead to the reduced on-resistance. The “buried-p RESURF” MOSFETs have higher on-resistances than the “double RESURF” MOSFETs, due to the resistance of parasitic JFET inside the RESURF region. The dose designing for double RESURF MOSFETs has been optimized by using device simulation. A double RESURF MOSFET exhibits a breakdown voltage of 750 V and an on-resistance of 52 m/cm2.

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Zou, Yuan, Jue Wang, Hongyi Xu, and Hengyu Wang. "Investigation of SiC Trench MOSFETs’ Reliability under Short-Circuit Conditions." Materials 15, no. 2 (January 13, 2022): 598. http://dx.doi.org/10.3390/ma15020598.

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In this paper, the short-circuit robustness of 1200 V silicon carbide (SiC) trench MOSFETs with different gate structures has been investigated. The MOSFETs exhibited different failure modes under different DC bus voltages. For double trench SiC MOSFETs, failure modes are gate failure at lower dc bus voltages and thermal runaway at higher dc bus voltages, while failure modes for asymmetric trench SiC MOSFETs are soft failure and thermal runaway, respectively. The shortcircuit withstanding time (SCWT) of the asymmetric trench MOSFET is higher than that of the double trench MOSFETs. The thermal and mechanical stresses inside the devices during the short-circuit tests have been simulated to probe into the failure mechanisms and reveal the impact of the device structures on the device reliability. Finally, post-failure analysis has been carried out to verify the root causes of the device failure.

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Noborio, Masato, Jun Suda, and Tsunenobu Kimoto. "1.5 kV Lateral Double RESURF MOSFETs on 4H-SiC (000-1)C Face." Materials Science Forum 615-617 (March 2009): 757–60. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.757.

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SiC lateral double RESURF MOSFETs have been fabricated on the 4H-SiC (000-1)C face. By utilizing the C face, the channel resistance can be reduced because the C-face MOSFETs show higher channel mobility than the Si-face MOSFETs. In addition, by employing the double RESURF structure, the drift resistance is decreased and the breakdown voltage is increased with increasing the RESURF doses. The fabricated RESURF MOSFETs on the 4H-SiC (000-1)C face have demonstrated a low on-resistance of 40 mΩcm2 at an oxide field of 3 MV/cm and a breakdown voltage of 1580 V at zero gate bias. The figure-of-merit of the MOSFET is 62 MW/cm2, which is more than 10 times better than the conventional “Si limit” and the highest value among any lateral MOSFETs to date.

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IÑIGUEZ, BENJAMIN, ROMAIN RITZENTHALER, and FRANÇOIS LIME. "COMPACT MODELING OF DOUBLE AND TRI-GATE MOSFETs." International Journal of High Speed Electronics and Systems 22, no. 01 (November 2013): 1350004. http://dx.doi.org/10.1142/s0129156413500043.

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This chapter presents some insights into the modeling of different Multi-Gate SOI MOSFET structures, and in particular Double-Gate MOSFETs (DG MOSFETs) and Tri-Gate MOSFETs (TGFETs). For long-channel case an electrostatic model can be developed from the solution of the 1D Poisson's equation (in the case of DG MOSFETs) and the 2D Poisson's equation in the section perpendicular to the channel (in the case of TGFETs). Allowing it to be incorporated in quasi-2D compact models. For short-channel devices a model can be derived from a 2D (in the case of DG MOSFETs) or a 3D (in the case of TGFETs) electrostatic analysis. The models were successfully compared with 2D and 3D TCAD simulations and, in some cases, experimental measurements. Short-channel effects, such as subthrehold slope degradation, threshold voltage roll-off and DIBL were accurately reproduced.

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Yun, Nick, Justin Lynch, and Woong Je Sung. "Experimental Analysis of 600V 4H-SiC Vertical and Lateral MOSFETs Fabricated on the same 6-Inch Substrate Using a Single Process." Materials Science Forum 1004 (July 2020): 830–36. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.830.

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This paper aims to provide detailed experimental results of 4H-SiC vertical and lateral MOSFETs fabricated on the same 6-inch substrate using a single process flow. The cell optimization and fabrication scheme of both vertical and lateral MOSFETs are described in this paper. The measured electrical characteristics from both structures such as on-resistance, transconductance, threshold voltage, breakdown voltage, and capacitances are discussed. Resistance distribution and figure-of-merits of [Ron×Ciss], [Ron×Coss], and [Ron×Crss] for vertical and lateral MOSFETs are compared to further improve the characteristic of the lateral MOSFET.

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Hino, Shiro, Masanao Ito, Naruhisa Miura, Masayuki Imaizumi, and Satoshi Yamakawa. "Investigation on Internally Unbalanced Switching Behavior for Realization of 1-cm² SiC-MOSFET." Materials Science Forum 778-780 (February 2014): 963–66. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.963.

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The influences of internally unbalanced switching behavior on the switching characteristics and RBSOA were investigated in order to realize a large-size SiC-MOSFET. Specially designed small-size MOSFETs in which the unbalanced behavior is enhanced by adjusting the geometrical gate structures were fabricated, and their switching characteristics were evaluated. It was found that the same switching characteristics can be obtained by regarding them as MOSFETs with high inner gate resistances. A 1-cm2 SiC-MOSFET was fabricated, and high dV/dt switching and high turn-off endurance were demonstrated.

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Albrecht, Matthaeus, David Pérez, R. Christian Martens, Anton J. Bauer, and Tobias Erlbacher. "Impact of Channel Implantation on a 4H-SiC CMOS Operational Amplifier for High Temperature Applications." Materials Science Forum 1004 (July 2020): 1123–28. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.1123.

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In this work, the impact of channel implantations (IMP) on the electrical characteristics of SiC n-and p-MOSFETs and analog SiC-CMOS operational amplifiers (OpAmp) is investigated. For this purpose, MOSFETs and Miller OpAmps with and without IMP were fabricated and electrically characterized from room temperature up to 350°C. For devices with IMP the absolute values of the threshold voltages of n-and p-MOSFETs were reduced by 1.5 V and the mobility of the n-MOSFET was increased from 13 to 23 cm2/Vs whereas the mobility of the p-MOSFET remained constant at 6 cm2/Vs. For the resulting OpAmp with IMP, the common-mode input voltage range as well as the open loop gain was increased by 1.5 V and 4 dB compared to non-implanted devices. This improvement was observed across the entire analyzed temperature range from room temperature up to 350°C.

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Bottaro, Enrico, Santi Agatino Rizzo, and Nunzio Salerno. "Circuit Models of Power MOSFETs Leading the Way of GaN HEMT Modelling—A Review." Energies 15, no. 9 (May 7, 2022): 3415. http://dx.doi.org/10.3390/en15093415.

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Gallium nitride high-electron-mobility transistor (GaN HEMT) is a key enabling technology for obtaining high-efficient and compact power electronic systems. At the design stage of a power converter, the proper modelling of the GaN HEMT is essential to benefit from their good features and to account for the limits of the current technology. Circuit models of power MOSFETs have been deeply investigated by academia and industry for a long time. These models are able to emulate the datasheet information, and they are usually provided by device manufacturers as netlists that can be simulated in any kind of SPICE-like software. This paper firstly highlights the similarities and differences between MOSFETs and GaN HEMTs at the datasheet level. According to this analysis, the features of MOSFET circuit models that can be adopted for GaN HEMT modelling are discussed. This task has been accomplished by overviewing the literature on MOSFETs circuit models as well as analysing manufacturers netlists, thus highlighting the models MOSFETs valid or adaptable to GaN HEMTs. The study has revealed show that some models can be adapted for the GaN HEMT devices to emulate static characteristics at room temperature while the MOSFET models of dynamic characteristics can be used for GaN HEMT devices. This study enables the devices modellers to speed up the GaN HEMT modelling thanks to the use of some well-established MOSFET models. In this perspective, some suggestions to develop accurate GaN HEMT models are also provided.

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Min, So-Ra, Min-Su Cho, Sang-Ho Lee, Jin Park, Hee-Dae An, Geon-Uk Kim, Young-Jun Yoon, et al. "Analysis for DC and RF Characteristics Recessed-Gate GaN MOSFET Using Stacked TiO2/Si3N4 Dual-Layer Insulator." Materials 15, no. 3 (January 21, 2022): 819. http://dx.doi.org/10.3390/ma15030819.

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The self-heating effects (SHEs) on the electrical characteristics of the GaN MOSFETs with a stacked TiO2/Si3N4 dual-layer insulator are investigated by using rigorous TCAD simulations. To accurately analyze them, the GaN MOSFETs with Si3N4 single-layer insulator are conducted to the simulation works together. The stacked TiO2/Si3N4 GaN MOSFET has a maximum on-state current of 743.8 mA/mm, which is the improved value due to the larger oxide capacitance of TiO2/Si3N4 than that of a Si3N4 single-layer insulator. However, the electrical field and current density increased by the stacked TiO2/Si3N4 layers make the device’s temperature higher. That results in the degradation of the device’s performance. We simulated and analyzed the operation mechanisms of the GaN MOSFETs modulated by the SHEs in view of high-power and high-frequency characteristics. The maximum temperature inside the device was increased to 409.89 K by the SHEs. In this case, the stacked TiO2/Si3N4-based GaN MOSFETs had 25%-lower values for both the maximum on-state current and the maximum transconductance compared with the device where SHEs did not occur; Ron increased from 1.41 mΩ·cm2 to 2.56 mΩ·cm2, and the cut-off frequency was reduced by 26% from 5.45 GHz. Although the performance of the stacked TiO2/Si3N4-based GaN MOSFET is degraded by SHEs, it shows superior electrical performance than GaN MOSFETs with Si3N4 single-layer insulator.

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Lichtenwalner, Daniel J., Akin Akturk, James McGarrity, Jim Richmond, Thomas Barbieri, Brett Hull, Dave Grider, Scott Allen, and John W. Palmour. "Reliability of SiC Power Devices against Cosmic Ray Neutron Single-Event Burnout." Materials Science Forum 924 (June 2018): 559–62. http://dx.doi.org/10.4028/www.scientific.net/msf.924.559.

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High-energy neutrons produced by cosmic ray interactions with our atmosphere are known to cause single-event burnout (SEB) failure in power devices operating at high fields. We have performed accelerated high-energy neutron SEB testing of SiC and Si power devices at the Los Alamos Neutron Science Center (LANCSE). Comparing Wolfspeed SiC MOSFETs having different voltage (900V – 3300V) and current (3.5A – 72A) ratings, we find a universal behavior when scaling failure rates by active area, and scaling drain bias by avalanche voltage. Moreover, diodes and MOSFETs behave similarly, revealing that the SiC drift dominates the failure characteristics for both device types. This universal scaling holds for SiC MOSFETs from other manufacturers as well. The SEB characteristics of Si power IGBT and MOSFET devices show that near their rated voltages failure rates of Si devices can be 10X higher than that of comparable SiC MOSFET devices. Thus, Si devices are more susceptible to SEB failure from voltage overshoot conditions.

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Peruzzi, Vinicius Vono, William Cruz, Gabriel Augusto Da Silva, Eddy Simoen, Cor Claeys, and Salvador Pinillos Gimenez. "Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments." Journal of Integrated Circuits and Systems 15, no. 2 (August 10, 2020): 1–5. http://dx.doi.org/10.29292/jics.v15i2.185.

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This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) present in the structure of Diamond MOSFETs. Therefore, the Diamond layout style can be consid-ered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS inte-grated circuits (ICs) applications.

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Konishi, Kumiko, Ryusei Fujita, Yuki Mori, and Akio Shima. "Investigation of Forward Voltage Degradation due to Process-Induced Defects in 4H-SiC MOSFET." Materials Science Forum 924 (June 2018): 365–68. http://dx.doi.org/10.4028/www.scientific.net/msf.924.365.

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We investigated process induced defects at various ion implantation conditions, and evaluated forward voltage degradation of body diode in 3.3 kV SiC MOSFET. First, by using photoluminescence (PL) observation, we evaluated the formation level of Basal Plane Dislocations (BPD) induced by Al implantation and anneal process with various Al implantation dose. Second, 3.3 kV double-diffused SiC MOSFETs were fabricated and forward current stress tests were performed to body diodes in SiC MOSFETs. Then, electrical characteristics of SiC MOSFETs before and after the stress test were measured, and expanded Stacking faults (SFs) in SiC epitaxial layer after the stress test were observed by PL imaging method. These results indicate that low dose or high temperature Al implantation conditions can suppress the formation of BPDs, and SiC MOSFETs fabricated using optimized Al implantation conditions show high reliability under current stress test.

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Merad, Faiza, and Ahlam Guen-Bouazza. "DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (August 1, 2020): 4043. http://dx.doi.org/10.11591/ijece.v10i4.pp4043-4052.

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With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model .This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity . The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversion-mode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion / Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV / V.

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Nakano, Yuki, R. Nakamura, H. Sakairi, Shuhei Mitani, and T. Nakamura. "690V, 1.00 mΩcm² 4H-SiC Double-Trench MOSFETs." Materials Science Forum 717-720 (May 2012): 1069–72. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1069.

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The trench gate structure MOSFET, with its lack of JFET resistance, is one of the structures able to achieve low on-state resistance [1,2]. In 2008, this group succeeded in fabricating 790V SiC trench MOSFETs with the lowest Ron,sp (1.7 mΩcm2) at room temperature. However these devices had issues regarding oxide destruction at the trench bottom during high drain-source voltage application. In order to improve this problem, this group developed the double-trench MOSFET structure. This structure has both source trenches and gate trenches. This paper compares two kinds of trench MOSFETs: the conventional, single trench structure and a double-trench structure. Also, the latest characteristics are presented.

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Wu, Li-Feng, Yong Guan, Xiao-Juan Li, and Jie Ma. "Anomaly Detection and Degradation Prediction of MOSFET." Mathematical Problems in Engineering 2015 (2015): 1–5. http://dx.doi.org/10.1155/2015/573980.

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The MOSFET is an important power electronic transistor widely used in electrical systems. Its reliability has an effect on the performance of systems. In this paper, the failure models and mechanisms of MOSFETs are briefly analyzed. The on-resistanceRonis the key failure precursor parameter representing the degree of degradation. Based on the experimental data, a nonlinear dual-exponential degradation model for MOSFETs is obtained. Then, we present an approach for MOSFET degradation state prediction using a strong tract filter based on the obtained degradation model. Lastly, the proposed algorithm is shown to perform effectively on experimental data. Thus, it can provide early warning and enhance the reliability of electrical systems.

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Hitchcock, Collin W., and T. Paul Chow. "Common-Drain Bidirectional 1200V SiC MOSFETs." Materials Science Forum 1004 (July 2020): 882–88. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.882.

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Using commercially available SiC MOSFET dice, bidirectional MOSFETs were assembled and their electrical performance was tested. With proper gate biasing, the pair is capable of blocking at or near the rated value of the component MOSFETs in each direction. The pair conducts in both directions with an on-state resistance comparable to the sum of the constituent device resistances. With optimization of the component devices, this configuration promises to improve bidirectional switch performance beyond that of the simple assembled pair.

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Watanabe, Yukimune, Noriyasu Kawana, Tsuyoshi Horikawa, and Kiichi Kamimura. "Electrical Characterization of 3C-SiC Lateral MOSFETs Fabricated on Heteroepitaxial Films Including High Density of Defects." Materials Science Forum 821-823 (June 2015): 733–36. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.733.

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We have fabricated lateral MOSFETs on heteroepitaxial 3C-SiC films included high density of defects. Electrical characteristics of 3C-SiC MOSFETs and their temperature dependence were measured to discuss effects of defects on the electrical characteristics. A field effect mobility of 156 cm2/Vs was obtained at room temperature. After applying a drain voltage of 10 V or higher, the drain current - gate voltage curve shifted toward the positive gate voltage. This shift was caused mainly by the charge trapping in the gate oxide. The light emission was observed on the surface of the active MOSFET. The spatial distribution of the emission light from MOSFETs indicated that the charge was generated at the source edge of the gate channel.

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Kim, Tae-Woo. "Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications." Electronics 9, no. 1 (December 26, 2019): 29. http://dx.doi.org/10.3390/electronics9010029.

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We created tri-gate sub-100 nm In0.53Ga0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al2O3/HfO2 gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (Wfin) at gate lengths of sub-100 nm. For Lg = 60 nm In0.53Ga0.47As tri-gate MOSFETs, EOT and Wfin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In0.53Ga0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse VT degradation compared to planar InGaAs MOSFET with the same gate stack and EOT. This is due to the effects of both of the etched fin’s sidewall interfaces.

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Prado, Edemar O., Pedro C. Bolsi, Hamiltom C. Sartori, and José R. Pinheiro. "An Overview about Si, Superjunction, SiC and GaN Power MOSFET Technologies in Power Electronics Applications." Energies 15, no. 14 (July 20, 2022): 5244. http://dx.doi.org/10.3390/en15145244.

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This work presents a comparative analysis among four power MOSFET technologies: conventional Silicon (Si), Superjunction (SJ), Silicon Carbide (SiC) and Gallium Nitride (GaN), indicating the voltage, current and frequency ranges of the best performance for each technology. For this, a database with 91 power MOSFETs from different manufacturers was built. MOSFET losses are related to individual characteristics of the technology: drain-source on-state resistance, input capacitance, Miller capacitance and internal gate resistance. The total losses are evaluated considering a drain-source voltage of 400 V, power levels from 1 kW to 16 kW (1 A–40 A) and frequencies from 1 kHz to 500 kHz. A methodology for selecting power MOSFETs in power electronics applications is also presented.

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Zhu, Shengnan, Tianshi Liu, Junchong Fan, Arash Salemi, Marvin H. White, David Sheridan, and Anant K. Agarwal. "A New Cell Topology for 4H-SiC Planar Power MOSFETs for High-Frequency Switching." Materials 15, no. 19 (September 27, 2022): 6690. http://dx.doi.org/10.3390/ma15196690.

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A new cell topology named the dodecagonal (a polygon with twelve sides, short for Dod) cell is proposed to optimize the gate-to-drain capacitance (Cgd) and reduce the specific ON-resistance (Ron,sp) of 4H-SiC planar power MOSFETs. The Dod and the octagonal (Oct) cells are used in the layout design of the 650 V SiC MOSFETs in this work. The experimental results confirm that the Dod-cell MOSFET achieves a 2.2× lower Ron,sp, 2.1× smaller high-frequency figure of merit (HF-FOM), higher turn on/off dv/dt, and 29% less switching loss than the fabricated Oct-cell MOSFET. The results demonstrate that the Dod cell is an attractive candidate for high-frequency power applications.

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Yun, Minghui, Miao Cai, Daoguo Yang, Yiren Yang, Jing Xiao, and Guoqi Zhang. "Bond Wire Damage Detection Method on Discrete MOSFETs Based on Two-Port Network Measurement." Micromachines 13, no. 7 (July 7, 2022): 1075. http://dx.doi.org/10.3390/mi13071075.

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Bond wire damage is one of the most common failure modes of metal-oxide semiconductor field-effect transistor (MOSFET) power devices in wire-welded packaging. This paper proposes a novel bond wire damage detection approach based on two-port network measurement by identifying the MOSFET source parasitic inductance (LS). Numerical calculation shows that the number of bond wire liftoffs will change the LS, which can be used as an effective bond wire damage precursor. Considering a power MOSFET as a two-port network, LS is accurately extracted from frequency domain impedance (Z−parameter) using a vector network analyzer under zero biasing conditions. Bond wire cutoff experiments are employed to validate the proposed approach for bond wire damage detection. The result shows that LS increases with the rising severity of bond wire faults, and even the slight fault shows a high sensitivity, which can be effectively used to quantify the number of bond wire liftoffs of discrete MOSFETs. Meanwhile, the source parasitic resistance (RS) extracted from the proposed two-port network measurement can be used for the bond wire damage detection of high switching frequency silicon carbide MOSFETs. This approach offers an effective quality screening technology for discrete MOSFETs without power on treatment.

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Potbhare, Siddharth, Neil Goldsman, Gary Pennington, Aivars J. Lelis, and J. M. McGarrity. "Time Dependent Trapping and Generation-Recombination of Interface Charges: Modeling and Characterization for 4H-SiC MOSFETs." Materials Science Forum 556-557 (September 2007): 847–50. http://dx.doi.org/10.4028/www.scientific.net/msf.556-557.847.

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SiC MOSFETs have very large interface trap densities which degrade device performance. The effect of traps on inversion layer mobility and inversion charge concentration has been studied, and mobility models suitable for inclusion in Drift-Diffusion simulators have been developed for steady state operation of SiC MOSFET devices. Here, we attempt to model the transient behavior of SiC MOSFETs, and at the same time, extract the time constants for the filling and emptying of interface traps. As compared to the inversion layer, interface traps in SiC MOSFETs are slow in reacting to change in gate bias. So, at the positive edge of a gate pulse, we see a large current in the MOSFET, which then decays slowly to the steady state value as the interface traps fill up. We have developed a generation/recombination model for minority carriers in a SiC MOSFET based on the Shockley-Read-Hall recombination model for electrons and holes. In our model, the generation/recombination takes place between minority carriers in the inversion layer, and the traps at the SiC-SiO2 interface. Comparing our simulated current vs. time curves to experiment, we have been able to extract time constants for the filling and emptying of traps at the SiC-SiO2 interface.

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Galembeck, Egon Henrique Salerno, Denis Flandre, Christian Renaux, and Salvador Pinillos Gimenez. "Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment." Journal of Integrated Circuits and Systems 14, no. 2 (August 25, 2019): 1–8. http://dx.doi.org/10.29292/jics.v14i2.34.

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This present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.

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Qiu, Guoqing, Kedi Jiang, Shengyou Xu, Xin Yang, and Wei Wang. "Modeling and analysis of the characteristics of SiC MOSFET." Journal of Physics: Conference Series 2125, no. 1 (November 1, 2021): 012051. http://dx.doi.org/10.1088/1742-6596/2125/1/012051.

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Abstract Although the superior performance of SiC MOSFET devices has beenvalidated by many studies, it is necessary to overcome many technical bottlenecks to make SiC MOSFET gradually replace Si-based power devices into the mainstream. In view of the current situation where the performance of SiC MOSFETs in power conversion devices cannot be evaluated well at this stage, it is necessary to carry out fine modeling of SiC MOSFETs and establish accurate simulation models. In this paper, the powerful mathematical processing capability and rich modules of Matlab/Simulink are used to build a SiC MOSFET model, and then the product data sheet is compared with the fitted data. The results show that the switching simulation waveforms are in general agreement with the data sheet waveforms, and the error is less than 7%. Verifing the accuracy of the model and reducing the difficulty of modeling, it provides a new idea for establishing the circuit simulation model of SiC MOSFET in Matlab/Simulink.

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Qin, Mo, Xun, Zhang, and Dong. "A Digital-Controlled SiC-Based Solid State Circuit Breaker with Soft Switch-Off Method for DC Power System." Electronics 8, no. 8 (July 26, 2019): 837. http://dx.doi.org/10.3390/electronics8080837.

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Due to the lower on-state resistance, direct current (DC) solid state circuit breakers (SSCBs) based on silicon-carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) can reduce on-state losses and the investment of the cooling system when compared to breakers based on silicon (Si) MOSFETs. However, SiC MOSFETs, with smaller die area and higher current density, lead to weaker short-circuit ability, shorter short-circuit withstand time and higher protection requirements. To improve the reliability and short-circuit capability of SiC-based DC solid state circuit breakers, the short-circuit fault mechanisms of Si MOSFETs and SiC MOSFETs are revealed. Combined with the desaturation detection (DESAT), a “soft turn-off” short-circuit protection method based on source parasitic inductor is proposed. When the DESAT protection is activated, the “soft turn-off” method can protect the MOSFET against short-circuit and overcurrent. The proposed SSCB, combined with the flexibility of the DSP, has the μs-scale ultrafast response time to overcurrent detection. Finally, the effectiveness of the proposed method is validated by the experimental platform. The method can reduce the voltage stress of the power device, and it can also suppress the short-circuit current.

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He, Yan Jing, Hong Liang Lv, Xiao Yan Tang, Qing Wen Song, Yi Meng Zhang, and Yu Ming Zhang. "Hole Trapping in the NBTI Characteristic of SiC MOSFETs." Materials Science Forum 924 (June 2018): 667–70. http://dx.doi.org/10.4028/www.scientific.net/msf.924.667.

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P-type implanted metal oxide semiconductor capacitors (MOSCAPs) and metal oxide semiconductor field effect transistors (MOSFETs) have been fabricated. The characteristics of hole trapping at the interface of SiO2/SiC are investigated through capacitance-voltage (CV) measurements with different starting voltages. The negative shift voltage ∆Vshift and the hysteresis voltages ∆VH which caused by the hole traps in the MOSCAPs and MOSFETs are extracted from CV results. The results show that the hole traps extracted from MOSCAPs are larger than the that extracted from the threshold voltage shift in the MOSFETs. It suggests holes trapping are the primary mechanism contributing to the NBTI, but not all the holes work. Part of the hole traps are compensation by sufficient electrons in the MOSFET structure.

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Chen, Jiangui, Yan Li, and Mei Liang. "A Gate Driver Based on Variable Voltage and Resistance for Suppressing Overcurrent and Overvoltage of SiC MOSFETs." Energies 12, no. 9 (April 29, 2019): 1640. http://dx.doi.org/10.3390/en12091640.

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A SiC MOSFET is a suitable replacement for a Si MOSFET due to its lower on-state resistance, faster switching speed, and higher breakdown voltage. However, due to the parasitic parameters and the low damping in the circuit, the turn-on overcurrent and turn-off overvoltage of a SiC MOSFET become more severe as the switching speed increases. These effects limit higher frequency applications of SiC MOSFET. Based on the causes of overcurrent and overvoltage of SiC MOSFET, a novel gate driver with the variable driving voltage and variable gate resistance is proposed in this paper to suppress the overcurrent and overvoltage of SiC MOSFETs. The proposed gate driver can realize the variation in driving voltage and gate resistance during switching transitions. It not only suppresses the overcurrent and overvoltage of SiC MOSFETs, but also has little effect on switching loss. The working principle of the proposed gate driver is analyzed in this paper. Finally, experimental verification on a double-pulse test platform is performed to verify the effectiveness of the proposed gate driver.

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Kampitsis, Georgios E., Stavros A. Papathanassiou, and Stefanos N. Manias. "Comparative Analysis of the Thermal Stress of Si and SiC MOSFETs during Short Circuits." Materials Science Forum 856 (May 2016): 362–67. http://dx.doi.org/10.4028/www.scientific.net/msf.856.362.

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In this paper, the performance of silicon (Si) and silicon carbide (SiC) power MOSFETs during short circuits is investigated. The response of both semiconductors is examined under hard switch fault and fault under load conditions using a short circuit tester board. In addition, their failure mechanism is recorded and analyzed. Examination results show that the SiC MOSFET fails in the energy limiting mode, due to gate oxide rupture, while the Si MOSFET is destructed during the power limiting mode, at the beginning of the fault. The electro-thermal characterization of these devices is performed through three-dimensional finite element analysis, utilizing the experimentally extracted power dissipation for each transistor. Simulation results confirm the exceptional ruggedness that SiC power MOSFETs exhibit outside their safe operating area.

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Okamoto, Mitsuo, Mieko Tanaka, Tsutomu Yatsuo, and Kenji Fukuda. "Fabrication of 4H-SiC p-Channel MOSFET with High Channel Mobility." Materials Science Forum 527-529 (October 2006): 1301–4. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1301.

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We have fabricated inversion-type p-channel MOSFETs on 4H-SiC substrates. In this paper, influences of gate oxidation process on the properties of p-channel MOSFETs were investigated. The gate oxide was formed under these three conditions: (i) dry oxidation, (ii) dry oxidation following wet re-oxidation, and (iii) wet oxidation. The C-V measurements of p-type 4H-SiC MOS capacitors revealed that wet oxidation process reduced the interface states near the valence band. The p-channel MOSFET with low interface states near the valence band indicated low threshold voltage (Vth), high field effect channel mobility (μFE) and low subthreshold swing (S). We obtained 4H-SiC p-channel MOSFET with high μFE of 15.6cm2/Vs by using wet oxidation as gate oxidation process.

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Journal articles on the topic 'MOSFETs'

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