Journal articles: 'MOSFET'

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Gonçalves Filho, Luiz C., and Luiz A. P. Santos. "An electronic dosimeter for diagnostic X-ray beams based on a differential amplifier circuit with MOSFETs." EPJ Web of Conferences 288 (2023): 09001. http://dx.doi.org/10.1051/epjconf/202328809001.

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It is known that the device MOSFET works as a dosimeter in radiation beams for cancer radiotherapy. Basically, the radiation beam generates defects in a way that produces in the MOSFET the variation in its threshold voltage, VT, which is proportional to the accumulated radiation dose. Recently, MOSFETs were also tested under X-ray beams commonly used in the energy range applied to medical diagnoses, which is lower energy than radiotherapy. Indeed, it was already shown that the MOSFET drain current varies with the radiation dose for energies in the range applied to diagnostic radiology. In this paper, an innovative method based on a differential amplifier circuit with two electronically matched MOSFETs is presented. Therefore, before irradiation the differential output voltage signal, Vdif = 0. Actually, it is a differential amplifier circuit with one of the MOSFETs shielded from the ionizing radiation beam. Therefore, if such a circuit is irradiated the difference between ID1 and ID2, from MOSFET1 and MOSFET2 respectively, will result Vdif ≠ 0. To evaluate the response of this electronic dosimeter it was tested under a diagnostic radiology beam typically used in clinics to take radiography of patients. The results showed that the proposed dosimeter works and varies linearly with the radiation dose. The technology developed in this paper will allow research to be carried out for optimizing such electronic dosimeter to make it a wearable device and can be able to use it by workers exposed to ionizing radiation in nuclear power plants or even in outer space.

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Li, Ruizhe. "The advantages and short circuit characteristics of SiC MOSFETs." Applied and Computational Engineering 49, no. 1 (March 22, 2024): 58–64. http://dx.doi.org/10.54254/2755-2721/49/20241059.

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SiC MOSFETs have exhibited considerable benefits in high-frequency, high-voltage, and high-temperature power electronics applications with outstanding material attributes as a result of the rapid advancement of power electronics technology. SiC MOSFETs slower short-circuit tolerance and faster switching rates provide new issues for the short-circuit prevention technology. In the opening section of the study, Si and SiC MOSFETs are compared and evaluated using various models and parametric factors. It has been demonstrated that SiC MOSFETs outperform Si MOSFETs in a variety of conditions and applications. The many SiC MOSFET short-circuit failure types as well as their underlying theories are initially explained in the papers main body. In addition, it examines the fundamentals of short-circuit test procedures and SiC MOSFET test circuits. The issues and limitations of the currently available SiC MOSFET short-circuit protection technology are then explored, along with factors impacting the short-circuit of SiC MOSFETs that are thoroughly examined. Lastly, the SiC MOSFET short-circuit protection technology development trend is forecasted, and potential future areas for improvement and innovation are considered. SiC MOSFET short-circuit protection technology will be enhanced and optimized to satisfy the needs of efficient and dependable power electronic systems as technology advances and application requirements expand.

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Kaur Sidhu, Rajdevinder, Jagpal Singh Ubhi, Alpana Agarwal, and Balwinder Raj. "Design and Comparative Analysis of Silicon and GaAs MOSFET for Low Power Applications." Journal of Nanoelectronics and Optoelectronics 18, no. 8 (August 1, 2023): 915–23. http://dx.doi.org/10.1166/jno.2023.3460.

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The demand for low power consumption in modern electronic devices has led to the development of various technologies, including usage of different materials such as Si and GaAs. In this paper, we present a design and comparative analysis of Si and GaAs MOSFETs for low power applications. The analysis includes the electrical characteristics, performance parameters, and power consumption of both devices. The Si MOSFET and GaAs MOSFET are simulated and analyzed using TCAD tools, and the results are compared. The simulation results show that the GaAs MOSFET has a higher transconductance (gm) compared to the Si MOSFET. However, the Si MOSFET has a lower gate leakage current (Ig) and lower power consumption at low operating frequencies. We also investigate the effect of scaling on the performance and power consumption of both MOSFETs. The results show that scaling improves the performance of both devices, but the power consumption increases as the device dimensions are reduced. The comparative analysis of Si and GaAs MOSFETs for low power applications provides useful insights into the selection of suitable MOSFET technology for specific applications. The results show that both Si and GaAs MOSFETs have their advantages and disadvantages, and the choice depends on the application requirements.

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Luo, Qixiao. "Research on the advantages and development status of new material MOSFET." Highlights in Science, Engineering and Technology 33 (February 21, 2023): 210–18. http://dx.doi.org/10.54097/hset.v33i.5313.

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When using MOSFETs, in order to improve the operating speed, so that higher power density and lower functional consumption can be obtained in the process, researchers have explored in multiple dimensions. In this paper, three popular new material MOSFETs are mainly explained, including SiC MOSFET, GaN MOSFET and graphene MOSFET. This paper introduces their advantages and their development status, so as to compare the advantages of new materials. In conclusion, By adding materials, the electron mobility and stability of the FET can be increased in some situation. The research in this paper will undoubtedly promote the further development of MOSFET.

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Chek Yee, Ooi, Mok Kai Ming, and Wong Pei Voon. "DEVICE AND CIRCUIT LEVEL SIMULATION STUDY OF NOR GATE LOGIC FAMILIES DESIGNED USING NANO-MOSFETs." Platform : A Journal of Science and Technology 4, no. 1 (May 31, 2021): 73. http://dx.doi.org/10.61762/pjstvol4iss1art11064.

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The investigation of silicon-based nano-MOSFETs logic circuits is helpful to gain more comprehensive knowledge about nanoscale transistors. Therefore, a simulation study has been performed on four logic families of two inputs NOR gate logic circuits, namely (i) nano-CMOS NOR gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NOR gate, (iii) 733.8 Ω resistive loaded nano-MOSFET NOR gate, and finally (iv) pseudo-n-type nano-MOSFET NOR gate. The nano-MOSFET technology node studied in this paper is 10 nm. Device simulation is done using an online NanoMOS simulator, whereas circuit simulation is carried out using freeware WinSpice. The main obstacle encountered during downscaling of nano-MOSFETs is low power dissipation and high-speed nano-MOSFET logic circuits. Correct logical NOR operation has been proven by observing simulated timing waveforms. Transient timing analysis on nano-MOSFET loaded n-type nano-MOSFET NOR gate has shown that propagation delays calculated from theory and simulation are 66% matched. From the analysis, this 10 nm nano-MOSFET NOR logic circuit design exhibit a dynamic power reduction of 148 times and a propagation delay improvement of 33 times when benchmarked against a typical 120 nm MOSFET logic circuit. Keywords: nano transistor, electrical characteristics, channel length, channel width, benchmarking, power, speed

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Albrecht, Matthaeus, Tobias Erlbacher, Anton J. Bauer, and Lothar Frey. "Potential of 4H-SiC CMOS for High Temperature Applications Using Advanced Lateral p-MOSFETs." Materials Science Forum 858 (May 2016): 821–24. http://dx.doi.org/10.4028/www.scientific.net/msf.858.821.

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In this work, the impact of the n-well doping concentration on the channel mobility and threshold voltage of p-MOSFETs and their applications in CMOS-devices is evaluated. For this purpose lateral p-channel MOSFETs with different channel lengths (L = 800 μm, 10 μm, 5 μm, and 3 μm) and doping concentrations (ND = 1015 cm-3 and 8·1015 cm-3) were fabricated and the respective field-effect mobility was extracted from the transfer-characteristics. Comparable to n-MOSFETs the mobility of p-MOSFETs was found to be the highest for the lowest doping concentration in the channel and the absolute value of the threshold voltage increases with increasing doping concentration [4]. To investigate its suitability for CMOS applications, inverters with different doping concentrations for n-MOSFET (NA = 1015 cm-3 and 1017 cm-3) und p-MOSFET (ND = 1015 cm-3 and 8·1015 cm-3) were built. For logic levels of 0 V and 10 V, the voltage transfer characteristic with the highest input ranges was obtained for a low p-MOSFET and a high n-MOSFET doping concentration. The lowest propagation delay time could be achieved with a low p-MOSFET and a low n-MOSFET doping concentration. At room temperature as well as at high temperatures T = 573 K the drain current of p-MOSFETs with channel lengths below 3 μm is hampered by the series resistance of the source and drain region which limits the performance of CMOS devices.

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Yoshioka, Hironori, Junji Senzaki, Atsushi Shimozato, Yasunori Tanaka, and Hajime Okumura. "Characterization of Interface State Density from Subthreshold Slope of MOSFETs at Low Temperatures (≥ 10 K)." Materials Science Forum 821-823 (June 2015): 745–48. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.745.

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We have evaluated interface state density (DIT) for EC−ET > 0.00 eV from the subthreshold slope deterioration of MOSFETs at low temperatures. We have compared two n-channel MOSFETs on the C- and a-faces with the gate oxide formed by pyrogenic oxidation followed by annealing in H2. The peak field-effect mobility (µFE,peak) for the C-face MOSFET was 57 cm2V-1s-1 at 300 K, which is lower than the half of 135 cm2V-1s-1 for the a-face MOSFET. We have shown that DIT very close to EC can well explain why µFE for C-face MOSFETs is lower than that for a-face MOSFETs. The value of DIT at 0.00 eV corresponding to the subthreshold slope at 11 K was 1.6×1014 cm-2eV-1 for the C-face MOSFET, which is more than the double of 6.4×1013 cm-2eV-1 for the a-face MOSFET.

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Che, Haoming. "Simulation study on dynamic characteristics of SiC MOSFET." Theoretical and Natural Science 5, no. 1 (May 25, 2023): 805–14. http://dx.doi.org/10.54254/2753-8818/5/20230507.

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In this paper, the third generation power MOSFET is introduced, and the physical model based on silicon based MOSFET is improved for SiC MOSFET, and the commercial planar gate and trench gate 1.2kV SiC MOSFET are simulated. The accuracy of physical modals is tested by comparing the static characteristics with commercial ones. The dynamic characteristics of two MOSFETs are simulated by inductively clamped double pulse circuit, and the circuit parameters are analyzed according to the static characteristics of the devices. The switching loss of the two MOSFETs is calculated and compared by using TCAD software. In the two devices with the same volume, the trench gate structure has the larger switching loss.

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Ahn, Tae Jun, and Yun Seop Yu. "Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter." Journal of Nanoscience and Nanotechnology 21, no. 8 (August 1, 2021): 4252–57. http://dx.doi.org/10.1166/jnn.2021.19388.

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We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

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10

Lichtenwalner, Daniel J., Brett Hull, Vipindas Pala, Edward Van Brunt, Sei-Hyung Ryu, Joe J. Sumakeris, Michael J. O’Loughlin, Albert A. Burk, Scott T. Allen, and John W. Palmour. "Performance and Reliability of SiC Power MOSFETs." MRS Advances 1, no. 2 (2016): 81–89. http://dx.doi.org/10.1557/adv.2015.57.

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ABSTRACTDue to the wide bandgap and other key materials properties of 4H-SiC, SiC MOSFETs offer performance advantages over competing Si-based power devices. For example, SiC can more easily be used to fabricate MOSFETs with very high voltage ratings, and with lower switching losses. Silicon carbide power MOSFET development has progressed rapidly since the market release of Cree’s 1200V 4H-SiC power MOSFET in 2011. This is due to continued advancements in SiC substrate quality, epitaxial growth capabilities, and device processing. For example, high-quality epitaxial growth of thick, low-doped SiC has enabled the fabrication of SiC MOSFETs capable of blocking extremely high voltages (up to 15kV); while dopant control for thin highly-doped epitaxial layers has helped enable low on-resistance 900V SiC MOSFET production. Device design and processing improvements have resulted in lower MOSFET specific on-resistance for each successive device generation. SiC MOSFETs have been shown to have a long device lifetime, based on the results of accelerated lifetime testing, such as high-temperature reverse-bias (HTRB) stress and time-dependent dielectric breakdown (TDDB).

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11

Mohd Salleh, Siti NorFarah Nadia, Alhan Farhanah Abd Rahim, Nurul Syuhadah Mohd Razali, Rosfariza Radzali, Ainorkhilah Mahmood, and Irni Hamiza Hamzah. "Study of Strained-SiGe Channel P-MOSFET Using Silvaco TCAD: Impact of Channel Thickness." Key Engineering Materials 947 (May 31, 2023): 39–45. http://dx.doi.org/10.4028/p-3a337l.

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Compressively strained SiGe is an interesting channel material for sub 45 nm p-MOSFETs because of its superior hole mobility (up to 10x over bulk Si channels) and compatibility with current Si manufacturing technologies. In this work, the impact of heterostructure composition and SiGe channel thickness on the electrical characteristics of p-MOSFET are studied. Using strained Si0.8Ge0.2 p-MOSFET, the thickness was altered to a few thicknesses of 3 nm, 5 nm, 7 nm, and 9 nm respectively. The optimal thickness was then used for Ge compositions (x = 0.2). The project was realized utilizing computer-aided Silvaco TCAD tools, with ATHENA tools creating the p-MOSFET structure and ATLAS tools doing the device simulation. The strained-Si1-xGex p-MOSFET and the Si p-MOSFET were compared in terms of their performances. The ID-VG and ID-VD characteristics, as well as the threshold voltage, VTH extraction, were the focus of the device simulation. The 7 nm thickness strained-Si0.8Ge0.2 p-MOSFET exhibited lower VTH than other SiGe thicknesses and the Si p-MOSFET which is VTH = 0.074 V. The lower threshold voltage of the strained-Si0.8Ge0.2 with 7 nm thickness indicating that the strained-Si1-xGex contributed to the decreased power consumption. In addition, the extracted IDsat for the strained-Si0.8Ge0.2 p-MOSFET with 7nm thickness provided higher IDsat compared to conventional Si p-MOSFET and other SiGe thicknesses devices. As compared to Si p-MOSFETs, the output characteristics of the strained-Si1-xGex demonstrated a drain current improvement by a factor of 1.01.

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Funaki, Tsuyoshi, Yuki Nakano, and Takashi Nakamura. "Comparative Study of SiC MOSFETs in High Voltage Switching Operation." Materials Science Forum 717-720 (May 2012): 1081–84. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1081.

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SiC power device is expected to have high breakdown voltage with low on resistance, which cannot be attainable for conventional Si device. This study evaluates the switching performance of high voltage SiC MOSFETs with comparing to that of conventional Si power MOSFET having equivalent breakdown voltage. To this end, turn-on and turn-off switching operation of MOSFETs are assessed with resistive load for same conduction current density. Though the on resistance of SiC MOSFETs are quite lower than Si MOSFET, especially for trench gate type. But, SiC MOSFETs have larger terminal capacitance. Therefore, SiC MOSFETs show slower switching speed than Si MOSFETs for same current density condition.

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Chen, Jiangui, Yan Li, and Mei Liang. "A Gate Driver Based on Variable Voltage and Resistance for Suppressing Overcurrent and Overvoltage of SiC MOSFETs." Energies 12, no. 9 (April 29, 2019): 1640. http://dx.doi.org/10.3390/en12091640.

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A SiC MOSFET is a suitable replacement for a Si MOSFET due to its lower on-state resistance, faster switching speed, and higher breakdown voltage. However, due to the parasitic parameters and the low damping in the circuit, the turn-on overcurrent and turn-off overvoltage of a SiC MOSFET become more severe as the switching speed increases. These effects limit higher frequency applications of SiC MOSFET. Based on the causes of overcurrent and overvoltage of SiC MOSFET, a novel gate driver with the variable driving voltage and variable gate resistance is proposed in this paper to suppress the overcurrent and overvoltage of SiC MOSFETs. The proposed gate driver can realize the variation in driving voltage and gate resistance during switching transitions. It not only suppresses the overcurrent and overvoltage of SiC MOSFETs, but also has little effect on switching loss. The working principle of the proposed gate driver is analyzed in this paper. Finally, experimental verification on a double-pulse test platform is performed to verify the effectiveness of the proposed gate driver.

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Kong, Moufu, Zewei Hu, Ronghe Yan, Bo Yi, Bingke Zhang, and Hongqiang Yang. "A novel SiC high-k superjunction power MOSFET integrated Schottky barrier diode with improved forward and reverse performance." Journal of Semiconductors 44, no. 5 (May 1, 2023): 052801. http://dx.doi.org/10.1088/1674-4926/44/5/052801.

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Abstract A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode (Hk-SJ-SBD MOSFET) is proposed, and has been compared with the SiC high-k MOSFET (Hk MOSFET), SiC superjuction MOSFET (SJ MOSFET) and the conventional SiC MOSFET in this article. In the proposed SiC Hk-SJ-SBD MOSFET, under the combined action of the p-type region and the Hk dielectric layer in the drift region, the concentration of the N-drift region and the current spreading layer can be increased to achieve an ultra-low specific on-resistance (R on,sp). The integrated Schottky barrier diode (SBD) also greatly improves the reverse recovery performance of the device. TCAD simulation results indicate that the R on,sp of the proposed SiC Hk-SJ-SBD MOSFET is 0.67 mΩ·cm2 with a 2240 V breakdown voltage (BV), which is more than 72.4%, 23%, 5.6% lower than that of the conventional SiC MOSFET, Hk SiC MOSFET and SJ SiC MOSFET with the 1950, 2220, and 2220 V BV, respectively. The reverse recovery time and reverse recovery charge of the proposed MOSFET is 16 ns and18 nC, which are greatly reduced by more than 74% and 94% in comparison with those of all the conventional SiC MOSFET, Hk SiC MOSFET and SJ SiC MOSFET, due to the integrated SBD in the proposed MOSFET. And the trade-off relationship between the R on,sp and the BV is also significantly improved compared with that of the conventional MOSFET, Hk MOSFET and SJ MOSFET as well as the MOSFETs in other previous literature, respectively. In addition, compared with conventional SJ SiC MOSFET, the proposed SiC MOSFET has better immunity to charge imbalance, which may bring great application prospects.

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Chaudhry, Amit, and Nath Roy. "A comparative study of hole and electron inversion layer quantization in MOS structures." Serbian Journal of Electrical Engineering 7, no. 2 (2010): 185–93. http://dx.doi.org/10.2298/sjee1002185c.

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In this paper, an analytical model has been developed to study inversion layer quantization in nanoscale Metal Oxide Semiconductor Field Effect Oxide p-(MOSFET). n-MOSFETs have been studied using the variation approach and the p-MOSFETs have been studied using the triangular well approach. The inversion charge density and gate capacitance analysis for both types of transistors has been done. There is a marked decrease in the inversion charge density and the capacitance of the p-MOSFET as compared to n-MOSFETs. The results are compared with the numerical results showing good agreement.

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Ebiike, Yuji, Toshikazu Tanioka, Masayuki Furuhashi, Ai Osawa, and Masayuki Imaizumi. "Characteristics of High-Threshold-Voltage Low-Loss 4H-SiC MOSFETs with Improved MOS Cell Structure." Materials Science Forum 858 (May 2016): 829–32. http://dx.doi.org/10.4028/www.scientific.net/msf.858.829.

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High threshold voltage low loss 600 V 4H-SiC MOSFETs have been fabricated successfully using a re-oxidation technique for gate oxides and an n-type doping in the Junction Field Effect Transistor region of the MOSFET with shrunk MOS cells. The MOSFET has exhibited a high threshold voltage of more than 4 V and a low specific on resistance of 5.2 mΩ·cm2 at 25 °C. The MOSFET has also exhibited a sufficient blocking characteristic at VG of 0 V at 150 °C. High speed switching with low switching losses has been demonstrated successfully using the MOSFET at 150 °C.

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Na, Jaeyeop, and Kwangsoo Kim. "A Novel 4H-SiC Double Trench MOSFET with Built-In MOS Channel Diode for Improved Switching Performance." Electronics 12, no. 1 (December 26, 2022): 92. http://dx.doi.org/10.3390/electronics12010092.

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This study proposed a novel 4H-SiC double trench metal-oxide-semiconductor field-effect-transistor (DTMCD-MOSFET) structure with a built-in MOS channel diode. Further, its characteristics were analyzed using TCAD simulation. The DTMCD-MOSFET comprised active and dummy gates that were divided horizontally; the channel diode operated through the dummy gate and the p-base and N+ source regions at the bottom of the dummy gate. Because the bult-in channel diode was positioned at the bottom, the DTMCD-MOSEFT minimized static deterioration. Despite having a 5.2% higher specific on-resistance (Ron-sp) than a double-trench MOSFET (DT-MOSFET), the DTMCD-MOSFET exhibited a significantly superior body diode and switching properties. In comparison to the DT-MOSFET, its turn-on voltage (VF) and reverse recovery charge (Qrr) were decreased by 27.2 and 30.2%, respectively, and the parasitic gate-drain capacitance (Crss) was improved by 89.4%. Thus, compared with the DT-MOSFET, the total switching energy loss (Etot) was reduced by 41.4%.

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Qiu, Guoqing, Kedi Jiang, Shengyou Xu, Xin Yang, and Wei Wang. "Modeling and analysis of the characteristics of SiC MOSFET." Journal of Physics: Conference Series 2125, no. 1 (November 1, 2021): 012051. http://dx.doi.org/10.1088/1742-6596/2125/1/012051.

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Abstract Although the superior performance of SiC MOSFET devices has beenvalidated by many studies, it is necessary to overcome many technical bottlenecks to make SiC MOSFET gradually replace Si-based power devices into the mainstream. In view of the current situation where the performance of SiC MOSFETs in power conversion devices cannot be evaluated well at this stage, it is necessary to carry out fine modeling of SiC MOSFETs and establish accurate simulation models. In this paper, the powerful mathematical processing capability and rich modules of Matlab/Simulink are used to build a SiC MOSFET model, and then the product data sheet is compared with the fitted data. The results show that the switching simulation waveforms are in general agreement with the data sheet waveforms, and the error is less than 7%. Verifing the accuracy of the model and reducing the difficulty of modeling, it provides a new idea for establishing the circuit simulation model of SiC MOSFET in Matlab/Simulink.

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Singh, Ajay Kumar. "Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 2 (March 4, 2019): 815–28. http://dx.doi.org/10.1108/compel-08-2018-0327.

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Purpose This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs. Design/methodology/approach This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach. Findings It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement. Originality/value Compact Analytical models for undoped symmetric double gate MOSFETs.

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Dzakwan, Muhammad Irfan, Iwan Setiawan, Agung Warsito, and Trias Andromeda. "PERANCANGAN KONVERTER ARUS SEARAH TIPE PENURUN TEGANGAN DENGAN MOSFET SINKRON DAN TANPA MOSFET SINKRON." TRANSIENT 7, no. 1 (March 21, 2018): 160. http://dx.doi.org/10.14710/transient.7.1.160-165.

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Sistem elektronika saat ini membutuhkan sumber daya yang memiliki efisiensi tinggi. Konverter arus searah berfungsi untuk mengkonversi tegangan masukan arus searah menjadi tegangan keluaran arus searah dengan nilai yang berbeda, selain itu dapat juga digunakan untuk mengatur tegangan keluaran terhadap variasi beban. Peningkatan efisiensi pada konverter arus searah dapat dilakukan dengan mengganti saklar pasif yang berupa dioda dengan saklar aktif yang berupa MOSFET. Konverter arus searah yang telah menggunakan MOSFET sebagai pengganti dari dioda bisa disebut sebagai konverter arus searah sinkron. Pada penelitian ini merancang sebuah konverter arus searah tipe penurun tegangan. Perancagan alat pada penelitian ini akan mengaplikasikan metode sinkronisasi MOSFET dengan cara mengaktifkan kedua MOSFET secara bergantian dan bekerja pada besaran frekuensi yang sama. Pada penelitian ini akan dilakukan perbandingan efisiensi antara konverter arus searah dengan MOSFET sinkron dan tanpa MOSFET sinkron. Pada konverter arus searah tipe penurun tegangan tanpa MOSFET sinkron semakin tinggi duty cycle maka akan semakin tinggi nilai efisisiensinya. Pada konverter arus searah dengan MOSFET sinkron nilai efisiensi cenderung stabil pada duty cycle berapapun. Pada penelitian ini didapatkan hasil bahwa konverter arus searah tipe penurun tegangan dengan MOSEFT sinkron lebih efisien daripada konverter arus searah tipe penurun tegangan tanpa MOSFET sinkron.

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Han, Ki Jeong, B. Jayant Baliga, and Woong Je Sung. "1.2 kV 4H-SiC Split-Gate Power MOSFET: Analysis and Experimental Results." Materials Science Forum 924 (June 2018): 684–88. http://dx.doi.org/10.4028/www.scientific.net/msf.924.684.

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This paper presents a 1.2kV-rated 4H-SiC Split-Gate power MOSFET (SG-MOSFET) with superior high frequency figures-of-merit (HF-FOM). Electrical characteristics including reverse transfer capacitance and gate-to-drain charge are measured from fabricated devices on a 6-inch SiC wafer, demonstrating excellent performance. Compared to the conventional MOSFETs, the SG-MOSFET provides about 7x smaller HF-FOM [RonxCgd] and 2x smaller HF-FOM [RonxQgd] with improved reverse transfer capacitance and gate-to-drain charge.

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Na, Jaeyeop, Minju Kim, and Kwangsoo Kim. "High Performance 3.3 kV SiC MOSFET Structure with Built-In MOS-Channel Diode." Energies 15, no. 19 (September 22, 2022): 6960. http://dx.doi.org/10.3390/en15196960.

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Built-in freewheeling diode metal–oxide–semiconductor field-effect transistors (MOSFETs) that ensure high performance and reliability at high voltages are crucial for chip integration. In this study, a 4H–SiC built-in MOS-channel diode MOSFET with a center P+ implanted structure (CIMCD–MOSFET) is proposed and simulated via technology computer-aided design (TCAD). The CIMCD–MOSFET contains a P+ center implant region, which protects the gate oxide edge from high electric field crowding. Moreover, the region also makes it possible to increase the junction FET (JFET) and N-drift doping concentration of the device by dispersing the high electric field. Consequently, the CIMCD–MOSFET is stable even at a high voltage of 3.3 kV without static degradation and gate oxide reliability issues. The CIMCD–MOSFET also has higher short-circuit withstanding capability owing to the low saturation current and improved switching characteristics due to the low gate-drain capacitance, compared to the conventional MOSFET (C–DMOSFET) and the built-in Schottky barrier diode MOSFET (SBD–MOSFET). The total switching time of a CIMCD–MOSFET is reduced by 52.2% and 42.2%, and the total switching loss is reduced by 67.8% and 41.8%, respectively, compared to the C–DMOSFET and SBD–MOSFET.

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Petrosyants, Konstantin O., Igor A. Kharitonov, and Lev M. Sambursky. "Hardware-Software Subsystem for MOSFETs Characteristic Measurement and Parameter Extraction with Account for Radiation Effects." Advanced Materials Research 718-720 (July 2013): 750–55. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.750.

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Hardware-software subsystem designed for MOSFETs characteristic measurement and SPICE model parameter extraction taking into account radiation effects is presented. Parts of the system are described. The macromodel approach is used to account for radiation effects in MOSFET modeling. Particularities of the account for radiation effects in MOSFETs within the measurement and model parameter extraction procedures are emphasized. Application of the subsystem is illustrated on the example of radiation hardened 0.25 μm SOI MOSFET test structures.

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Hsu, Fu Jen, Cheng Tyng Yen, Hsiang Ting Hung, Jia Wei Hu, and Chih Fang Huang. "High Density 65W AC-DC Adaptor Enabled by SiC MOSFET with Ultralow VGS(on)." Key Engineering Materials 948 (June 6, 2023): 89–93. http://dx.doi.org/10.4028/p-tuypqj.

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SiC MOSFETs are rarely used in low-power consumer applications because of their cost and gate driving circuitry requirement. In this work, a cost-efficient SiC MOSFET with a usable 10V of VGS is proposed. The proposed SiC MOSFET could enable low-power applications, which is around tens to hundreds of watt, to implement SiC MOSFETs. As a result, the thermal performance is better than the GaN solution thanks to the better thermal conductance of the SiC.

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Patel, Dax, Soham Sojitra, Jay Kadia, Bhavik Chaudhary, and Rutu Parekh. "Comparative Study of Double Gate and Silicon on Insulator MOSFET by Varying Device Parameters." Trends in Sciences 19, no. 7 (March 14, 2022): 3216. http://dx.doi.org/10.48048/tis.2022.3216.

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A comparative study of the single gate MOSFET (SG MOSFET), double-gate MOSFET (DG MOSFET) and silicon-on-insulator MOSFET (SOI MOSFET) is done using MOSFET simulation tool. Device simulation is done by varying different physical parameters of the device structure such as oxide thickness, channel length, temperature and different gate electrodes. Contour plots of SOI and DG MOSFET for electron concentration and potential at initial and final bias are simulated. The drain current vs gate voltage (Id-Vg) characteristics performance simulations show that DG MOSFET is better than SOI MOSFET for different oxide thickness and channel length. It was further noticed that with an increase in the oxide thickness, drain current decreases for DG and SOI MOSFETs. When oxide thickness is reduced from 10 to 7 nm keeping all other parameters same, in DG MOSFET drain current increased by 49.49 % and in SOI MOSFET drain current increased by 66.6 %. When channel length is reduced from 80 to 75 nm in DG MOSFET drain current increased by 1.35 % and in SOI MOSFET drain current increased by 2 %. The performance simulations show that aluminium (Al) gate electrode is better than n+ poly silicon (Si) and tungsten (W) for every MOSFET devices. With respect to aluminium gate electrode in DG MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.89 and 30.5 %, respectively and in SOI MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.84 and 34.61 %, respectively. HIGHLIGHTS Comparative study of Double Gate and Silicon on Insulator MOSFET Simulation of DG and SOI MOSFET using MOSFET simulation tool on nanohub.org Performance analysis of DG and SOI MOSFET by varying different physical parameters like oxide thickness, channel length, temperature and gate electrodes Drain current vs gate voltage (Id-Vg) characteristics performance simulation of DG and SOI MOSFET Contour plot for electron concentration and potential GRAPHICAL ABSTRACT

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Devadas, Shree Chakravarthy, and Ramani Kannan. "COMPARATIVE ANALYSIS OF THERMAL STRESS OF Si AND SiC MOSFETs." Platform : A Journal of Engineering 5, no. 2 (June 30, 2021): 23. http://dx.doi.org/10.61762/pajevol5iss2art12810.

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The performance of power MOSFET is affected by high thermal stress exposure. A high level of thermal stress is induced when the MOSFET experiences a temperature change. This finding is about the bonding wire lift-off on the solder pad. The MOSFET model is designed with the heatsink to ensure accurate results are obtained in this research work. The key intention of this research is to investigate the condition of silicon and silicon carbide power MOSFETs during thermal stress. The thermal properties of silicon and silicon carbide MOSFET were investigated by developing a 3D modal and thermal stress simulation in the COMSOL Multiphysics software. Thermal resistance was calculated by randomly selecting a power loss value of 100 Watts. Junction temperature for silicon and silicon carbide MOSFET was taken from several articles mentioned in the results and discussion. Keywords: Thermal stress, bonding wire lift-off, temperature change, MOSFET

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Allen, Scott, Vipindas Pala, E. VanBrunt, Brett Hull, Lin Cheng, S. Ryu, Jim Richmond, M. O’Loughlin, Al Burk, and J. Palmour. "Next-Generation Planar SiC MOSFETs from 900 V to 15 kV." Materials Science Forum 821-823 (June 2015): 701–4. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.701.

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A family of planar MOSFETs with voltage ratings from 900 V to 15 kV are demonstrated. This family of planar MOSFETs represents Cree’s next generation MOSFET design and process, in which we continue to refine and evolve device design and processing to further shrink die sizes and enhance device performance. At voltage ratings of 3.3 kV and above, the specific on-resistance of the MOSFETs is approaching the theoretical limit. MOSFET switching performance in a clamped inductive switching circuit for the full range of voltage ratings is also demonstrated. Finally, improved threshold voltage and body diode stability under long-term stresses are presented.

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Das, Sanat, Bibek Chettri, Prasanna Karki, Bhakta Kunwar, Pronita Chettri, and Bikash Sharma. "Impact of high-k metal oxide as gate dielectric on the certain electrical properties of silicon nanowire field-effect transistors: A simulation study." Facta universitatis - series: Electronics and Energetics 36, no. 4 (2023): 553–65. http://dx.doi.org/10.2298/fuee2304553d.

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Standard Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are gaining prominence in low-power nanoscale applications. This is largely attributed to their proximity to physical and thermal limits, rendering them a compelling option for energy-efficient electronic devices. In this study, we hypothesized that the high-? HfO2 in a quasi-ballistic SiNW MOSFET acts as the gate dielectric. In this case, the data from the TCAD simulation and the model demonstrated exceptional agreement. The proposed model for a SiNW MOSFET with high-? HfO2 exhibits a consistently increasing drain current, albeit with a smaller magnitude compared to a quasi-ballistic device (QBD). Additionally, it shows reduced mobility and decreased transconductance when considering the combined effects of scattering and temperature. As gate voltage increases, temperatureinduced transconductance decline in SiNW MOSFETs becomes significant. Our method is suitable for modeling scattered SiNW MOSFETs with temperature effects, as TGF values are similar in the subthreshold region for both Near Ballistic and Scattered SiNW MOSFET models.

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Liu, Hao, Jiaxing Wei, Zhaoxiang Wei, Siyang Liu, and Longxing Shi. "Experimental Comparison of a New 1.2 kV 4H-SiC Split-Gate MOSFET with Conventional SiC MOSFETs in Terms of Reliability Robustness." Electronics 12, no. 11 (June 5, 2023): 2551. http://dx.doi.org/10.3390/electronics12112551.

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In this paper, we compare a new 1.2 kV rated 4H-SiC split-gate (SG) MOSFET with the conventional planar-gate (PG) MOSFETs. Both structures were fabricated with the same design rules and process platform. Therefore, the structures have similar electrical parameters, such as ON-state drain-source resistance (RON), breakdown voltage (BV), threshold voltage (Vth), and body diode forward voltage (VSD). It is shown that the Ciss/Coss/Crss capacitances of the SG-MOSFET can be reduced by 7%/8%/17%, respectively, compared with PG-MOSFET. It is also shown that the SG-MOSFET has the potential to reduce switching losses without compromising the static performance. Moreover, it maintains the robustness of the device, and an optimized layout design with spaced holes in the gate poly is adopted. Therefore, there is no obvious degradation between the SG-MOSFET and the PG-MOSFET in terms of avalanche and short-circuit endurance capabilities.

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Kannan, Ramani, Saranya Krishnamurthy, Chay Che Kiong, and Taib B. Ibrahim. "Impact of gamma-ray irradiation on dynamic characteristics of Si and SiC power MOSFETs." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 2 (April 1, 2019): 1453. http://dx.doi.org/10.11591/ijece.v9i2.pp1453-1460.

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Power electronic devices in spacecraft and military applications requires high radiation tolerant. The semiconductor devices face the issue of device degradation due to their sensitivity to radiation. Power MOSFET is one of the primary components of these power electronic devices because of its capabilities of fast switching speed and low power consumption. These abilities are challenged by ionizing radiation which damages the devices by inducing charge built-up in the sensitive oxide layer of power MOSFET. Radiations degrade the oxides in a power MOSFET through Total Ionization Dose effect mechanism that creates defects by generation of excessive electron–hole pairs causing electrical characteristics shifts. This study investigates the impact of gamma ray irradiation on dynamic characteristics of silicon and silicon carbide power MOSFET. The switching speed is limit at the higher doses due to the increase capacitance in power MOSFETs. Thus, the power circuit may operate improper due to the switching speed has changed by increasing or decreasing capacitances in power MOSFETs. These defects are obtained due to the penetration of Cobalt60 gamma ray dose level from 50krad to 600krad. The irradiated devices were evaluated through its shifts in the capacitance-voltage characteristics, results were analyzed and plotted for the both silicon and silicon carbide power MOSFET.

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Taberkit, Amine Mohammed, Ahlam Guen-Bouazza, and Benyounes Bouazza. "Modeling and Simulation of Biaxial Strained P-MOSFETs: Application to a Single and Dual Channel Heterostructure." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (February 1, 2018): 421. http://dx.doi.org/10.11591/ijece.v8i1.pp421-428.

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The objectives of this work are focused on the application of strained silicon on MOSFET transistor. To do this, impact and benefits obtained with the use of strained silicon technology on p-channel MOSFETs are presented. This research attempt to create conventional and two-strained silicon MOSFETs fabricated from the use of TCAD, which is a simulation tool from Silvaco. In our research, two-dimensional simulation of conventional MOSFET, biaxial strained PMOSFET and dual channel strained P-MOSFET has been achieved to extract their characteristics. ATHENA and ATLAS have been used to simulate the process and validate the electronic characteristics. Our results allow showing improvements obtained by comparing the three structures and their characteristics. The maximum of carrier mobility improvement is achieved with percentage of 35.29 % and 70.59 % respectively, by result an improvement in drive current with percentage of 36.54 % and 236.71 %, and reduction of leakage current with percentage of 59.45 % and 82.75 %, the threshold voltage is also enhaced with percentage of: 60 % and 61.4%. Our simulation results highlight the importance of incorporating strain technology in MOSFET transistors.

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Grabiński, Władysław, Matthias Bucher, Jean-Michel Sallese, and Franc¸ois Krummenacher. "Advanced compact modeling of the deep submicron technologies." Journal of Telecommunications and Information Technology, no. 3-4 (December 30, 2000): 31–42. http://dx.doi.org/10.26636/jtit.2000.3-4.29.

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The technology of CMOS large-scale integrated circuits (LSI`s) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 um LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model

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Kawahara, Koutarou, Shiro Hino, Koji Sadamatsu, Yukiyasu Nakao, Toshiaki Iwamatsu, Shuhei Nakata, Shingo Tomohisa, and Satoshi Yamakawa. "Impact of Embedding Schottky Barrier Diodes into 3.3 kV and 6.5 kV SiC MOSFETs." Materials Science Forum 924 (June 2018): 663–66. http://dx.doi.org/10.4028/www.scientific.net/msf.924.663.

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External Schottky barrier diodes (SBDs) used as free-wheel diodes should be larger in higher voltage devices to avoid bipolar degradation consequent on current conduction of body diodes in SiC MOSFETs. By embedding an external SBD into an SiC MOSFET, we achieved compact 3.3 kV and 6.5 kV SiC MOSFETs that are free from bipolar degradation. The active area of the 3.3 kV/6.5 kV samples is only about a half/quarter of the total active area of a conventional MOSFET and a coupled external SBD.

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Cho, Geunho. "A Study on the Design Method of Hybrid MOSFET-CNTFET Based SRAM – A Secondary Publication." Journal of Electronic Research and Application 8, no. 1 (February 20, 2024): 106–12. http://dx.doi.org/10.26689/jera.v8i1.6115.

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More than 10,000 carbon nanotube field-effect transistors (CNTFETs) have been successfully integratedinto one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Thesetransistors offer advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, andtransparency. The three-dimensional multilayer structure of the CNTFET semiconductor chip, along with ongoing researchin CNTFET manufacturing processes, increases the potential for creating a hybrid MOSFET-CNTFET semiconductorchip. This chip combines conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and CNTFETs inone integrated system. This paper discusses a methodology to design 6T binary static random-access memory (SRAM)using a hybrid MOSFET-CNTFET. This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAMby leveraging existing MOSFET SRAM or CNTFET SRAM design approaches. Additionally, this paper compares itsperformance with conventional MOSFET SRAM and CNTFET SRAM designs.

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Hino, Shiro, Masanao Ito, Naruhisa Miura, Masayuki Imaizumi, and Satoshi Yamakawa. "Investigation on Internally Unbalanced Switching Behavior for Realization of 1-cm² SiC-MOSFET." Materials Science Forum 778-780 (February 2014): 963–66. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.963.

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The influences of internally unbalanced switching behavior on the switching characteristics and RBSOA were investigated in order to realize a large-size SiC-MOSFET. Specially designed small-size MOSFETs in which the unbalanced behavior is enhanced by adjusting the geometrical gate structures were fabricated, and their switching characteristics were evaluated. It was found that the same switching characteristics can be obtained by regarding them as MOSFETs with high inner gate resistances. A 1-cm2 SiC-MOSFET was fabricated, and high dV/dt switching and high turn-off endurance were demonstrated.

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Ataseven, Ismail, Ilker Sahin, and Salih Baris Ozturk. "Design and Implementation of a Paralleled Discrete SiC MOSFET Half-Bridge Circuit with an Improved Symmetric Layout and Unique Laminated Busbar." Energies 16, no. 6 (March 21, 2023): 2903. http://dx.doi.org/10.3390/en16062903.

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Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) have many advantages compared to silicon (Si) MOSFETs: low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency. As a result, Si MOSFETs are replaced with SiC MOSFETs in many industrial applications. However, there are still not as many SiC modules to customize for each application. To meet the high-power requirement for custom applications, paralleling discrete SiC MOSFETs is an essential solution. However, it comes with many technical challenges; inequality in current sharing, different switching losses, different transient characteristics, and so forth. In this paper, the detailed MATLAB®/Simulink® Simpscape model of the SiC MOSFET from the datasheet and the simulation of the half-bridge circuit are investigated. Furthermore, this paper proposes the implementation of the four-paralleled SiC MOSFET half-bridge circuit with an improved symmetric gate driver layout. Moreover, a unique laminated busbar connected directly to the printed circuit board (PCB) is proposed to increase current and thermal capacity and decrease parasitic effects. Finally, the experimental and simulation results are presented using a 650 V SiC MOSFET (CREE) double-pulse test (DPT) circuit. The voltage overshoot problems and applied solutions are also presented.

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Cha, Kyuhyun, and Kwangsoo Kim. "Asymmetric Split-Gate 4H-SiC MOSFET with Embedded Schottky Barrier Diode for High-Frequency Applications." Energies 14, no. 21 (November 4, 2021): 7305. http://dx.doi.org/10.3390/en14217305.

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4H-SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) with embedded Schottky barrier diodes are widely known to improve switching energy loss by reducing reverse recovery characteristics. However, it weakens the static characteristics such as specific on-resistance and breakdown voltage. To solve this problem, in this paper, an Asymmetric 4H-SiC Split Gate MOSFET with embedded Schottky barrier diode (ASG-MOSFET) is proposed and analyzed by conducting a numerical TCAD simulation. Due to the asymmetric structure of ASG-MOSFET, it has a relatively narrow junction field-effect transistor width. Therefore, despite using the split gate structure, it effectively protects the gate oxide by dispersing the high drain voltage. The Schottky barrier diode (SBD) is also embedded next to the gate and above the Junction Field Effect transistor (JFET) region. Accordingly, since the SBD and the MOSFET share a current path, the embedded SBD does not increase in RON,SP of MOSFET. Therefore, ASG-MOSFET improves both static and switching characteristics at the same time. As a result, compared to the conventional 4H-SiC MOSFET with embedded SBD, Baliga′s Figure of Merit is improved by 17%, and the total energy loss is reduced by 30.5%, respectively.

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LIU, WEIDONG, and CHENMING HU. "BSIM3V3 MOSFET MODEL." International Journal of High Speed Electronics and Systems 09, no. 03 (September 1998): 671–701. http://dx.doi.org/10.1142/s0129156498000294.

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The BSIM3v3 compact MOSFET model is reviewed. It is a physics-based model that is accurate, smooth, continuous, scalable, predictive and computationally robust over different regions of operation and a wide geometry range. BSIM3v3 considers all major physical effects in deep submicron MOSFETs, making it a good base for future sub-0.1m device models and for statistical circuit designs. A key feature of the model lies in its thorough, accurate and functional mathematical representation of MOS device physics, which has made BSIM3v3 selected by an international consortium of semiconductor companies as the first industry standard MOSFET model.

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Ejury, Jens. "Advanced Thermal Simulation Model for Power MOSFETs." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000598–603. http://dx.doi.org/10.4071/isom-2013-wa64.

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Modern Power MOSFETs are widely used for high efficiency SMPS applications. Also, they provide very low on-resistance which reduces conduction losses in Oring or eFuse applications. These applications as well as others have transition states in which they drive the MOSFET in linear mode operation during turn-on and turn-off events respectively. The high cell density in modern Power MOSFETs provokes uneven current distribution in linear mode operation which locally stresses certain cell areas more than others. To prevent destruction, the SOA of these MOSFETs has a thermal limit line boundary imposed. With existing L3 MOSFET models it is possible to simulate temperature rise and power loss of the entire MOSFET. However, the local heating effect is not represented in this model. Here, a wrapper is being introduced. It converts a standard L3-model into a model that incorporates a dynamic representation of the entire SOA diagram. The temperature rise follows the hottest cell so that simulations in linear mode become a valid way to predict the highest junction temperature. The limitations of this approach will be outlined.

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Bakhoum, Ezzat G., and Cheng Zhang. "Field Effect Transistor with Nanoporous Gold Electrode." Micromachines 14, no. 6 (May 28, 2023): 1135. http://dx.doi.org/10.3390/mi14061135.

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Nanoporous gold (NPG) has excellent catalytic activity and has been used in the recent literature on this issue as a sensor in various electrochemical and bioelectrochemical reactions. This paper reports on a new type of metal–oxide–semiconductor field-effect transistor (MOSFET) that utilizes NPG as a gate electrode. Both n-channel and p-channel MOSFETs with NPG gate electrodes have been fabricated. The MOSFETs can be used as sensors and the results of two experiments are reported: the detection of glucose and the detection of carbon monoxide. A detailed comparison of the performance of the new MOSFET to that of the older generation of MOSFETs fitted with zinc oxide gate electrodes is given.

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Vanitha, Dr D. "Comparative Analysis of Power switches MOFET and IGBT Used in Power Applications." International Journal on Recent Technologies in Mechanical and Electrical Engineering 9, no. 5 (May 31, 2022): 01–09. http://dx.doi.org/10.17762/ijrmee.v9i5.368.

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In this paper, deals with detailed analysis between MOSFET and IGBT. There always a race between MOSFET and IGBT in the power electronics markets. This paper will gives the complete details about them. This paper also discuss how they are used for various applications. By reading this paper any beginners who wants to need detailed analysis between IGBT and MOSGET they can get.

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Vanitha, Dr D. "Comparative Analysis of Power switches MOFET and IGBT Used in Power Applications." International Journal on Recent Technologies in Mechanical and Electrical Engineering 9, no. 3 (September 23, 2022): 01–09. http://dx.doi.org/10.17762/ijrmee.v9i3.368.

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In this paper, deals with detailed analysis between MOSFET and IGBT. There always a race between MOSFET and IGBT in the power electronics markets. This paper will gives the complete details about them. This paper also discuss how they are used for various applications. By reading this paper any beginners who wants to need detailed analysis between IGBT and MOSGET they can get.

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43

Green, Ronald, Aivars J. Lelis, and Daniel B. Habersat. "Charge Trapping in Sic Power MOSFETs and its Consequences for Robust Reliability Testing." Materials Science Forum 717-720 (May 2012): 1085–88. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1085.

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Threshold voltage (VT) instability remains an important issue for the performance, reliability, and qualification of SiC power MOSFET devices. The direct application of existing reliability test standards to SiC power MOSFETs can in some cases result in an inconsistent pass/fail response for a given device. To ensure SiC MOSFET device reliability, some modifications to existing test methods may be necessary..

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Okada, Masakazu, Teruaki Kumazawa, Yusuke Kobayashi, Masakazu Baba, and Shinsuke Harada. "Highly Efficient Switching Operation of 1.2 kV-Class SiC SWITCH-MOS." Materials Science Forum 1004 (July 2020): 795–800. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.795.

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A 1.2 kV silicon carbide (SiC) SBD-wall-integrated trench metal oxide semiconductor field effect transistor (MOSFET) (SWITCH-MOS) exhibits potential for solving body-PiN-diode-related problems such as bipolar forward degradation and switching losses among relatively low breakdown voltage 1.2 kV-class SiC MOSFETs. In this study, dynamic characteristics and switching losses of the SWITCH-MOS and conventional MOSFET are compared. The results demonstrate that the SWITCH-MOS exhibits smaller turn-on and reverse recovery losses than a conventional MOSFET at high temperatures. Ruggedness performances such as short circuit and unclamped inductive switching capabilities were evaluated.

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Wu, Li-Feng, Yong Guan, Xiao-Juan Li, and Jie Ma. "Anomaly Detection and Degradation Prediction of MOSFET." Mathematical Problems in Engineering 2015 (2015): 1–5. http://dx.doi.org/10.1155/2015/573980.

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The MOSFET is an important power electronic transistor widely used in electrical systems. Its reliability has an effect on the performance of systems. In this paper, the failure models and mechanisms of MOSFETs are briefly analyzed. The on-resistanceRonis the key failure precursor parameter representing the degree of degradation. Based on the experimental data, a nonlinear dual-exponential degradation model for MOSFETs is obtained. Then, we present an approach for MOSFET degradation state prediction using a strong tract filter based on the obtained degradation model. Lastly, the proposed algorithm is shown to perform effectively on experimental data. Thus, it can provide early warning and enhance the reliability of electrical systems.

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Gu, Jie, Qingzhu Zhang, Zhenhua Wu, Jiaxin Yao, Zhaohao Zhang, Xiaohui Zhu, Guilei Wang, et al. "Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs." Nanomaterials 11, no. 2 (January 26, 2021): 309. http://dx.doi.org/10.3390/nano11020309.

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A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

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Abdelmalek, N., F. Djeffal, M. Meguellati, and T. Bendib. "Numerical Analysis of Nanoscale Junctionless MOSFET Including Effects of Hot-Carrier Induced Interface Charges." Advanced Materials Research 856 (December 2013): 137–41. http://dx.doi.org/10.4028/www.scientific.net/amr.856.137.

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In this work, we aim at highlighting the immunity of the junctionless Gate All Around (JLGAA) MOSFET against the induced interface tarps degradation at nanoscale level. In this context, a numerical investigation has been proposed to study the subthreshold behavior of the (JLGAA) MOSFET for ultra-low power applications. Based on 2-D numerical investigation, a small-signal parameters model for nanoscale JLGAA MOSFETs, including the hot-carrier induced interface charge effects, is developed. The numerical analysis has been used to simulate the transconductance and output-conductance in subthreshold region and to compare the performance of the investigated design and conventional GAA MOSFET, where the hot-carrier effects are included. High reliability, low fabrication cost and integration ability make JLGAA MOSFET promising candidate to improve the device reliability for the ultra-low power applications.

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Jena, Biswajit, Sidhartha Dash, Soumya Ranjan Routray, and Guru Prasad Mishra. "Inner-Gate-Engineered GAA MOSFET to Enhance the Electrostatic Integrity." Nano 14, no. 10 (October 2019): 1950128. http://dx.doi.org/10.1142/s1793292019501285.

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Gate-all-around (GAA) MOSFETs are the best multi-gate MOSFET structure due to their strong electrostatic control over the channel. The electrostatic controllability can be enhanced further by applying some gate engineering technique to the existing GAA structure. This paper investigates the effect of inner gate (core gate) on the electrostatic performance of conventional GAA MOSFET. The inner gate engineering increases both the electrostatic control and packing density of GAA MOSFET. In this paper, we have presented an inner-gate-engineered (IGE) GAA MOSFET and inspected its advantages over conventional counterparts. The proposed structure exhibits higher [Formula: see text] ratio, low threshold voltage and improved RF performances as compared to the conventional structure. Analytic simulation has been carried out for numerous figures of merit (FOMs) for different technology nodes.

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Ibrahim, Mesfin Seid, Waseem Abbas, Muhammad Waseem, Chang Lu, Hiu Hung Lee, Jiajie Fan, and Ka-Hong Loo. "Long-Term Lifetime Prediction of Power MOSFET Devices Based on LSTM and GRU Algorithms." Mathematics 11, no. 15 (July 26, 2023): 3283. http://dx.doi.org/10.3390/math11153283.

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Predicting the long-term lifetime of power MOSFET devices plays a central role in the prevention of unprecedented failures for power MOSFETs used in safety-critical applications. The various traditional model-based approaches and statistical and filtering algorithms for prognostics have limitations in terms of handling the dynamic nature of failure precursor degradation data for these devices. In this paper, a prognostic model based on LSTM and GRU is developed that aims at estimating the long-term lifetime of discrete power MOSFETs using dominant failure precursor degradation data. An accelerated power cycling test has been designed and executed to collect failure precursor data. For this purpose, commercially available power MOSFETs passed through power cycling tests at different temperature swing conditions and potential failure precursor data were collected using an automated curve tracer after certain intervals. The on-state resistance degradation data identified as one of the dominant failure precursors and potential aging precursors has been analyzed using RNN, LSTM, and GRU-based algorithms. The LSTM and GRU models have been found to be superior compared to RNN, with MAPE of 0.9%, 0.78%, and 1.72% for MOSFET 1; 0.90%, 0.66%, and 0.6% for MOSFET 5; and 1.05%, 0.9%, and 0.78%, for MOSFET 9, respectively, predicted at 40,000 cycles. In addition, the robustness of these methods is examined using training data at 24,000 and 54,000 cycles of starting points and is able to predict the long-term lifetime accurately, as evaluated by MAPE, MSE, and RMSE metrics. In general, the prediction results showed that the prognostics algorithms developed were trained to provide effective, accurate, and useful lifetime predictions and were found to address the reliability concerns of power MOSFET devices for practical applications.

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Gowthaman, Naveenbalaji, and Viranjay Srivastava. "Analysis of InN/La2O3 Twosome for Double-Gate MOSFETs for Radio Frequency Applications." Materials Science Forum 1048 (January 4, 2022): 147–57. http://dx.doi.org/10.4028/www.scientific.net/msf.1048.147.

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Abstract:

The channel material of a gate describes the operating condition of the MOSFET. A suitable operating condition prevails in MOSFETs if the transistors are quite enough to observe and control at the nanometer regime. An efficient gate and channel material have been proposed in this work which is based on the electrical properties they exhibit at the temperature of 300K. The doping concentration for the electrons and holes is maintained to be 1Χ1019cm-3 for the entire electronic simulator. The simulation results show that using La2O3 along with Indium Nitride (InN) material for the designing of Double-Gate (DG) MOSFETs provides better controllability over the transistor at a channel length of 50nm. This proposed DG-MOSFET is more compliant than the conventional coplanar MOSFETs based on Silicon.

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Journal articles on the topic 'MOSFET'

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