Dissertations / Theses on the topic 'MOSFET'
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Ngabonziza, Nyampame Christian. "Drivning av Likströmsmotor med MOSFET : DC Motor control by MOSFET." Thesis, Linnéuniversitetet, Institutionen för datavetenskap, fysik och matematik, DFM, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-11294.
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Detta projekt är ett examensarbete för kandidatexamen som är obligatorisk för alla studenter. För att ta ut examen måste jag lämna en skriftlig rapport om vad jag har gjort. Redovisa simuleringar och mätningar på olika kretsar. I mitt fall var jag intresserad på att studera hur varvtalet på en likströmsmotor kan regleras med hjälp av olika metoder. Detta är mycket utmanande för mig eftersom jag inte har sett så många lösningar på detta problem. Jag kommer att använda kunskap, teknik och komponenter från Kraftelektronik för att utföra mitt arbete. Det blir mycket intressant att med dagens utveckling av tekniken se hur olika metoder kan användas för att undersöka hur kraftelektronik kan användas i kontroll av varvtal, frekvens och rotationsriktning av elektriska maskiner.
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Lui, Jerome C. (Jerome Chun Lung). "Automated MOSFET parameter extraction." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36583.
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Major, Jan. "Počítačové modelování MOSFET tranzistoru." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219148.
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Work is focused on computer modeling of PN junction and MOSFET transistor in the program COMSOL Multiphysics and in program TiberCAD. The text is discussed on the drift and diffusion in semiconductors. Also shown is a method of modeling the PN junction and MOSFET transistor in the programs and compare models.
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Munteanu, Daniela. "Modélisation et caractérisation des transistors SOI : du pseudo-MOSFET au MOSFET submicronique ultramince." Grenoble INPG, 1999. http://www.theses.fr/1999INPG0104.
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L'objet de cette these est de contribuer a l'analyse et a l'optimisation des materiaux soi et au developpement de modeles physiques et de methodes de caracterisation adaptees aux dispositifs soi. Dans le premier chapitre, nous rappelons l'interet de la technologie soi, ses avantages et ses inconvenients par rapport a la technologie si massif. Le deuxieme chapitre est consacre a la caracterisation du materiau, en utilisant la technique -mosfet, methode tres appropriee pour comparer la qualite et les parametres electriques des differentes structures soi. Une analyse approfondie de la validite de cette technique est realisee par simulation numerique. La technique -mosfet est ensuite appliquee a l'analyse de plusieurs materiaux soi et de certains procedes technologiques. Le troisieme chapitre porte sur la caracterisation des dispositifs soi finis, avec une etude detaillee du fonctionnement en haute et basse temperature. Nous presentons une analyse de transistors soi ultimes : (a) le fonctionnement en basse temperature du dt-mos est etudie experimentalement et ses avantages par rapport aux structures classiques sont mis en evidence ; (b) des mesures sur des tmos ultra-minces demontrent leur fonctionnalite ainsi que l'impact de mecanismes physiques particuliers (inversion volumique, fort couplage des interfaces, effets quantiques). Le quatrieme chapitre est consacre a l'analyse et a la modelisation des mecanismes transitoires dans les tmos/soi. Differents types de transitoires du courant de drain (overshoot et undershoot, simple et double grille) sont mesures et simules avec atlas et soi-spice. Ces phenomenes sont utilises a l'extraction de la duree de vie des porteurs, parametre essentiel qui reflete la qualite du film soi.
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Shah, Nirav. "Stress modeling of nanoscale MOSFET." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0012221.
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Prokhorov, Andrey, and Olesya Gerzheva. "Model of MOSFET in Delphi." Thesis, Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-14209.
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In modern times the increasing complexity of transistors and their constant decreasingsize require more effective techniques to display and interpret the processes that are inside of devices. In this work, we are modeling a two‐dimensional n‐MOSFET with a long channeland uniformly doped substrate. We assume that this device is a large geometry device so that short‐channel and narrow‐width effects can be neglected. As a result of the thesis, a demonstration program was built. In this executable file, the user can choose parameters of the MOSFET‐model: drain and gate voltage, and different geometrical parameters of the device (junction depth and effective channel length). In the advanced regime of the program, the user can also specify the model re‐calculation parameter, doping concentration in n+ and bulk regions. The program shows the channel between the source and drain region with surface diagrams of carrier density and potential energy as an output. It is possible to save all calculated results to a file and process it in any other program, for example, plot graphics in Matlab or Matematica. The model can be used in lectures that are related to semiconductor physics in order to explain the basic working mechanisms of MOSFETs as well as for further detailed analysis of the processes in MOSFETs. It is possible to use our modeling techniques to rebuild the model in another computer language, or even to build other models of transistors, performing similar calculations and approximations. It is possible to download the executable file of the model here: http://studentdevelop.com/projects/MOSFET_model.zip
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Chen, Max Chuan. "Modeling of KTH UTBSOI MOSFET." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177444.
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Semiconductor devices such as transistors and integrated circuits are everywhere in our daily lives, it's one of the most important foundations of today's information society. Nanotechnology enables the production of lighter, faster and more efficient components and systems. Manufacturing technology has improved considerably over the past 40 years, but in recent years, the bulk transistors have reaching the limits of Moore’s law as the size shrinking too few tens of nanometers. The main difficulties are to reduce the power consumption, improve the speed meanwhile maintain the low manufacturing cost. This has given an opportunity for some emerging semiconductor technologies. One of the most promising approaches is implementation of new device architectures, such as FinFET and UTBSOI. This bachelor thesis covers the basics of compact modeling of UTBSOI MOSFET, by using the BSIMSOI compact model and SPICE software Cadence to model the KTH Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) transistor. The result of this paper shows the accuracy of BSIMSOI and can be used for future extraction work.Halvledarkomponenter såsom transistorer och integrerade kretsar finns överallt i vår vardag, det är en av de viktigaste grunderna för dagens informationssamhälle. Nanoteknik möjliggör produktion av lättare, snabbare och effektivare komponenter och system. Tillverkningstekniken har förbättrats avsevärt under de senaste 40 åren, men på de senaste åren har de bulktillverkade transistorerna nått gränserna för Moores lag, när storleken krymper till några tiotal nanometer. De största svårigheterna är att minska energiförbrukningen, förbättra hastigheten samt bevara den låga tillverkningskostnaden. Detta har gett möjlighet för att utvecklar ny halvledarteknik. En av de mest lovande metoderna är implementering av nya transitor arkitekturer, till exempel FinFET och UTBSOI. Detta examensarbete omfattar grunderna i modellering av SOIMOSFET, med hjälp av BSIMSOI och SPICE programvara Cadence kan man modellera KTH transistor. Resultatet av denna studie visar noggrannheten hos BSIMSOI och kan användas för framtida arbete inom ämnet.
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李華剛 and Eddie Herbert Li. "Narrow-channel effect in MOSFET." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1990. http://hub.hku.hk/bib/B31209312.
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Wang, Yao. "MOSFET strain sensor for microcantilevers." Thesis, Queen's University Belfast, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675436.
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Microcantilever structure was used to design and fabricate strain sensors. P-channel MOSFETs were designed and fabricated for strain sensors as hole mobility under uniaxial stress has higher mobility enhancement than that of electron mobility under either uniaxial stress or biaxial stress. For MOSFET sensors on microcantilevers, anchor area is the traditional position for sensors due to its highest stress. The aim of this research is to investigate the assumption of biaxial stress at the anchor area which makes the anchor location less sensitive. COMSOL software was employed to simulate stress profiles in silicon beams. Four-pointbending provides almost uniaxial stress at the surface, but cantilever bending generates biaxial stress at the anchor region but uniaxial stress away from anchor. The transverse stress at the anchor region increases with the bending and is depends on the longitudinal stress. In this research, the sensitivity of the sensor at the cantilever anchor was lower than that under uniaxial stress from four-point-bending measurement. It is suggested that the transverse stress at the anchor region will degrade the sensitivity compared to that under uniaxial stress. Although narrower cantilever provides higher longitudinal stress at the anchor, it brings higher transverse stress at the anchor as well. Possible solutions such as employing stressed layer, holes and slots were proposed to reduce the transverse stress without impact on the longitudinal stress, thus to increase the sensitivity. In comparison, employing slots is recommended as the transverse stress can be concentrated to nearly zero at the slot region with enhanced and elongated longitudinal stress.
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Araújo, Guido Costa Souza de 1962. "Simulação bidimensional de dispositivos MOSFET." [s.n.], 1990. http://repositorio.unicamp.br/jspui/handle/REPOSIP/261310.
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Orientador : Bernard WaldmanDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica
Made available in DSpace on 2018-07-13T21:47:06Z (GMT). No. of bitstreams: 1 Araujo_GuidoCostaSouzade_M.pdf: 7097802 bytes, checksum: 3989d5131b3e9436f6f55fc6d620a10e (MD5) Previous issue date: 1990
Resumo: Com a drástica diminuição das dimensões nas novas gerações de transistores MOS VLSI, um aumento considerável de efeitos dimensionais no comportamento destes dispositivos tem surgido. Isto traz como conseqüência imediata, a impossibilidade de utilização dos modelos clássicos analíticos no projeto e no estudo destes transistores. A proposta deste trabalho é a de desenvolver um simulador bidimensional para transistores MOSFET de canal curto, que permita uma caracterização precisa destes dispositivos em equilíbrio termodinâmico. Nesta situação, a influência de efeitos dimensionais sobre VT pode ser melhor estudada, possibilitando assim a obtenção de uma primeira aproximação para o projeto destes dispositivos
Mestrado
Mestre em Engenharia Elétrica
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Peters, Chris (Christopher Joseph) Carleton University Dissertation Engineering Electrical. "MOSFET based gamma radiation detector." Ottawa, 1992.
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Maréchal, Aurélien. "Metal-oxide-semiconductor capacitor for diamond transistor : simulation, fabrication and electrical analysis." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT094/document.
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Plus de deux décennies de progrès technologiques dans le contrôle de la qualité de la croissance, du dopage et dans la conception de composants ont conduit à l'émergence de nouvelles potentialités pour des applications d'électronique de puissance. Comme le diamant représente le semi-conducteur ultime en raison de ses propriétés physiques supérieures, des efforts ont été réalisés pour développer divers dispositifs électroniques, tels que des diodes Schottky, des transistors à effet de champ (MOSFET), transistor bipolaire, jonctions pin ...Le développement d'outils de simulation capables d'anticiper les propriétés électriques des dispositifs électroniques ainsi que leur architecture pour profiter pleinement des propriétés physiques du diamant est une condition préalable à la mise au point de nouveaux composants de puissance. D'autre part, l'étude expérimentale du contact de grille, la deuxième brique élémentaire du transistor, est fondamentale en vue de développer des dispositifs de haute performance. À cet égard, on peut considérer plusieurs questions ouvertes: (i) Les outils de simulation sont-ils capables de prendre en compte les spécificités du diamant pour modéliser les composants électroniques? (ii) L'oxyde d'aluminium est-il approprié pour développer un contact de grille de transistor? (iii) Si oui, l'interface oxyde/diamant est-elle d'assez bonne qualité? (iv) La fabrication d'un MOSFET en diamant est-elle un obstacle technologique?Ce projet de doctorat, vise à répondre à ces questions et à ouvrir la voie vers la réalisation du MOSFET à canal d'inversion.Les propriétés physiques du diamant seront soulignées et aideront à comprendre pourquoi ce matériau est le semi-conducteur ultime. L'état de l'art des dispositifs en diamant sera présenté en se concentrant sur des transistors à effet de champ. L'anticipation des propriétés électriques et de l'architecture grâce à des logiciels de simulation basés sur la méthode des éléments finis constitue un sujet complémentaire. Ainsi, le besoin d'outils de simulation fiables sera présenté.D'une part, les principaux modèles mis en œuvre dans les outils de simulation seront présentés en insistant sur les propriétés électriques du diamant. Pour la simulation du MOSFET diamant, l'étude de deux briques élémentaires est nécessaire: la jonction pn et le contact de grille. Les propriétés idéales de la grille seront présentées tandis que la jonction pn servira de base pour le calibrage des paramètres physiques mises en œuvre dans le logiciel de simulation. L'influence des modèles de génération-recombinaison sur les propriétés électriques simulée de jonction pn sera discutée. Enfin, la simulation des propriétés électriques d'un MOSFET en diamant sera présentée.D'autre part, l'accent sera mis sur la fabrication et la caractérisation électrique du condensateur diamant métal-oxyde-semi-conducteur (MOSCAP). Plus précisément, le raccordement des bandes à l'interface Al2O3/diamant à terminaison oxygène (O-diamant) a été étudiée en utilisant la méthode de spectroscopie photoélectronique à rayons X. Les résultats ont permis l'établissement du diagramme de bande de l'hétérostructure Al2O3/O-diamant et démontre que l'Al2O3 est utilisable en tant qu'oxyde de grille. Ensuite, l'étude de la densité des états d'interface a révélé l'ancrage du niveau de Fermi à l'interface entre l'Al2O3 et le diamant. En outre, les courants de fuite à travers la couche d'Al2O3 seront discutés en termes d'effet tunnel assisté par pièges de trous de la couche de diamant au contact de grille. Enfin, la caractérisation électrique du premier MOSFET en diamant, effectuée au National Institute for Advanced Industrial Science and Technology (AIST) au Japon, sera présentée. Cette première tentative s'est révélée infructueuse. Néanmoins, les résultats sont très prometteurs pour le développement de diamant MOSFET étant donné que la démonstration de la réalisation du composant est clairement établieOver two decades of technological progresses in growth quality, doping control and device processing have led to the emergence of new potentialities for power electronic applications. As diamond represents the ultimate semiconductor owing to its superior physical properties, efforts have been conducted to develop various electronic devices, such as Schottky diodes, field effect transistors, bipolar transistor, p-i-n junctions...As a prerequisite to the development of new generation diamond power devices, on one side, is the development of simulation tools able to anticipate the device electrical properties as well as its architecture in order to take full advantage of the material physical properties. On the other hand, experimental study of the gate contact, the second building block of the transistor, is fundamental in order to develop high performance devices. In this regard, one can consider several open questions: (i) Are the simulation tools able to take into account the specificities of diamond to model electrical devices? (ii) Is the aluminum oxide suitable to develop a MOSFET gate contact? (iii) If so, is the oxide/diamond interface of good enough quality? (iv) Is the fabrication of a diamond MOSFET a technological issue?This PhD project, attend to answer these questions and pave the way towards the inversion mode MOSFET.Emphasize on the diamond physical properties will help to understand why this material is the ultimate WBG semiconductor. State of the art diamond devices will be presented focusing on field effect transistors. A complementary topic for the development of new generation diamond power device is the anticipation of device electrical properties and architecture through finite element base simulation software. Thus the need for reliable simulation tools will be presented.On one hand, the main models implemented in the simulation tools will be presented and emphasize on the diamond electrical properties will be given. For the simulation of diamond metal-oxide-semiconductor field effect transistor (MOSFET), the study of two building blocks is required: the p-n junction and the gate contact. The later ideal properties will be presented while the former will serve as a basis for the calibration of the physical parameters implemented in the finite element based software. Generation-recombination models influence on the simulated p-n junction electrical properties will be discussed. Finally, the simulation of the electrical properties of a diamond metal-oxide-semiconductor field effect transistor (MOSFET) will be shown.On the other hand, focus will be made on diamond metal-oxide-semiconductor capacitor (MOSCAP) fabrication and electrical characterization. Specifically, the interfacial band configuration of the Al2O3/oxygen-terminated diamond (O-diamond) has been investigated using X-ray photoelectron spectroscopy. The results allowed establishing the band diagram of the Al2O3/O-diamond heterostructure. Then, the electrical properties of the diamond MOSCAP will be shown. Specifically, investigation of the interface states density revealed the pinning of the Fermi level at the interface between the Al2O3 and the O-diamond. Moreover, the leakage currents through the Al2O3 layer will be discussed in terms of temperature dependent trap assisted tunneling of holes from the diamond layer to the top gate contact. Finally, the electrical characterization of the first diamond MOSFET, performed at the National Institute for Advanced Industrial Science and Technology (AIST) in Japan, will be presented. Even if this first attempt was unsuccessful, it is promising for the development of diamond MOSFET since the demonstration of the actual realization of the device is clearly established
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NEDELJKOVIC, SONJA R. "PARAMETER EXTRACTION AND DEVICE PHYSICS PROJECTIONS ON LATERAL LOW VOLTAGE POWER MOSFET CONFIGURATIONS." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1005163403.
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Mohta, Nidhi. "MOSFET piezoresistance coefficients on (100) silicon." [Gainesville, Fla.] : University of Florida, 2006. http://purl.fcla.edu/fcla/etd/UFE0017761.
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Wang, Lihui. "Quantum Mechanical Effects on MOSFET Scaling." Diss., Available online, Georgia Institute of Technology, 2006, 2006. http://etd.gatech.edu/theses/available/etd-07072006-111805/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.Philip First, Committee Member ; Ian F. Akyildiz, Committee Member ; Russell Dupuis, Committee Member ; James D. Meindl, Committee Chair ; Willianm R. Callen, Committee Member.
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Lin, Xinnan. "Double gate MOSFET technology and applications /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LIN.
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Gajula, Durga Rao. "Optimization of germanium MOSFET fabrication processes." Thesis, Queen's University Belfast, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.602509.
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As silicon MOSFETs have reached their saturation limits due to aggressive scaling, high mobility channel materials like germanium are offering a future generation of semiconductor materials. Germanium's smaller band-gap broadens the optical absorption spectrum, and its low melting point considerably reduces the process temperature compared with silicon. However its unstable native oxide, large diffusion constant of n-type dopants, high series resistance of metal contacts on germanium, susceptibility to implantation damage, Fermi-level pinning of metal contacts on n-type source/drain regions, poor-quality interfaces between germanium and high-k dielectrics, etc. are compromising the performance of germanium MOSFETS. Implant-less nickel germanide source and drain p-channel MOSFETs were successfully fabricated at a low thermal budget. A effective hole mobility of -340 cm2/Vsec was measured on nickel germanide source/drain p-MOSFETs with Hf02/GeOxNy as gate dielectric. The Fermi level of aluminium contacts on germanium was successfully unpinned by using atomic layer deposited layers. A barrier height from ~O.7e V for Al contacts on n-Ge to a value of 0.28 e V was realized with insertion of a thin alumina interfacial layer (28.5 A)
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Rudnicki, Kamil. "MOSFET transistor fabrication on AFM tip." Thesis, University of Glasgow, 2014. http://theses.gla.ac.uk/5398/.
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The project is concerned with the development of methods for the fabrication of magnetic sensor devices on Atomic Force Microscopy (AFM) probes and their characterization. The devices use the principle of the Hall effect (based on the Lorentz force) to sense the magnetic properties of a magnetized specimen. In the past Hall bar sensors have been fabricated using semimetals such as Bismuth, or using 2-d electron gas material based on heterojunctions in III-V material. The former probes are limited by low sensitivity. The latter are limited by the difficulty encountered when trying to integrate the device with a force-sensing cantilever. The highest spatial resolution reported for a Hall bar operating at room temperature is 50 nm. Due to quantum effects (long mean free path), scaling down devices based on high mobility material results in a drop in sensitivity. For magnetic material studies of current interest higher resolutions are required. To achieve this goal in a material system which is compatible with micromachining the proposed approach utilises silicon as the sensing material. Silicon Hall bars have already been reported to work for large scale devices. This thesis presents the development of p-type enhancement mode MOSFET transistor fabrication process on a tip of Atomic Force Microscope (AFM) probe. The active device fabrication process was developed in order to allow fabrication of a magnetic sensor for Scanning Hall Probe Microscope (SHPM). The Hall bar was constructed on the apex of the AFM tip of attractive mode probes. The fabrication is performed in batches by using common semiconductor techniques leading to micromachining of the Si substrate, formation of the active device and cantilever release step. The transistor characteristics are presented, compared with expected performance of the modelled device and the reasons for differences are discussed. In this work, a method for application of spin-on-dopant on highly topographic structures is developed. Other encountered process incompatibilities are dealt with to finally present a full process for p-type enhancement mode MOSFET transistor on AFM tip fabrication.
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Iyengar, Pravin. "Pulsed MOSFET based linear transformer driver." Thesis, University of Strathclyde, 2014. http://oleg.lib.strath.ac.uk:80/R/?func=dbin-jump-full&object_id=24217.
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Pulsed power flash radiography is a rapidly growing technology which involves the generation of intense and short bursts of electric pulses to generate high energy X-rays to inspect dense objects. The generation of fast transition, short width, repetitive pulses for effective output requires switching technology which has limitations. From the traditional slow switching gas trigger switches, switching technology has evolved to semiconductors which has led to improved switching characteristics and delivered pulse shapes. One such semiconductor which is of interest in flash radiography is a power MOSFET. Due to superior switching speeds, repetition rates and modularity, MOSFETs are a strong contender in future pulsed power applications. This thesis focuses on the design of a MOSFET based pulsed power system capable of generating 2.2kV, 200A pulses with turn on and turn off times of less than 10ns and 20ns respectively. In order to achieve the target specification, a high speed current source MOSFET gate driver design specific to the application is proposed. Further, an inductive voltage adder system which utilises multiple lower voltage pulse sources driven by MOSFETs and outputs a higher voltage which is the summation of the total number of voltage sources, is designed to be compatible with the proposed gate driver scheme. A compact high power density pulsed power prototype is demonstrated which provides a benchmark for future research into the development of a larger scale system for flash radiography.
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Dybek, Marcin. "Ocena przydatności detektorów MOSFET w radioterapii." Doctoral thesis, Katowice : Uniwersytet Śląski, 2012. http://hdl.handle.net/20.500.12128/5372.
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Częstość występowania nowotworów w Europie gwałtownie rośnie w ostatnich
dziesięcioleciach. Szacowane jest 3,2 miliona nowych przypadków (53% występujących
u mężczyzn, 47% kobiet) oraz 1,7 miliona zgonów (56% mężczyzn, 44% kobiet) każdego
roku. Nowotwory generują poważny problem dla zdrowia publicznego Europy, a starzenie się
ludności spowoduje, że te wartości będą wzrastać, nawet jeżeli liczebność każdej grupy
wiekowej pozostanie stała. Radioterapia, poza chemioterapią i chirurgią, jest jednym ze
sposobów leczenia nowotworów w dużym zakresie ich typów i lokalizacji. Ma na celu
wyleczenie nowotworu, jednakże nieuniknionym skutkiem ubocznym jest uszkodzenie
zdrowych tkanek znajdujących się w obszarze napromienianym. Jest to niezamierzony efekt,
wywołany własnościami fizycznymi wiązki promieniowania jonizującego i niekorzystnym
rozkładem dawki w tkance. Skuteczna radioterapia nowotworów prowadzona jest więc na
drodze kompromisu pomiędzy dawką promieniowania zapewniającą największe
prawdopodobieństwo miejscowego wyleczenia nowotworu, a dawką powodującą najmniejsze
uszkodzenia zdrowych tkanek znajdujących się w obszarze napromienianym. Promieniowanie
jonizujące może być deponowane w obszarze zmiany nowotworowej w dwojaki sposób.
Poprzez stosowanie teleterapii, gdy źródło promieniowania znajduje się na zewnątrz
napromienianej zmiany nowotworowej, lub brachyterapii, w której źródło promieniowania
umieszcza się wewnątrz lub w sąsiedztwie zmiany nowotworowej. Czasami stosowane jest
połączenie tych dwóch technik.Niniejsze opracowanie przedstawia wyniki badań charakterystyk detektorów typu
MOSFET oraz możliwości ich zastosowania w dozymetrii promieniowania w radioterapii ze
szczególnym uwzględnieniem użycia ich w pomiarach in vivo stosowanych technik leczenia
w radioterapii, jak również wykorzystania w weryfikacji systemów planowania leczenia.
Wszystkie badania przedstawione w niniejszej rozprawie przeprowadzone zostały
w Zakładzie Radioterapii Szpitala im. Stanisława Leszczyńskiego w Katowicach.
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Chvátal, Miloš. "Transportní a šumové charakteristiky tranzistorů MOSFET." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-233635.
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This doctoral thesis is focused on the analysis of transport characteristics of submicron and micron transistors MOSFET. The assumption is a constant gradient of concentration, which leads to the fact that the diffusion current density is independent of the distance from the source. Active energy was determined from temperature dependence. The proposed physical model made it possible to determine the value of access resistance between drain and source their temperature dependence. Based on the assumption that the divergence of the gradient of the current density in the channel is zero. IV characteristics of the transistor MOSFET are derived and conducted experimental monitoring current channel depending on the collector voltage for the series of samples with different channel lengths in a wide temperature range from 10 to 350 K. Information on the concentration of charge transport in the channel and the position of the Fermi level at the point of active trap, which is the source of RTS noise, is obtained from the analysis of the transport characteristics. Determining the concentration of charge transport and the position of the Fermi level is important because these variables determine the intensity of quantum transitions and their values are not the same throughout the length of the channel. It was experimentally proved from the analysis of the characteristics of RTS noise that concentration at the local channel decreases with increasing current at a constant voltage on the gate and a variable voltage at the collector. Further, the position of active traps of RTS noise was intended and it was found that this is located near the collector. Active trap is located at the point where the Fermi level coincides with energy level of the traps.
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Clavijo, William. "Nanowire Zinc Oxide MOSFET Pressure Sensor." VCU Scholars Compass, 2014. http://scholarscompass.vcu.edu/etd/625.
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Fabrication and characterization of a new kind of pressure sensor using self-assembly Zinc Oxide (ZnO) nanowires on top of the gate of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Self-assembly ZnO nanowires were fabricated with a diameter of 80 nm and 800 nm height (80:8 aspect ratio) on top of the gate of the MOSFET. The sensor showed a 110% response in the drain current due to pressure, even with the expected piezoresistive response of the silicon device removed from the measurement. The pressure sensor was fabricated through low temperature bottom up ultrahigh aspect ratio ZnO nanowire growth using anodic alumina oxide (AAO) templates. The pressure sensor has two main components: MOSFET and ZnO nanowires. Silicon Dioxide growth, photolithography, dopant diffusion, and aluminum metallization were used to fabricate a basic MOSFET. In the other hand, a combination of aluminum anodization, alumina barrier layer removal, ZnO atomic layer deposition (ALD), and wet etching for nanowire release were optimized to fabricate the sensor on a silicon wafer. The ZnO nanowire fabrication sequence presented is at low temperature making it compatible with CMOS technology.
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Budihardjo, Irwan Kukuh. "A charge based power MOSFET model /." Thesis, Connect to this title online; UW restricted, 1995. http://hdl.handle.net/1773/5975.
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Fiala, Zbyněk. "Budiče spínacích výkonových tranzistorů GaN MOSFET." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242073.
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The thesis describes the procedure during the proposal of the driver circuits for the GaN MOSFET transistors, which are known for their fast switching especially. In the first instance of this thesis the issue of GaN MOSFET transistors is described and also the thesis describes the different types of MOSFET transistors in the way of their electrical and mechanical attributes. The specific type driver circuit is stated in the thesis, which was selected in the semestral thesis. For this circuit the boost converter with an output power 600W and high switching frequency 800kHz was proposed as an attempt measurement circuit. This boost converter was measured after its construction was done. The waveforms captured by the oscilloscope are commented also. In the conclusion the assessment is done about this new technology of power switching transistors.
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Constant, Aurore. "SiC oxidation processing technology for MOSFETs fabrication." Thesis, Montpellier 2, 2011. http://www.theses.fr/2011MON20061.
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De nos jours, les dispositifs d'électroniques de puissance sont principalement basés sur la technologie silicium qui est mature et très bien établie. Toutefois, le silicium présente quelques limitations importantes concernant les pertes de puissance, le fonctionnement à haute température et la vitesse de commutation. Par ailleurs, la technologie silicium a presque atteint ses limites physiques. Ainsi, une nouvelle génération de dispositifs de puissance à base de nouveaux matériaux doit être développée pour faire face aux futurs défis énergiques. Aujourd'hui, le matériau semi-conducteur le plus prometteur est le carbure de silicium (SiC). SiC est considéré de plus en plus comme le meilleur candidat pour surmonter les limites intrinsèques du silicium pour l'élaboration de dispositifs de haute puissance et haute température. Il montre le meilleur compromis entre les caractéristiques théoriques et les réelles disponibilités commerciales de la matière première et de la maturité de ses procédés technologiques.Cette thèse est axée sur les dispositifs d'alimentation à base de SiC, en particulier, sur l'un des enjeux majeurs de la technologie SiC: le procédé d'oxydation. En effet, le SiC peut être facilement oxydé comme le silicium pour former une fine couche de dioxyde de silicium (SiO2). Ceci fournit une occasion unique de développer des dispositifs Métal-Oxyde-Semiconducteur (MOS), comme en technologie silicium. Malheureusement, la qualité de l'interface oxyde/SiC et la fiabilité de l'oxyde sont des obstacles majeurs à la fabrication de dispositifs MOSFET avancés en SiC. Des solutions alternatives ont été développées pour surmonter ces problèmes. Toutefois, les MOSFETs en SiC ont seulement été récemment commercialisés, principalement en raison des problèmes de fiabilité. Le procédé de fabrication de MOSFETs adapté à la production de masse est encore un défi.Les principaux efforts réalisés dans le cadre de cette thèse concernent le développement des MOSFETs en SiC par l'amélioration du procédé d'oxydation pour la fabrication de l'oxyde de grille. Un nouveau procédé basé sur l'oxydation par Rapid Thermal Processing (RTP) est démontré. De plus, les mécanismes physiques associés à la formation de l'oxyde et des propriétés de l'interface SiO2/SiC sont proposés. Ce procédé d'oxydation a été testé sur le SiC hexagonal (4H-SiC) et le SiC cubique (3C-SiC). En outre, la technologie d'oxydation étudiée a été intégrée dans la fabrication de MOSFETs en 4H-SiC. La fiabilité des composants a été aussi évaluée pour des stress en tension jusqu'à des températures de fonctionnement de 300°CPower electronic devices are mainly based on the mature and very well established silicon technology. However, silicon exhibits some important limitations regarding power losses, operation temperature and speed of switching. Furthermore, unfortunately the successful silicon technology has almost reached its physical limits. Hence, a new generation of power devices based on new materials must be developed to face the future global energetic challenges. Nowadays, the most promising semiconductor material is silicon carbide (SiC). SiC is increasingly considered as the best candidate to overcome the intrinsic limitations of silicon in developing high-power and high-temperature electronic devices. It shows the best trade-off between theoretical characteristics and real commercial availability of the starting material and maturity of its technological processes.This thesis is focused on SiC-based power devices, particularly, on one of the major issues in SiC technology: the gate oxidation process. Indeed, SiC can be easily oxidized to form a thin silicon dioxide (SiO2) layer. This provides a unique opportunity to develop power Metal Oxide Semiconductor (MOS) devices, as in the Si-based technology. SiC-based power MOSFETs are expected to have great potential for high-speed and low-loss switching devices. Unfortunately, the oxide/SiC interface quality and oxide reliability are major barriers to the fabrication of advanced SiC power MOSFET devices. Alternative solutions have been developed to overcome these problems. However, SiC MOSFETs have only been recently commercially available, mainly due to reliability concerns. The MOSFET process suitable for mass production is still a challenge. The main efforts carried out in the framework of this thesis are addressed towards the development of SiC MOSFETs by improving the current gate oxide process state-of-the-art. A newly gate oxidation process based on rapid thermal processing is demonstrated, and the physical mechanisms associated with oxide formation and the SiO2/SiC interface properties are proposed. This oxidation process has been tested on hexagonal SiC (4H-SiC) and cubic SiC (3C-SiC). Furthermore, the investigated oxidation processing technology is integrated into the fabrication of reliable 4H-SiC MOSFETs, and the bias-stress instability has been evaluated up to operating temperatures of 300 ºC
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Guérin, Chloé. "Etude de la dégradation par porteurs chauds des technologies CMOS avancées en fonctionnement statique et dynamique." Aix-Marseille 1, 2008. http://www.theses.fr/2008AIX11041.
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La miniaturisation des dernières technologies s’est effectuée à tension d’alimentation quasi constante. Cela se traduit par une augmentation du champ latéral du transistor MOSFET. Un risque important réapparaît en terme de fiabilité : la dégradation par porteurs chauds (HC). Pour garantir le meilleur compromis entre fiabilité et performance, il est important de comprendre toutes les causes physiques de la dégradation par porteurs chauds. Grâce à une étude menée pour des conditions de polarisation et de température variées, sur différentes épaisseurs d’oxyde et longueurs de canal, nous avons mis en place un formalisme physique s’appuyant à la fois sur l’énergie et le nombre de porteurs. Cette double dépendance se traduit par une compétition entre trois modes de dégradations, dominant chacun à leur tour en fonction de la gamme d’énergie des porteurs. A forte énergie, la dégradation s’explique par l’interaction d’un seul porteur avec une liaison Si-H (mode 1). Mais quand l’énergie des porteurs diminue, leur nombre est prépondérant tout d’abord pour l’interaction entre porteurs EES (mode 2) et surtout à très basse énergie, où nous avons montré que la dégradation peut être importante à cause d’interactions multiples entre les « porteurs froids » du canal et les liaisons d’interface (mode 3). On parle alors d’excitation multivibrationnelle des liaisons. Ce nouveau modèle assure une meilleure extrapolation de la durée de vie dans les conditions nominales. Appliqué à la dégradation sous signaux digitaux, il permet une estimation rigoureuse du rapport entre les dégradations en courant alternatif et continu (AC-DC) ainsi que l’élaboration de nouvelles consignes concernant les effets de fréquence, de charge et de temps de montée des signaux. Enfin, intégré au simulateur de Design-in Reliability, il autorise une simulation précise de la dégradation par porteurs chauds de blocs de circuitsIn the last technologies, dimension reduction is performed at constant bias which means an increase of the MOSFET lateral electrical field. Reliability risks in term of hot carriers are coming back. It is very important to understand the hot carrier degradation physical root causes to insure the best compromise between performance and reliability. After studying numerous stress biases, temperatures, oxide thicknesses and lengths, we established a new physical formalism based on both carrier energy and number. This double effect translates in a three degradation mode competition dominated by each of the modes depending on the energy range. At high energy, the degradation is due to a single carrier interaction with Si-H bonds (mode 1). But when the energy decreases, carrier number begins to dominate first trough Electron-Electron interactions (mode 2) and particularly at very low energy where we put forward that degradation increases due to bond multiple vibrational excitation with cold carriers (mode 3). This new modelling allows a better lifetime extrapolation at nominal biases. Applied to degradation under digital signals, it also enables a rigorous estimation of the degradation ratio between alternative and continuous current (AC-DC). Then new design guidelines concerning frequency, fanOut and rise time have been evidenced. Finally, this new modelling is now included in Design-in Reliability simulators to know precisely circuit bloc hot carrier degradation
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Bouguet, Christophe. "Développement d’un Driver Communicant pour MOSFET SiC." Thesis, Nantes, 2017. http://www.theses.fr/2017NANT4034/document.
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Les semi-conducteurs présents dans les convertisseurs de puissance sont associés à un circuit de commande rapprochée appelé « driver ». Ce circuit sert d’interface entre l’électronique de contrôle-commande et les modules de puissance qu’il pilote. Dans le cadre des travaux de thèse, un driver dédié aux transistors MOSFET SiC a été développé. Il est conçu pour des modules dont le calibre en courant est de 300A et travaillant sous une tension de bus continu de 1200V. Au-delà de la conception d’un driver spécifique aux transistors MOSFET SiC, un second aspect des travaux de thèse a consisté à implémenter des fonctions de communication dans les convertisseurs. Les drivers sont alors des éléments incontournables du réseau de communication ainsi formé. Un canal de communication compatible avec les exigences normatives relatives aux drivers et avec les contraintes de l’environnement de travail de l’électronique de puissance a été conçu. Il se positionne entre le primaire du driver et chacune de ses voies de commande , permettant ainsi au réseau de communication du convertisseur de s’étendre jusqu’à la zone où le potentiel du bus DC de 1200V est présent. L’isolation galvanique indispensable à la sécurité des utilisateurs est conservée et la capacité parasite induite par l’ajout de cette fonctionnalité reste inférieure à 2pF. Les applications rendues possibles par ce canal de communication sont discutées. Des essais expérimentaux réalisés sous fortes contraintes électriques (2kV / 125kV/μs) valident le fonctionnement du prototype de canal de communication développé. Des transmissions de données à une vitesse de 500kbits/s se basant sur le protocole CAN ont été réalisées avec succèsThe semiconductors used in power converters such as IGBT and MOSFET transistors are driven by an electronic circuit called “gate driver”. This circuit is an interface between the control command circuit and the power semiconductors. In the work done during this PhD, a driver dedicated to SiC MOSFET transistors has been developed. It is designed for components with a continuous drain current value of 300A and working under a drain- source voltage of 1200V. Beyond the development of a driver dedicated to SiC M OSFET transistors technology, a second aspect of the work presented in this PhD is about the implementation of communication functions within the power converters. Drivers are then essential elements of the communication network then constituted. A communi cation channel that suits the standards requirements relating to drivers and suits the requirements concerning the power electronics working environment has been designed. It is located between the primary side of the driver and each of its channels. Thus, the communication network in the power converter reaches the area where the DC bus voltage of 1200V is situated. The galvanic isolation necessary to the user’s safety is kept and the parasitic capacitance induced by the addition of this communication func tion remains lower than 2pF. The possible uses offered by this communication channel are discussed. Some trials done under high electric constraints (2kV / 125kV/μs) validate the functioning of the prototype of the communication channel that has been devel oped. Data transmissions reaching a speed of 500kbits/s and based on CAN protocol have been carried out
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Linewih, Handoko, and h. linewih@griffith edu au. "Design and Application of SiC Power MOSFET." Griffith University. School of Microelectronic Engineering, 2003. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20030506.013152.
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This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.
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Jackson, Keith M. (Keith Matthew). "Optimal MOSFET design for low temperature operation." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8565.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references.
The phenomenal scaling of MOSFET feature size, two orders of magnitude in the past 30 years, has provided the gains in performance and packing density that underlie the GHz microprocessors and 256 MB DRAMs that exist today. Looking forward, the connection between increased performance and smaller devices faces significant challenges. Lowering the operating temperature can help achieve the desired increases in performance as device size scales. Lowering the temperature reduces the off-state leakage of a MOSFET removing constraints on reducing the threshold voltage. In addition, lower temperatures increase the current drive via increased carrier mobility and saturation velocity. Equally as important, the parasitic resistances of the device and of the interconnect decrease as temperature decreases. The approach of this thesis is to use comparisons of optimal designs across channel lengths and across temperatures to accurately assess the performance increases and increased design flexibility that come with lowering the device operating temperature. Using analytical equations, the tradeoff between fully scaled performance and maintaining reasonable off-current levels is clearly shown. As an alternative to allowing off-currents to rise, two possible temperature scaling scenarios, that either meet or exceed fully scaled performance, are explored. Focusing on a nominal channel length of 90 nm (worst-case of 75 nm) operating at 200 K, a detailed analysis of channel doping profile design to achieve the highest on current at the nominal channel length, while meeting the off-current limit for the worst case channel length is performed. Using an inverse modeling approach, a 2-D numerical simulator is first calibrated at various temperatures to measured device data down to 80 nm channel lengths. Coupling the simulator with an optimizer, a range of different halo, retrograde, and uniform doping profiles are examined. Halo doping is found to give the best device performance due to its lower threshold voltage, lower threshold voltage decrease with channel length, and lower body effect. The halo profiles become more abrupt for lower temperature designs. Comparing optimal designs for a 90 nm nominal device across temperature, on-current gains, and thus switching speed gains, of 3.5% for every 10 °C decrease in temperature can be achieved.
by Keith M. Jackson.
Ph.D.
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Al, Kzair Christian. "SiC MOSFET function in DC-DC converter." Thesis, Uppsala universitet, Elektricitetslära, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-415147.
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This thesis evaluate the state of art ROHM SCT3080KR silicon carbide mosfet in a synchronous buck converter. The converter was using the ROHM P02SCT3040KR-EVK-001 evaluation board for driving the mosfets in a half bridge configuration. Evaluation of efficiency, waveforms, temperature and a theoretical comparison between a silicon mosfet (STW12N120K5) is done. For the efficiency test the converter operate at 200 V input voltage and 100 V output voltage at output currents of 7 A to 12 A, this operation was tested at switching frequencies of 50 kHz, 80 kHz and 100 kHz. The result of the efficiency test showed an efficiency of 98-97 % for 50 kHz, 97.7-96.4 % for 80 kHz and 97-96.2 % for the 100 kHz test. The temperature test shows a small difference in comparison of the best case scenario and the worst case scenario, temperature ranges from 25.5 to 33.5 °C for the high side mosfet while the low side mosfet temperature ranges from 29.8 to 35 °C. The waveform test was conducted at 50 kHz and 100 kHz for output currents of 4 A and 12 A (at 200 V input and 100 V output). The result of the waveform test shows a rise and fall time of the voltages in range of 10-12 ns while the current rise and fall time was 16 ns for the 4 A test and 20 ns for the 12 A test. Overall SiC mosfet show a clear advantage over silicon mosfet in terms of efficiency and high power capabilities.
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SUNDARAM, KARTHIK. "A DYNAMIC MOSFET MODEL IN VHDL-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1154637877.
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Tuladhar, Looja R. "Resonant Power MOSFET Driver for LED Lighting." Youngstown State University / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ysu1264709029.
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Tuladhar, Looja R. "Resonant power MOSFET drivers for LED lighting /." Connect to resource online, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ysu1264709029.
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Linewih, Handoko. "Design and Application of SiC Power MOSFET." Thesis, Griffith University, 2003. http://hdl.handle.net/10072/367638.
Full textAbstract:
This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Microelectronic Engineering
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Matiaško, Maroš. "Experimentální spínaný zdroj s tranzistory GaN MOSFET." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242061.
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This master’s thesis deals with the design of the switching power supply on the principle of high frequency converter. The goal of this thesis is construction of converter which is using GaN MOSFET transistors and SiC diodes for switching. The converter uses two switch forward power supply topology. Unusually high switching frequency was chosen for the design with power transformer with open magnetic core. The outcome of this work is functional converter which is primarily intended for educational and demonstrational purposes. Multiple parts of this converter are divided into individual blocks, which can be further used for construction of other types of switching converters.
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Guerfi, Youssouf. "Réalisation et caractérisation de transistors MOS à base de nanofils verticaux en silicium." Thesis, Toulouse 3, 2015. http://www.theses.fr/2015TOU30253/document.
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Afin de poursuivre la réduction d'échelle des transistors MOS, l'industrie des semiconducteurs a su anticiper les limitations de la miniaturisation par l'introduction de nouveaux matériaux ou de nouvelles architectures. L'avènement des structures à triples grilles (FinFET) a permis de maitriser les effets canaux courts et poursuivre les efforts de miniaturisation (nœud technologique 14 nm en 2014). Le cas ultime pour le contrôle électrostatique de la grille sur le canal est donné par une grille entourant totalement le canal du dispositif. A cet effet, un transistor à nanofil à grille entourante est considéré comme la structure la plus adaptée pour les nœuds technologiques en dessous de 7 nm. Au cours de cette thèse, un procédé de réalisation large échelle de transistors MOSFET miniaturisés à base de nanofils verticaux en silicium a été développé. Tout d'abord, les nanofils verticaux ont été réalisés par une approche descendante via le transfert par gravure d'un masque de résine en Hydrogène Silsesquioxane (HSQ), réalisé par lithographie électronique à basse tension d'accélération. Une stratégie de dessin inédite dite "en étoile " a été développée pour définir des nanofils parfaitement circulaires. Les nanofils en Si sont obtenus par gravure plasma puis amincis par oxydation humide sacrificielle. Ce procédé permet d'obtenir des nanofils verticaux en Si avec des parois parfaitement anisotropes, une parfaite reproductibilité et un rendement maximal. L'implémentation des MOSFETs sur les réseaux nanofils a été effectuée par l'ingénierie successive de couches minces nanométriques (conductrices et diélectriques). Dans ce cadre, un procédé innovant de réalisation de couches d'isolations en HSQ par gravure chimique contrôlée a démontré une excellente planéité associée à une rugosité de surface inférieure à 2 nm. Enfin, un procédé utilisant la photolithographie UV conventionnelle a été développé pour réaliser le transistor de longueur de grille nanométrique. Ces dispositifs ont démontré d'excellentes performances électriques avec des courants de conduction supérieurs à 600 µA/µm et une excellente maîtrise des effets de canaux courts (pente sous le seuil de 95 mV/dec et DIBL à 25 mV/V) malgré l'extrême miniaturisation de la longueur de grille (15 nm). Enfin, nous présentons une première preuve de concept d'un inverseur CMOS à base de cette technologie à nanofils verticauxIn order to further downscaling of the MOS transistors, the semiconductor industry has anticipated the limitations of miniaturization by the introduction of new materials and new architectures. The advent of triple gate structures (FinFET) allowed mastering the short channel effects and further miniaturization efforts (14 nm technology node in 2014). The ultimate case to the electrostatic control of the gate on the channel is given by a gate completely surrounding the device channel. For this purpose, Gate All Around (GAA) nanowire transistor is considered as the most suitable structure for technology nodes below 7 nm. In this thesis, a large scale process for the realization of miniaturized MOSFETs based on vertical silicon nanowires has been developed. Firstly, the vertical nanowires were made by a top down approach by the transfer by etching of hard mask made of Hydrogen silsesquioxane (HSQ) resist created at low voltage electron beam lithography. An original design strategy called "star" was developed to define perfectly circular nanowires. Si nanowires are obtained by plasma etching then thinned by sacrificial wet oxidation. This method allows obtaining vertical Si nanowires with perfectly anisotropic walls, a perfect reproducibility and a maximum yield. The implementation of the MOSFETs on the nanowire network was done by successive engineering of nanoscale thin films (conductive and dielectric). In this context, an innovative process for producing insulation layers in HSQ by controlled chemical etching showed excellent flatness associated with surface roughness of less than 2 nm. Finally, a method using conventional UV photolithography has been developed to achieve the nanometer gate length transistor. These devices have demonstrated excellent electrical performances with conduction currents superior than 600 µA/µm and excellent control of short channel effects (subthreshold slope of 95 mV/dec and DIBL of 25 mV/V) despite extreme miniaturization of the gate length (15 nm). Finally, we present a first proof of concept of a CMOS inverter based on vertical nanowires technology
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Ljunggren, Tobias. "Investigation of PWM-controlled MOSFET with inductive load." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1271.
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This report is the basis for a Bachelor of Science thesis in engineering done at Volvo Powertrain in Gothenburg. The problem consisted of investigating a circuit with a PWM-controlled MOSFET driving a DC-motor.
The problem was to investigate what caused the circuit to break the transistor. Finally an improvement of the circuit is designed making the MOSFET withstand the stressful conditions exposed to.
An overall description of the problems with switching an inductive load using a MOSFET as switch is done. Some methods to protect the MOSFET from failure are also discussed. Finally a discussion is held to suggest what broke the MOSFET, and an improved design is proposed.
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Escobedo-Cousin, Enrique. "Material characterisation of strained Si/SiGe MOSFET devices." Thesis, University of Newcastle upon Tyne, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.485864.
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In this study, material investigations of strained Si/SiGe platforms for MOSFET applications are presented. The device performance advantages of introducing strain in the MOSFET channel have become well established in recent years. Biaxial strain changes carrier mobility by altering the band structure of the channel, leading to a reduction in carrier effective mass and the time between scattering events. Electron mobility benefits from the tensile strain achieved by the epitaxial growth of Si on a strain-relaxed SiGe buffer (SRB). Since holes, in contrast, benefit from compressive strein, dual-channel architectures comprising a compressively strained SiGe layer beneath a tensely strained Si surface channel have been proposed for CMOS applications. However, dual-channel nMOSFETs consistently exhibit lower performance than those fabricated on single channel structures having the same channel strain. This difference has been attributed to additional midscale surface corrugations induced by the buried SiGe. This additional roughness had not been characterised separately from the large-scale crosshatch morphology commonly observed in SiGe SRBs. In this work, a surface roughness analysis technique has been developed to study the separate contribution from surface roughne~s components at different scales. It is shown that the addition,a. l midscale roughness induced by the buried compressive SiGe channel is fundamentally governed by the degree of compressive strain. Results correlate well with electrical data from devices fabricated on dual-channel structures. The use of supercritical strained Si channels is an alternative to improve hole mobility without incurring in additional midscale surface roughness introduced by compressive strain in the dual channel. Biaxially strained channels are commonly formed by growing Si on a strain-relaxed SiGe buffer (SRB). However, the device self-heating due to the low thermal conductivity of SiGe remains an obstacle to realising the full advantages of strained Si technology. Self-heating effects are further aggravated by the fact that SiGe buffers are typically several microns thick. Novel epitaxy techniques have enabled the production of ultrathin SRB in order to lessen the impact of selfheating. In this work, the material quality and stability of thin SRBs produced by two different growth techniques are investigated in terms of surface morphology and crystal defects. Both sub- and supercritical thickness layers are studied. Supercritical thickness layers have the potential to eliminate several challenges associated with processing SiGe, if material quality can be maintained. Also, improved hole mobility could be achieved in supercritical highly~strainedSi layers. The thermal stability of the thin SRB grown by a carbon-induced-relaxation technique is analysed by annealing the material at temperatures commonly used during device processing. Although strain measurements by Raman spectroscopy suggest good thermal resilience of this thin SRB, chemical defect etching demonstrates the evolution of dislocations, suggesting a weak thermal resilience. Supercritical strained Si layers growp on these thin SRBs exhibited prominent surface defects, most likely resulting·from additional strain-relief mechanisms in the thin SRB in addition to stacking faults. Defect etching techniques were developed in order to distinguish defect types from individual layers throughout the epitaxial layer stack. MOSFETs were also fabricated on thin SiGe buffers produced by a lowtemperature growth method and performance was compared with co-processed devices on a conventional thick SRB. The thin SRB devices exhibited reduced selfheating levels in comparison with conventional thick SRB devices. The lowtemperature growth technique leads to reduced surface roughness, which appears to improve key 'electrical parameters in addition to mobility, including gate leakage, reliability, noise and interface trap density. The impact of growth temperature on surface roughness and performance is also analysed.
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Zhang, Yucai. "Multiharmonic tuning behavior of MOSFET RF power amplifiers." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ63040.pdf.
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Murray, D. C. "MOSFET flicker noise : its characterisation and its origins." Thesis, University of Southampton, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315505.
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Huang, Yan-Hua, and 黃彥皓. "Radio frequency MOSFET." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/47630350584396371167.
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碩士國立交通大學
電子工程系
87
Small signal S parameters of a quarter micron Si MOSFET in common source configuration are measured from 100MHz to 18 GHz in different biasing conditions. From the S parameters we found the evidence of the non-quasi-static (NQS) effects, namely the low-pass nature of the transconductance, and the nonzero real part of the impedance looking into the gate. Also the output impedance is lowered by the finite conductance of the substrate. In order to fit the S parameters, we chose BSIM3v3, which is successful in describing the small geometry effects, as the basic model. DC characteristics of Si MOSFET of various channel lengths and widths were measured, and BSIM3v3 model parameters were carefully extracted. A gate resistor originating from the NQS effect showing up at the frequency range of interest, and a network accounting for the substrate resistance are added. The measured S parameters are used as the guideline in determining the added components. Good fitting was obtained. The variation of the gate resistance with bias was investigated, and was in agreement with the theory.
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Lo, Hung-Ming, and 駱宏明. "n-MOSFET Performance Evaluation." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/96059871089398717314.
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碩士國立高雄應用科技大學
電子與資訊工程研究所碩士班
92
Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been widely used in ULSI semiconductor technology. The major advantages of MOSFET are high yield, low cost, dense packing, and low power consumption. The carrier mobility in the inversion charge layer of MOSFET has become increasingly important as device scale down to deep submicron due to its deterministic property in drain current. Therefore, the inversion-layer mobility is a vital important parameter to understand the mechanisms of charge transport in the surface inversion layer. In this thesis, we measure the current-voltage (I-V) characteristics of n-MOSFET with the gate lengths of 10μm and 4μm. A simple model is used to extract the effective carrier mobility (μeff) with respect to the gate voltage (VG). Our results show that the change of the mobility is strongly dependent on the gate bias, and its trend agrees well in comparison to other theoretical and experimental works. In the region of small VG, the mobility is mainly determined by impurity scattering, but the increase of surface roughness scattering in high field region instead of the role of impurity becomes a deterministic factor in mobility degradation. The fitting model proposed in the thesis enables reliable values in the changes of mobility, effective oxide capacitance, doping concentration, and threshold voltage with respect to the gate bias.
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Lin, Sheng-Zhi, and 林聖智. "p-MOSFET Performance Evaluation." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/00293290458545871034.
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碩士國立高雄應用科技大學
電子與資訊工程研究所碩士班
92
In this paper , we measure the I-V characteristics of the p-MOSFETs with the gate lengths of 4μm and 10μm, and apply a simple model to extract the change of mobility with respect to the gate voltage. Our results show that the changes of the mobility for both p-MOSFETs are strongly dependent on the gate bias due to the interplay of interface roughness scattering, ionized impurity scattering, and the change of density-of-state. The strength of the impurity scattering is reduced by increasing VG due to the decrease of density of state, and the screening effect in increasing the carrier density, which results to the increase of mobility. However, the increasing VG enhances the interface roughness scattering, and results to the mobility degradation. Moreover, an anomaly around VG ~ 1.1V is observed in the plot of the mobility with respect to the gate bias. It is mainly attributed to the change of the oxide charge as the gate bias crossover 1.1V.
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Yeh, Ting-Hsien, and 葉婷銜. "Double-gate MOSFET Simulator." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/23537537074173278742.
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碩士國立交通大學
電子研究所
101
It is well known that the scaling of the traditional bulk MOSFETs would encounter several issues like the short channel effects (SCE). To deal with this problem, many of methods have been proposed, one of which is new device architectures, such as multi-gate structures. The aim of this work is to develop a double-gate n-MOSFET simulator by using self-consistent solving of Schrödinger and Poisson equations with some physical models taken into account. Besides, for many simulators in the literature, the boundary conditions of Schrödinger’s equation are often making an infinite potential barrier height at the silicon/gate-oxide interface. Nevertheless, we know that the actual barrier height is finite and is equal to a few electron-volts. Therefore, wave-function actually can penetrate into the gate-oxide dielectric. Hence, we also add wave-function penetration effect to our simulator, and discuss the influences of penetration effect and electron tunneling effective mass on the double-gate structure performance. Finally, we also build mobility and stress related model, and compare those with literature values. From the comparison results, our simulations are consistent with Schred as well as with some articles with and without wave-function penetration included, except for the mobility of thinner substrate thickness which should consider more scattering mechanisms. That is to say, our simulator comes to be reasonable for calculating fundamental properties in DG n-MOSFETs.
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Tsai, Ming-Tsang, and 蔡明蒼. "High Voltage Contact Gate MOSFET (CG-MOSFET) with Fully CMOS Logic Compatible Process." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/62642110513392707942.
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碩士國立清華大學
電子工程研究所
99
In recent years, the improvement of power electronics and power devices is one of keys when the energy issues become more important. The cost down and the tradeoff between breakdown voltage and on-resistance have always been major concerns in designing power devices. Many studies have proposed their structure only needs few masks. However, it is still special process which needs wire bonding to connect the power device and main circuit. It is a limit for cost down. In this thesis, a novel 20V-class device with CMOS logic compatible process is proposed which called Contact Gate MOSFET (CGMOS). Since the device does not need the mask of drift region and wire bonding, it could be cost down substantially. By T-CAD simulation and measurement, the newly designed device has breakdown voltage up to 18 volt and 8.8mΩ∙mm2 specific on-resistance. From statistical distribution, the stability of device is up to 87%. And no characteristic variation can be observed after long term temperature stress at 125˚C for 1000 hours.
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Yen, Wei-Ting, and 顏瑋廷. "A Self-Aligned Nanowire MOSFET." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/h7jr5d.
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碩士國立中央大學
電機工程研究所
94
In this thesis, the formation of NiSi silicide using rapid thermal annealing is investigated. The NiSi salicidation process is, then, incorporated into the fabrication of novel self-aligned nanowire MOSFET devices structure. A self-aligned nanowire MOSFET fabricated on a 70-nm-thick SOI wafer, features advanced process modules including recessed nitride spacer, fully silicided (NiSi) source/drain, and self-aligned poly silicon gate. In the pursuit of low series resistance in a thin SOI, it is critical to optimize spacer width and utilize fully-silicide S/D. Since LOCOS process is integrated in a nanowire MOSFET process flow, one doesn’t require e-beam lithography to do precise alignment for ultra narrow gate stacked structure. A self-aligned poly gate technology is utilized to improve manufacturing yield efficiently. A recessed spacer structure is carried out using hot phosphoric acid etching, which is highly selective between Si3N4 and Si. Edge effects of Ni polycide formation are enhanced by such recessed spacer and result in Rs reduction further. Finally, the device performance is evaluated.
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"Simulação bidimensional de dispositivos MOSFET." Tese, Biblioteca Digital da Unicamp, 1990. http://libdigi.unicamp.br/document/?code=vtls000026459.
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Chen, Hsun-Hsiang, and 陳勛祥. "MOSFET characteristics at low temperature." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/21445052136293516335.
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Sung, Tung-Hao, and 宋東壕. "Backscattering-Oriented MOSFET Mismatch Experiment." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/12720514739231663603.
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碩士國立交通大學
電子工程系所
96
In this thesis, we have derived several mathematical models to express the mismatch properties of MOS transistors based on the backscattering theory. We have extracted the KBT layer’s width from the experimental analysis and we have found a simple model to express its mismatch properties based on the parabolic potential barrier. The mean-free-path and the backscattering coefficient have also been discussed in this thesis. For the purpose of the accuracy, the source/drain series resistance has been incorporated in to our parameters extraction. Straightforwardly, we have developed a drain current mismatch model based on backscattering theory in the saturation region.
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"The extraction of MOSFET parameters." Chinese University of Hong Kong, 1988. http://library.cuhk.edu.hk/record=b5886228.
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