Relevant bibliographies by topics / MOSFET

Academic literature on the topic 'MOSFET'

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Published: 4 June 2021
Last updated: 8 June 2024

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Journal articles on the topic "MOSFET"

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Gonçalves Filho, Luiz C., and Luiz A. P. Santos. "An electronic dosimeter for diagnostic X-ray beams based on a differential amplifier circuit with MOSFETs." EPJ Web of Conferences 288 (2023): 09001. http://dx.doi.org/10.1051/epjconf/202328809001.

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It is known that the device MOSFET works as a dosimeter in radiation beams for cancer radiotherapy. Basically, the radiation beam generates defects in a way that produces in the MOSFET the variation in its threshold voltage, VT, which is proportional to the accumulated radiation dose. Recently, MOSFETs were also tested under X-ray beams commonly used in the energy range applied to medical diagnoses, which is lower energy than radiotherapy. Indeed, it was already shown that the MOSFET drain current varies with the radiation dose for energies in the range applied to diagnostic radiology. In this paper, an innovative method based on a differential amplifier circuit with two electronically matched MOSFETs is presented. Therefore, before irradiation the differential output voltage signal, Vdif = 0. Actually, it is a differential amplifier circuit with one of the MOSFETs shielded from the ionizing radiation beam. Therefore, if such a circuit is irradiated the difference between ID1 and ID2, from MOSFET1 and MOSFET2 respectively, will result Vdif ≠ 0. To evaluate the response of this electronic dosimeter it was tested under a diagnostic radiology beam typically used in clinics to take radiography of patients. The results showed that the proposed dosimeter works and varies linearly with the radiation dose. The technology developed in this paper will allow research to be carried out for optimizing such electronic dosimeter to make it a wearable device and can be able to use it by workers exposed to ionizing radiation in nuclear power plants or even in outer space.
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Li, Ruizhe. "The advantages and short circuit characteristics of SiC MOSFETs." Applied and Computational Engineering 49, no. 1 (March 22, 2024): 58–64. http://dx.doi.org/10.54254/2755-2721/49/20241059.

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SiC MOSFETs have exhibited considerable benefits in high-frequency, high-voltage, and high-temperature power electronics applications with outstanding material attributes as a result of the rapid advancement of power electronics technology. SiC MOSFETs slower short-circuit tolerance and faster switching rates provide new issues for the short-circuit prevention technology. In the opening section of the study, Si and SiC MOSFETs are compared and evaluated using various models and parametric factors. It has been demonstrated that SiC MOSFETs outperform Si MOSFETs in a variety of conditions and applications. The many SiC MOSFET short-circuit failure types as well as their underlying theories are initially explained in the papers main body. In addition, it examines the fundamentals of short-circuit test procedures and SiC MOSFET test circuits. The issues and limitations of the currently available SiC MOSFET short-circuit protection technology are then explored, along with factors impacting the short-circuit of SiC MOSFETs that are thoroughly examined. Lastly, the SiC MOSFET short-circuit protection technology development trend is forecasted, and potential future areas for improvement and innovation are considered. SiC MOSFET short-circuit protection technology will be enhanced and optimized to satisfy the needs of efficient and dependable power electronic systems as technology advances and application requirements expand.
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Kaur Sidhu, Rajdevinder, Jagpal Singh Ubhi, Alpana Agarwal, and Balwinder Raj. "Design and Comparative Analysis of Silicon and GaAs MOSFET for Low Power Applications." Journal of Nanoelectronics and Optoelectronics 18, no. 8 (August 1, 2023): 915–23. http://dx.doi.org/10.1166/jno.2023.3460.

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The demand for low power consumption in modern electronic devices has led to the development of various technologies, including usage of different materials such as Si and GaAs. In this paper, we present a design and comparative analysis of Si and GaAs MOSFETs for low power applications. The analysis includes the electrical characteristics, performance parameters, and power consumption of both devices. The Si MOSFET and GaAs MOSFET are simulated and analyzed using TCAD tools, and the results are compared. The simulation results show that the GaAs MOSFET has a higher transconductance (gm) compared to the Si MOSFET. However, the Si MOSFET has a lower gate leakage current (Ig) and lower power consumption at low operating frequencies. We also investigate the effect of scaling on the performance and power consumption of both MOSFETs. The results show that scaling improves the performance of both devices, but the power consumption increases as the device dimensions are reduced. The comparative analysis of Si and GaAs MOSFETs for low power applications provides useful insights into the selection of suitable MOSFET technology for specific applications. The results show that both Si and GaAs MOSFETs have their advantages and disadvantages, and the choice depends on the application requirements.
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Luo, Qixiao. "Research on the advantages and development status of new material MOSFET." Highlights in Science, Engineering and Technology 33 (February 21, 2023): 210–18. http://dx.doi.org/10.54097/hset.v33i.5313.

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When using MOSFETs, in order to improve the operating speed, so that higher power density and lower functional consumption can be obtained in the process, researchers have explored in multiple dimensions. In this paper, three popular new material MOSFETs are mainly explained, including SiC MOSFET, GaN MOSFET and graphene MOSFET. This paper introduces their advantages and their development status, so as to compare the advantages of new materials. In conclusion, By adding materials, the electron mobility and stability of the FET can be increased in some situation. The research in this paper will undoubtedly promote the further development of MOSFET.
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Chek Yee, Ooi, Mok Kai Ming, and Wong Pei Voon. "DEVICE AND CIRCUIT LEVEL SIMULATION STUDY OF NOR GATE LOGIC FAMILIES DESIGNED USING NANO-MOSFETs." Platform : A Journal of Science and Technology 4, no. 1 (May 31, 2021): 73. http://dx.doi.org/10.61762/pjstvol4iss1art11064.

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The investigation of silicon-based nano-MOSFETs logic circuits is helpful to gain more comprehensive knowledge about nanoscale transistors. Therefore, a simulation study has been performed on four logic families of two inputs NOR gate logic circuits, namely (i) nano-CMOS NOR gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NOR gate, (iii) 733.8 Ω resistive loaded nano-MOSFET NOR gate, and finally (iv) pseudo-n-type nano-MOSFET NOR gate. The nano-MOSFET technology node studied in this paper is 10 nm. Device simulation is done using an online NanoMOS simulator, whereas circuit simulation is carried out using freeware WinSpice. The main obstacle encountered during downscaling of nano-MOSFETs is low power dissipation and high-speed nano-MOSFET logic circuits. Correct logical NOR operation has been proven by observing simulated timing waveforms. Transient timing analysis on nano-MOSFET loaded n-type nano-MOSFET NOR gate has shown that propagation delays calculated from theory and simulation are 66% matched. From the analysis, this 10 nm nano-MOSFET NOR logic circuit design exhibit a dynamic power reduction of 148 times and a propagation delay improvement of 33 times when benchmarked against a typical 120 nm MOSFET logic circuit. Keywords: nano transistor, electrical characteristics, channel length, channel width, benchmarking, power, speed
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Albrecht, Matthaeus, Tobias Erlbacher, Anton J. Bauer, and Lothar Frey. "Potential of 4H-SiC CMOS for High Temperature Applications Using Advanced Lateral p-MOSFETs." Materials Science Forum 858 (May 2016): 821–24. http://dx.doi.org/10.4028/www.scientific.net/msf.858.821.

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In this work, the impact of the n-well doping concentration on the channel mobility and threshold voltage of p-MOSFETs and their applications in CMOS-devices is evaluated. For this purpose lateral p-channel MOSFETs with different channel lengths (L = 800 μm, 10 μm, 5 μm, and 3 μm) and doping concentrations (ND = 1015 cm-3 and 8·1015 cm-3) were fabricated and the respective field-effect mobility was extracted from the transfer-characteristics. Comparable to n-MOSFETs the mobility of p-MOSFETs was found to be the highest for the lowest doping concentration in the channel and the absolute value of the threshold voltage increases with increasing doping concentration [4]. To investigate its suitability for CMOS applications, inverters with different doping concentrations for n-MOSFET (NA = 1015 cm-3 and 1017 cm-3) und p-MOSFET (ND = 1015 cm-3 and 8·1015 cm-3) were built. For logic levels of 0 V and 10 V, the voltage transfer characteristic with the highest input ranges was obtained for a low p-MOSFET and a high n-MOSFET doping concentration. The lowest propagation delay time could be achieved with a low p-MOSFET and a low n-MOSFET doping concentration. At room temperature as well as at high temperatures T = 573 K the drain current of p-MOSFETs with channel lengths below 3 μm is hampered by the series resistance of the source and drain region which limits the performance of CMOS devices.
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Yoshioka, Hironori, Junji Senzaki, Atsushi Shimozato, Yasunori Tanaka, and Hajime Okumura. "Characterization of Interface State Density from Subthreshold Slope of MOSFETs at Low Temperatures (≥ 10 K)." Materials Science Forum 821-823 (June 2015): 745–48. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.745.

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We have evaluated interface state density (DIT) for EC−ET > 0.00 eV from the subthreshold slope deterioration of MOSFETs at low temperatures. We have compared two n-channel MOSFETs on the C- and a-faces with the gate oxide formed by pyrogenic oxidation followed by annealing in H2. The peak field-effect mobility (µFE,peak) for the C-face MOSFET was 57 cm2V-1s-1 at 300 K, which is lower than the half of 135 cm2V-1s-1 for the a-face MOSFET. We have shown that DIT very close to EC can well explain why µFE for C-face MOSFETs is lower than that for a-face MOSFETs. The value of DIT at 0.00 eV corresponding to the subthreshold slope at 11 K was 1.6×1014 cm-2eV-1 for the C-face MOSFET, which is more than the double of 6.4×1013 cm-2eV-1 for the a-face MOSFET.
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Che, Haoming. "Simulation study on dynamic characteristics of SiC MOSFET." Theoretical and Natural Science 5, no. 1 (May 25, 2023): 805–14. http://dx.doi.org/10.54254/2753-8818/5/20230507.

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In this paper, the third generation power MOSFET is introduced, and the physical model based on silicon based MOSFET is improved for SiC MOSFET, and the commercial planar gate and trench gate 1.2kV SiC MOSFET are simulated. The accuracy of physical modals is tested by comparing the static characteristics with commercial ones. The dynamic characteristics of two MOSFETs are simulated by inductively clamped double pulse circuit, and the circuit parameters are analyzed according to the static characteristics of the devices. The switching loss of the two MOSFETs is calculated and compared by using TCAD software. In the two devices with the same volume, the trench gate structure has the larger switching loss.
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Ahn, Tae Jun, and Yun Seop Yu. "Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter." Journal of Nanoscience and Nanotechnology 21, no. 8 (August 1, 2021): 4252–57. http://dx.doi.org/10.1166/jnn.2021.19388.

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We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.
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Lichtenwalner, Daniel J., Brett Hull, Vipindas Pala, Edward Van Brunt, Sei-Hyung Ryu, Joe J. Sumakeris, Michael J. O’Loughlin, Albert A. Burk, Scott T. Allen, and John W. Palmour. "Performance and Reliability of SiC Power MOSFETs." MRS Advances 1, no. 2 (2016): 81–89. http://dx.doi.org/10.1557/adv.2015.57.

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ABSTRACTDue to the wide bandgap and other key materials properties of 4H-SiC, SiC MOSFETs offer performance advantages over competing Si-based power devices. For example, SiC can more easily be used to fabricate MOSFETs with very high voltage ratings, and with lower switching losses. Silicon carbide power MOSFET development has progressed rapidly since the market release of Cree’s 1200V 4H-SiC power MOSFET in 2011. This is due to continued advancements in SiC substrate quality, epitaxial growth capabilities, and device processing. For example, high-quality epitaxial growth of thick, low-doped SiC has enabled the fabrication of SiC MOSFETs capable of blocking extremely high voltages (up to 15kV); while dopant control for thin highly-doped epitaxial layers has helped enable low on-resistance 900V SiC MOSFET production. Device design and processing improvements have resulted in lower MOSFET specific on-resistance for each successive device generation. SiC MOSFETs have been shown to have a long device lifetime, based on the results of accelerated lifetime testing, such as high-temperature reverse-bias (HTRB) stress and time-dependent dielectric breakdown (TDDB).
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Dissertations / Theses on the topic "MOSFET"

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Ngabonziza, Nyampame Christian. "Drivning av Likströmsmotor med MOSFET : DC Motor control by MOSFET." Thesis, Linnéuniversitetet, Institutionen för datavetenskap, fysik och matematik, DFM, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-11294.

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Detta projekt är ett examensarbete för kandidatexamen som är obligatorisk för alla studenter. För att ta ut examen måste jag lämna en skriftlig rapport om vad jag har gjort. Redovisa simuleringar och mätningar på olika kretsar.  I mitt fall var jag intresserad på att studera hur varvtalet på en likströmsmotor kan regleras med hjälp av olika metoder.  Detta är mycket utmanande för mig eftersom jag inte har sett så många lösningar på detta problem.  Jag kommer att använda kunskap, teknik och komponenter från Kraftelektronik för att utföra mitt arbete.  Det blir mycket intressant att med dagens utveckling av tekniken se hur olika metoder kan användas för att undersöka hur kraftelektronik kan användas i kontroll av varvtal, frekvens och rotationsriktning av elektriska maskiner.
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Lui, Jerome C. (Jerome Chun Lung). "Automated MOSFET parameter extraction." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36583.

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Major, Jan. "Počítačové modelování MOSFET tranzistoru." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219148.

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Work is focused on computer modeling of PN junction and MOSFET transistor in the program COMSOL Multiphysics and in program TiberCAD. The text is discussed on the drift and diffusion in semiconductors. Also shown is a method of modeling the PN junction and MOSFET transistor in the programs and compare models.
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Munteanu, Daniela. "Modélisation et caractérisation des transistors SOI : du pseudo-MOSFET au MOSFET submicronique ultramince." Grenoble INPG, 1999. http://www.theses.fr/1999INPG0104.

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L'objet de cette these est de contribuer a l'analyse et a l'optimisation des materiaux soi et au developpement de modeles physiques et de methodes de caracterisation adaptees aux dispositifs soi. Dans le premier chapitre, nous rappelons l'interet de la technologie soi, ses avantages et ses inconvenients par rapport a la technologie si massif. Le deuxieme chapitre est consacre a la caracterisation du materiau, en utilisant la technique -mosfet, methode tres appropriee pour comparer la qualite et les parametres electriques des differentes structures soi. Une analyse approfondie de la validite de cette technique est realisee par simulation numerique. La technique -mosfet est ensuite appliquee a l'analyse de plusieurs materiaux soi et de certains procedes technologiques. Le troisieme chapitre porte sur la caracterisation des dispositifs soi finis, avec une etude detaillee du fonctionnement en haute et basse temperature. Nous presentons une analyse de transistors soi ultimes : (a) le fonctionnement en basse temperature du dt-mos est etudie experimentalement et ses avantages par rapport aux structures classiques sont mis en evidence ; (b) des mesures sur des tmos ultra-minces demontrent leur fonctionnalite ainsi que l'impact de mecanismes physiques particuliers (inversion volumique, fort couplage des interfaces, effets quantiques). Le quatrieme chapitre est consacre a l'analyse et a la modelisation des mecanismes transitoires dans les tmos/soi. Differents types de transitoires du courant de drain (overshoot et undershoot, simple et double grille) sont mesures et simules avec atlas et soi-spice. Ces phenomenes sont utilises a l'extraction de la duree de vie des porteurs, parametre essentiel qui reflete la qualite du film soi.
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Shah, Nirav. "Stress modeling of nanoscale MOSFET." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0012221.

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Prokhorov, Andrey, and Olesya Gerzheva. "Model of MOSFET in Delphi." Thesis, Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-14209.

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In modern times the increasing complexity of transistors and their constant decreasingsize require more effective techniques to display and interpret the processes that are inside of devices. In this work, we are modeling a two‐dimensional n‐MOSFET with a long channeland uniformly doped substrate. We assume that this device is a large geometry device so that short‐channel and narrow‐width effects can be neglected. As a result of the thesis, a demonstration program was built. In this executable file, the user can choose parameters of the MOSFET‐model: drain and gate voltage, and different geometrical parameters of the device (junction depth and effective channel length). In the advanced regime of the program, the user can also specify the model re‐calculation parameter, doping concentration in n+ and bulk regions. The program shows the channel between the source and drain region with surface diagrams of carrier density and potential energy as an output. It is possible to save all calculated results to a file and process it in any other program, for example, plot graphics in Matlab or Matematica. The model can be used in lectures that are related to semiconductor physics in order to explain the basic working mechanisms of MOSFETs as well as for further detailed analysis of the processes in MOSFETs. It is possible to use our modeling techniques to rebuild the model in another computer language, or even to build other models of transistors, performing similar calculations and approximations. It is possible to download the executable file of the model here: http://studentdevelop.com/projects/MOSFET_model.zip
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Chen, Max Chuan. "Modeling of KTH UTBSOI MOSFET." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177444.

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Semiconductor devices such as transistors and integrated circuits are everywhere in our daily lives, it's one of the most important foundations of today's information society. Nanotechnology enables the production of lighter, faster and more efficient components and systems. Manufacturing technology has improved considerably over the past 40 years, but in recent years, the bulk transistors have reaching the limits of Moore’s law as the size shrinking too few tens of nanometers. The main difficulties are to reduce the power consumption, improve the speed meanwhile maintain the low manufacturing cost. This has given an opportunity for some emerging semiconductor technologies. One of the most promising approaches is implementation of new device architectures, such as FinFET and UTBSOI. This bachelor thesis covers the basics of compact modeling of UTBSOI MOSFET, by using the BSIMSOI compact model and SPICE software Cadence to model the KTH Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) transistor. The result of this paper shows the accuracy of BSIMSOI and can be used for future extraction work.
Halvledarkomponenter såsom transistorer och integrerade kretsar finns överallt i vår vardag, det är en av de viktigaste grunderna för dagens informationssamhälle. Nanoteknik möjliggör produktion av lättare, snabbare och effektivare komponenter och system. Tillverkningstekniken har förbättrats avsevärt under de senaste 40 åren, men på de senaste åren har de bulktillverkade transistorerna nått gränserna för Moores lag, när storleken krymper till några tiotal nanometer. De största svårigheterna är att minska energiförbrukningen, förbättra hastigheten samt bevara den låga tillverkningskostnaden. Detta har gett möjlighet för att utvecklar ny halvledarteknik. En av de mest lovande metoderna är implementering av nya transitor arkitekturer, till exempel FinFET och UTBSOI. Detta examensarbete omfattar grunderna i modellering av SOIMOSFET, med hjälp av BSIMSOI och SPICE programvara Cadence kan man modellera KTH transistor. Resultatet av denna studie visar noggrannheten hos BSIMSOI och kan användas för framtida arbete inom ämnet.
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李華剛 and Eddie Herbert Li. "Narrow-channel effect in MOSFET." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1990. http://hub.hku.hk/bib/B31209312.

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Wang, Yao. "MOSFET strain sensor for microcantilevers." Thesis, Queen's University Belfast, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675436.

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Microcantilever structure was used to design and fabricate strain sensors. P-channel MOSFETs were designed and fabricated for strain sensors as hole mobility under uniaxial stress has higher mobility enhancement than that of electron mobility under either uniaxial stress or biaxial stress. For MOSFET sensors on microcantilevers, anchor area is the traditional position for sensors due to its highest stress. The aim of this research is to investigate the assumption of biaxial stress at the anchor area which makes the anchor location less sensitive. COMSOL software was employed to simulate stress profiles in silicon beams. Four-pointbending provides almost uniaxial stress at the surface, but cantilever bending generates biaxial stress at the anchor region but uniaxial stress away from anchor. The transverse stress at the anchor region increases with the bending and is depends on the longitudinal stress. In this research, the sensitivity of the sensor at the cantilever anchor was lower than that under uniaxial stress from four-point-bending measurement. It is suggested that the transverse stress at the anchor region will degrade the sensitivity compared to that under uniaxial stress. Although narrower cantilever provides higher longitudinal stress at the anchor, it brings higher transverse stress at the anchor as well. Possible solutions such as employing stressed layer, holes and slots were proposed to reduce the transverse stress without impact on the longitudinal stress, thus to increase the sensitivity. In comparison, employing slots is recommended as the transverse stress can be concentrated to nearly zero at the slot region with enhanced and elongated longitudinal stress.
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Araújo, Guido Costa Souza de 1962. "Simulação bidimensional de dispositivos MOSFET." [s.n.], 1990. http://repositorio.unicamp.br/jspui/handle/REPOSIP/261310.

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Orientador : Bernard Waldman
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica
Made available in DSpace on 2018-07-13T21:47:06Z (GMT). No. of bitstreams: 1 Araujo_GuidoCostaSouzade_M.pdf: 7097802 bytes, checksum: 3989d5131b3e9436f6f55fc6d620a10e (MD5) Previous issue date: 1990
Resumo: Com a drástica diminuição das dimensões nas novas gerações de transistores MOS VLSI, um aumento considerável de efeitos dimensionais no comportamento destes dispositivos tem surgido. Isto traz como conseqüência imediata, a impossibilidade de utilização dos modelos clássicos analíticos no projeto e no estudo destes transistores. A proposta deste trabalho é a de desenvolver um simulador bidimensional para transistores MOSFET de canal curto, que permita uma caracterização precisa destes dispositivos em equilíbrio termodinâmico. Nesta situação, a influência de efeitos dimensionais sobre VT pode ser melhor estudada, possibilitando assim a obtenção de uma primeira aproximação para o projeto destes dispositivos
Mestrado
Mestre em Engenharia Elétrica
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Books on the topic "MOSFET"

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Taylor, B. E. Power Mosfet design. Chichester, W. Sussex, England: Wiley, 1993.

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Motorola. Power MOSFET transistor data. (s.l.): Motorola, 1988.

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Baliga, B. Jayant. Advanced Power MOSFET Concepts. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-5917-1.

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Motorola. Power mosfet transistor data. 4th ed. (s.l.): Motorola, 1989.

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Baliga, B. Jayant. Advanced power MOSFET concepts. New York: Springer, 2010.

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Warner, R. M. MOSFET theory and design. New York: Oxford University Press, 1999.

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Cheng, Yuhua. MOSFET modeling & BSIM3 user's guide. New York: Kluwer Academic Publishers, 2002.

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Chenming, Hu, ed. MOSFET modeling & BSIM3 user's guide. Boston: Kluwer Academic Publishers, 1999.

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Cheng, Yuhua. MOSFET modeling & BSIM3 user's guide. Boston: Kluwer Academic Publishers, 1999.

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Kulkarni, Shukla Purushottam. Subthreshold modelling of the MOSFET. Birmingham: University of Birmingham, 1995.

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Book chapters on the topic "MOSFET"

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Di Paolo Emilio, Maurizio. "MOSFET." In Microelectronics, 35–43. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-22545-6_3.

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Cumberbatch, Ellis. "MOSFET Modelling." In Proceedings of the Second European Symposium on Mathematics in Industry, 167–79. Dordrecht: Springer Netherlands, 1988. http://dx.doi.org/10.1007/978-94-009-2979-1_10.

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Schroeder, Dietmar. "MOSFET Gate." In Computational Microelectronics, 172–84. Vienna: Springer Vienna, 1994. http://dx.doi.org/10.1007/978-3-7091-6644-4_8.

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Robins, I. "MOSFET devices." In Chemical Sensors, 225–35. Dordrecht: Springer Netherlands, 1988. http://dx.doi.org/10.1007/978-94-010-9154-1_10.

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Uyemura, John P. "MOSFET Characteristics." In Circuit Design for CMOS VLSI, 21–77. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_2.

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Nguyen, Cam, and Youngman Um. "Switching MOSFET." In SpringerBriefs in Electrical and Computer Engineering, 37–44. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-46248-2_4.

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Ramshaw, R. S. "The MOSFET." In Power Electronics Semiconductor Switches, 244–93. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4757-6219-8_6.

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Neacşu, Dorin O. "Power MOSFET." In Automotive Power Systems, 191–210. Boca Raton : CRC Press, 2020.: CRC Press, 2020. http://dx.doi.org/10.1201/9781003053231-10.

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Xanthakis, John P. "The MOSFET." In Electronic Conduction, 195–236. First edition. | Boca Raton : CRC Press, 2021. | Series: Textbook series in physical sciences: CRC Press, 2020. http://dx.doi.org/10.1201/9780429506444-7.

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Divekar, Dileep. "Mosfet Models." In The Kluwer International Series in Engineering and Computer Science, 57–143. Boston, MA: Springer US, 1988. http://dx.doi.org/10.1007/978-1-4613-1687-9_5.

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Conference papers on the topic "MOSFET"

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Xiao, Deyuan, Gary Chen, Roger Lee, Daniel Lu, Leong Tan, Yung Liu, C. c. Shen, and Jong Kim. "PSDG MOSFET." In 2006 International Symposium on VLSI Technology, Systems, and Applications. IEEE, 2006. http://dx.doi.org/10.1109/vtsa.2006.251068.

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Nakachai, Rattapong, Toempong Phetchakul, Sawatdipong Poonsawat, and Amporn Poyai. "Simulation of MOSFET as horizontal magnetic mosfet (MAGFET)." In 2017 2nd International Conference on Frontiers of Sensors Technologies (ICFST). IEEE, 2017. http://dx.doi.org/10.1109/icfst.2017.8210464.

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Gokirmak, Ali. "Accumulated Body MOSFET." In 2006 64th Device Research Conference. IEEE, 2006. http://dx.doi.org/10.1109/drc.2006.305126.

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Fauzan, M. N. Z. A., I. Saad, R. Ismail, Mohamad Rusop, Rihanum Yahaya Subban, Norlida Kamarulzaman, and Wong Tin Wui. "Numerical Simulation Characterization of 50nm MOSFET Incorporating Dielectric Pocket (DP-MOSFET)." In INTERNATIONAL CONFERENCE ON ADVANCEMENT OF MATERIALS AND NANOTECHNOLOGY: (ICAMN—2007). AIP, 2010. http://dx.doi.org/10.1063/1.3377887.

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Cha, Kyuhyun, Jongwoon Yoon, Jinhee Cheon, and Kwangsoo Kim. "The limitation of the Split-Gate MOSFET(SG-MOSFET) at 3.3kV." In 2021 International Conference on Electronics, Information, and Communication (ICEIC). IEEE, 2021. http://dx.doi.org/10.1109/iceic51217.2021.9369734.

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Roscoe, N. M., Y. Zhong, and S. J. Finney. "Comparing SiC MOSFET, IGBT and Si MOSFET in LV distribution inverters." In IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society. IEEE, 2015. http://dx.doi.org/10.1109/iecon.2015.7392188.

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Garg, Aanchal, and Yashvir Singh. "Nanoscale SiGe Double Gate MOSFET (DG-MOSFET) for Analog/RF Circuits." In 2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON). IEEE, 2019. http://dx.doi.org/10.1109/upcon47278.2019.8980278.

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Ikutajima, Yuta, and Hirotaka Koizumi. "Choke-less Class-E Oscillator Using p-MOSFET and n-MOSFET." In 2023 IEEE 32nd International Symposium on Industrial Electronics (ISIE). IEEE, 2023. http://dx.doi.org/10.1109/isie51358.2023.10228146.

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Hogyoku, Michiru. "SOI MOSFET with Body-Terminal-Controlled Capacitive-Coupling (DYTONA SOI MOSFET)." In 2002 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2002. http://dx.doi.org/10.7567/ssdm.2002.p9-9.

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Madhavi, A., and P. Dass. "Investigation of transfer characteristics of enhancement MOSFET comparing with depletion MOSFET." In FIFTH INTERNATIONAL CONFERENCE ON APPLIED SCIENCES: ICAS2023. AIP Publishing, 2024. http://dx.doi.org/10.1063/5.0198193.

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Reports on the topic "MOSFET"

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Hu, Chenming. Dynamic Threshold-Voltage MOSFET. Fort Belvoir, VA: Defense Technical Information Center, September 1999. http://dx.doi.org/10.21236/ada368429.

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Zborowski, Jaroslaw T. GaAs-Based Mosfet Employing Epitaxial Al2O3. Fort Belvoir, VA: Defense Technical Information Center, June 1998. http://dx.doi.org/10.21236/ada363849.

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Sbrockey, Nick M., Gary S. Tompa, Michael G. Spencer, and Chandra M. V. S. Chandrashekhar. SiC Power MOSFET with Improved Gate Dielectric. Office of Scientific and Technical Information (OSTI), August 2010. http://dx.doi.org/10.2172/1067486.

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Wallace, Robert M. Device Performance and Reliability Improvements of AlGaBN/GaN/Si MOSFET. Fort Belvoir, VA: Defense Technical Information Center, February 2016. http://dx.doi.org/10.21236/ada636905.

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Zhou, Sida. Mobility Modeling and Simulation of SOI Si1-x Gex p-MOSFET. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6830.

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Chow, Louis C., and Robert J. Mauriello. Utilizing ISE-TCAD Software to Simulate Power MOSFET Devices Operating at Cryogenic Temperatures. Fort Belvoir, VA: Defense Technical Information Center, April 2001. http://dx.doi.org/10.21236/ada387644.

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Bloomfield, P. Materials preparation and fabrication of pyroelectric polymer/silicon MOSFET detector arrays. Final report. Office of Scientific and Technical Information (OSTI), March 1992. http://dx.doi.org/10.2172/106639.

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Thomas, Michael. Software Development for Data Visualization and Analysis of PN-Diodes & MOSFET Devices. Office of Scientific and Technical Information (OSTI), August 2022. http://dx.doi.org/10.2172/1880917.

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Wallace, Robert M. Device Performance and Reliability Improvements of AlGaN/GaN/Si MOSFET Using Defect-Free Gate Recess and Laser Annealing. Fort Belvoir, VA: Defense Technical Information Center, February 2015. http://dx.doi.org/10.21236/ada621256.

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Ferry, David K. Transport in Submicron MOSFETS. Fort Belvoir, VA: Defense Technical Information Center, September 1986. http://dx.doi.org/10.21236/ada173156.

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