Dissertations / Theses on the topic 'MOS-HEMT'

L’architecture latérale MOS-HEMT à grille gravée en nitrure de gallium (GaN), en cours de développement au CEA-Leti sur des substrat silicium de 200mm, vise à répondre aux besoins croissants d’électrification dans un contexte de forte demande pour des convertisseurs de puissance moyenne-haute tension (>200V). Les applications ciblées, incluent les chargeurs de téléphones, d'ordinateurs portables, les chargeurs embarqués pour les véhicules électriques, les micro-onduleurs photovoltaïques, etc., qui nécessitent des convertisseurs de meilleur rendement que ceux actuellement basés sur la technologie silicium. L’objectif de cette thèse, est d’étudier l'influence de l'architecture MOS-HEMT sur les propriétés physiques et les performances électriques. L’accent est mis sur l’optimisation de la résistance à l’état-passant des transistors (RON), qui est envisagée dans une perspective globale afin de maintenir les propriétés de blocage (RON/BV), et le comportement « normally-off » des composants (RON/VTH). Deux axes majeurs sont étudiés. Le premier concerne la résistance du canal de grille qui dépend de la gravure, qui elle-même joue sur la morphologie, et sur les mobilités du canal, auxquelles s’ajoute la contribution de la qualité de l’interface diélectrique/GaN (µ≤ 250cm2.V−1.s−1). Des variantes de cette morphologie de grille tels que l’angle (90° à 60°), la profondeur (50nm à 350nm), l’orientation cristallographique du canal, ainsi que l'impact des procédés de fabrication (ICP-RIE, ALE, nettoyage), ont été étudiées via des mesures électriques IDS(VG), C(VG), IDS(VDS) en blocage, puis simulées et modélisées sous TCAD. Une méthode d'extraction des contributions de mobilité autour de la grille a été proposée, et montre une meilleure mobilité du fond de la grille (≤190 cm2.V−1.s−1 à 25°C) comparée à celle liée aux flancs (≤ 93 cm2.V−1.s−1 à 25°C). De plus des corrélations entre les paramètres électriques (RON, VTH, SS) et le design ont été établies, et montrent un meilleur compromis RON/fuites de grille/source en régime bloqué à forte tension de drain, avec une profondeur de gravure intermédiaire de 150nm pour une longueur de grille de 0.5µm (RON=8.1Ω.mm à 25°C et 15.2 Ω.mm à 150°C). Le second axe porte sur la résistance des accès du transistor, liée aux propriétés de l’hétérojonction AlGaN/AlN/GaN et aux mécanismes de polarisation à l’origine du gaz d’électrons 2D à l’interface AlN/GaN (2DEG). Plusieurs variantes technologiques de l’hétérojonction incluant l’épaisseur de la couche AlN (0.7nm à 1.5nm), de la barrière AlGaN (7nm à 24nm), le pourcentage d’aluminium (24% à 60%), et le dopage, ont été caractérisées électriquement par des mesures 5 pointes I(VG) et C(VG) sur des structures Pan der Pauw à 25°C et 150°C. Des simulations Poisson-Schrödinger 1D ont également permis d’évaluer la charge d’interface de polarisation et de d’identifier les leviers d’amélioration de cette résistance 2DEG. Une valeur minimale de 213Ω/◻ été obtenue à 25°C pour le pourcentage de 60% d’aluminium (µ=1591 cm2.V−1.s−1 et nS =18.3×1012cm−2) et de 455 Ω/◻ à 150°C (µ=774 cm2.V−1.s−1 et nS =17.7×1012 cm−2), réduisant le RON de 2.1Ω.mm à 150°C. En conclusion, les résultats de cette thèse ouvrent la voie à de nouvelles perspectives pour les futures générations de transistors GaN, tant en termes d'optimisation des performances que d'amélioration des procédés de fabrication
The lateral MOS-HEMT architecture with etched gate ("normally-off") in gallium nitride (GaN), currently under development at CEA-Leti on 200mm silicon substrates, aims to meet the growing electrification needs in response to the high demand for medium-to-high voltage power converters (>200V). The targeted applications include phone chargers, laptop chargers, onboard chargers for electric vehicles, photovoltaic micro-inverters, etc., which require more efficient converters than those currently based on silicon technology. The objective of this thesis is to study the influence of the MOS-HEMT architecture on the physical properties and electrical performance. The focus is on optimizing the on-state resistance of the transistors (RON), with a global perspective on maintaining blocking properties (RON/BV) and the "normally-off" behavior of the components (RON/VTH). Two main areas are studied. The first concerns the gate channel resistance, which depends on the etching, influencing the morphology and the channel mobility, along with the contribution of the dielectric/GaN interface quality (µ≤ 250 cm2.V−1.s−1). Variations in gate morphology, such as angle (90° to 60°), depth (50nm to 350nm), channel crystallographic orientation, and the impact of fabrication processes (ICP-RIE, ALE, cleaning) were studied through electrical measurements IDS(VG), C(VG), IDS(VDS) in blocking mode, and were then simulated and modeled using TCAD. A mobility extraction method around the gate was proposed, showing better mobility at the bottom of the gate (≤190 cm2.V−1.s−1 at 25°C) compared to the sidewalls (≤ 93 cm2.V−1.s−1 at 25°C). Additionally, correlations between electrical parameters (RON, VTH, SS) and design were established, showing a better RON/leakage compromise with an intermediate etching depth of 150nm and a gate length of 0.5µm (RON=8.1Ω.mm at 25°C and 15.2 Ω.mm at 150°C). The second area focuses on the transistor's access resistance, linked to the properties of the AlGaN/AlN/GaN heterojunction and polarization mechanisms responsible for the 2D electron gas (2DEG) at the AlN/GaN interface. Several technological variations of the heterojunction, including the AlN layer thickness (0.7nm to 1.5nm), AlGaN barrier (7nm to 24nm), aluminum percentage (24% to 60%), and doping, were electrically characterized using 5-point I(VG) and C(VG) measurements on Van der Pauw structures at 25°C and 150°C. 1D Poisson-Schrödinger simulations were also used to assess the interface polarization charge and identify improvement levers for this 2DEG resistance. A minimum value of 213Ω/◻ was obtained at 25°C for 60% aluminum (µ=1591 cm2.V−1.s−1 and nS =18.3×1012cm−2) and 455Ω/◻ at 150°C (µ=774 cm2.V−1.s−1 and nS = nS =17.7×1012cm−2), reducing RON by 2.1Ω.mm at 150°C. In conclusion, the results of this thesis open up new perspectives for future generations of GaN transistors, both in terms of performance optimization and manufacturing process improvements

Les travaux présentés dans ce manuscrit sont axés sur le développement et la caractérisation de modules technologiques sur semiconducteurs à large bande interdite à base de nitrure de gallium (GaN), pour la réalisation de transistors et de cathodes froides. Ils ont été réalisés au sein du laboratoire III-V lab, commun aux entités : Alcatel - Thales - CEA Leti. Notre projet de recherche a bénéficié d'un soutien financier assuré par Thales Electron Devices (TED) et l'Agence Nationale de la Recherche ( ANR ). Concernant les transistors HEMT III-N, nos investigations se sont focalisées sur le développement des parties actives des transistors, incluant principalement la structuration des électrodes de grilles, l'étude de la passivation des grilles métalliques, ainsi que l'étude de diélectriques de grille pour la réalisation de structures MIS-HEMT.Les transistors MOS-HEMT « Normally-off » réalisés présentent des performances comparables à l'état de l'art, avec une densité de courant de drain maximum comprise entre 270 mA et 400 mA / mm, un ratio ION / IOFF > 1100, et des tensions de claquage > 200V. Les tensions de seuil sont comprises entre + 1,8 V et + 4 V. Nos contributions au développement des cathodes froides ont permis de démontrer une première émission dans le vide à partir de cathodes GaN, avec une densité de courant maximale de 300 µA / cm2 pour une tension de polarisation de 40 V
The results presented in this manuscript relate to technological developments and device processing on wide bandgap III-N semiconductor materials. They have been focused on III-N HEMT transistors and GaN cold cathodes. They have been realised within the III-V lab, which is a common entity between: Alcatel - Thales - CEA Leti. They have been financially supported by Thales Electron Devices company (TED) and the French National Research Agency ( ANR ). Regarding III-N HEMTs, our investigations have been focused on the development of device gate processing, which includes : the structuration of gate electrodes, the study of device passivation, and the realization of Metal-Insulator-Semiconductor High Mobility Electron Transistors ( MIS-HEMTs ). The “ Normally-off ” MOS-HEMT structures we have realized exhibit performances comparable to the state of the art, with a maximum drain current density between 270 and 400 mA / mm, a ION / IOFF ratio > 1.100, and a breakdown voltage > 200V. The threshold voltage values range between + 1,8 V and + 4V. We have also been able to demonstrate prototype GaN cold cathodes providing a maximum current density of 300 µA / cm2, emitted in vacuum for a bias voltage around 40 V

L’intégration monolithique hétérogène de composants III-N sur silicium (Si) offre de nombreuses possibilités en termes d’applications. Cependant, gérer l’hétéroépitaxie de matériaux à paramètres de maille et coefficients de dilatation très différents, tout en évitant les contaminations, et concilier des températures optimales de procédé parfois très éloignées requière inévitablement certains compromis. Dans ce contexte, nous avons cherché à intégrer des transistors à haute mobilité électronique (HEMT) à base de nitrure de Gallium (GaN) sur substrat Si par épitaxie sous jets moléculaires (EJM) en vue de réaliser des circuits monolithiques GaN sur CMOS Si
The monolithic integration of heterogeneous devices and materials such as III-N compounds with silicon (Si) CMOS technology paves the way for new circuits applications and capabilities for both technologies. However, the heteroepitaxy of such materials on Si can be challenging due to very different lattice parameters and thermal expansion coefficients. In addition, contamination issues and thermal budget constraints on CMOS technology may prevent the use of standard process parameters and require various manufacturing trade-offs. In this context, we have investigated the integration of GaN-based high electron mobility transistors (HEMTs) on Si substrates in view of the monolithic integration of GaN on CMOS circuits

Ce document présente les travaux de thèse ayant pour objet la recherche et développement d’une technologie co-intégrée HEMT GaN normale-on/normally-off compatible avec les matériaux et procédés technologiques de la technologie normally-on hyperfréquence. Un exposé théorique et une revue de l’état de l’art permettent d’abord d’entrevoir les différentes solutions technologiques qui s’offrent à nous, tout en affirmant et en précisant les applications visées. Différentes briques technologiques sont ensuite développées pour la fabrication de MOS-HEMTs GaN à recess de grille sur des épi-structures à barrière AlGaN ou (Ga)InAlN dédiées aux applications hyperfréquences. Nous insistons sur la possibilité d’intégrer les 2 fonctionnalités normally-off et normally-on de manière monolithique. Les échantillons ainsi réalisés sont ensuite caractérisés électriquement de manière conventionnelle, mais aussi en utilisant des techniques avancées de spectroscopie de pièges comme les paramètres S à basse fréquence et la mesure du transitoire de RON. Bien que certains phénomènes de piègeage dans l’oxyde de grille soient mis en évidence, les résultats sont très satisfaisants : des composants normally-off sont obtenus pour les 2 structures, et les performances sont au niveau de l’état de l’art mondial, avec plusieurs pistes d’amélioration en perspective
This document reports on research and development efforts towards a normally-on/normally-off integrated GaN HEMT technology that remains compatible with the material and processing dedicated to normally-on microwave devices. Following several theoretical considerations, the state-of-the-art is presented, which gives a perspective on the available technological solutions and helps define the specifications and the targeted applications. The development and optimization of new process steps enables the fabrication of gate-recessed MOS-HEMTs on epi-structures with AlGaN or (Ga)InAlN barrier, monolithically integrable with normally-on transistors. The samples are electrically characterized by means of standard measurements and more advanced trap spectroscopy techniques such as low-frequency S-parameters or RON transient monitoring. In spite of oxide-related trapping phenomena, the results are very promising: normally-off devices are obtained for both structures, and the performances are in line with literature accounts while identified possible improvements can be explored

High electron mobility transistors (HEMTs) have long been studied for high frequency and high-power application. Among widely known high electron mobility transistors, AlGaN/GaN HEMTs are having the upper hand due to high electron mobility of the GaN channel. Over the times, issues like current collapse, gate leakage, self-heating and gate lag have questioned the performance and reliability of these devices. In the recent years, engineers have come up with newer architectures to address some of these issues. Inserting a high-k dielectric oxide layer in the gate stack proved to be an effective solution to mitigate gate leakage, reduce interfacial traps and improve optimal working conditions. This work aims to study the reliability aspect of these so-called metal-oxide-semiconductor high electron mobility transistors (MOS-HEMT) specifically, HfO2 and HfZrO2 MOS-HEMTs. It was found through numerical simulations that though HfO2 and HfZrO2 dielectrics were able to mitigate gate leakage current, they tend to accumulate more heat in the channel region with respect to the conventional silicon nitride (SiN) passivated counterparts. Moreover, few asymmetric structures were proposed where silicon nitride was placed in the dielectric layer along with HfO2/HfZrO2. In this study it was found that these asymmetric structures showed superior thermal performance while showing near-zero gate leakage current.

Dans le domaine des semi-conducteurs, la technologie silicium (principalement l’architecture CMOS) répond à la majorité des besoins du marché et, de ce fait, elle est abondamment utilisée. Ce semi-conducteur profite d’une part, de son abondance dans la nature et par conséquent de son faible coût, et d’autre part de la grande maturité de sa technologie qui est étudiée depuis un demi-siècle. Cependant, le silicium (Si) souffre de plus en plus de ses propriétés électriques limitées qui l’excluent de certains domaines dans lesquels les technologies à base de matériaux III-V sont les plus utilisées. Bien que la technologie à base de matériaux III-V, notamment les hétérostructures à base de nitrure de gallium (GaN), soit très performante par rapport à celle à base du matériau historique (le silicium), cette nouvelle technologie est toujours limitée aux applications utilisant des circuits de moyennes voire faibles densités d’intégration. Ceci limite l’utilisation de cette technologie pour la réalisation de produits à très grande valeur ajoutée. Pour s’affranchir de cette limitation, plusieurs sujets de recherche ont été entrepris ces dernières années pour intégrer au sein du même circuit des composants à base de silicium et de matériaux III-V. En effet, la possibilité d’allier les bonnes performances dynamiques de la filière GaN/III-V et la grande densité d’intégration de la technologie Si dans le même circuit constitue une avancée importante avec un potentiel d’impact majeur pour ces deux filières technologiques. L’objectif ciblé par cette nouvelle technologie est la réalisation, sur substrat Si, d’un circuit à base d’hétérostructures GaN de haute performance assurant entre autres, la détection ou l’amplification du signal via des composants III-V tandis que la partie traitement du signal sera réalisée par les circuits CMOS Si. Ce projet de recherche de doctorat s’inscrit directement dans le cadre de l’intégration monolithique d’une technologie HEMT (High Electron Mobility Transistor) à base de matériaux GaN sur CMOS. L’objectif est de développer des architectures compatibles avec la stratégie d’intégration monolithique de transistors HEMTs GaN sur Si, en prenant en compte les exigences des différentes filières, circuits CMOS et croissance/fabrication de structures HEMTs GaN.

碩士
國立清華大學
電子工程研究所
102
In this thesis, we used TCAD for fitting AlGaN/GaN heterojunction Transmission Line Model (TLM) I-V characteristics. A physics-based model of self-heating is included in TCAD simulations to investigate the internal device behavior. A dual metal Schottky Barrier Diode (SBD) is also simulated with the constructed models. The fitting errors of less than ±10% for DC I-V characteristics in both cases have been achieved. Another topic of this thesis is to design a normally-off p-GaN MOS-HEMT. A p-GaN MOS-HEMT with Al2O3 as the gate dielectric can significantly reduce the gate leakage current and achieve normally-off operation. To build the best performing device we optimized the channel length and doping concentration of the p-GaN. A p-GaN MOS-HEMT performance can also be improved by adding an i-GaN layer as the channel layer. Compared with a p-GaN MOS-HEMT, the i-GaN layer design reduced the threshold voltage and increased the saturation current. The i-GaN channel MOS-HEMT with a channel length of 0.4µm and a gate-drain length of 10µm shows a specific on-resistance as low as 3.7mΩ•cm2. The channel region resistance is 0.41mΩ•cm2 which contributes about 11% of the total resistance. The largest part of the total resistance is 1.75mΩ•cm2 from the gate-drain distance and it contributes about 47%.

Thesis (M.S.) -- University of Tennessee, Knoxville, 2005.
Title from title page screen (viewed on August 31, 2005). Thesis advisor: Syed K. Islam. Document formatted into pages (x, 112 p. : ill. (some col.)). Vita. Includes bibliographical references (p. 108-110).

碩士
龍華科技大學
電子工程系碩士班
103
Gallium nitride compared with other materials has the advantage with wide bandgap, high breakdown electric field and high electron saturation velocity, etc. Gallium nitride is a good material for high power, high frequency and optics applications. Metal semiconductor junction high electron mobility transistor can't effectively suppress gate leakage current in high bias due to its limited barrier height properties. Therefore, we adopt metal oxide semiconductor structure high electron mobility transistors to reduce gate leakage and surface states density. In this thesis, we proposed in-situ silicon nitride as gate dielectric layer, and changed deposition conditions of silicon nitride to investigate the variety of deposition conditions of silicon nitride thin film for effect of device performance. Conventionally AlGaN/GaN HEMT device which operating mode is the depletion mode. Depletion mode of device for circuit design has high complexity and fail-safe problem in high power operation. For this reason, there are some methods to make device in enhancement mode. In this thesis, we proposed charge trapping method to confine electrons in the charge storage layer, to change space charge of device, so that threshold voltage toward positive voltage shift.

碩士
國立交通大學
光電系統研究所
103
In recent years, AlGaN/GaN high electron mobility transistors (HEMTs) have been widely studied for high power applications. However their performance and reliability are limited by the gate leakage current and drain current degradation. The utilization of insulator to form metal-oxide-semiconductor (M-O-S) gate structures has shown remarkable improvements in reducing gate leakage current and suppressing current degradation. In this study, we developed two kinds of MOS-HEMTs by using HfO2 and La2O3/HfO2 stacks to compare the electric properties with conventional HEMT. The gate leakage current of HfO2 MOS-HEMT and La2O3/HfO2 MOS-HEMT are individually suppressed almost two and four orders of magnitude compared with conventional HEMTs in positive bias region. Moreover, the current degradation of MOS-HEMT with HfO2 (PDA at 500°C) and La2O3/HfO2 (PDA at 600°C) as gate insulator was only decreased 7% and 0.8% (conventional HEMT decreased 21%). Besides, other DC characteristics such as maximum drain current, threshold voltage and transconductance also exhibited good performance in La2O3/HfO2 MOS-HEMT after PDA at 600°C. Furthermore, we obtained good quality of insulator deposition as revealed by the frequency dispersion, hysteresis effect and X-ray Photoelectron Spectroscopy (XPS) analysis in this study.

碩士
逢甲大學
電子工程學系
106
The thesis investigates field-plate-Al2O3-TiO2-dielectric InAlN/AlN/GaN metal-oxide-semiconductor heterostructure Field-effect transistors(MOS-HEMTs) with planar structure by using the ultrasonic spray pyrolysis deposition (USPD) and sputter technique to deposit oxide layer. Due to the enhanced gate control, the DC characteristic of device has been effectively improved. Depositing the high-k aluminum dioxide and titanium dioxide as a gate-dielectric layer, the gate leakage reduced by gate insulation and surface passivation. Providing the comparison of the characteristics, In this thesis, schottky -HEMT, Al2O3-MOS-HEMT, TiO2-MOS-HEMT, FP-Al2O3-TiO2-MOS- HEMT, and FP-TiO2-Al2O3-MOS-HEMT MOS Fin-HEMT have been achieved, including maximum drain-source saturation current density (IDS, max) of 544.2 mA/mm, 810.4 mA/mm, 815.7 mA/mm, 858.2 mA/mm, and 868.3 mA/mm, drain-source current density at VGS = 0 V (IDSS0) of 291.1 mA/mm, 331.3 mA/mm, 256.3 mA/mm, 650.3 mA/mm, and 670.4 mA/mm, maximum extrinsic transconductance (gm, max) of 212.2 mS/mm, 180.4 mS/mm, 194.7 mS/mm, 209 mS/mm and 210.1 mS/mm, gate leakage current (Ig) at VGS = -10 V of sample A to sample E were 1.4×10-2 mA/mm, 1.1×10-6 mA/mm, 4.1×10-3 mA/mm, 4×10-8 mA/mm, and 5.1×10-9 mA/mm, two-terminal off-state gate-drain breakdown voltage (BVGD) of -126 V, -185.5 V, -143.5 V, -232.2 V, and -311.1 V, respectively, at 300 K. From the experiment results, the superior performance of FP-TiO2-Al2O3 metal-oxide-semiconductor HEMTs (MOS-HEMT) can be effectively improve DC characteristics by sputter and USPD technique, and the field plate structure not only decrease leakage current but increase breakdown voltage of device.

碩士
國立成功大學
奈米積體電路工程碩士學位學程
104
This thesis proposes the halogen doping of aluminum oxide (Al2O3) stacked on the e-mode AlGaN/GaN high electron mobility transistors (HEMTs) by using ultrasonic spray pyrolysis deposition (USPD). We found that the doping oxide deposit on the enhancement mode AlGaN/GaN HEMTs can achieve more positive threshold voltage shift. In order to analyze the oxide layer composition, we utilized the atomic force microscopy (AFM), transmission electron microscopy (TEM), electron spectroscopy for chemical analysis (ESCA), and Hall measurement in the research. We observe that the surface roughness is quite uniform by AFM. Then, we confirm that the thickness of oxide layer is 20 nm through TEM. Besides, in ESCA analysis, the results show the oxide layer is exactly Al2O3. In addition, the decreased oxide layer trap density is confirmed by the hysteresis and interface state density. Gate recess, fluorine ion implantation and doping oxide are applied to the fabrication of AlGaN/GaN HEMTs. We found that threshold voltage of doping oxide device can shift to 1.5V, which is more positive 0.3V than only Al2O3 device. In addition, fluorine ion implantation device has larger drain current and reliability than gate recess device. Finally, we propose that the Al2O3 oxide layer applied to metal-oxide-semiconductor MOSHEMT by using ultrasonic spray pyrolysis technique is studied the optimal thickness of the oxide layer is 20 nm. Gate voltage of device can be operated up to 3V and the breakdown voltage is over 180 V. Moreover, threshold voltage of device with doping oxide achieves 25 % positive shift. Therefore, the device which deposited Al2O3 on AlGaN/GaN HEMTs by using ultrasonic spray pyrolysis technique with halogen doping is suitable for modulate threshold voltage and reduce gate leakage.

碩士
國立交通大學
國際半導體產業學院
107
With multiple outstanding material properties such as wide band gap, high electron mobility, high breakdown field, GaN has been widely used in in industry for high power applications. GaN is used to fabricate high electron mobility transistor, which is a D-mode device. One way to achieve E-mode operation is to add p-GaN layer above the AlGaN layer, which we called p-GaN HEMT. And for p-GaN HEMT, one main problem is its gate leakage current. In this study, the use of Metal-Oxide-Semiconductor structure is to solve the problem of gate leakage current and increase the threshold voltage. This study will start from introducing the process flow of p-GaN HEMT, p-GaN MOS-HEMT, and MOS capacitor. Next, we will explain why and which kind of oxide we had selected. Then, we will introduce some possible process flow and our process flow selection, explaining why we choose self-aligned etching process. After that, we successfully fabricated p-GaN MOS-HEMT with low gate leakage current and high threshold voltage. The comparison between p-GaN HEMT and p-GaN MOS-HEMT is also included. Finally, the oxide quality was identified by C-V measurement. This study proved that MOS structure is suitable for p-GaN HEMT device and can effectively suppress the gate leakage current and increase the threshold voltage.

碩士
逢甲大學
電子工程學系
103
The thesis investigates MgO-dielectric GaN/AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) by using the ultrasonic spray pyrolysis deposition (USPD) technique. Due to the enhanced gate insulation and surface passivation, the gate leakage current has been effectively reduced by depositing the high-k magnesium dioxide (MgO) as the gate dielectric layer. Improved device performances of the studied MgO-dielectric MOS-HEMT (a referenced Schottky-gate HEMT) have been achieved, including maximum drain-source saturation current density (IDS, max) of 681 (500) mA/mm, drain-source current density at VGS = 0 V (IDSS0) of 329 (289) mA/mm, maximum extrinsic transconductance (gm, max) of 112 (120) mS/mm, reduced gate leakage current (Ig) at VGS = -50 V of 3.73 × 10-5 (6.85 × 10-3) mA/mm, and two-terminal off-state gate-drain breakdown voltage (BVGD) of -123 (-104) V, respectively, at 300 K. Consequently, superior performance of the present MOS-HEMT has been successfully achieved in this thesis. High-k MgO MOS-gate structure has been obtained by using the cost-effective USPD technique. The present MOS-HEMT device can be promisingly applied to high-frequency RFIC technologies.