Relevant bibliographies by topics / MOS-HEMT

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'MOS-HEMT'

Author: Grafiati
Published: 25 January 2025

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Journal articles on the topic "MOS-HEMT"

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Chen, Yuan-Ming, Hsien-Cheng Lin, Kuan-Wei Lee, and Yeong-Her Wang. "Inverted-Type InAlAs/InAs High-Electron-Mobility Transistor with Liquid Phase Oxidized InAlAs as Gate Insulator." Materials 14, no. 4 (February 18, 2021): 970. http://dx.doi.org/10.3390/ma14040970.

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An inverted-type InAlAs/InAs metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) with liquid phase oxidized (LPO) InAlAs as the gate insulator is demonstrated. A thin InAs layer is inserted in the sub-channel layers of InGaAs to enhance the device performance. The proposed inverted-type InAlAs/InAs MOS-HEMT exhibits an improved maximum drain current density, higher transconductance, lower leakage current density, suppressed noise figures, and enhanced associated gain compared to the conventional Schottky-gate HEMT. Employing LPO to generate MOS structure improves the surface states and enhances the energy barrier. These results reveal that the proposed inverted-type InAlAs/InAs MOS-HEMT can provide an alternative option for device applications.
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Mazumder, Soumen, Parthasarathi Pal, Kuan-Wei Lee, and Yeong-Her Wang. "Remarkable Reduction in IG with an Explicit Investigation of the Leakage Conduction Mechanisms in a Dual Surface-Modified Al2O3/SiO2 Stack Layer AlGaN/GaN MOS-HEMT." Materials 15, no. 24 (December 19, 2022): 9067. http://dx.doi.org/10.3390/ma15249067.

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We demonstrated the performance of an Al2O3/SiO2 stack layer AlGaN/GaN metal–oxide semiconductor (MOS) high-electron-mobility transistor (HEMT) combined with a dual surface treatment that used tetramethylammonium hydroxide (TMAH) and hydrochloric acid (HCl) with post-gate annealing (PGA) modulation at 400 °C for 10 min. A remarkable reduction in the reverse gate leakage current (IG) up to 1.5×10−12 A/mm (@ VG = −12 V) was observed in the stack layer MOS-HEMT due to the combined treatment. The performance of the dual surface-treated MOS–HEMT was significantly improved, particularly in terms of hysteresis, gate leakage, and subthreshold characteristics, with optimized gate annealing treatment. In addition, an organized gate leakage conduction mechanism in the AlGaN/GaN MOS–HEMT with the Al2O3/SiO2 stack gate dielectric layer was investigated before and after gate annealing treatment and compared with the conventional Schottky gate. The conduction mechanism in the reverse gate bias was Poole–Frankel emission for the Schottky-gate HEMT and the MOS–HEMT before annealing. The dominant conduction mechanism was ohmic/Poole-Frankel at low/medium forward bias. Meanwhile, gate leakage was governed by the hopping conduction mechanism in the MOS–HEMT without gate annealing modulation at a higher forward bias. After post-gate annealing (PGA) treatment, however, the leakage conduction mechanism was dominated by trap-assisted tunneling at the low to medium forward bias region and by Fowler–Nordheim tunneling at the higher forward bias region. Moreover, a decent product of maximum oscillation frequency and gate length (fmax × LG) was found to reach 27.16 GHz∙µm for the stack layer MOS–HEMT with PGA modulation. The dual surface-treated Al2O3/SiO2 stack layer MOS–HEMT with PGA modulation exhibited decent performance with an IDMAX of 720 mA/mm, a peak extrinsic transconductance (GMMAX) of 120 mS/mm, a threshold voltage (VTH) of −4.8 V, a higher ION/IOFF ratio of approximately 1.2×109, a subthreshold swing of 82 mV/dec, and a cutoff frequency(ft)/maximum frequency of (fmax) of 7.5/13.58 GHz.
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Tsai, Jung-Hui, Jing-Shiuan Niu, Xin-Yi Huang, and Wen-Chau Liu. "Comparative Investigation of AlGaN/AlN/GaN High Electron Mobility Transistors with Pd/GaN and Pd/Al2O3/GaN Gate Structures." Science of Advanced Materials 13, no. 2 (February 1, 2021): 289–93. http://dx.doi.org/10.1166/sam.2021.3856.

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In this article, the electrical characteristics of Al0.28Ga0.72 N/AlN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) with a 20-nm-thick Al2O3 layer by using radio-frequency sputtering as the gate dielectric layer are compared to the conventional metal-semiconductor HEMT (MS-HEMT) with Pd/GaN gate structure. For the insertion of the Al2O3 layer, the energy band near the AlN/GaN heterojunction is lifted slightly up and the 2DEG at the heterojunction is reduced to shift the threshold voltage to the right side. Experimental results exhibits that though the maximum drain current decreases about 6.5%, the maximum transconductance increases of 9%, and the gate leakage current significantly reduces about five orders of magnitude for the MOS-HEMT than the MS-HEMT.
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ALOMARI, M., F. MEDJDOUB, E. KOHN, M.-A. DI FORTE-POISSON, S. DELAGE, J. F. CARLIN, N. GRANDJEAN, and C. GAQUIÈRE. "InAlN/GaN MOS-HEMT WITH THERMALLY GROWN OXIDE." International Journal of High Speed Electronics and Systems 19, no. 01 (March 2009): 137–44. http://dx.doi.org/10.1142/s0129156409006187.

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We report on the investigation of lattice matched InAlN / GaN MOS-HEMT structures prepared by thermal oxidation at 800 °C in oxygen atmosphere for two minutes. The gate leakage current was reduced by two orders of magnitude. Pulse measurements showed lag effects similar to what is observed for devices without oxidation, indicating a high quality native oxide. The MOS-HEMT showed no degradation in the small signal characteristics and yielded a power density of 5 W/mm at 30 V drain voltage at 10 GHz, power added efficiency of 42% and Ft and Fmax of 42 and 61 GHz respectively, illustrating the capability of such MOS-HEMT to operate at high frequencies.
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Perina, Welder, Joao Martino, and Paula Agopian. "(Digital Presentation) Analysis of MIS-HEMT Kink Effect in Saturation Region." ECS Transactions 111, no. 1 (May 19, 2023): 297–302. http://dx.doi.org/10.1149/11101.0297ecst.

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In this work, the Metal-Insulator-Semiconductor High Electron Mobility Transistor (MIS-HEMT) behavior in saturation region was analyzed and compared with a GaN MOSFET. The MIS-HEMT presents a current level about 30 times higher than GaN MOSFET, for the same bias conditions. The different saturation points (VDS sat) of the MOS and HEMT conductions is responsible for the appearance of a kink in the drain current (IDS) current as a function of drain voltage (VDS) curve. The output conductance (gD) of the MOSFET presented a strong dependence on VGT, while the MIS-HEMT only a slightly dependence was observed. The MIS-HEMT kink effect (MH kink) was defined by the drain voltage where the bump occurs. The MH kink only occurs for a high enough gate bias to enable the MOS conduction, and MH kink value increases with the gate voltage overdrive (VGT) and its variation tends to saturate for VGT higher than 3,5V.
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Yang, Shun-Kai, Soumen Mazumder, Zhan-Gao Wu, and Yeong-Her Wang. "Performance Enhancement in N2 Plasma Modified AlGaN/AlN/GaN MOS-HEMT Using HfAlOX Gate Dielectric with Γ-Shaped Gate Engineering." Materials 14, no. 6 (March 21, 2021): 1534. http://dx.doi.org/10.3390/ma14061534.

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In this paper, we have demonstrated the optimized device performance in the Γ-shaped gate AlGaN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) by incorporating aluminum into atomic layer deposited (ALD) HfO2 and comparing it with the commonly used HfO2 gate dielectric with the N2 surface plasma treatment. The inclusion of Al in the HfO2 increased the crystalline temperature (~1000 °C) of hafnium aluminate (HfAlOX) and kept the material in the amorphous stage even at very high annealing temperature (>800 °C), which subsequently improved the device performance. The gate leakage current (IG) was significantly reduced with the increasing post deposition annealing (PDA) temperature from 300 to 600 °C in HfAlOX-based MOS-HEMT, compared to the HfO2-based device. In comparison with HfO2 gate dielectric, the interface state density (Dit) can be reduced significantly using HfAlOX due to the effective passivation of the dangling bond. The greater band offset of the HfAlOX than HfO2 reduces the tunneling current through the gate dielectric at room temperature (RT), which resulted in the lower IG in Γ-gate HfAlOX MOS-HEMT. Moreover, IG was reduced more than one order of magnitude in HfAlOX MOS-HEMT by the N2 surface plasma treatment, due to reduction of N2 vacancies which were created by ICP dry etching. The N2 plasma treated Γ-shaped gate HfAlOX-based MOS-HEMT exhibited a decent performance with IDMAX of 870 mA/mm, GMMAX of 118 mS/mm, threshold voltage (VTH) of −3.55 V, higher ION/IOFF ratio of approximately 1.8 × 109, subthreshold slope (SS) of 90 mV/dec, and a high VBR of 195 V with reduced gate leakage current of 1.3 × 10−10 A/mm.
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Huang, Cheng-Yu, Soumen Mazumder, Pu-Chou Lin, Kuan-Wei Lee, and Yeong-Her Wang. "Improved Electrical Characteristics of AlGaN/GaN High-Electron-Mobility Transistor with Al2O3/ZrO2 Stacked Gate Dielectrics." Materials 15, no. 19 (October 5, 2022): 6895. http://dx.doi.org/10.3390/ma15196895.

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A metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) is proposed based on using a Al2O3/ZrO2 stacked layer on conventional AlGaN/GaN HEMT to suppress the gate leakage current, decrease flicker noise, increase high-frequency performance, improve power performance, and enhance the stability after thermal stress or time stress. The MOS-HEMT has a maximum drain current density of 847 mA/mm and peak transconductance of 181 mS/mm. The corresponding subthreshold swing and on/off ratio are 95 mV/dec and 3.3 × 107. The gate leakage current can be reduced by three orders of magnitude due to the Al2O3/ZrO2 stacked layer, which also contributes to the lower flicker noise. The temperature-dependent degradation of drain current density is 26%, which is smaller than the 47% of reference HEMT. The variation of subthreshold characteristics caused by thermal or time stress is smaller than that of the reference case, showing the proposed Al2O3/ZrO2 stacked gate dielectrics are reliable for device applications.
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Mazumder, Soumen, Ssu-Hsien Li, Zhan-Gao Wu, and Yeong-Her Wang. "Combined Implications of UV/O3 Interface Modulation with HfSiOX Surface Passivation on AlGaN/AlN/GaN MOS-HEMT." Crystals 11, no. 2 (January 28, 2021): 136. http://dx.doi.org/10.3390/cryst11020136.

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Surface passivation is critically important to improve the current collapse and the overall device performance in metal-oxide semiconductor high-electron mobility transistors (MOS-HEMTs) and, thus, their reliability. In this paper, we demonstrate the surface passivation effects in AlGaN/AlN/GaN-based MOS-HEMTs using ultraviolet-ozone (UV/O3) plasma treatment prior to SiO2 -gate dielectric deposition. X-ray photoelectron spectroscopy (XPS) was used to verify the improved passivation of the GaN surface. The threshold voltage (VTH) of the MOS-HEMT was shifted towards positive due to the band bending at the SiO2/GaN interface by UV/O3 surface treatment. In addition, the device performance, especially the current collapse, hysteresis, and 1/f characteristics, was further significantly improved with an additional 15 nm thick hafnium silicate (HfSiOX) passivation layer after the gate metallization. Due to combined effects of the UV/O3 plasma treatment and HfSiOX surface passivation, the magnitude of the interface trap density was effectively reduced, which further improved the current collapse significantly in SiO2-MOS-HEMT to 0.6% from 10%. The UV/O3-surface-modified, HfSiOX-passivated MOS-HEMT exhibited a decent performance, with IDMAX of 655 mA/mm, GMMAX of 116 mS/mm, higher ION/IOFF ratio of approximately 107, and subthreshold swing of 85 mV/dec with significantly reduced gate leakage current (IG) of 9.1 ×10−10 A/mm.
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Driss Bouguenna, Abbès Beloufa, Khaled Hebali, and Sajad Ahmad Loan. "Investigation of the Electrical Characteristics of AlGaN/AlN/GaN Heterostructure MOS-HEMTs with TiO2 High-k Gate Insulator." International Journal of Nanoelectronics and Materials (IJNeaM) 16, no. 3 (October 22, 2024): 607–20. http://dx.doi.org/10.58915/ijneam.v16i3.1325.

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This paper investigates the impact of TiO2 high-k gate insulator on the electrical characteristics of AlGaN/AlN/GaN MOS-HEMT transistors using MATLAB and Atlas-TCAD simulation software. The physical analytical model of the MOS-HEMTs is used for simulation from Al2O3, HfO2, and TiO2 as the gate dielectric materials, which provide higher performance and reliability of the MOS-HEMT devices. The device shows a good improvement in its result of the DC and AC characteristics with different permittivity of insulator materials. Thus, the DC and AC performance of GaN MOS-HEMTs is higher than with other insulators, such as Al2O3 and HfO2 by using TiO2 as the gate dielectric. Moreover, the simulation results proved that TiO2 is the better gate dielectric material to enhance the electrical reliability of the power switching devices for high-temperature applications such as electric automobiles.
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Cho, Seong-Kun, and Won-Ju Cho. "High-Sensitivity pH Sensor Based on Coplanar Gate AlGaN/GaN Metal-Oxide-Semiconductor High Electron Mobility Transistor." Chemosensors 9, no. 3 (February 25, 2021): 42. http://dx.doi.org/10.3390/chemosensors9030042.

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The sensitivity of conventional ion-sensitive field-effect transistors is limited to the Nernst limit (59.14 mV/pH). In this study, we developed a pH sensor platform based on a coplanar gate AlGaN/GaN metal-oxide-semiconductor (MOS) high electron mobility transistor (HEMT) using the resistive coupling effect to overcome the Nernst limit. For resistive coupling, a coplanar gate comprising a control gate (CG) and a sensing gate (SG) was designed. We investigated the amplification of the pH sensitivity with the change in the magnitude of a resistance connected in series to each CG and SG via Silvaco TCAD simulations. In addition, a disposable extended gate was applied as a cost-effective sensor platform that helped prevent damages due to direct exposure of the AlGaN/GaN MOS HEMT to chemical solutions. The pH sensor based on the coplanar gate AlGaN/GaN MOS HEMT exhibited a pH sensitivity considerably higher than the Nernst limit, dependent on the ratio of the series resistance connected to the CG and SG, as well as excellent reliability and stability with non-ideal behavior. The pH sensor developed in this study is expected to be readily integrated with wide transmission bandwidth, high temperature, and high-power electronics as a highly sensitive biosensor platform.
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Dissertations / Theses on the topic "MOS-HEMT"

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Piotrowicz, Clémentine. "Etude de l'influence de l'architecture des MOS-HEMT GaN de puissance à grille enterrée sur les propriétés physiques et les performances électriques des composants." Electronic Thesis or Diss., Bordeaux, 2024. http://www.theses.fr/2024BORD0269.

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L’architecture latérale MOS-HEMT à grille gravée en nitrure de gallium (GaN), en cours de développement au CEA-Leti sur des substrat silicium de 200mm, vise à répondre aux besoins croissants d’électrification dans un contexte de forte demande pour des convertisseurs de puissance moyenne-haute tension (>200V). Les applications ciblées, incluent les chargeurs de téléphones, d'ordinateurs portables, les chargeurs embarqués pour les véhicules électriques, les micro-onduleurs photovoltaïques, etc., qui nécessitent des convertisseurs de meilleur rendement que ceux actuellement basés sur la technologie silicium. L’objectif de cette thèse, est d’étudier l'influence de l'architecture MOS-HEMT sur les propriétés physiques et les performances électriques. L’accent est mis sur l’optimisation de la résistance à l’état-passant des transistors (RON), qui est envisagée dans une perspective globale afin de maintenir les propriétés de blocage (RON/BV), et le comportement « normally-off » des composants (RON/VTH). Deux axes majeurs sont étudiés. Le premier concerne la résistance du canal de grille qui dépend de la gravure, qui elle-même joue sur la morphologie, et sur les mobilités du canal, auxquelles s’ajoute la contribution de la qualité de l’interface diélectrique/GaN (µ≤ 250cm2.V−1.s−1). Des variantes de cette morphologie de grille tels que l’angle (90° à 60°), la profondeur (50nm à 350nm), l’orientation cristallographique du canal, ainsi que l'impact des procédés de fabrication (ICP-RIE, ALE, nettoyage), ont été étudiées via des mesures électriques IDS(VG), C(VG), IDS(VDS) en blocage, puis simulées et modélisées sous TCAD. Une méthode d'extraction des contributions de mobilité autour de la grille a été proposée, et montre une meilleure mobilité du fond de la grille (≤190 cm2.V−1.s−1 à 25°C) comparée à celle liée aux flancs (≤ 93 cm2.V−1.s−1 à 25°C). De plus des corrélations entre les paramètres électriques (RON, VTH, SS) et le design ont été établies, et montrent un meilleur compromis RON/fuites de grille/source en régime bloqué à forte tension de drain, avec une profondeur de gravure intermédiaire de 150nm pour une longueur de grille de 0.5µm (RON=8.1Ω.mm à 25°C et 15.2 Ω.mm à 150°C). Le second axe porte sur la résistance des accès du transistor, liée aux propriétés de l’hétérojonction AlGaN/AlN/GaN et aux mécanismes de polarisation à l’origine du gaz d’électrons 2D à l’interface AlN/GaN (2DEG). Plusieurs variantes technologiques de l’hétérojonction incluant l’épaisseur de la couche AlN (0.7nm à 1.5nm), de la barrière AlGaN (7nm à 24nm), le pourcentage d’aluminium (24% à 60%), et le dopage, ont été caractérisées électriquement par des mesures 5 pointes I(VG) et C(VG) sur des structures Pan der Pauw à 25°C et 150°C. Des simulations Poisson-Schrödinger 1D ont également permis d’évaluer la charge d’interface de polarisation et de d’identifier les leviers d’amélioration de cette résistance 2DEG. Une valeur minimale de 213Ω/◻ été obtenue à 25°C pour le pourcentage de 60% d’aluminium (µ=1591 cm2.V−1.s−1 et nS =18.3×1012cm−2) et de 455 Ω/◻ à 150°C (µ=774 cm2.V−1.s−1 et nS =17.7×1012 cm−2), réduisant le RON de 2.1Ω.mm à 150°C. En conclusion, les résultats de cette thèse ouvrent la voie à de nouvelles perspectives pour les futures générations de transistors GaN, tant en termes d'optimisation des performances que d'amélioration des procédés de fabrication
The lateral MOS-HEMT architecture with etched gate ("normally-off") in gallium nitride (GaN), currently under development at CEA-Leti on 200mm silicon substrates, aims to meet the growing electrification needs in response to the high demand for medium-to-high voltage power converters (>200V). The targeted applications include phone chargers, laptop chargers, onboard chargers for electric vehicles, photovoltaic micro-inverters, etc., which require more efficient converters than those currently based on silicon technology. The objective of this thesis is to study the influence of the MOS-HEMT architecture on the physical properties and electrical performance. The focus is on optimizing the on-state resistance of the transistors (RON), with a global perspective on maintaining blocking properties (RON/BV) and the "normally-off" behavior of the components (RON/VTH). Two main areas are studied. The first concerns the gate channel resistance, which depends on the etching, influencing the morphology and the channel mobility, along with the contribution of the dielectric/GaN interface quality (µ≤ 250 cm2.V−1.s−1). Variations in gate morphology, such as angle (90° to 60°), depth (50nm to 350nm), channel crystallographic orientation, and the impact of fabrication processes (ICP-RIE, ALE, cleaning) were studied through electrical measurements IDS(VG), C(VG), IDS(VDS) in blocking mode, and were then simulated and modeled using TCAD. A mobility extraction method around the gate was proposed, showing better mobility at the bottom of the gate (≤190 cm2.V−1.s−1 at 25°C) compared to the sidewalls (≤ 93 cm2.V−1.s−1 at 25°C). Additionally, correlations between electrical parameters (RON, VTH, SS) and design were established, showing a better RON/leakage compromise with an intermediate etching depth of 150nm and a gate length of 0.5µm (RON=8.1Ω.mm at 25°C and 15.2 Ω.mm at 150°C). The second area focuses on the transistor's access resistance, linked to the properties of the AlGaN/AlN/GaN heterojunction and polarization mechanisms responsible for the 2D electron gas (2DEG) at the AlN/GaN interface. Several technological variations of the heterojunction, including the AlN layer thickness (0.7nm to 1.5nm), AlGaN barrier (7nm to 24nm), aluminum percentage (24% to 60%), and doping, were electrically characterized using 5-point I(VG) and C(VG) measurements on Van der Pauw structures at 25°C and 150°C. 1D Poisson-Schrödinger simulations were also used to assess the interface polarization charge and identify improvement levers for this 2DEG resistance. A minimum value of 213Ω/◻ was obtained at 25°C for 60% aluminum (µ=1591 cm2.V−1.s−1 and nS =18.3×1012cm−2) and 455Ω/◻ at 150°C (µ=774 cm2.V−1.s−1 and nS = nS =17.7×1012cm−2), reducing RON by 2.1Ω.mm at 150°C. In conclusion, the results of this thesis open up new perspectives for future generations of GaN transistors, both in terms of performance optimization and manufacturing process improvements
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Malela-Massamba, Ephrem. "Développement et caractérisation de modules Technologiques sur semiconducteur GaN : application à la réalisation de cathodes froides et de transistor HEMT AlGaN/GAN." Thesis, Lyon, 2016. http://www.theses.fr/2016LYSE1078.

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Les travaux présentés dans ce manuscrit sont axés sur le développement et la caractérisation de modules technologiques sur semiconducteurs à large bande interdite à base de nitrure de gallium (GaN), pour la réalisation de transistors et de cathodes froides. Ils ont été réalisés au sein du laboratoire III-V lab, commun aux entités : Alcatel - Thales - CEA Leti. Notre projet de recherche a bénéficié d'un soutien financier assuré par Thales Electron Devices (TED) et l'Agence Nationale de la Recherche ( ANR ). Concernant les transistors HEMT III-N, nos investigations se sont focalisées sur le développement des parties actives des transistors, incluant principalement la structuration des électrodes de grilles, l'étude de la passivation des grilles métalliques, ainsi que l'étude de diélectriques de grille pour la réalisation de structures MIS-HEMT.Les transistors MOS-HEMT « Normally-off » réalisés présentent des performances comparables à l'état de l'art, avec une densité de courant de drain maximum comprise entre 270 mA et 400 mA / mm, un ratio ION / IOFF > 1100, et des tensions de claquage > 200V. Les tensions de seuil sont comprises entre + 1,8 V et + 4 V. Nos contributions au développement des cathodes froides ont permis de démontrer une première émission dans le vide à partir de cathodes GaN, avec une densité de courant maximale de 300 µA / cm2 pour une tension de polarisation de 40 V
The results presented in this manuscript relate to technological developments and device processing on wide bandgap III-N semiconductor materials. They have been focused on III-N HEMT transistors and GaN cold cathodes. They have been realised within the III-V lab, which is a common entity between: Alcatel - Thales - CEA Leti. They have been financially supported by Thales Electron Devices company (TED) and the French National Research Agency ( ANR ). Regarding III-N HEMTs, our investigations have been focused on the development of device gate processing, which includes : the structuration of gate electrodes, the study of device passivation, and the realization of Metal-Insulator-Semiconductor High Mobility Electron Transistors ( MIS-HEMTs ). The “ Normally-off ” MOS-HEMT structures we have realized exhibit performances comparable to the state of the art, with a maximum drain current density between 270 and 400 mA / mm, a ION / IOFF ratio > 1.100, and a breakdown voltage > 200V. The threshold voltage values range between + 1,8 V and + 4V. We have also been able to demonstrate prototype GaN cold cathodes providing a maximum current density of 300 µA / cm2, emitted in vacuum for a bias voltage around 40 V
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Comyn, Rémi. "Développement de briques technologiques pour la co-intégration par l'épitaxie de transistors HEMTs AlGaN/GaN sur MOS silicium." Thesis, Université Côte d'Azur (ComUE), 2016. http://www.theses.fr/2016AZUR4098.

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L’intégration monolithique hétérogène de composants III-N sur silicium (Si) offre de nombreuses possibilités en termes d’applications. Cependant, gérer l’hétéroépitaxie de matériaux à paramètres de maille et coefficients de dilatation très différents, tout en évitant les contaminations, et concilier des températures optimales de procédé parfois très éloignées requière inévitablement certains compromis. Dans ce contexte, nous avons cherché à intégrer des transistors à haute mobilité électronique (HEMT) à base de nitrure de Gallium (GaN) sur substrat Si par épitaxie sous jets moléculaires (EJM) en vue de réaliser des circuits monolithiques GaN sur CMOS Si
The monolithic integration of heterogeneous devices and materials such as III-N compounds with silicon (Si) CMOS technology paves the way for new circuits applications and capabilities for both technologies. However, the heteroepitaxy of such materials on Si can be challenging due to very different lattice parameters and thermal expansion coefficients. In addition, contamination issues and thermal budget constraints on CMOS technology may prevent the use of standard process parameters and require various manufacturing trade-offs. In this context, we have investigated the integration of GaN-based high electron mobility transistors (HEMTs) on Si substrates in view of the monolithic integration of GaN on CMOS circuits
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Trinh, Xuan Linh. "Fonction normally-on, normally-off compatible de la technologie HEMT GaN pour des applications de puissance, hyperfréquences." Thesis, Limoges, 2018. http://www.theses.fr/2018LIMO0106/document.

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Ce document présente les travaux de thèse ayant pour objet la recherche et développement d’une technologie co-intégrée HEMT GaN normale-on/normally-off compatible avec les matériaux et procédés technologiques de la technologie normally-on hyperfréquence. Un exposé théorique et une revue de l’état de l’art permettent d’abord d’entrevoir les différentes solutions technologiques qui s’offrent à nous, tout en affirmant et en précisant les applications visées. Différentes briques technologiques sont ensuite développées pour la fabrication de MOS-HEMTs GaN à recess de grille sur des épi-structures à barrière AlGaN ou (Ga)InAlN dédiées aux applications hyperfréquences. Nous insistons sur la possibilité d’intégrer les 2 fonctionnalités normally-off et normally-on de manière monolithique. Les échantillons ainsi réalisés sont ensuite caractérisés électriquement de manière conventionnelle, mais aussi en utilisant des techniques avancées de spectroscopie de pièges comme les paramètres S à basse fréquence et la mesure du transitoire de RON. Bien que certains phénomènes de piègeage dans l’oxyde de grille soient mis en évidence, les résultats sont très satisfaisants : des composants normally-off sont obtenus pour les 2 structures, et les performances sont au niveau de l’état de l’art mondial, avec plusieurs pistes d’amélioration en perspective
This document reports on research and development efforts towards a normally-on/normally-off integrated GaN HEMT technology that remains compatible with the material and processing dedicated to normally-on microwave devices. Following several theoretical considerations, the state-of-the-art is presented, which gives a perspective on the available technological solutions and helps define the specifications and the targeted applications. The development and optimization of new process steps enables the fabrication of gate-recessed MOS-HEMTs on epi-structures with AlGaN or (Ga)InAlN barrier, monolithically integrable with normally-on transistors. The samples are electrically characterized by means of standard measurements and more advanced trap spectroscopy techniques such as low-frequency S-parameters or RON transient monitoring. In spite of oxide-related trapping phenomena, the results are very promising: normally-off devices are obtained for both structures, and the performances are in line with literature accounts while identified possible improvements can be explored
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5

ISLAM, MD SHAHRUL. "Can Asymmetry Quench Self-Heating in MOS High Electron Mobility Transistors?" OpenSIUC, 2020. https://opensiuc.lib.siu.edu/theses/2736.

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High electron mobility transistors (HEMTs) have long been studied for high frequency and high-power application. Among widely known high electron mobility transistors, AlGaN/GaN HEMTs are having the upper hand due to high electron mobility of the GaN channel. Over the times, issues like current collapse, gate leakage, self-heating and gate lag have questioned the performance and reliability of these devices. In the recent years, engineers have come up with newer architectures to address some of these issues. Inserting a high-k dielectric oxide layer in the gate stack proved to be an effective solution to mitigate gate leakage, reduce interfacial traps and improve optimal working conditions. This work aims to study the reliability aspect of these so-called metal-oxide-semiconductor high electron mobility transistors (MOS-HEMT) specifically, HfO2 and HfZrO2 MOS-HEMTs. It was found through numerical simulations that though HfO2 and HfZrO2 dielectrics were able to mitigate gate leakage current, they tend to accumulate more heat in the channel region with respect to the conventional silicon nitride (SiN) passivated counterparts. Moreover, few asymmetric structures were proposed where silicon nitride was placed in the dielectric layer along with HfO2/HfZrO2. In this study it was found that these asymmetric structures showed superior thermal performance while showing near-zero gate leakage current.
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6

Comyn, Rémi. "Développement de briques technologiques pour la co-intégration par l’épitaxie de transistors HEMTs AlGaN/GaN sur MOS silicium." Thèse, Université de Sherbrooke, 2016. http://hdl.handle.net/11143/9891.

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Dans le domaine des semi-conducteurs, la technologie silicium (principalement l’architecture CMOS) répond à la majorité des besoins du marché et, de ce fait, elle est abondamment utilisée. Ce semi-conducteur profite d’une part, de son abondance dans la nature et par conséquent de son faible coût, et d’autre part de la grande maturité de sa technologie qui est étudiée depuis un demi-siècle. Cependant, le silicium (Si) souffre de plus en plus de ses propriétés électriques limitées qui l’excluent de certains domaines dans lesquels les technologies à base de matériaux III-V sont les plus utilisées. Bien que la technologie à base de matériaux III-V, notamment les hétérostructures à base de nitrure de gallium (GaN), soit très performante par rapport à celle à base du matériau historique (le silicium), cette nouvelle technologie est toujours limitée aux applications utilisant des circuits de moyennes voire faibles densités d’intégration. Ceci limite l’utilisation de cette technologie pour la réalisation de produits à très grande valeur ajoutée. Pour s’affranchir de cette limitation, plusieurs sujets de recherche ont été entrepris ces dernières années pour intégrer au sein du même circuit des composants à base de silicium et de matériaux III-V. En effet, la possibilité d’allier les bonnes performances dynamiques de la filière GaN/III-V et la grande densité d’intégration de la technologie Si dans le même circuit constitue une avancée importante avec un potentiel d’impact majeur pour ces deux filières technologiques. L’objectif ciblé par cette nouvelle technologie est la réalisation, sur substrat Si, d’un circuit à base d’hétérostructures GaN de haute performance assurant entre autres, la détection ou l’amplification du signal via des composants III-V tandis que la partie traitement du signal sera réalisée par les circuits CMOS Si. Ce projet de recherche de doctorat s’inscrit directement dans le cadre de l’intégration monolithique d’une technologie HEMT (High Electron Mobility Transistor) à base de matériaux GaN sur CMOS. L’objectif est de développer des architectures compatibles avec la stratégie d’intégration monolithique de transistors HEMTs GaN sur Si, en prenant en compte les exigences des différentes filières, circuits CMOS et croissance/fabrication de structures HEMTs GaN.
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Peng, Po-Chin, and 彭柏瑾. "Simulation and Design of P-GaN MOS-HEMT." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/ssw69e.

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碩士
國立清華大學
電子工程研究所
102
In this thesis, we used TCAD for fitting AlGaN/GaN heterojunction Transmission Line Model (TLM) I-V characteristics. A physics-based model of self-heating is included in TCAD simulations to investigate the internal device behavior. A dual metal Schottky Barrier Diode (SBD) is also simulated with the constructed models. The fitting errors of less than ±10% for DC I-V characteristics in both cases have been achieved. Another topic of this thesis is to design a normally-off p-GaN MOS-HEMT. A p-GaN MOS-HEMT with Al2O3 as the gate dielectric can significantly reduce the gate leakage current and achieve normally-off operation. To build the best performing device we optimized the channel length and doping concentration of the p-GaN. A p-GaN MOS-HEMT performance can also be improved by adding an i-GaN layer as the channel layer. Compared with a p-GaN MOS-HEMT, the i-GaN layer design reduced the threshold voltage and increased the saturation current. The i-GaN channel MOS-HEMT with a channel length of 0.4µm and a gate-drain length of 10µm shows a specific on-resistance as low as 3.7mΩ•cm2. The channel region resistance is 0.41mΩ•cm2 which contributes about 11% of the total resistance. The largest part of the total resistance is 1.75mΩ•cm2 from the gate-drain distance and it contributes about 47%.
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Alam, Mohmmad Tanvir. "Analytical modeling and simulation of SiGe MOS gate HEMT." 2005. http://etd.utk.edu/2005/AlamMohmmad.pdf.

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Thesis (M.S.) -- University of Tennessee, Knoxville, 2005.
Title from title page screen (viewed on August 31, 2005). Thesis advisor: Syed K. Islam. Document formatted into pages (x, 112 p. : ill. (some col.)). Vita. Includes bibliographical references (p. 108-110).
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Lai, Sin-Hong, and 賴信宏. "Characteristic Analysis of SiN Gate Dielectric Layer MIS-HEMT Device and Investigation of MOS-HEMT Flash Memory." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/24505796689449958478.

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碩士
龍華科技大學
電子工程系碩士班
103
Gallium nitride compared with other materials has the advantage with wide bandgap, high breakdown electric field and high electron saturation velocity, etc. Gallium nitride is a good material for high power, high frequency and optics applications. Metal semiconductor junction high electron mobility transistor can't effectively suppress gate leakage current in high bias due to its limited barrier height properties. Therefore, we adopt metal oxide semiconductor structure high electron mobility transistors to reduce gate leakage and surface states density. In this thesis, we proposed in-situ silicon nitride as gate dielectric layer, and changed deposition conditions of silicon nitride to investigate the variety of deposition conditions of silicon nitride thin film for effect of device performance. Conventionally AlGaN/GaN HEMT device which operating mode is the depletion mode. Depletion mode of device for circuit design has high complexity and fail-safe problem in high power operation. For this reason, there are some methods to make device in enhancement mode. In this thesis, we proposed charge trapping method to confine electrons in the charge storage layer, to change space charge of device, so that threshold voltage toward positive voltage shift.
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Lan, Wei-Cheng, and 藍偉誠. "The Study of La2O3/HfO2 GaN MOS-HEMT for High Power Application." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/05521736013009704108.

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碩士
國立交通大學
光電系統研究所
103
In recent years, AlGaN/GaN high electron mobility transistors (HEMTs) have been widely studied for high power applications. However their performance and reliability are limited by the gate leakage current and drain current degradation. The utilization of insulator to form metal-oxide-semiconductor (M-O-S) gate structures has shown remarkable improvements in reducing gate leakage current and suppressing current degradation. In this study, we developed two kinds of MOS-HEMTs by using HfO2 and La2O3/HfO2 stacks to compare the electric properties with conventional HEMT. The gate leakage current of HfO2 MOS-HEMT and La2O3/HfO2 MOS-HEMT are individually suppressed almost two and four orders of magnitude compared with conventional HEMTs in positive bias region. Moreover, the current degradation of MOS-HEMT with HfO2 (PDA at 500°C) and La2O3/HfO2 (PDA at 600°C) as gate insulator was only decreased 7% and 0.8% (conventional HEMT decreased 21%). Besides, other DC characteristics such as maximum drain current, threshold voltage and transconductance also exhibited good performance in La2O3/HfO2 MOS-HEMT after PDA at 600°C. Furthermore, we obtained good quality of insulator deposition as revealed by the frequency dispersion, hysteresis effect and X-ray Photoelectron Spectroscopy (XPS) analysis in this study.
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Book chapters on the topic "MOS-HEMT"

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Kundu, Atanu, and Mousiki Kar. "Multigate MOS-HEMT." In HEMT Technology and Applications, 115–27. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2165-0_9.

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Nayak, Amrutamayee, Vandana Kumari, Mridula Gupta, and Manoj Saxena. "Comparative Study of AlGaN/GaN HEMT and MOS-HEMT Under Positive Gate Bias-Induced Stress." In Computers and Devices for Communication, 506–12. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-8366-7_74.

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Amarnath, G., Manisha Guduri, A. Vinod, and M. Kavicharan. "Study of Temperature Effect on MOS-HEMT Small-Signal Parameters." In Lecture Notes in Electrical Engineering, 255–63. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3767-4_24.

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Do, Nguyen-Trung, Nguyen-Hoang Thoan, Tran Minh Quang, Dao Anh Tuan, and Nguyen-Ngoc Trung. "An Analytical Model for AlGaN/GaN MOS-HEMT for High Power Applications." In Springer Proceedings in Materials, 477–85. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-45120-2_39.

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Panda, D. K., and T. R. Lenka. "Device Optimization of E-Mode N-Polar GaN MOS-HEMT for Low Noise RF and Microwave Applications." In Springer Proceedings in Physics, 171–76. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-97604-4_26.

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ALOMARI, M., F. MEDJDOUB, E. KOHN, M. A. DI FORTE-POISSON, S. DELAGE, J. F. CARLIN, N. GRANDJEAN, and C. GAQUIÈRE. "InAlN/GaN MOS-HEMT WITH THERMALLY GROWN OXIDE." In Selected Topics in Electronics and Systems, 137–44. WORLD SCIENTIFIC, 2009. http://dx.doi.org/10.1142/9789814287876_0016.

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Bhargav Peesa, Rohit, Pydimarri Manoj Kumar, and D. K. Panda. "Simulation of GaN MOS-HEMT based bio-sensor for breast cancer detection." In Computer-Aided Developments: Electronics and Communication, 269–74. CRC Press, 2019. http://dx.doi.org/10.1201/9780429340710-31.

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Conference papers on the topic "MOS-HEMT"

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Touati, Zine-eddine, Zahra Hamaizia, and Zitouni Messai. "DC and RF characteristics of AlGaN/GaN HEMT and MOS-HEMT." In 2015 4th International Conference on Electrical Engineering (ICEE). IEEE, 2015. http://dx.doi.org/10.1109/intee.2015.7416850.

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Zhou, Xiuju, Qiang Li, and Kei May Lau. "InAlAs/InGaAs metamorphic HEMT and MOS-HEMT with regrown Source/Drain by MOCVD." In 2011 69th Annual Device Research Conference (DRC). IEEE, 2011. http://dx.doi.org/10.1109/drc.2011.5994437.

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Djelti, Hamida. "The DC behavior of the Al0.25Ga0.75N/GaN MOS-HEMT." In 2016 International Renewable and Sustainable Energy Conference (IRSEC). IEEE, 2016. http://dx.doi.org/10.1109/irsec.2016.7984009.

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Bhat, Aasif Mohammad, Nawaz Shafi, and C. Periasamy. "AlGaN/GaN HEMT AC/DC Performance Analysis of Conventional and Gate Recessed MOS-HEMT With Temperature Variation." In 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech). IEEE, 2019. http://dx.doi.org/10.1109/iementech48150.2019.8981125.

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Kume, Eiji, Hiroyuki Ishii, Hiroyuki Hattori, Wen-Hsin Chang, Mutsuo Ogura, Haruichi Kanaya, Tanemasa Asano, and Tatsuro Maeda. "InAs MOS-HEMT power detector for 1.0 THz on quartz glass." In 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM). IEEE, 2017. http://dx.doi.org/10.1109/edtm.2017.7947562.

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Tseng, Ming-Chun, Ming-Hsien Hung, Dong-Sing Wuu, and Ray-Hua Horng. "Study of interface state trap density on characteristics of MOS-HEMT." In SPIE OPTO, edited by Jen-Inn Chyi, Hiroshi Fujioka, and Hadis Morkoç. SPIE, 2015. http://dx.doi.org/10.1117/12.2076678.

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Mohamad, B., C. Le Royer, F. Rigaud-Minet, C. Piotrowicz, P. Fernandes Paes Pinto Rocha, C. Leurquin, W. Vandendaele, et al. "Deep Insights into Recessed Gate MOS-HEMT Technology for Power Applications." In 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2023. http://dx.doi.org/10.1109/edtm55494.2023.10102971.

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Mukherjee, Hrit, Rajanya Dasgupta, Mousiki Kar, and Atanu Kundu. "A Comparative Analysis of Analog Performances of Underlapped Dual Gate AlGaN/GaN Based MOS-HEMT and Schottky-HEMT." In 2020 IEEE Calcutta Conference (CALCON). IEEE, 2020. http://dx.doi.org/10.1109/calcon49167.2020.9106420.

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Tang, Cen, Gang Xie, and Kuang Sheng. "Enhancement-mode GaN-on-Silicon MOS-HEMT using pure wet etch technique." In 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2015. http://dx.doi.org/10.1109/ispsd.2015.7123432.

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Wu, Jianzhi, Wei Lu, and Paul K. L. Yu. "Normally-OFF AlGaN/GaN MOS-HEMT with a two-step gate recess." In 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2015. http://dx.doi.org/10.1109/edssc.2015.7285184.

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