Dissertations / Theses on the topic 'Module Integrated Converter'

Point-of-load (POL) converters have been used extensively in IT products. Today, almost every microprocessor is powered by a multi-phase POL converter with high output current, which is also known as voltage regulator (VR). In the state-of-the-art VRs, the circuits are mostly constructed with discrete components and situated on the motherboard, where it can occupy more than 1/3 of the footprint of the motherboard. A compact POL is desirable to save precious space on motherboards to be used for some other critical functionalities. Recently, industry has released many modularized POL converters, in which the bulky inductor is integrated with the active components to increase the power density. This concept has been demonstrated at current levels less than 5A and power density around 600-1000W/in3. This might address the needs of small hand-held equipment such as smart phones, but it is far from meeting the needs for the applications such as laptops, desktops and servers, where tens and hundreds of amperes are needed. A 3D integrated POL module with an output current of tens of ampere has been successfully demonstrated at the Center for Power Electronic Systems (CPES), Virginia Tech. In this structure, the inductor is elaborated with low temperature co-fire ceramic (LTCC) ferrite, as a substrate where the active components are placed. The lateral flux inductor is proposed to achieve both a low profile and high power density. Generally, the size of the inductor can be continuously shrunk by raising the switching frequency. The emerging gallium-nitride (GaN) power devices enable the creation and use of a multi-MHz, high efficiency POL converter. This dissertation firstly explores the LTCC inductor substrate design in the multi-MHz range for a high-current POL module with GaN devices. The impacts of different frequencies and different LTCC ferrite materials on the inductor are also discussed. Thanks to the DC flux cancellation effect, the inverse coupled inductor further improves the power density of a 20A, 5MHz two-phase POL module to more than 1kW/in3. An FEA simulation model is developed to study the core loss of the lateral flux coupled inductor, which shows the inverse coupling is also beneficial for core loss reduction. The ceramic-based 3D integrated POL module, however, is not widely adopted in industrial products because of the relatively high cost of the LTCC ferrite material and complicated manufacturing process. To solve that problem, a printed circuit board (PCB) inductor substrate with embedded alloy flake composite core is proposed. The layerwise magnetic core is laminated into a multi-layer PCB, and the winding of the inductor then is formed by the copper layers and conventional PCB vias. As a demonstration of system integration, a 20A, 1.5MHz integrated POL module is designed and fabricated based on a 4-layer PCB with embedded flake core, which realizes more than 85% efficiency and 600W/in3 power density. The application of standardized PCB processes reduces the cost for manufacturing the integrated modules due to the easy automation and the low temperature manufacturing process. Combining the PCB-embedded coupled inductor substrate and advanced control strategy, the two-phase 40A POL modules are elaborated as a complete integrated laptop VR solution. The coupled inductor structure is slightly modified to improve its transient performance. The nonlinearity of the inductance is controlled by adding either air slots or low permeability magnetic slots into the leakage flux path of the coupled inductor. Then the leakage flux, which determines the transient response of the coupled inductor, can be well controlled. If we directly replace the discrete VR solution with the proposed integrated modules, more than 50% of the footprint on the motherboard can be saved. Although the benefits of the lateral flux inductor have been validated in terms of its high power density and low profile, the planar core is excited under very non-uniform flux. Some parts of the core are even pushed into the saturation region, which totally goes against the conventional sense of magnetic design. The final part of this dissertation focuses on evaluating the performance of the planar core with variable flux. The counterbalance between DC flux and AC flux is revealed, with which the AC flux and the core loss density are automatically limited in the saturated core. The saturation is essentially no longer detrimental in this special structure. Compared with the conventional uniform flux design, the variable flux structure extends the operating point into the saturation region, which gives better utilization of the core. In addition, the planar core with variable flux also provides better thermal management and more core loss reduction under light load. As conclusions, this research first challenges the conventional magnetic design rules, which always assumes uniform flux. The unique characteristics and benefits of the variable flux core are proved. As an example of taking advantages of the lateral flux inductor, the PCB integrated POL modules are proposed and demonstrated as a high-density VR solution. The integrated modules are cost-effective and ready to be commercialized, which could enable the next technological innovation for the whole computing and telecom industry.
Ph. D.

Advances in very large scale integration (VLSI) technologies impose challenges for voltage regulator modules (VRM) to deliver high-quality power to modern microprocessors. As an enabling technology, multiphase converters have become the standard practice in VRM industry. The primary objectives of this dissertation are to develop advanced topologies and innovative integrated magnetics for high-efficiency, high-power-density and fast-transient VRMs. The optimization of multiphase VRMs has also been addressed. Todayâ s multiphase VRMs are almost universally based on the buck topology. With increased input voltage and decreased output voltage, the multiphase buck converter suffers from a very small duty cycle and cannot achieve a desirable efficiency. The multiphase tapped-inductor buck converter is one of the simplest topologies with a decent duty cycle. However, the leakage inductance of its tapped inductors causes a severe voltage spike problem. An improved topology, named the multiphase coupled-buck converter, is proposed. This innovative topology enables the use of a larger duty cycle with clamped device voltage and recovered leakage energy. Under the same transient responses, the multiphase coupled-buck converter has a significantly better efficiency than the multiphase buck converter. By integrating all the magnetic components into a single core, in which the windings are wound around the center leg and the air gaps are placed on the two outer legs, it is possible for multiphase VRMs to further improve efficiency and cut the size and cost. Unfortunately, this structure suffers from an undesirable core structure and huge leakage inductance. An improved integrated magnetic structure is proposed to overcome these limitations. All the windings are wound around the two outer legs and the air gap is placed on the center leg. The improved structure also features the flux ripple cancellation in the center leg and strongly reverse-coupled inductors. Both core loss and winding loss are reduced. The steady-state current ripples can be reduced without compromising the transient responses. The overall efficiency of the converter is improved. The input inductor can also be integrated in the improved integrated magnetic structure. Currently, selecting the appropriate number of channels for multiphase VRMs is still an empirical trial-and-error process. This dissertation proposes a methodology for determining the right number of channels for the optimal multiphase design. The problem formulation and general method for the optimization are proposed. Two examples are performed step by step to demonstrate the proposed optimization methodology. Both are focused on typical VRM 9.0 designs for the latest Pentium 4® microprocessors and their results are compared with the industry practice.
Ph. D.

Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 2001.
Thesis advisor(s): Ciezki, John G. ; Ashton, Robert W. "December 2001." Includes bibliographical references (p. 201-202). Also available in print.

The thesis has three main themes: analysis and optimal design of Cuk DC-DC converters; integration of Cuk DC-DC converters with photovoltaic (PV) modules to improve operation during partial shading; and an artificial intelligence model for the PV module, permitting an accurate maximum power point (MPP) tracking in the integrated system. The major contribution of the thesis is the control of an integrated photovoltaic module and DC-DC converter configuration for obtaining maximum power generation under non-uniform solar illumination. In place of bypass diodes, the proposed scheme embeds bidirectional Cuk DC-DC converters within the serially connected PV modules. A novel control scheme for the converters has been developed to adjust their duty ratios, enabling all the PV modules to operate at the MPPs corresponding to individual lighting conditions. A detailed analysis of a step-down Cuk converter has been carried out leading to four transfer functions of the converter in two modes, namely variable input - constant output voltage, and variable output - constant input voltage. The response to switch duty ratio variation is shown to exhibit a non-minimum phase feature. A novel scheme for selecting the circuit components is developed using the criteria of suppressing input current and output voltage ripple percentages at a steady state, and minimising the time integral of squared transient response errors. The designed converter has been tested in simulation and in practice, and has been shown to exhibit improved responses in both operating modes. A Neuro-Fuzzy network has been applied in modelling the characteristics of a PV module. Particle-Swarm-Optimisation (PSO) has been employed for the first time as the training algorithm, with which the tuning speed has been improved. The resulting model has optimum compactness and interpretability and can predict the MPPs of individual PV modules in real time. Experimental data have confirmed its improved accuracy. The tuned Neuro-Fuzzy model has been applied to a practical PV power generation system for MPP control. The results have shown an average error of 1.35% compared with the maximum extractable power of the panel used. The errors obtained, on average, are also about four times less than those using the genetic-algorithm-based model proposed in a previous research. All the techniques have been incorporated in a complete simulation system consisting of three PV panels, one boost and two bidirectional Cuk DC-DC converters. This has been compared under the same weather conditions as the conventional approach using bypass diodes. The results have shown that the new system can generate 32% more power.

This thesis examines converter topologies suitable for Module Integrated Converters (MICs) in grid interactive photovoltaic (PV) systems, and makes a contribution to the development of the MIC topologies based on the two-inductor boost converter, which has received less research interest than other well known converters. The thesis provides a detailed analysis of the resonant two-inductor boost converter in the MIC implementations with intermediate constant DC links. Under variable frequency control, this converter is able to operate with a variable DC gain while maintaining the resonant condition. A similar study is also provided for the resonant two-inductor boost converter with the voltage clamp, which aims to increase the output voltage range while reducing the switch voltage stress. An operating point with minimized power loss can be also established under the fixed load condition. Both the hard-switched and the soft-switched current fed two-inductor boost converters are developed for the MIC implementations with unfolding stages. Nondissipative snubbers and a resonant transition gate drive circuit are respectively employed in the two converters to minimize the power loss. The simulation study of a frequency-changer-based two-inductor boost converter is also provided. This converter features a small non-polarised capacitor in a second phase output to provide the power balance in single phase inverter applications. Four magnetic integration solutions for the two-inductor boost converter have also been presented and they are promising in reducing the converter size and power loss.

This thesis examines the development of DC-DC converters that are suitable for Module Integrated Converters, (MICs), in grid interactive photovoltaic (PV) systems, and especially concentrates on the study of the half bridge dual converter, which was previously developed from the conventional half bridge converter. Both hard-switched and soft-switched half bridge dual converters are constructed, which are rated at 88W each and transform a nominal 17.6Vdc input to an output in the range from 340V to 360Vdc. An initial prototype converter operated at 100kHz and is used as a base line device to establish the operational behaviours of the converter. The second hard-switched converter operated at 250kHz and included a coaxial matrix transformer that significantly reduced the power losses related to the transformer leakage inductance. The soft-switched converter operated at 1MHz and is capable of absorbing the parasitic elements into the resonant tank. Extensive theoretical analysis, simulation and experimental results are provided for each converter. All three converters achieved conversion efficiencies around 90%. The progressive increases in the operation frequency, while maintaining the conversion efficiency, will translate into the reduced converter size and weight. Finally different operation modes for the soft-switched converter are established and the techniques for predicting the occurrence of those modes are developed. The analysis of the effects of the transformer winding capacitance also shows that soft switching condition applies for both the primary side mosfets and the output rectifier diodes.

Thesis (Electrical Engineer)--Naval Postgraduate School, September 2001.
Thesis Advisor(s): Robert W. Ashton, John G. Ciezki, Todd R. Weatherford. Includes bibliographical references (p. 175-177). Also available online.

It has been well-recognized that non-uniform solar irradiation of photovoltaic (PV) panels causes electrical mismatching of cells and may result in reduced output power and cell thermal breakdown. Bypass diodes are commonly used, but challenges exist into obtaining the maximum power point tracking in these partially shaded PV panels for each weather condition. This is due to that there are multiple peak power points present in their Power-Voltage characteristic curves which makes difficult to locate the global maximum power point. The work presented in this thesis studies in detail the converter topologies and control methods which can be used in the PV power generation systems to overcome effectively the shortcomings caused by partial shading. The proposed topology is an integrated bi-directional Cuk converter and PV-panel module. The particular example investigated includes two PV panels connected across two terminals of the Cuk converter. The features of this system in power harness are studied under partial shading conditions, its superior performance in power generation is demonstrated through simulation and practical tests. The generated power is 30% higher than that from a two PV panel system using only bypass diodes. To develop the control schemes for the above system a detailed study was performed leading to the derivation of the transfer function model describing the dynamic responses of voltages across the two PV panels corresponding to the variations of converter switch duty ratio. Experimental verification of this confirms that the model is sufficiently accurate for the application of controller design and tests. A novel maximum power point tracking scheme is developed. This consists of a switching selection scheme and a model based on an optimal control algorithm. The former determines which switch-diode pair in the bidirectional Cuk converter to be active according to measured light levels on each PV panel and the ability to predict the optimal voltage values across the individual PV panels under any practical irradiance and temperature levels. The performance of the controller is tested in simulation as well as in practice under various modes of partial shading, all giving desired results in achieving the maximum power generation. The final contribution lies in the design and construction of an experimental prototype consisting of an inner bidirectional Cuk converter across two PV panels and a terminal boost converter, controlled by DSP-based microcontroller. This setup enables further development and verification of the control schemes for this integrated converter and PV-panel system. Keywords: Photovoltaic Systems, Partial Shading, Cuk Converter, DC-DC Power Converters, Solar Power Generation, Maximum Power Point Tracking, Bypass Diode.

The non-isolated POL converters are widely used in computers, telecommunication systems, portable electronics, and many other applications. These converters are usually constructed using discrete components, and operated at a lower frequency around 200 ~ 600 kHz to achieve a decent efficiency at the middle of 80\'s%. The passive components, such as inductors and capacitors, are bulky, and they occupy a considerable foot-print. As the power demands increase for POL converters and the limited real estate of the mother board, the POL converters must be made significantly smaller than what they have demonstrated to date. To achieve these goals, two things have to happen simultaneously. The first is a significant increase in the switching frequency to reduce the size and weight of the inductors and capacitors. The second is to integrate passive components, especially magnetics, with active components to realize the needed power density.
Today, this concept has been demonstrated at a level less than 5A and a power density around 300-700W/in3 by using silicon-based power semiconductors. This might address the need of small hand-held equipment such as PDAs and smart phones. However, it is far from meeting the needs for applications, such as netbook, notebook, desk-top and server applications where tens and hundreds of amperes are needed.
After 30 years of silicon MOSFET development, the silicon has approached its theoretical limits. The recently emerged GaN transistors as a possible candidate to replace silicon devices in various power conversion applications. GaN devices are high electron mobility transistors (HEMT) and have higher band-gap, higher electron mobility, and higher electron velocity than silicon devices, and offer the potential benefits for high frequency power conversions. By implementing the GaN device, it is possible to build the POL converter that can achieve high frequency, high power density, and high efficiency at the same time. GaN technology is in its early stage; however, its significant gains are projected in the future. The first generation GaN devices can outperform the state-of-the-art silicon devices with superior FOM and packaging.
The objective of this work is to explore the design of high frequency, high power density 12 V input POL modules with GaN devices and the 3D integration technique. This work discusses the fundamental differences between the enhancement mode and depletion mode GaN transistors, the effect of parasitics on the performance of the high frequency GaN POL, the 3D technique to integrate the active layer with LTCC magnetic substrate, and the thermal design of a high density module using advanced substrates with improved thermal conductivity.
The hardware demonstrators are two 12 V to 1.2 V highly integrated 3D POL modules, the single phase 10 A module and two phase 20 A module, all built with depletion mode GaN transistors and low profile LTCC inductors.

Master of Science

Questa tesi descrive un convertitore di potenza DC/DC a condensatori commutati per applicazioni di energy harvesting da sorgenti ambientali a bassa potenza caratterizzato da guadagno/frequenza di commutazione configurabili dinamicamente. I convertitori di potenza a switching convenzionali richiedono tipicamente componenti magnetici (ad es. induttori) difficilmente integrabili, quindi è solitamente necessario aggiungerli come componenti esterni con conseguente aumento dell'area e dei costi. D'altra parte, i convertitori a condensatori commutati sono particolarmente interessanti in un'ampia gamma di applicazioni poiché non richiedono tali componenti esterni, essendo basati solo su condensatori, che possono essere completamente integrati. Questa soluzione è particolarmente interessante nello scenario IoT, dove le dimensioni e l'integrabilità dei dispositivi possono essere un punto cruciale nello sviluppo. Questo lavoro è incentrato sullo studio di tali architetture con un nuovo paradigma che considera gli aspetti funzionali e di efficienza con riferimento specifico ai trasduttori per energy harvesting (ad es. fotovoltaico indoor, termoelettrico, radiofrequenza, ecc.), che sono caratterizzati da basse tensioni in uscita, basse potenze, elevate resistenze di uscita. Allo stesso tempo, considerando l’obiettivo della riduzione dei consumi di potenza, verrà adottato come oscillatore interno un oscillatore ad anello in configurazione current-starved. Questa tesi studia principalmente la progettazione sia dello schematico che del layout di alcuni blocchi analogici del convertitore, specificamente legati al modulo di controllo in retroazione. Il progetto dello schematico e del layout del sistema adottano una tecnologia CMOS 180nm, e sono sviluppati in ambiente CAD Cadence.

L’augmentation des performances des produits portables requièrent une exploitation la plus efficace possible de la batterie afin de permettre à ces produits d’être utilisés le plus longtemps possible avant d’être rechargés. Les circuits en aval ont besoin d’une source de tension stable qui peut varier pour chacun d’entre eux entre 1.0 V et 5.5 V à partir d’une tension d’entrée pouvant varier entre 2.5V et 5V. Un convertisseur DC-DC à 4 interrupteurs de type dévolteur-survolteur apparait comme une solution intéressante permettant des opérations de diminutions et d’augmentations de tension d’une part, et d’autres part le meilleur compromis entre rendement, performances dynamiques et coûts (en termes de place occupée sur le Silicium et sur la carte). ON Semiconductor a développé et produit un prototype en technologie CMOS 0.25 µm (procédé propriétaire) d’un tel convertisseur qui sert d’étude de cas pour la thèse. Le convertisseur opère selon plusieurs modes de fonctionnement (mode dévolteur, mode survolteur et mode dévolteur-survolteur) à cause d’un impératif de fonctionnement en fréquence de commutation fixe. Le mode dévolteur-survolteur est le sujet principal traité dans la thèse. Le mode dévolteur-survolteur, aussi appelé mode de transition, peut être implémenté via plusieurs Séquences de Topologie (SdT) possibles. Trois SdTs sont comparées en termes de rendement parmi lesquelles figure la SdT implémentée par le prototype. Les performances dynamiques du convertisseur dans ses différents mode de fonctionnement sont ensuite étudiées en dérivant les expressions analytiques des fonctions de transfert qui les caractérisent. Les modèles dérivés dans Matlab et Mathcad pour évaluer le rendement et les performances dynamiques du convertisseur sont ensuite utilisés pour développer un outil servant à obtenir un dimensionnement rapide de la boucle de contrôle du convertisseur. À partir de cette étape, la stabilité du convertisseur dans ses différents modes de fonctionnement est analysée en utilisant la théorie de Floquet et un modèle échantillonné-linéarisé du convertisseur permettant l’établissement d’une méthodologie de conception d’un tel convertisseur. Enfin, pour améliorer le rendement en mode de transition pour tous les points de fonctionnement, un algorithme contrôlant la valeur de l’hystérésis du comparateur utilisé dans la boucle de contrôle a été développé en Verilog, simulé dans l’environnement CADENCE et implémenté en FPGA. Cet algorithme peut améliorer le rendement de près de 3% en mode de transition comparé au réglage initial de la valeur d’hystérésis
The increase in the performances of the portable devices calls for an energy conversion from the battery that is the most efficient as possible in order to make the devices last as long as possible. The downstream circuits need a steady voltage supply which can vary for each one of them from 1.0 V to 5.5 V from an input voltage varying between 2.5 V and 5 V. A 4-Switch Buck-Boost (4SBB) DC-DC converter appears to be the solution which can perform step-up and step-down voltage perations and get the best trade-off between fficiency, dynamic performances and costs (in terms of Silicium and Board area). ON Semiconductor has developed and taped out in CMOS 0.25 µm (ON Semiconductor process) a 4SBB converter which serves as the case study of the thesis. The converter operates in multiple modes (namely Buck mode, Boost mode and Buck-Boost mode) due to fixed frequency operations. The Buck-Boost mode is the main topic dealt with in the thesis. The Buck-Boost mode, also called "transition mode", can be implemented using several possible Sequences of Topologies (SoT). Three SoTs are compared in terms of efficiency among which the one implemented in the converter. Then the dynamical performances of the converter are studied for the different modes of operations by deriving the analytical expressions of the relevant transfer functions. The models derived in Matlab and Mathcad to evaluate efficiency and dynamical performances are then used to develop a tool to get a rapid sizing of the converter’s control loop components. From this step, the stability of the converter is analyzed using Floquet’s theory and Sampled-Data modeling enabling the building of a design methodology to design such a converter. Finally, to enhance efficiency in Buck-Boost mode whatever the working conditions, an algorithm controlling the hysteresis value of the control loop’s comparator has been developed in Verilog, simulated in CADENCE and implemented in FPGA. This algorithm can improve efficiency by almost 3% in Buck-Boost mode compared to its default setting

abstract: With the rapid expansion of the photovoltaic industry over the last decade, there has been a huge demand in the PV installations in the residential sector. This thesis focuses on the analysis and implementation of a dc-dc boost converter at photovoltaic sub-module level. The thesis also analyses the various topologies like switched capacitors and extended duty ratio which can be practically implemented in the photovoltaic panels. The results obtained in this work have concentrated on the use of novel strategies to substitute the use of central dc-dc converter used in PV module string connection. The implementation of distributed MPPT at the PV sub-module level is also an integral part of this thesis. Using extensive PLECS simulations, this thesis came to the conclusion that with the design of a proper compensation at the dc interconnection of a series or parallel PV Module Integrated Converter string, the central dc-dc converter can be substituted. The dc-ac interconnection voltage remains regulated at all irradiance level even without a dc-dc central converter at the string end. The foundation work for the hardware implementation has also been carried out. Design of parameters for future hardware implementation has also been presented in detail in this thesis.
Dissertation/Thesis
M.S. Electrical Engineering 2012

碩士
國立清華大學
電機工程學系
101
In view of the problems of global climate change, environmental impact and shortage of fossil fuels, exploring the use of renewable energy has drawn a lot of attention internationally. Among a variety of renewable energy technologies, photovoltaic technology has more environmental and economic benefits than the others. However, existing DC converters still face the partial shading effects bottleneck problem. Recently, module-integrated converters (MIC) have become a hot research topic as a means for overcoming the partial shading effects of photovoltaic systems and achieving high safety. Hence, in this thesis, to further improve the energy yield, emphasis is placed on the development of a novel ZVS isolated module-integrated converter for photovoltaic systems. Major contributions of this thesis can be summarized as follows. First, a novel MIC with pseudo dc-link and galvanic isolation is proposed. It consists of an isolated SEPIC converter cascaded with a full-bridge inverter operating under line frequency to achieve high efficiency. Furthermore, active-clamped circuits are added to the isolated SEPIC converter to achieve zero voltage switching and alleviate the reverse-recovery current of the output diodes. Secondly, a simple control strategy is proposed to generate a rectified sine waveform voltage at the dc-link capacitors. Also, to reduce input current ripple, an interleaved control strategy is adopted. It has been found that the duty ratio of the active switches can be operated in full range to achieve wider output voltage control range. Finally, a prototype with 25 V input, 110 Vrms output and 150 W rating has been constructed for verifying the feasibility of the proposed MIC. Experimental results have shown that the overall efficiency of the MIC can be maintained above 86.7% as the load varies from 40 W to 150 W, and the highest efficiency of 92.4% has been achieved at 40W.

博士
國立清華大學
電機工程學系
102
Due to the limited fossil energy and greenhouse effect, more and more countries are devoting to development and promotion of renewable energy sources. Among the various renewable energy sources, solar energy has the advantages of being inexhaustible and noiseless. Hence, installation of photovoltaic (PV) energy harvesting system keeps a rather high growing rate in recent years. For most PV systems, a switching power converter is required as a regulator for harvesting the maximum output power. However, the inherent current ripple of switching power converter may cause significant impact on the output of PV system. In this dissertation, the first objective is focused on the study of the quantitative ripple-affected power reduction of PV energy harvesting systems as well as proposing a passive ripple cancelling technique to solve the above dilemma. A passive continuous ripple cancelling circuit (PCRCC) and a passive pulsating ripple cancelling circuit (PPRCC) are proposed for eliminating the continuous and pulsating current ripple of power converters, respectively. Special features of the proposed passive ripple cancelling circuits (PRCCs) include simple, modular structure, and high degree of design flexibility. A zero input current ripple Ćuk-type converter is adopted and analyzed as an example for the proposed PCRCC because of its step up/down capability and non-pulsating input/output current feature. On the other hand, for the proposed PPRCC, a zero input current ripple flyback-type converter is proposed and analyzed as an example because of its comprehensive utilization in small power rating commercial products. The corresponding steady-state analysis, zero ripple design criteria, and the topologies of several conventional power converters integrated with the proposed PCRCC/PPRCC are provided. In addition, a novel high voltage gain single-stage DC/AC converter is proposed for low-voltage and high-current output PV module applications. A flyback-type auxiliary circuit is integrated with an isolated Ćuk-derived voltage source DC/AC converter to achieve a much higher voltage gain so that the conversion efficiency can be enhanced. Steady-state characteristics, performance analysis, simulation and experimental results are given to show the merits of the proposed high voltage gain single-stage DC/AC converter. Based on the same integration concept, a family of different topologies is also presented for reference. Moreover, the proposed PRCC is also integrated into the proposed high voltage gain DC/AC converter as an example for further increasing the output power. Finally, three converter prototypes are constructed for verifying the effectiveness of the proposed PCRCC, PPRCC, and high voltage gain DC/AC converter, respectively. First, the experimental results of the 90W rating zero input current ripple Ćuk-type converter prototype show that the resulting peak-to-peak input current ripple is reduced by 98% of the original Ćuk converter input current ripple, and the harvested average PV power of the proposed converter can be increased by 7% as compared with that of the converter without the proposed PCRCC. Second, the experimental results of the 100W rating zero input current ripple flyback-type converter prototype show that the resulting peak-to-peak input current ripple is reduced by 98% of the original flyback converter input current ripple, and nearly 2.83% and 10.23% improvement in efficiency can be achieved by the proposed PPRCC, at 70W and 100W load conditions, respectively. Third, the experimental results of the 200W rating high voltage gain DC/AC converter show that the highest efficiency of 92.3% can be achieved. There is approximately 10% improvement in efficiency at 40W light load as compared with the conventional isolated Ćuk-derived DC/AC converter. Also, it indicates that nearly 3% and 1.4% improvement in efficiency can be achieved by the proposed DC/AC converter, under 120W and 200W load conditions, respectively.

Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters(ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get more battery life. Because of their ubiquitous nature, ADCs are prime blocks in the signal chain in which power is intended to be reduced. In this thesis, four techniques to reduce power in high speed pipelined ADCs have been proposed. The first is a capacitor and opamp sharing technique that reduces the load on the first stage opamp by three fold. The second is a capacitor reset technique that aids removing the sample and hold block to reduce power. The third is a modified MDAC which can take rail-to-rail input swing to get an extra bit thus getting rid of a power hungry opamp. The fourth is a hybrid architecture which makes use of an asynchronous SAR ADC as the backend of a pipelined ADC to save power. Measurement and simulation results that prove the efficiency of the proposed techniques are presented.
Graduation date: 2009