Journal articles: 'Modern processors'

1

Chen, Kuo Yi, Fuh Gwo Chen, and Jr Shian Chen. "A Cost-Effective Hardware Approach for Measuring Power Consumption of Modern Multi-Core Processors." Applied Mechanics and Materials 110-116 (October 2011): 4569–73. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.4569.

Full text

Abstract:

Multiple processor cores are built within a chip by advanced VLSI technology. With the decreasing prices, multi-core processors are widely deployed in both server and desktop systems. The workload of multi-threaded applications could be separated to different cores by multiple threads, such that application threads can run concurrently to maximize overall execution speed of the applications. Moreover, for the green trend of computing nowadays, most of modern multi-core processors have a functionality of dynamic frequency turning. The power-level tuning techniques are based on Dynamic Voltage and Frequency Scaling (DVFS). In order to evaluate the performance of various power-saving approaches, an appropriate technique to measure the power consumption of multi-core processors is important. However, most of approaches estimate CPU power consumption only from CMOS power consumption data and CPU frequency. These approaches only estimate the dynamic power consumption of multi-core processors, the static power consumption is not be included. In this study, a hardware approach for the power consumption measurement of multi-core processors is proposed. Thus the power consumption of a CPU could be measured precisely, and the performance of CPU power-saving approaches can be evaluated well.

APA, Harvard, Vancouver, ISO, and other styles

2

Muralidharan, K., and S. Uma Maheswari. "Design of Low Power Cam Memory Cell for the Next Generation Network Processors." IRO Journal on Sustainable Wireless Systems 3, no. 4 (December 3, 2021): 208–18. http://dx.doi.org/10.36548/jsws.2021.4.001.

Full text

Abstract:

In the modern world, high performance embedded applications in the field of multimedia, networking, and imaging are increasing day by day. These applications require high performance and more complex out-of-order superscalar processor. These complex dynamic instructions scheduling superscalar processors need higher levels of on-chip integration designs which are often associated with power dissipation. These out-of-order superscalar processors achieve higher performance compared to other processors by simultaneous fetching, decoding and execution for multiple instructions in out-of-order that are used in the next generation network processors. The main data path resources of the processor use CAM+RAM structure which is the major power consuming unit in the overall out-of-order processor design. The proposed new design of CAM+RAM with power-gating technique reduces the overall average power consumption compared to the conventional design without any significant impact on their performance.

APA, Harvard, Vancouver, ISO, and other styles

3

Sharma, Anuj, and Elias S. Manolakos. "Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures." BioMed Research International 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/563674.

Full text

Abstract:

Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel’s experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel’s Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a highF-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlyingrckskelalgorithmic skeletons library, is available via GitHub.

APA, Harvard, Vancouver, ISO, and other styles

4

Kidwai, Hashir Karim, Fadi N. Sibai, and Tamer Rabie. "Parallelization and Performance Evaluation of an Edge Detection Algorithm on a Streaming Multi-Core Engine." Journal of Information Technology Research 2, no. 4 (October 2009): 81–91. http://dx.doi.org/10.4018/jitr.2009062906.

Full text

Abstract:

In the world of multi-core processors, the STI Cell Broadband Engine (BE) stands out as a heterogeneous 9-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). The Cell BE architecture is designed to improve upon conventional processors in graphics and related areas by integrating 8 computation engines each with multiple execution units and large register sets to achieve a high performance per area return. In this paper, we discuss the parallelization, implementation and performance evaluation of an edge detection image processing application based on the Roberts edge detector on the Cell BE. The authors report the edge detection performance measured on a computer with one Cell processor and with varying numbers of synergic processor engines enabled. These results are compared to the results obtained on the Cell’s single PPE with all 8 SPEs disabled. The results indicate that edge detection performs 10 times faster on the Cell BE than on modern RISC processors.

APA, Harvard, Vancouver, ISO, and other styles

5

Vyukova, N. I., V. A. Galatenko, and S. V. Samborskij. "Exploiting Vector Extensions of Modern Processors." PROGRAMMNAYA INGENERIA 7, no. 4 (April 12, 2016): 147–57. http://dx.doi.org/10.17587/prin.7.147-157.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Deris, Kaveh Jokar, and Amirali Baniasadi. "Power-aware BTB for modern processors." Computers & Electrical Engineering 36, no. 5 (September 2010): 902–11. http://dx.doi.org/10.1016/j.compeleceng.2008.04.008.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Hanafi Por, Porya Soltani, Abbas Ramazani, and Mojtaba Hosseini Toodeshki. "Temperature and performance evaluation of multiprocessors chips by optimal control method." Bulletin of Electrical Engineering and Informatics 12, no. 2 (April 1, 2023): 749–59. http://dx.doi.org/10.11591/eei.v12i2.4291.

Full text

Abstract:

Multi-core processors support all modern electronic devices nowadays. However, temperature and performance management are one of the most critical issues in the design of today’s microprocessors. In this paper, we propose a framework by using an optimal control method based on fan speed and frequency control of the multi-core processor. The goal is to optimize performance and at the same time avoid violating an expected temperature. Our proposed method uses a high-precision thermal and power model for multi-core processors. This method is validated on asymmetric ODROID-XU4 multi-core processor. The experimental results show the ability of the proposed method to achieve the adequate trade-off between performance and temperature control.

APA, Harvard, Vancouver, ISO, and other styles

8

Kuzminsky, Mikhail Borisovich. "Modern server ARM processors for supercomputers: A64FX and others. Initial data of benchmarks." Program Systems: Theory and Applications 13, no. 1 (February 22, 2022): 131–94. http://dx.doi.org/10.25209/2079-3316-2022-13-1-131-194.

Full text

Abstract:

A comparative analysis of the performance of ARM server processors used on supercomputers or also aimed at high-performance computing (HPC) is given. Fujitsu A64FX, Marvell ThunderX2 and Huawei Kunpeng 920 were selected for the initial performance analysis. The HPC performance review focuses primarily on benchmarks and applications for the A64FX, which supports longer vectors than other ARM processors and has higher peak performance. The performance of the A64FX is compared against corresponding data for Intel Xeon Skylake and Cascade Lake, and AMD EPYC with Zen 2 and 3 (Roma and Milan), as well as Nvidia V100 and A100 GPUs. A short set of potential pros and cons of the A64FX microarchitecture has been formulated. Comparison of performance data obtained using different compilers for A64FX. Features have been formed when A64FX usually gives advantages in performance over x86-64, and when it concedes to x86-64. It is clear that the use of A64FX in supercomputers can grow further. There is an assumption that x86-64 hegemony in HPC will decrease, in particular, due to the increased use of server ARM processors. But the analysis of A64FX and new AArch64 processors expected in the near future showed that A64FX will not necessarily lead in this process.

APA, Harvard, Vancouver, ISO, and other styles

9

Faeq, Mays K., and Safaa S. Omran. "Cache coherency controller for MESI protocol based on FPGA." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (April 1, 2021): 1043. http://dx.doi.org/10.11591/ijece.v11i2.pp1043-1052.

Full text

Abstract:

In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultanously for more than one job or all the cores working in parallel for the same job. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So if one core requestes a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores.This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using very high speed integrated circuit hardware description language (VHDL) coding and implemented using ISE Xilinx software. The protocol used in this design is the modified, exclusive, shared and invalid (MESI) protocol. Test results were taken by using test bench, and showed all the states of the protocol are working correctly.

APA, Harvard, Vancouver, ISO, and other styles

10

Chattra, Eka, and Obrin Candra Brillyant. "Implementation of Meltdown Attack Simulation for Cybersecurity Awareness Material." ACMIT Proceedings 7, no. 1 (July 7, 2021): 6–13. http://dx.doi.org/10.33555/acmit.v7i1.102.

Full text

Abstract:

One of the rising risk in cybersecurity is an attack on cyber physical system. Today’s computer systems has evolve through the development of processor technology, namely by the use of optimization techniques such as out-of-order execution. Using this technique, processors can improve computing system performance without sacrificing manufacture processes. However, the use of these optimization techniques has vulnerabilities, especially on Intel processors. The vulnerability is in the form of data exfiltration in the cache memory that can be exploit by an attack. Meltdown is an exploit attack that takes advantage of such vulnerabilities in modern Intel processors. This vulnerability can be used to extract data that is processed on that specific computer device using said processors, such as passwords, messages, or other credentials. In this paper, we use qualitative research which aims to describe a simulation approach with experience meltdown attack in a safe environment with applied a known meltdown attack scheme and source code to simulate the attack on an Intel Core i7 platform running Linux OS. Then we modified the source code to prove the concept that the Meltdown attack can extract data on devices using Intel processors without consent from the authorized user.

APA, Harvard, Vancouver, ISO, and other styles

11

Masten, Michael K., and Issa Panahi. "Digital Signal Processors in Modern Control Systems." IFAC Proceedings Volumes 29, no. 1 (June 1996): 7213–17. http://dx.doi.org/10.1016/s1474-6670(17)58845-x.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Masten, M. K., and I. Panahi. "Digital signal processors for modern control systems." Control Engineering Practice 5, no. 4 (April 1997): 449–58. http://dx.doi.org/10.1016/s0967-0661(97)00024-5.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Haj-Yihia, Jawad, and Yosi Ben-Asher. "Software Static Energy Modeling for Modern Processors." International Journal of Parallel Programming 46, no. 2 (March 13, 2017): 284–312. http://dx.doi.org/10.1007/s10766-017-0496-z.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Schneider, M., H. Blume, and T. G. Noll. "Power estimation on functional level for programmable processors." Advances in Radio Science 2 (May 27, 2005): 215–19. http://dx.doi.org/10.5194/ars-2-215-2004.

Full text

Abstract:

Abstract. In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW)-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA). Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW) -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA). This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated the input parameters of the Correspondence to: H. Blume (blume@eecs.rwth-aachen.de) arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. This approach is exemplarily demonstrated and evaluated applying two modern digital signal processors and a variety of basic algorithms of digital signal processing. The resulting estimation values for the inspected algorithms are compared to physically measured values. A resulting maximum estimation error of 3% is achieved.

APA, Harvard, Vancouver, ISO, and other styles

15

Shen, Luyi. "Bit-Serial Logical Operation Processor Based on Shift Registers and Mealy Machine." Journal of Physics: Conference Series 2435, no. 1 (February 1, 2023): 012008. http://dx.doi.org/10.1088/1742-6596/2435/1/012008.

Full text

Abstract:

Abstract With the rapid development of modern processors, logical operation processors could not only process data by logical operations but also store the data. The logical operation processor designed in this paper will be the bit-serial logical operation processor. In order to build the processor, four units should be designed first: the Shift Register Unit, Computation Unit, Routing Unit, and Control Unit. Among them, the Register Unit and the Control Unit are the most important. For the Register Unit, there will be two 4-bit registers. For the Control Unit, this circuit will implement a Mealy machine to determine the output and state of the circuit. The input to the processor will first get into the Control Unit, and then the data given outside will be stored in the Shift Register Unit and will be input to the Computation Unit and finally returned to the Shift Register Unit after Routing Unit. Since the processor is operating in series, the Control Unit and the Shift Register Unit should work synchronously.

APA, Harvard, Vancouver, ISO, and other styles

16

Lan, Mengqiao, Libo Huang, Ling Yang, Sheng Ma, Run Yan, Yongwen Wang, and Weixia Xu. "Late-Stage Optimization of Modern ILP Processor Cores via FPGA Simulation." Applied Sciences 12, no. 23 (November 29, 2022): 12225. http://dx.doi.org/10.3390/app122312225.

Full text

Abstract:

Late-stage (post-RTL implementation) optimization is important in achieving target performance for realistic processor design. However, several challenges remain for modern out-of-order ILP (instruction-level-parallelism) processors, such as simulation speed, flexibility, and complexity problems. This paper restudy FPGA simulation as an effective performance simulation method and proposes FPGA-enhanced design flow as an effective method to address these problems. It features a late-stage aware RTL design that parameterizes various potential design options induced from early-stage optimization. This flow enables the feasibility of late-stage design space exploration. To resolve the performance accuracy of the FPGA system for peripheral designs, reference models are introduced. With an example implementation of out-of-order core running up to 80 MHz, the experimental results show that the proposed method is practical and allows the fine-grain optimization of the processor core to be more effective.

APA, Harvard, Vancouver, ISO, and other styles

17

Surchenko, Alexander Viktorovich. "Evaluation of Hardware Data Compression in Interprocessor Links of Elbrus Processors." Proceedings of the Institute for System Programming of the RAS 34, no. 1 (2022): 49–58. http://dx.doi.org/10.15514/ispras-2022-34(1)-4.

Full text

Abstract:

The tendency to increase core count in modern processor systems leads to a higher strain on memory subsystem. In particular, one of the most critical points in terms of throughput is interprocessor links, where bandwidth is significantly less than in processor data buses. Hardware data compression can be considered as one of the ways to increase throughput in interprocessor links, as it allows to decrease the amount of information transmitted over the links. This paper presents the evaluation of hardware data compression in interprocessor links of Elbrus processors. BΔI*-HL compression algorithm is chosen for the evaluation. The results are obtained of FPGA prototype of “Elbrus-16C” processor for the tasks of SPEC CPU2000 benchmark suite. They show that by using hardware data compression 38,0% of all data packets were compressed and that the amount of information transmitted overall has decreased by 13,4%. These results demonstrate that the use of hardware data compression in interprocessor links of Elbrus processors is justified and has potential to significantly increase memory subsystem performance.

APA, Harvard, Vancouver, ISO, and other styles

18

Nikolic, Goran, Bojan Dimitrijevic, Tatjana Nikolic, and Mile Stojcev. "Fifty years of microprocessor evolution: from single CPU to multicore and manycore systems." Facta universitatis - series: Electronics and Energetics 35, no. 2 (2022): 155–86. http://dx.doi.org/10.2298/fuee2202155n.

Full text

Abstract:

Nowadays microprocessors are among the most complex electronic systems that man has ever designed. One small silicon chip can contain the complete processor, large memory and logic needed to connect it to the input-output devices. The performance of today's processors implemented on a single chip surpasses the performance of a room-sized supercomputer from just 50 years ago, which cost over $ 10 million [1]. Even the embedded processors found in everyday devices such as mobile phones are far more powerful than computer developers once imagined. The main components of a modern microprocessor are a number of general-purpose cores, a graphics processing unit, a shared cache, memory and input-output interface and a network on a chip to interconnect all these components [2]. The speed of the microprocessor is determined by its clock frequency and cannot exceed a certain limit. Namely, as the frequency increases, the power dissipation increases too, and consequently the amount of heating becomes critical. So, silicon manufacturers decided to design new processor architecture, called multicore processors [3]. With aim to increase performance and efficiency these multiple cores execute multiple instructions simultaneously. In this way, the amount of parallel computing or parallelism is increased [4]. In spite of mentioned advantages, numerous challenges must be addressed carefully when more cores and parallelism are used. This paper presents a review of microprocessor microarchitectures, discussing their generations over the past 50 years. Then, it describes the currently used implementations of the microarchitecture of modern microprocessors, pointing out the specifics of parallel computing in heterogeneous microprocessor systems. To use efficiently the possibility of multi-core technology, software applications must be multithreaded. The program execution must be distributed among the multi-core processors so they can operate simultaneously. To use multi-threading, it is imperative for programmer to understand the basic principles of parallel computing and parallel hardware. Finally, the paper provides details how to implement hardware parallelism in multicore systems.

APA, Harvard, Vancouver, ISO, and other styles

19

Razouk, Rami R., Terri Stewart, and Michael Wilson. "Measuring operating system performance on modern micro-processors." ACM SIGMETRICS Performance Evaluation Review 14, no. 1 (May 1986): 193–202. http://dx.doi.org/10.1145/317531.317552.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Nilsen, Kelvin D., and Bernt Rygg. "Worst-case execution time analysis on modern processors." ACM SIGPLAN Notices 30, no. 11 (November 1995): 20–30. http://dx.doi.org/10.1145/216633.216650.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Middelfart, Morten, Torben Bach Pedersen, and Jan Krogsgaard. "Efficient Sentinel Mining Using Bitmaps on Modern Processors." IEEE Transactions on Knowledge and Data Engineering 25, no. 10 (October 2013): 2231–44. http://dx.doi.org/10.1109/tkde.2012.198.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Jia, Zhen, Jianfeng Zhan, Lei Wang, Chunjie Luo, Wanling Gao, Yi Jin, Rui Han, and Lixin Zhang. "Understanding Big Data Analytics Workloads on Modern Processors." IEEE Transactions on Parallel and Distributed Systems 28, no. 6 (June 1, 2017): 1797–810. http://dx.doi.org/10.1109/tpds.2016.2625244.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Ju, Lihan, Xingsheng Tang, Yuan Wen, and Tianzhou Chen. "Bhs: An Novel Scheduling Strategy on Modern Processors." Procedia Engineering 15 (2011): 5030–34. http://dx.doi.org/10.1016/j.proeng.2011.08.935.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Yoon, Chanmin, Seokjun Lee, Yonghun Choi, Rhan Ha, and Hojung Cha. "Accurate power modeling of modern mobile application processors." Journal of Systems Architecture 81 (November 2017): 17–31. http://dx.doi.org/10.1016/j.sysarc.2017.10.001.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Zhang, Zhuo, Yu-fan Lu, Wen-feng Shen, Wei-min Xu, and Yan-heng Zheng. "Blocking optimized SIMD tree search on modern processors." Journal of Shanghai University (English Edition) 15, no. 5 (October 2011): 437–44. http://dx.doi.org/10.1007/s11741-011-0765-2.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Borin, Edson, Philippe R. B. Devloo, Gilvan S. Vieira, and Nathan Shauer. "Accelerating engineering software on modern multi-core processors." Advances in Engineering Software 84 (June 2015): 77–84. http://dx.doi.org/10.1016/j.advengsoft.2014.12.003.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Li, Xiaobin, and Jean-Luc Gaudiot. "Tolerating Radiation-Induced Transient Faults in Modern Processors." International Journal of Parallel Programming 38, no. 2 (July 24, 2009): 85–116. http://dx.doi.org/10.1007/s10766-009-0114-9.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Bate, I. "Use of Modern Processors in Safety-Critical Applications." Computer Journal 44, no. 6 (June 1, 2001): 531–43. http://dx.doi.org/10.1093/comjnl/44.6.531.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Hur, I., and C. Lin. "Adaptive History-Based Memory Schedulers for Modern Processors." IEEE Micro 26, no. 1 (January 2006): 22–29. http://dx.doi.org/10.1109/mm.2006.1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Forsberg, H. "Sensitometric Control of Roentgen Film Processors." Acta Radiologica 28, no. 3 (May 1987): 339–43. http://dx.doi.org/10.1177/028418518702800322.

Full text

Abstract:

Monitoring of film processors performance is essential since image quality, patient dose and costs are influenced by the performance. A system for sensitometric constancy control of film processors and their associated components is described. Experience with the system for 3 years is given when implemented on 17 film processors. Modern high quality film processors have a stability that makes a test frequency of once a week sufficient to maintain adequate image quality. The test system is so sensitive that corrective actions almost invariably have been taken before any technical problem degraded the image quality to a visible degree.

APA, Harvard, Vancouver, ISO, and other styles

31

Bekayev, Е., and А. Kaharman. "Features of analysis and selection of microprocessors in modern control systems." Q A Iasaýı atyndaǵy Halyqaralyq qazaq-túrіk ýnıversıtetіnіń habarlary (fızıka matematıka ınformatıka serııasy) 24, no. 1 (March 30, 2023): 139–53. http://dx.doi.org/10.47526/2023-1/2524-0080.13.

Full text

Abstract:

The article discusses the results of a brief retrospective review of the current microprocessors in control systems and the main directions of their development. The main requirements and selection criteria presented at the stage of the microprocessor design process in modern control systems, classification and architectural features of microprocessors are described. In addition, the «pipeline» processing method for maximizing processor performance, features of the analysis and selection of microprocessors in modern control systems using various architectural solutions for the elimination of contradictions arising in it related to conflicts are studied. According to the «pipeline» principle, three main types of processor architecture (VLIW – Very Long Instruction Word) with superscalar and multiple computing devices working in parallel are defined - depending on data, management and structural conflicts. Therefore, their use in VLIW processors and the limitation of their application in the field of scientific research is justified, due to the fact that the source codes are transmitted in a «closed» form. The main advantage of superscalar microprocessors is the independence of program-executable codes from their structure and the possibility of their execution on any processor models. In addition, the features of the EPIC architecture are described, which combines the advantages of the two different architectural solutions considered.

APA, Harvard, Vancouver, ISO, and other styles

32

Igene, L., O. Solomon, M. Osifo, and B. E. Akagbosu. "Assessment of Information Needs of Shea Butter Processors’ on Modern Processing Technologies in North Central Agro-Ecological Zone of Nigeria." Sustainable Agriculture Research 8, no. 1 (December 21, 2018): 59. http://dx.doi.org/10.5539/sar.v8n1p59.

Full text

Abstract:

To ensure sustainable shea butter production in North Central Agro-ecological zone of Nigeria using modern shea butter processing technologies necessitated this study. The major objective of the study was to identify the information needs of shea butter processors’ on modern shea butter processing technologies whilst examining the respondents’ socio-economic characteristics, ascertaining their awareness, areas of information needs, sources of information, and perception on the effect of inadequate information on modern processing technologies were the specific objectives. Primary data were collected from 216 processors’ using multi-stage sampling procedure. The data were analysed using descriptive and inferential statistics. Findings revealed that most (90.3%) of the processors’ were females, young and married with little or no formal education and having between 6 to 15 years of processing experience. Respondents obtained information mostly from fellow processors ( =70) and cooperative societies ( = 67). Perceived areas of information need include kneading ( = 89), crushing ( = 88), roasting ( = 85) and milling ( = 84). Perceived effects of inadequate information on modern processing technologies were low yield of shea butter ( = 78), low income ( = 76), and local use of local technologies ( = 71) and poor packaging of shea butter ( = 78). Respondents’ sex (χ2 = 22.076, 0.000), educational level (χ2 = 86.983, 0.000) and years of processing experience (χ2 = 22.076, 0.000) had significant association with their perception of information needs. Creation of awareness on modern shea butter processing technologies through the use of more radio programmes aired at appropriate time and the use of leaflets produced both in English and local languages is recommended.

APA, Harvard, Vancouver, ISO, and other styles

33

Ayanfunke, Tijani Sarafat, and Sanusi Mohammed Kabiru. "Characteristics of shea butter processing in Niger State, Nigeria." Journal of Agricultural Extension 24, no. 4 (October 28, 2020): 53–61. http://dx.doi.org/10.4314/jae.v24i4.6.

Full text

Abstract:

The study examined the characteristics of Shea Butter processing and factors associated with the output in Niger states, Nigeria. Two stage sampling procedure was used to select 315 respondents. Interview schedule was used in data collection. Data collected were analysed with percentages, Chisquare, the Pearson Product Moment Coefficient (PPMC) and simple regression model at α 0.05. The result revealed that the majority (80.6%) of the respondents used semi-mechanised method in processing Shea butter. The average unit price of Shea butter was ₦476.07K per Kilogramme, while the average income was ₦439,650.37K per annum. Processors had low level of accessibility to modern processing technologies (66.2%) and more than half (64.8%) of the processors were producing at low level. Lack of credit facilities and high cost of processing equipment were identified as severe constraint to Shea butter processing. There were significant relationship between level of education (χ²=11.18, p≤0.05), level of engagement (χ²=8.71, p≤0.05), income (r=0.819, p≤0.05) and accessibility to modern Shea butter processing technologies (r=0.164, p≤0.05) with level of Shea butter processing output. The major determinants of Shea butter processing output were income, household size, unit price and accessibility to modern processing technologies. Financial institutions should provide soft loans to Shea butter processors to acquire inputs and equipment. Similarly, government agencies should provide Shea butter processing equipment to the processors to improve access to the technologies that could lead to increase Shea butter production in Niger state. Keywords: Shea butter processing, determinants of processing output, technology accessibility and processors

APA, Harvard, Vancouver, ISO, and other styles

34

Koltakov, S. A., and A. A. Cherepnev. "HARDWARE-SOFTWARE COMPLEX FOR DIGITAL PROCESSING OF HYDROACOUSTIC SIGNALS." Issues of radio electronics, no. 5 (June 8, 2019): 60–63. http://dx.doi.org/10.21778/2218-5453-2019-5-60-63.

Full text

Abstract:

The article describes the hardware‑software complex (HSC) based on the debugging stand, its composition, modules and operations. A method for synthesizing the output signal is described, a formula and a table of parameters for its calculation are given. Signals and spectra at the input and output of the developed HSC are shown. The obtained parameters of the performance of various agribusiness, based on the signal processor with a General‑purpose processor and two variants with General‑purpose processors. The proposed version of the HSC2–3 times wins in performance compared to the HSC based on the general‑ purpose processor of Intel. This is achieved through the use of modern methods and programming tools, digital signal processing modules, as well as the optimization of the executable code. Recommendations for possible further improvement of the proposed complex are given, which is possible due to the use of modern FPGAs and high‑speed interface.

APA, Harvard, Vancouver, ISO, and other styles

35

Abdu-Raheem, K. A., F. M. Oluwatusin, A. O. Kolawole, A. O. Adekunmi, O. C. Ajewole, and F. O. Osundare. "Willingness to Pay for Centralized Modern Locust Bean Processing Equipment in Ekiti State, Nigeria." European Journal of Nutrition & Food Safety 15, no. 7 (June 27, 2023): 42–49. http://dx.doi.org/10.9734/ejnfs/2023/v15i71321.

Full text

Abstract:

This study investigated the propensity to pay for modern apparatus processing locust beans in Ekiti State, Nigeria. Utilizing primary data and a multistage sampling strategy, 240 processors were chosen for the study. The collected data were analyzed utilizing descriptive statistics and an inferential statistical instrument, such as Logit and ordinary least square regression analysis. About 72 percent of processors were married and had an average of eight years of experience processing locust legumes. The majority of respondents belonged to a cooperative group (66.7%) and had no access to credit (100%). The average monthly income from processing was N18,000. The majority of respondents (65%) were unwilling to pay for the service of centralized, advanced or contemporary processing equipment. According to the results of the Logit regression analysis, the variables that significantly influence willingness to pay for the service of centralized modern locust bean processing equipment were household income and processing experience (1%), level of education and age (5%), and household size (10%). The Ordinary Least Square (OLS) analysis reveals that household size and education level were significant at the 1% level, while age and marital status were significant at the 5% level and processing experience was significant at the 1% level. The study suggests that processors ready to pay should form a formidable cooperative to secure grants or loans to establish a centralized, contemporary locust processing cottage. The government should educate processors on modern food processing and safety at all levels.

APA, Harvard, Vancouver, ISO, and other styles

36

Wang, Nenzi, Hsin-Yi Chen, and Yu-Wen Chen. "Fluid-film lubrication computing with many-core processors and graphics processing units." Advances in Mechanical Engineering 10, no. 10 (October 2018): 168781401880471. http://dx.doi.org/10.1177/1687814018804719.

Full text

Abstract:

The advancement of modern processors with many-core and large-cache may have little computational advantages if only serial computing is employed. In this study, several parallel computing approaches, using devices with multiple or many processor cores, and graphics processing units are applied and compared to illustrate the potential applications in fluid-film lubrication study. Two Reynolds equations and an air bearing optimum design are solved using three parallel computing paradigms, OpenMP, Compute Unified Device Architecture, and OpenACC, on standalone shared-memory computers. The newly developed processors with many-integrated-core are also using OpenMP to release the computing potential. The results show that the OpenACC computing can have a better performance than the OpenMP computing for the discretized Reynolds equation with a large gridwork. This is mainly due to larger sizes of available cache in the tested graphics processing units. The bearing design can benefit most when the system with many-integrated-core processor is being used. This is due to the many-integrated-core system can perform computation in the optimization-algorithm-level and using the many processor cores effectively. A proper combination of parallel computing devices and programming models can complement efficient numerical methods or optimization algorithms to accelerate many tribological simulations or engineering designs.

APA, Harvard, Vancouver, ISO, and other styles

37

García, Andrés Amaya, David May, and Ed Nutting. "Integrated Hardware Garbage Collection." ACM Transactions on Embedded Computing Systems 20, no. 5 (July 2021): 1–25. http://dx.doi.org/10.1145/3450147.

Full text

Abstract:

Garbage collected programming languages, such as Python and C#, have accelerated software development. These modern languages increase productivity and software reliability as they provide high-level data representation and control structures. Modern languages are widely used in software development for mobile, desktop, and server devices, but their adoption is limited in real-time embedded systems. There is clear interest in supporting modern languages in embedded devices as emerging markets, like the Internet of Things, demand ever smarter and more reliable products. Multiple commercial and open-source projects, such as Zerynth and MicroPython, are attempting to provide support. But these projects rely on software garbage collectors that impose high overheads and introduce unpredictable pauses, preventing their use in many embedded applications. These limitations arise from the unsuitability of conventional processors for performing efficient, predictable garbage collection. We propose the Integrated Hardware Garbage Collector (IHGC); a garbage collector tightly coupled with the processor that runs continuously in the background. Further, we introduce a static analysis technique to guarantee that real-time programs are never paused by the collector. Our design allocates a memory cycle to the collector when the processor is not using the memory. The IHGC achieves this by careful division of collection work into single-memory-access steps that are interleaved with the processor’s memory accesses. As a result, our collector eliminates run-time overheads and enables real-time program analysis. The principles behind the IHGC can be used in conjunction with existing architectures. For example, we simulated the IHGC alongside the ARMv6-M architecture. Compared to a conventional processor, our experiments indicate that the IHGC offers 1.5–7 times better performance for programs that rely on garbage collection. The IHGC delivers the benefits of garbage-collected languages with real-time performance but without the complexity and overheads inherent in software collectors.

APA, Harvard, Vancouver, ISO, and other styles

38

Adamov, Andrey, Pavel Pavlukhin, Dmitriy Bikonov, Alexey Eisymont, and Leonid Eisymont. "Modern GPGPU Alternative Perspective Universal and Specialized Processors-Accelerators." Voprosy kiberbezopasnosti, no. 4(32) (2019): 13–21. http://dx.doi.org/10.21681/2311-3456-2019-4-13-21.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Refan, Fatemeh, Bijan Alizadeh, and Zainalabedin Navabi. "Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 10 (October 2018): 1845–53. http://dx.doi.org/10.1109/tvlsi.2018.2835833.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Nery, Alexandre S., Lech Jóźwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, and Felipe M. G. França. "Hardware reuse in modern application-specific processors and accelerators." Microprocessors and Microsystems 37, no. 6-7 (August 2013): 684–92. http://dx.doi.org/10.1016/j.micpro.2012.06.005.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Asyaei, Mohammad, and Ali Peiravi. "Low power wide gates for modern power efficient processors." Integration 47, no. 2 (March 2014): 272–83. http://dx.doi.org/10.1016/j.vlsi.2013.08.005.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Ismail, Nabil A. "Evaluation of dynamic branch predictors for modern ILP processors." Microprocessors and Microsystems 26, no. 5 (June 2002): 215–31. http://dx.doi.org/10.1016/s0141-9331(02)00023-6.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Cleemput, Jeroen V., Bart Coppens, and Bjorn De Sutter. "Compiler mitigations for time attacks on modern x86 processors." ACM Transactions on Architecture and Code Optimization 8, no. 4 (January 2012): 1–20. http://dx.doi.org/10.1145/2086696.2086702.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Bate, Iain, and Usman Khan. "WCET analysis of modern processors using multi-criteria optimisation." Empirical Software Engineering 16, no. 1 (June 8, 2010): 5–28. http://dx.doi.org/10.1007/s10664-010-9133-9.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Basoglu, Chris, Yongmin Kim, and Vikram Chalana. "A Real-Time Scan Conversion Algorithm on Commercially Available Microprocessors." Ultrasonic Imaging 18, no. 4 (October 1996): 241–60. http://dx.doi.org/10.1177/016173469601800402.

Full text

Abstract:

We have developed a new ultrasound scan conversion algorithm that can be executed very efficiently on modern microprocessors. Our algorithm is designed to handle the address calculations and input and output (I/O) data loading concurrently with the interpolation. The processing unit's computing power can be dedicated to performing pixel interpolations while the other operations are handled by an independent direct memory access (DMA) controller. By making intelligent use of the I/O transfer capabilities of the DMA controller, the algorithm avoids spending the processing unit's valuable computing cycles in address calculations and nonactive pixel blanking. Furthermore, the new approach speeds up the computation by utilizing the ability of superscalar and very long instruction word (VLIW) processors to perform multiple operations in parallel. Our scan conversion algorithm was implemented on a multimedia and imaging system based on the Texas Instruments TMS320C80 Multimedia Video Processor (MVP). Computing cycles are spent only on predeterminable nonzero output pixels. For example, an execution time of 11.4 ms was achieved when there are 101,829 nonzero output pixels. This algorithm demonstrates a substantial improvement over previous scan conversion algorithms, and its optimized implementation enables modern commercially available programmable processors to support scan conversion at video rates.

APA, Harvard, Vancouver, ISO, and other styles

46

Osundare, Foluso, and Temidayo Olowoyeye. "Assesment of the Behaviour and Investment Preference of Women Cassava Processors in Ekiti State, Nigeria." International Journal of Social Science Research 6, no. 2 (August 26, 2018): 10. http://dx.doi.org/10.5296/ijssr.v6i2.12682.

Full text

Abstract:

The behavior and pattern of investment of cassava processors depends largely on their level of income; the need to assess their investment preference necessitated this study. The research was carried out in Ekiti State Nigeria to describe the socioeconomic characteristics of women cassava processors; examine their investment patterns; determine their propensities to invest and; analyze the factors influencing their investment decision. Information was obtained from a total of 180 women cassava processors through a well-structured questionnaire. A multi-stage sampling technique was used in the selection of respondents. The analytical tools employed were descriptive statistics, Friedman ranking analysis, and Probit regression analysis. The study showed that the mean annual income and investment of respondents were ₦488,750 and ₦164,300 respectively with marginal propensity to invest for every income generated at ₦0.228. The Probit regression analysis showed that the major factors influencing the respondents’ decision to invest in the study area were household size, annual income and return on investment. The studies showed that investment potential not only exists among the women cassava processor in the study area, they were actually investing, but their unwillingness to invest in processing equipment is worrisome. It’s therefore recommended that modern processing facilities should be subsidized to reduce the processing cost, encourage future investment on them, reduce drudgery, increase value addition, income and consequently increased investment. Secondly, soft loans free of collateral should be giving to the processors to facilitate purchase of processing equipment, develop and expand their processing sheds.

APA, Harvard, Vancouver, ISO, and other styles

47

Obisesan, Omobolaji Olubukunmi, Kabir Kayode Salman, Kemisola O. Adenegan, and Ghene Oghenerueme Obi-Egbedi. "Choice of processing techniques among rice processors in Nigeria." World Journal of Entrepreneurship, Management and Sustainable Development 15, no. 1 (February 21, 2019): 70–83. http://dx.doi.org/10.1108/wjemsd-07-2018-0060.

Full text

Abstract:

PurposeRice processing, an important feature in rice production involving the transformation of harvested paddy into edible rice, is dependent on the type of rice processing techniques used. The purpose of this paper is to analyze the choice of processing techniques among rice processors in Nigeria.Design/methodology/approachThe study was carried out in Nigeria using structured questionnaires among 410 rice processors selected from four states (Ebonyi, Ekiti, Ogun and Nasarawa) from three geo-political zones (Southeast, Southwest and North-central) of Nigeria. Information on socio-economic characteristics (age, sex, household size, marital status and education) and processing characteristics (experience, paddy source, processing activities, processing techniques, credit and distance) were obtained. Data were analyzed with the use of descriptive statistics and multinomial logistic regression model at 0.05.FindingsThe mean age of processors was 47.8±9.9 years, mean household size was 6.5±4.2 persons and 88.7 percent were married. In total, 73.6 percent had formal education and mean years of experience was 16.4±9.2 years. Main processing activities were parboiling and drying (50.0 percent); milling (40.0 percent); and de-stoning (10.0 percent). In all, 65.7, 20.4 and 13.9 percent used traditional and modern techniques (TMTs), traditional techniques (TTs) and purely modern techniques (PMTs), respectively. The probability of choice of TT relative to TMT reduced by years of education (4.5 percent), paddy source (1.8 percent) and distance to processing center (4.4 percent), while probability of choice of PMT relative to TMT increased for male processors (7.3 percent), membership of association(18.0 percent) and other income sources (6.2 percent).Research limitations/implicationsLevel of education of processors and reduction in the distance taken to paddy source reduced choice of TTs.Practical implicationsOther income sources increased the choice of PMTs of rice processing in Nigeria.Social implicationsProcessors with high level of education, who also engage in other income generating activities, were able to choose modern processing techniques.Originality/valueThis research was an original research carried out among rice processors in Nigeria.

APA, Harvard, Vancouver, ISO, and other styles

48

Adesope, A. A. A., O. A. Fatoki, and T. O. Oguntoye. "Value Chain and Profitability Analysis of Shea Butter Production in Kwara State, Nigeria." Journal of Agroforestry and Environment 15, no. 2 (December 30, 2022): 91–97. http://dx.doi.org/10.55706/jae1522.

Full text

Abstract:

The study assessed the value chain and economic viability of shea butter production in Kwara State, Nigeria. A well-structured questionnaire was used to gather information from 247 participants in the shea butter value chain industry within the State. Descriptive statistics, gross margin analysis, and linear regression were used to analyze the data gathered. The study found out that the shea nut processors and marketers were women (92%), while men (54,7%) were mostly shea nuts collectors. The average age of collectors was 43 and that of the processors and marketers were 46. Findings also revealed that the shea butter value chain is made up of collectors, assemblers, processors and marketers who perform various functions in getting the butter bye product from the shea nuts to the consumers. According to the profitability analysis that was carried out, the study discovers that the gathering, processing, and sale of shea nuts in the study area were profitable. The gross margin for 100kg of shea nut collected was ₦7,094 (1USD≈450₦) while that of the processors/marketers for 20kg of shea butter produced was ₦16,200. The major constraint facing shea nuts collectors was the felling of shea trees (82.7%) while that of processors/marketers was the lack of modern processing equipment. It is therefore necessary for government to provide credit facilities and modern processing equipment’s for rural women involved in shea butter production to enable them produce in large quantities.

APA, Harvard, Vancouver, ISO, and other styles

49

Batty, Mark. "Compositional relaxed concurrency." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 375, no. 2104 (September 4, 2017): 20150406. http://dx.doi.org/10.1098/rsta.2015.0406.

Full text

Abstract:

There is a broad design space for concurrent computer processors: they can be optimized for low power, low latency or high throughput. This freedom to tune each processor design to its niche has led to an increasing diversity of machines, from powerful pocketable devices to those responsible for complex and critical tasks, such as car guidance systems. Given this context, academic concurrency research sounds notes of both caution and optimism. Caution because recent work has uncovered flaws in the way we explain the subtle memory behaviour of concurrent systems: specifications have been shown to be incorrect, leading to bugs throughout the many layers of the system. And optimism because our tools and methods for verifying the correctness of concurrent code—although built above an idealized model of concurrency—are becoming more mature. This paper looks at the way we specify the memory behaviour of concurrent systems and suggests a new direction. Currently, there is a siloed approach, with each processor and programming language specified separately in an incomparable way. But this does not match the structure of our programs, which may use multiple processors and languages together. Instead we propose a compositional approach, where program components carry with them a description of the sort of concurrency they rely on, and there is a mechanism for composing these. This will support not only components written for the multiple varied processors found in a modern system but also those that use idealized models of concurrency, providing a sound footing for mature verification techniques. This article is part of the themed issue ‘Verified trustworthy software systems’.

APA, Harvard, Vancouver, ISO, and other styles

50

Sovietov, Pyotr Nikolaevich. "Accelerating the Development of DSL Compilers for Specialized Processors." Proceedings of the Institute for System Programming of the RAS 32, no. 5 (2020): 35–56. http://dx.doi.org/10.15514/ispras-2020-32(5)-3.

Full text

Abstract:

Specialized processors programmable in domain-specific languages are increasingly used in modern computing systems. The compiler-in-the-loop approach, based on the joint development of a specialized processor and a compiler, is gaining popularity. At the same time, the traditional tools, like GCC and LLVM, are insufficient for the agile development of optimizing compilers that generate target code of an exotic, irregular architecture with static parallelism of operations. The article proposes methods from the field of program synthesis for the implementation of machine-dependent compilation phases. The phases are based on a reduction to SMT problem which allows to get rid of heuristic and approximate approaches, that requires complex software implementation of a compiler. In particular, a synthesis of machine-dependent optimization rules, instruction selection and instruction scheduling combined with register allocation are implemented with help of SMT solver. Practical applications of the developed methods and algorithms are illustrated by the example of a compiler for a specialized processor with an instruction set that accelerates the implementation of lightweight cryptography algorithms in the Internet of Things. The results of compilation and simulation of 8 cryptographic primitives for 3 variants of specialized processor (CISC-like, VLIW-like and a variant with delayed load instruction) show the vitality of the proposed approach.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Modern processors'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles