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Journal articles on the topic 'Modeling of processor design'

Author: Grafiati

Published: 25 May 2024

Last updated: 31 July 2025

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1

Li, Lei, Hai-bin Shen, Kai Huang, Xiao-lang Yan, Han Sangil, and Ahmed A Jerraya. "Distributed Memory Service Modeling in Multi-Processor Design." Journal of Electronics & Information Technology 30, no. 11 (2011): 2750–54. http://dx.doi.org/10.3724/sp.j.1146.2007.00596.

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2

Lee, Je-Hoon. "Power Modeling Framework for an Asynchronous Processor." Journal of Circuits, Systems and Computers 25, no. 06 (2016): 1650057. http://dx.doi.org/10.1142/s0218126616500572.

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This paper presents two power models for an asynchronous processor, A8051. The first one is a pipeline accurate model which models power consumption at each pipeline stage. The other one is a micro-architectural model which models power consumption at micro-operation level. Then, we demonstrate the feasibility of the proposed approach on an A8051 processor case study. The experimental results based on applying the proposed pipeline-accurate and micro-architectural power models on an A8051 processor demonstrate that the proposed power models have high accuracy with simulation times much faster

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3

Eyerman, Stijn, and Lieven Eeckhout. "Probabilistic job symbiosis modeling for SMT processor scheduling." ACM SIGPLAN Notices 45, no. 3 (2010): 91–102. http://dx.doi.org/10.1145/1735971.1736033.

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LIN, S., Y. CHEN, C. YU, Y. LIU, and C. LEE. "Dynamic modeling and control structure design of an experimental fuel processor." International Journal of Hydrogen Energy 31, no. 3 (2006): 413–26. http://dx.doi.org/10.1016/j.ijhydene.2005.06.027.

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Wu, Wei, Shu-Bo Yang, Jenn-Jiang Hwang, and Xinggui Zhou. "Design, modeling, and optimization of a lightweight MeOH-to-H2 processor." International Journal of Hydrogen Energy 43, no. 31 (2018): 14451–65. http://dx.doi.org/10.1016/j.ijhydene.2018.05.135.

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6

So, Hwisoo, Yohan Ko, Jinhyo Jung, Kyoungwoo Lee, and Aviral Shrivastava. "gemV-tool: A Comprehensive Soft Error Reliability Estimation Tool for Design Space Exploration." Electronics 12, no. 22 (2023): 4573. http://dx.doi.org/10.3390/electronics12224573.

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With aggressive technology scaling, soft errors have become a major threat in modern computing systems. Several techniques have been proposed in the literature and implemented in actual devices as countermeasures to this problem. However, their effectiveness in ensuring error-free computing cannot be ascertained without an accurate reliability estimation methodology. This can be achieved by using the vulnerability metric: the probability of system failure as a function of the time the program data are exposed to transient faults. In this work, we present a gemV-tool, a comprehensive toolset fo

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Kumar, K. S., and J. H. Tracey. "Modeling and Description of Processor-Based Systems with DTMSII." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 1 (1987): 116–27. http://dx.doi.org/10.1109/tcad.1987.1270254.

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8

Martin, Grant. "Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors." Journal of Signal Processing Systems 53, no. 1-2 (2007): 113–27. http://dx.doi.org/10.1007/s11265-007-0153-7.

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Oliveira, Marcio F. da S., Eduardo W. Brião, Francisco A. Nascimento, and Flávio R. Wagner. "Model Driven Engineering for MPSoC Design Space Exploration." Journal of Integrated Circuits and Systems 3, no. 1 (2008): 13–22. http://dx.doi.org/10.29292/jics.v3i1.277.

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This paper presents a Model Driven Engineering approach for MPSoC Design Space Exploration (DSE) to deal with the ever-growing challenge of designing complex embedded systems. This approach allows the designer to automatically select the most adequate modeling solution for application, platform, and mapping between application and platform, in an integrated and simultaneous way and at a very early design stage, before system synthesis and code generation have been performed. The exploration is based on high-level estimates of physical characteristics of each candidate solution. In an experimen

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Martono and Zulfi. "Perancangan Aplikasi Point of Sale (POS) pada Karya Maju Jaya." Jurnal PROCESSOR 17, no. 2 (2022): 114–24. http://dx.doi.org/10.33998/processor.2022.17.2.1266.

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Karya maju jaya is one of the shops that engaged in the provision of services and goods in the form of workshops. Currently at karya maju Jaya, the process of managing transactions and financial reports still uses paper media as a means of storing data, causing many weaknesses in terms of security, effectiveness from the aspect of time, higher costs to the high possibility of errors in processing and processing information. Therefore, the author decided to conduct a research that the author gave the title point of sale (POS) application design on the work of karya maju jaya with the aim of ans

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11

Lakhdara, Zakaria, and Salah Merniz. "A SysML and CLEAN Based Methodology for RISC Processor Micro-Architecture Design." International Journal of Embedded and Real-Time Communication Systems 6, no. 1 (2015): 101–31. http://dx.doi.org/10.4018/ijertcs.2015010105.

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Nowadays, processor micro-architectures are becoming more and more complex. Consequently, designers increasingly need powerful abstraction and structuration mechanisms, as well as design methodologies that automatically and formally derive low-level concrete designs from high-level abstract ones. In this context, this paper proposes a methodology for RISC processor micro-architecture design. The proposed methodology uses mainly SysML to model both ISA and MA levels and the functional language CLEAN to describe them. Functional specifications in CLEAN are automatically generated from the ISA an

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12

Prado, Bruno, Edna Barros, Thiago Figueredo, and André Aziz. "HdSC: A Fast and Preemptive Modeling for on Host HdS Development." Journal of Integrated Circuits and Systems 7, no. 1 (2012): 61–71. http://dx.doi.org/10.29292/jics.v7i1.356.

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In modern embedded systems, the Hardware-dependent Software (HdS) plays a critical role due to its processor and platform dependency, such as device drivers and boot initialization. To support HdS development starting in an initial system design phase, fast and accurate preemptive processor models should be provided for simulating the software. These models should provide a register level interface to enable a compatible programming view on the host machine environment. This paper presents a strategy for processor modeling that enables HdS development, using the host machine tool chain. The pr

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13

Fleury, M., A. C. Downton, and A. F. Clark. "Modelling pipelines for embedded parallel processor system design." Electronics Letters 33, no. 22 (1997): 1852. http://dx.doi.org/10.1049/el:19971249.

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14

Eeckhout, Lieven, Robert H. Bell Jr., Bastiaan Stougie, Koen De Bosschere, and Lizy K. John. "Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies." ACM SIGARCH Computer Architecture News 32, no. 2 (2004): 350. http://dx.doi.org/10.1145/1028176.1006730.

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15

Conte, T. M., K. N. Menezes, S. W. Sathaye, and M. C. Toburen. "System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, no. 2 (2000): 129–37. http://dx.doi.org/10.1109/92.831433.

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16

Chakraborty, Bidesh, Mamata Dalui, and Biplab K. Sikdar. "Design of a Reliable Cache System for Heterogeneous CMPs." Journal of Circuits, Systems and Computers 27, no. 14 (2018): 1850219. http://dx.doi.org/10.1142/s0218126618502195.

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The embedded system-on-a-chip (SoC), that integrates heterogeneous processors with variation in coherence protocol, adds complexity in maintaining coherency in the data caches. It further complicates the task of coherence verification in such systems. This work targets effective solution for coherence verification in heterogeneous chip multiprocessors (CMPs) through introduction of highly efficient verification unit. It is developed around the modeling tool of cellular automaton (CA) invented by von Neumann in 1950s. The modular and cascadable structure of CA ensures high scalability and robus

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Fleury, M., R. P. Self, and A. C. Downton. "Large-Scale, Parallel Embedded Applications: A Hardware Design Model for Software Engineers." International Journal of Electrical Engineering & Education 38, no. 4 (2001): 348–67. http://dx.doi.org/10.7227/ijeee.38.4.8.

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Parallel servers are becoming an important sector in the embedded systems marketplace. If software engineers are to implement the multi-algorithm applications that these servers support, then educators should provide clear design routes which inculcate system-level thinking. Pipelined Processor Farms (PPF) is one such top-down design strategy. The contemporary hardware diversity within both processor- and instruction-level parallellism requires incorporation of a coprocessor model at the node or sub-system layer. Two suitable software-based approaches are reviewed: one which maintains the trad

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18

Mukherji, Rana, and Manishita Das. "System Level Modeling Methodology of Application Specific Instruction Set Processor (Asip) Using Systemc." DIU Journal of Science & Technology 7, no. 1 (2024): 44–49. https://doi.org/10.5281/zenodo.13733703.

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In recent years, the development of application specific instruction set processors (ASIP) is the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that constructing such architecture is a difficult assignment that needs skilled knowledge in distinct domains: application software development tools, processor hardware implementation, and system integration and verification. To specify the design and implementation of such systems and incorporate the functionality implemented in both hardware and software forms, we are compelled to move on from traditional Ha

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19

Gadag, Shiva P., Susan K. Patra, Volkan Ozguz, Phillipe Marchand, and Sadik Esener. "Design and Analysis: Thermal Emulator Cubes for Opto-Electronic Stacked Processor." Journal of Electronic Packaging 124, no. 3 (2002): 198–204. http://dx.doi.org/10.1115/1.1481894.

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3D finite element modeling of thermal emulator cube and its composition consisting of composite stack of multi-layer chip are developed. Thermal analysis of the Multi-Chip Module consisting of 16 alternate layers Si processor and heat sink layers with Si spacers and AlN ceramic cap is undertaken. The various alternatives for design of the emulator cubes such as thermal cube floating in free-space, thermal cube-on-substrate, thermal cube-on-flex cable with a continuous joint of solder and thermal cube embedded in rectangular Si-spacer are investigated for their heat extraction capability. Therm

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20

Uma, S., and P. Sakthivel. "Hardware Evaluation and Software Framework Construction for Performance Measurement of Embedded Processor." Journal of Computational and Theoretical Nanoscience 15, no. 2 (2018): 586–94. http://dx.doi.org/10.1166/jctn.2018.7126.

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A frame work for analysing the capabilities and area of improvements for working of an embedded processor is constructed, and also a methodology for comparative study of simulation of processor on load and hardware results are explained in this paper. The processor can be modelled as a standalone processor or as a group of processors working together to take parallel program execution mode. The proposed frame work and simulation method uses the processor representation of current embedded processor model which is relevant in product design and devices modelling. This system utilizes the ARM pr

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21

Knopf, George K., and Madan M. Gupta. "Design of a multitask neurovision processor." Journal of Mathematical Imaging and Vision 2, no. 2-3 (1992): 233–50. http://dx.doi.org/10.1007/bf00118592.

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22

Jain, Abhishek, and Richa Gupta. "Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors." VLSI Design 2016 (September 26, 2016): 1–14. http://dx.doi.org/10.1155/2016/7283471.

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In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP) RTL and firmware development. In this paper, we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW) implementation, reference for firmware (FW) implementation, and bit-true certificat

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23

Reshadi, Mehrdad, Bita Gorjiara, and Nikil D. Dutt. "Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 12 (2006): 2904–18. http://dx.doi.org/10.1109/tcad.2006.882597.

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24

Pon Pushpa, S. Ewins, and Manamalli Devasikamani. "Schedulability Analysis for Rate Monotonic Algorithm-Shortest Job First Using UML-RT." Modelling and Simulation in Engineering 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/206364.

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System modelling with a unified modelling language (UML) is an active research area for developing real-time system development. UML is widely used modelling language in software engineering community, to specify the requirement, and analyse the target system successfully. UML can be used to provide multiple views of the system under design with the help of a variety of structural and behavioural diagrams at an early stage. UML-RT (unified modelling language-real time) is a language used to build an unambiguous executable specification of a real-time system based on UML concepts. This paper pr

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25

Kim, Sung Je, and Young Man Cho. "Optimal design of a rapid thermal processor via physics-based modeling and convex optimization." Control Engineering Practice 10, no. 11 (2002): 1199–210. http://dx.doi.org/10.1016/s0967-0661(02)00098-9.

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26

Yao, Wu-Sung. "Modeling and stabilization of eccentric gravity machinery." Advances in Mechanical Engineering 10, no. 1 (2018): 168781401775178. http://dx.doi.org/10.1177/1687814017751782.

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In general, eccentric gravity machinery is a rotation mechanism with eccentric pendulum mechanism, which can be used to convert continuously kinetic energy generated by gravity energy to electric energy. However, a stable rotated velocity of the eccentric gravity machinery is difficult to be achieved only using gravity energy. In this article, a stable velocity control system applied to eccentric gravity machinery is proposed. The dynamic characteristic of eccentric gravity machinery is analyzed and its mathematical model is established, which is used to design the controller. A stable running

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27

Zou, An, Huifeng Zhu, Jingwen Leng, et al. "System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System." ACM Transactions on Architecture and Code Optimization 18, no. 4 (2021): 1–27. http://dx.doi.org/10.1145/3468145.

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Despite being employed in numerous efforts to improve power delivery efficiency, the integrated voltage regulator (IVR) approach has yet to be evaluated rigorously and quantitatively in a full power delivery system (PDS) setting. To fulfill this need, we present a system-level modeling and design space exploration framework called Ivory for IVR-assisted power delivery systems. Using a novel modeling methodology, it can accurately estimate power delivery efficiency, static performance characteristics, and dynamic transient responses under different load variations and external voltage/frequency

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28

Zhang, Qi, and Wenhui Pei. "DSP Processer-in-the-Loop Tests Based on Automatic Code Generation." Inventions 7, no. 1 (2022): 12. http://dx.doi.org/10.3390/inventions7010012.

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The digital signal processing (DSP) processor-in-the-loop tests based on automatic code generation technology are studied. Firstly, the idea of model-based design is introduced, and the principle and method of embedded code automatic generation technology are analyzed by taking the automatic code generation of the DSP control algorithm for pulse width modulation (PWM) output as an example. Then, the control system model is established on MATLAB/Simulink. After verifying the model through simulation, the target board platform is established with DSP as the core processor, and the automatically

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29

Chadha, Ankit, Shreyas Gaonkar, and Aditi Desai. "Design, Modeling and Implementation of 8-bit Processor for Intelligent Automatic Chocolate Vending Machine (AVM)." International Journal of Computer Applications 89, no. 17 (2014): 1–7. http://dx.doi.org/10.5120/15720-4549.

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30

Yurovych, Ivan, and Vladimir Zaitsev. "Method of determining timing parameters of real time systems." Management of Development of Complex Systems, no. 59 (September 27, 2024): 148–54. http://dx.doi.org/10.32347/2412-9933.2024.59.148-154.

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Real-time systems are widely used and actively implemented in advanced developments across many industries, from medicine to aerospace. Research and modelling of real-time systems are crucial tasks at the design stage, as they help in the determination of whether the system being modelled meets the specified timing characteristics and, accordingly, assess the system's ability to satisfy timing requirements. After all, the success of a real-time system depends not only on their logical correctness but also on the time it takes for the system to generate a result. Considering the various types o

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Ogbodo, Mark, Khanh Dang, Fukuchi Tomohide, and Abderazek Abdallah. "Architecture and Design of a Spiking Neuron Processor Core Towards the Design of a Large-scale Event-Driven 3D-NoC-based Neuromorphic Processor." SHS Web of Conferences 77 (2020): 04003. http://dx.doi.org/10.1051/shsconf/20207704003.

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Neuromorphic computing tries to model in hardware the biological brain which is adept at operating in a rapid, real-time, parallel, low power, adaptive and fault-tolerant manner within a volume of 2 liters. Leveraging the event driven nature of Spiking Neural Network (SNN), neuromorphic systems have been able to demonstrate low power consumption by power gating sections of the network not driven by an event at any point in time. However, further exploration in this field towards the building of edge application friendly agents and efficient scalable neuromorphic systems with large number of sy

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Telmanov, Merlan, Mikhail Suchkov, Zukhra Abdiakhmetova, and Amandyk Kartbayev. "Strategic processor task allocation through game-theoretic modeling in distributed computing environments." Bulletin of Electrical Engineering and Informatics 14, no. 2 (2025): 1371–80. https://doi.org/10.11591/eei.v14i2.9257.

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This paper explores a game-theoretic model for task allocation in distributed systems, where processors with varying speeds and external load factors are considered strategic players. The goal is to understand the impact of processors' strategic behaviors on workload management and overall system efficiency, focusing on the attainment of a pure strategy Nash Equilibrium (NE). The research rigorously develops a formal mathematical model and validates it through extensive simulations, highlighting how NE ensures stability but may not always yield optimal system performance. The adaptive algorith

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Liu, Shaohan, and Dake Liu. "Design Space Exploration of 1-D FFT Processor." Journal of Signal Processing Systems 90, no. 11 (2018): 1609–21. http://dx.doi.org/10.1007/s11265-018-1393-4.

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34

Ziolek, Scott A., and Pieter C. Kruithof. "Human Modeling & Simulation: A Primer for Practitioners." Proceedings of the Human Factors and Ergonomics Society Annual Meeting 44, no. 38 (2000): 825–27. http://dx.doi.org/10.1177/154193120004403839.

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More and more, digital human modeling and simulation is being used in conjunction with CAD systems to address ergonomic issues early within the development and manufacturing process. However, purchasing a human modeling software package does not guarantee a user-centered design anymore than purchasing a word processor makes someone an author. This paper addresses some of the practical issues that confront human modeling and simulation users, including the collection of geometry, posturing the manikin, and selection of an analysis. For the purposes of discussion, human simulation will be divide

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35

Srinivasan, V. Prasanna, and A. P. Shanthi. "A BBN-Based Framework for Design Space Pruning of Application Specific Instruction Processors." Journal of Circuits, Systems and Computers 25, no. 04 (2016): 1650028. http://dx.doi.org/10.1142/s0218126616500286.

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During the synthesis phase of the embedded system design process, the designer has to take early decisions for selecting the optimal system components such as processors, memories, communication interfaces, etc. from the available huge design alternatives. In order to obtain the optimal design configurations from the available huge design alternatives, an efficient design space pruning technique that will ease the design space exploration (DSE) process is required. The knowledge about the target architectural parameters affecting the overall objectives of the system should be considered during

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36

Duan, Feng Yang, Li Min Chang, and Ye Zhan. "Realization of the Detecting Method for Aircraft Digital Image Transmission System Based on Multi-Processor." Advanced Materials Research 490-495 (March 2012): 2352–56. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2352.

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The technologies of image block, pyramid and multi-threading were used in this program to design the high-speed image generation display module and the processes of image data scheduling and mapping and solve the problems of large-capacity image data modeling and high-speed displaying. The technology of direct digital frequency synthesis (DDS) was used to design the Doppler shifting signal generation module and the multi-processor parallel system architecture, which can analog the Doppler frequency shifting of the data communication signals and solve the problem of the authenticity of communic

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37

Garrett, James H., and Steven J. Fenves. "A knowledge-based standards processor for structural component design." Engineering with Computers 2, no. 4 (1987): 219–38. http://dx.doi.org/10.1007/bf01276414.

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38

Hamblen, James O. "Using Vhdl Based Modeling, Synthesis, and Simulation in an Introductory Computer Architecture Laboratory." International Journal of Electrical Engineering & Education 33, no. 3 (1996): 251–60. http://dx.doi.org/10.1177/002072099603300306.

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Using VHDL based modelling, synthesis, and simulation in an introductory computer architecture laboratory In many existing curricula, there is a notable lack of recent research advances in CAD tools and rapid prototyping using logic synthesis. This paper describes a novel introductory computer architecture laboratory that utilizes these new developments. VHDL based logic synthesis and timing simulations are used to design a RISC processor.

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Ugwueze, Ogechukwu Kingsley, Chijindu C. V., Udeze C. C., et al. "Modeling cache performance for embedded systems." Bulletin of Electrical Engineering and Informatics 10, no. 5 (2021): 2910–20. http://dx.doi.org/10.11591/eei.v10i5.2459.

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This paper presents a cache performance model for embedded systems. The need for efficient cache design in embedded systems has led to the exploration of various methods of design for optimal cache configurations for embedded processor. Better users’ experiences are realized by improving performance parameters of embedded systems. This work presents a cache hit rate estimation model for embedded systems that can be used to explore optimal cache configurations using Bourneli’s binomial cumulative probability based on application of reuse distance profiles. The model presented was evaluated usin

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Sarigul, N., M. Jin, G. R. Kolar, and H. A. Kamel. "Design of array processor software for nonlinear structural analysis." Computers & Structures 20, no. 6 (1985): 963–74. http://dx.doi.org/10.1016/0045-7949(85)90016-1.

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BAHN, JUN HO, SEUNG EUN LEE, YOON SEOK YANG, JUNGSOOK YANG, and NADER BAGHERZADEH. "ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE." Parallel Processing Letters 18, no. 02 (2008): 239–55. http://dx.doi.org/10.1142/s0129626408003363.

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As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either traditional or multi-layer bus architectures because of their poor scalability and bandwidth limitation on a single bus. While new interconnection techniques have been explored to overcome such a limitation, the notion of utilizing Network-on-Chip (NoC) technologies for the future generation of high performance and low power chips for myriad of applications, in particular for wireless communication and multimedia proc

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Zhang, Zeng Nian, Zun Yi Wang, Mian Mian Chen, and Jiong Shi. "Intelligent Transportation Video Detecting System Based on DSP." Applied Mechanics and Materials 701-702 (December 2014): 498–504. http://dx.doi.org/10.4028/www.scientific.net/amm.701-702.498.

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This paper proposes a method of realizing a moving vehicle video detecting system based on DSP processor, and describes the system's hardware architecture and software design in detail. Based on the characteristic of dual-core of DM6437 processor, the methods of communication protocol between ARM and DSP, as well as the double-buffer switching method are presented. Background modeling is made on the traffic video data from DM6437 via difference accumulation. Background subtraction is used to detect vehicle movement areas. With the adoption of algorithms such as Otsu, morphological filtering an

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KIM, H. Y. "Trace-Driven Performance Simulation Modeling for Fast Evaluation of Multimedia Processor by Simulation Reuse." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 12 (2005): 3306–14. http://dx.doi.org/10.1093/ietfec/e88-a.12.3306.

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Zeba, khan, and Vinod Kapse Dr. "DDR-SDRAM Controller ASIC Design for High Speed Interfacing." International Journal of Advanced and Innovative Research 7, no. 2 (2018): 46–50. https://doi.org/10.5281/zenodo.1184886.

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The goal of this work is to develop DRAM controller between Main Processor and the main memory for fast interfacing of the data and this is achieved with the help of a new Super Harvard type of interfacing parallel interfacing for the data, program data and instructions, also the proposed work used four stage pipelining to achieve high throughput and high speed interfacing. Vertex Corse grain FPGA has been used for the design of the work hence the area can be minimized also the mix modeling architecture is been used. The architecture is designed in Xilinx EDA using Verilog HDL and verification

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Bai, Mingsian R., and Kwuen-Yieng Ou. "Design and Implementation of Electromagnetic Active Control Actuators." Journal of Vibration and Control 9, no. 8 (2003): 997–1017. http://dx.doi.org/10.1177/10775463030098006.

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We present the modeling, parameter identification and design procedure of a linear voice-coil motor. A numerical simulation has been carried out to facilitate system integration. In particular, we use electromechanical analogy and the time-domain identification procedure with the eigensystem realization algorithm to predict the system response. In order to evaluate the performance of the voice-coil motor, we conducted an experimental investigation. Voice-coil motors mounted on a ball bearing housing are used for generating counter forces to cancel the transverse vibrations of a shaft. A contro

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Dzitac, Pavel, and Md Mazid Abdul. "Modeling of an Object Manipulation Motion Planner and Grasping Rules." Applied Mechanics and Materials 278-280 (January 2013): 664–72. http://dx.doi.org/10.4028/www.scientific.net/amm.278-280.664.

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This paper presents the development of a Motion Planning Module for object manipulation, which is a part of previously developed robotic grasping and manipulation controller. The Motion Planning Module consists of a sensing processor, decision making module, instinctive controller, motion planner and a planned motion controller. Details related to the design and modelling of the motion planning module have been offered. Results of experiments on human grasping rule, suitable for the grasping and manipulation controller, have been discussed. The output of this research may be useful to those de

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ISKANDARANI, MAHMOUD Z. "MATHEMATICAL MODELING OF THE PROGRAMING FIELD IN A NEURAL SWITCH USING THE SEMI-INFINITE COPLANAR ELECTRODE APPROXIMATION." Advances in Complex Systems 09, no. 03 (2006): 193–207. http://dx.doi.org/10.1142/s021952590600080x.

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The design and mathematical modeling of the programing electric field in a neural switch is carried out. The specified function for the switch is to operate as a synaptic processor behaving in an adaptive manner and suitable to be used as a compact programable device with other artificial neural network hardware. Modeling of the switch is carried out by means of complex mathematical analysis employing the Schwarz–Christoffel transform. The effect of inter-electrode separation on the field strength is analyzed in two dimensions. The realized power law function of the programing field is discuss

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Haj Ahmad, Hanan, Ehab M. Almetwally, and Dina A. Ramadan. "Investigating the Relationship between Processor and Memory Reliability in Data Science: A Bivariate Model Approach." Mathematics 11, no. 9 (2023): 2142. http://dx.doi.org/10.3390/math11092142.

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Modeling the failure times of processors and memories in computers is crucial for ensuring the reliability and robustness of data science workflows. By understanding the failure characteristics of the hardware components, data scientists can develop strategies to mitigate the impact of failures on their computations, and design systems that are more fault-tolerant and resilient. In particular, failure time modeling allows data scientists to predict the likelihood and frequency of hardware failures, which can help inform decisions about system design and resource allocation. In this paper, we a

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A S, Asif Ahmad. "A Cost Effective DVI interface on Virtex-5 FPGA Through Verilog HDL." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, no. 2 (2014): 4230–36. http://dx.doi.org/10.24297/ijct.v13i2.2905.

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There is a definite need for video and image processing technologies in today's world. However the computer vision technologies need to be tested and optimized. There is need for testing these interfaces for the platform which we work on. This modeling is a cost effective architecture for interfacing Digital Visual Interface(DVI) on Virtex5 FPGA's. The architecture is modeled in such a way that it does not use XPS micro blaze or Power PCÂ processor but simple pixel feeder design, configuration of the Chrontel 7301C chip design and the interface between them.

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Zaitsev, Vladimir, and Evgeniy Tsybaev. "Estimation of timing characteristics in real-time computer systems using Petri nets." Management of Development of Complex Systems, no. 54 (June 2, 2023): 48–62. http://dx.doi.org/10.32347/2412-9933.2023.54.48-62.

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The work is devoted to the problem of determining the time characteristics of tasks in real-time systems, the success of which depends not only on their logical correctness, but also on the time for which they receive the result. Determining such time characteristics of the system at the design stage is a rather difficult problem. Its solution is currently based on the use of two main methods: theoretical calculations related to the calculation of the so-called feasibility criteria and modeling of the system's operation on models. Among the models, statistical models of mass service systems ar

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