Dissertations / Theses on the topic 'Mixed analogue digital integrate circuit'
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Garagate, C. "Simulation backplane : an integrated environment for mixed-mode simulation of multiple analogue, digital and behavioural circuit simulators." Thesis, University of Southampton, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241981.
Full textChang, Yu-Hsu Henry. "Macromodeling and simulation of high-performance mixed Analog/Digital circuits /." Thesis, Connect to this title online; UW restricted, 1994. http://hdl.handle.net/1773/5956.
Full textWemple, Ivan L. "Parasitic substrate modeling for monolithic mixed analog/digital circuit design and verification /." Thesis, Connect to this title online; UW restricted, 1996. http://hdl.handle.net/1773/5944.
Full textKasturi, Prasan. "A CAD tool for analog and mixed signal CMOS circuits /." View online ; access limited to URI, 2006. http://0-digitalcommons.uri.edu.helin.uri.edu/dissertations/AAI3248232.
Full textHirschman, Karl D. "Process development of an analog/digital mixed-mode BiCMOS system at RIT /." Online version of thesis, 1992. http://hdl.handle.net/1850/11238.
Full textVALLICELLI, ELIA ARTURO. "Design of Mixed-Signal Electronic Instrumentation for Proton Sound Detectors." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2021. http://hdl.handle.net/10281/301978.
Full textAcoustic proton range experimental verification technique (iono-acoustics) is based on sensing the weak thermoacoustic signal emitted by the fast energy deposition (and/or the heating process) at the end of the beam range (Bragg Peak). In this context, this thesis presents the main characteristics of the micro-electronics instrumentation used for proton sound detectors introducing specific design techniques strongly oriented to both maximization of the acoustic Signal-to-Noise-Ratio (at the Acoustic Sensor level) and Noise-Figure minimization (at analog amplifier level). The first part of this thesis addresses all the instrumentation challenges related to iono-acoustic experiments providing specific technical details regarding both acoustic sensor design (i.e. how to build the sensor while maximizing the SNR) and the LNA design. The experimental results of a first experiment carried out at Maier-Leibniz Laboratory in Garching, Munich, with a proton beam at 20 MeV (sub-clinical energy) will be presented and it will be shown how a dedicated mixed-signal electronics design allows to significantly improve the signal-to-noise ratio and the accuracy of the BP localization by 6 dB. In this context, this first detector development achieves two important objectives: the improvement of the acoustic SNR and a strong simplification of the detector instrumentation w.r.t. state-of-the-art, enabling increasing accuracy of the acoustic pulse measurement, and at the same time the portability and compactness of the device. In clinical hadron-therapy applications, variable beam energy (from 65 MeV up to 200 MeV) and variable doses are used as a function of the selected medical treatment. This induces different acoustic pulses amplitude and bandwidth, forcing advanced technological solutions capable of handling a wide spectrum of signals in terms of bandwidth, amplitude, and noise. For this reason, the second part of this thesis proposes an efficient and innovative Matlab Model of the ionoacoustic physical phenomenon, based on englobing in a single mathematical Linear-Time-Invariant-System all energy conversion processes involved in iono-acoustics. The proposed ionoacoustics model replaces classical and complex simulation tools (used to characterize the proton induced acoustic signal) and facilitates the development of dedicated detectors. Finally, the design of a second version of the Proton Sound Detector will be presented that introduces the concept of space-domain averaging (instead of time-domain averaging based on multiple beam shot processing for noise attenuation and thus extra-doses). This detector uses a multi-channel sensor to perform a spatial average of the acquired signals and increase the SNR by 18 dB at the same dose compared to the classic single channel approach. This approach however requires the development of highly miniaturized electronics that cannot be implemented with off-the-shelf components on Printed Circuit Boards. The design and characterization of a multichannel analog front-end implemented on a CMOS 28 nm Application-Specified-Integrated-Circuit (ASIC) which allows to process the 64 channels of the acoustic sensor in parallel is then presented. This High-Resolution Proton Sound Detector (HR-ProSD) is completed by digital circuits implemented on Field Programmable Gate Array (FPGA) that allow to locate in real time the deposition of energy in space.
Toner, Michael F. "MADBIST : a scheme for built-in self-test of mixed analog-digital integrated circuits." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=40451.
Full textal-Sarʻāwī, Said Fares. "Design techniques for low power mixed analog-digital circuits with application to smart wireless systems /." Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.
Full textHedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology." Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.
Full textQC 20170905
Sadeghifar, Mohammad Reza. "On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters." Licentiate thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114274.
Full textKorhonen, E. (Esa). "On-chip testing of A/D and D/A converters:static linearity testing without statistically known stimulus." Doctoral thesis, University of Oulu, 2010. http://urn.fi/urn:isbn:9789514263064.
Full textOliveira, Vlademir de Jesus Silva [UNESP]. "Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS." Universidade Estadual Paulista (UNESP), 2009. http://hdl.handle.net/11449/100280.
Full textConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS...
In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture
Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
Full textOliveira, Vlademir de Jesus Silva. "Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS /." Ilha Solteira : [s.n.], 2009. http://hdl.handle.net/11449/100280.
Full textBanca: Suely Cunha Amaro Mantovani
Banca: Jozué Vieira Filho
Banca: Marcelo Arturo Jara Perez
Banca: Paulo Augusto Dal fabbro
Resumo: Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS... (Resumo completo, clicar acesso eletrônico abaixo)
Abstract: In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture
Doutor
Douglas, Dale Scott. "Flicker noise in cmos lc oscillators." Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26550.
Full textChitnis, Danial. "Single photon avalanche diodes for optical communications." Thesis, University of Oxford, 2013. http://ora.ox.ac.uk/objects/uuid:5fd582dd-8167-4fe4-88f8-871ba905ade1.
Full textOpperman, Tjaart Adriaan Kruger. "A 5 GHz BiCMOS I/Q VCO with 360° variable phase outputs using the vector sum method." Diss., Pretoria : [s.n.], 2009. http://upetd.up.ac.za/thesis/available/etd-04082009-171225/.
Full textIncludes summaries in Afrikaans and English. Includes bibliographical references (leaves [74]-78). Mode of access: World Wide Web.
Reddy, Reeshen. "Spurious free dynamic range enhancement of high-speed integrated digital to analogue converters using bicmos technology." Diss., 2015. http://hdl.handle.net/2263/48947.
Full textDissertation (MEng)--University of Pretoria, 2015.
Electrical, Electronic and Computer Engineering
MEng
Unrestricted
"High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems." Doctoral diss., 2017. http://hdl.handle.net/2286/R.I.44261.
Full textDissertation/Thesis
Doctoral Dissertation Electrical Engineering 2017
al-Sarʻāwī, Said Fares. "Design techniques for low power mixed analog-digital circuits with application to smart wireless systems." 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.
Full textLata, Kusum. "Formal Verification Of Analog And Mixed Signal Designs Using Simulation Traces." Thesis, 2010. http://etd.iisc.ernet.in/handle/2005/1271.
Full textElshazly, Amr. "Performance enhancement techniques for low power digital phase locked loops." Thesis, 2012. http://hdl.handle.net/1957/31116.
Full textGraduation date: 2013
Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014
Radic, Aleksandar. "Practical Volume-reduction Strategies for Low-power High-frequency Switch Mode Power Supplies." Thesis, 2014. http://hdl.handle.net/1807/44131.
Full textKäberlein, Andreas. "Entwurf eines ADCs in einer 0.35μm Technologie." 2012. https://monarch.qucosa.de/id/qucosa%3A33505.
Full text