Relevant bibliographies by topics / Micro-Architectural Attacks

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  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Micro-Architectural Attacks'

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Published: 1 February 2025

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Journal articles on the topic "Micro-Architectural Attacks"

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Alam, Manaar, Sarani Bhattacharya, and Debdeep Mukhopadhyay. "Victims Can Be Saviors." ACM Journal on Emerging Technologies in Computing Systems 17, no. 2 (April 2021): 1–31. http://dx.doi.org/10.1145/3439189.

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Micro-architectural side-channel attacks are major threats to the most mathematically sophisticated encryption algorithms. In spite of the fact that there exist several defense techniques, the overhead of implementing the countermeasures remains a matter of concern. A promising strategy is to develop online detection and prevention methods for these attacks. Though some recent studies have devised online prevention mechanisms for some categories of these attacks, still other classes remain undetected. Moreover, to detect these side-channel attacks with minimal False Positives is a challenging effort because of the similarity of their behavior with computationally intensive applications. This article presents a generalized machine learning--based multi-layer detection technique that targets these micro-architectural side-channel attacks, while not restricting its attention only on a single category of attacks. The proposed mechanism gathers low-level system information by profiling performance counter events using Linux perf tool and then applies machine learning techniques to analyze the data. A novel approach using time-series analysis of the data is implemented to find out the correlation of the execution trace of the attack process with the secret key of encryption, which helps in dealing with False-Positives and unknown attacks. This article also provides a detailed theoretical analysis of the detection mechanism of the proposed model along with its security analysis. The experimental results show that the proposed method is superior to the state-of-the-art reported techniques with high detection accuracy, low False Positives, and low implementation overhead while being able to detect before the completion of the attack.
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Polychronou, Nikolaos-Foivos, Pierre-Henri Thevenon, Maxime Puys, and Vincent Beroulle. "A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms." ACM Transactions on Design Automation of Electronic Systems 27, no. 1 (January 31, 2022): 1–35. http://dx.doi.org/10.1145/3471936.

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With the advances in the field of the Internet of Things (IoT) and Industrial IoT (IIoT), these devices are increasingly used in daily life or industry. To reduce costs related to the time required to develop these devices, security features are usually not considered. This situation creates a major security concern. Many solutions have been proposed to protect IoT/IIoT against various attacks, most of which are based on attacks involving physical access. However, a new class of attacks has emerged targeting hardware vulnerabilities in the micro-architecture that do not require physical access. We present attacks based on micro-architectural hardware vulnerabilities and the side effects they produce in the system. In addition, we present security mechanisms that can be implemented to address some of these attacks. Most of the security mechanisms target a small set of attack vectors or a single specific attack vector. As many attack vectors exist, solutions must be found to protect against a wide variety of threats. This survey aims to inform designers about the side effects related to attacks and detection mechanisms that have been described in the literature. For this purpose, we present two tables listing and classifying the side effects and detection mechanisms based on the given criteria.
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Xiong, Wenjie, and Jakub Szefer. "Survey of Transient Execution Attacks and Their Mitigations." ACM Computing Surveys 54, no. 3 (June 2021): 1–36. http://dx.doi.org/10.1145/3442479.

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Transient execution attacks, also known as speculative execution attacks, have drawn much interest in the last few years as they can cause critical data leakage. Since the first disclosure of Spectre and Meltdown attacks in January 2018, a number of new transient execution attack types have been demonstrated targeting different processors. A transient execution attack consists of two main components: transient execution itself and a covert channel that is used to actually exfiltrate the information.Transient execution is a result of the fundamental features of modern processors that are designed to boost performance and efficiency, while covert channels are unintended information leakage channels that result from temporal and spatial sharing of the micro-architectural components. Given the severity of the transient execution attacks, they have motivated computer architects in both industry and academia to rethink the design of the processors and to propose hardware defenses. To help understand the transient execution attacks, this survey summarizes the phases of the attacks and the security boundaries across which the information is leaked in different attacks.This survey further analyzes the causes of transient execution as well as the different types of covert channels and presents a taxonomy of the attacks based on the causes and types. This survey in addition presents metrics for comparing different aspects of the transient execution attacks and uses them to evaluate the feasibility of the different attacks. This survey especially considers both existing attacks and potential new attacks suggested by our analysis. This survey finishes by discussing different mitigations that have so far been proposed at the micro-architecture level and discusses their benefits and limitations.
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Sepúlveda, Johanna, Mathieu Gross, Andreas Zankl, and Georg Sigl. "Beyond Cache Attacks." ACM Transactions on Embedded Computing Systems 20, no. 2 (March 2021): 1–23. http://dx.doi.org/10.1145/3433653.

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System-on-Chips (SoCs) are a key enabling technology for the Internet-of-Things (IoT), a hyper-connected world where on- and inter-chip communication is ubiquitous. SoCs usually integrate cryptographic hardware cores for confidentiality and authentication services. However, these components are prone to implementation attacks. During the operation of a cryptographic core, the secret key may passively be inferred through cache observations. Access-driven attacks exploiting these observations are therefore a vital threat to SoCs operating in IoT environments. Previous works have shown the feasibility of these attacks in the SoC context. Yet, the SoC communication structure can be used to further improve access-based cache attacks. The communication attacks are not as well-understood as other micro-architectural attacks. It is important to raise the awareness of SoC designers of such a threat. To this end, we present four contributions. First, we demonstrate an improved Prime+Probe attack on four different AES-128 implementations (original transformation tables,T0-Only,T2KB, and S-Box). As a novelty, this attack exploits the collisions of the bus-based SoC communication to further increase its efficiency. Second, we explore the impact of preloading on the efficiency of our communication-optimized attack. Third, we integrate three countermeasures (shuffling,mini-tables, andTime-Division Multiple Access (TDMA) bus arbitration) and evaluate their impact on the attack. Althoughshufflingandmini-tablescountermeasures were proposed in previous work, their application as countermeasures against the bus-based attack was not studied before. In addition, TDMA as a countermeasure for bus-based attacks is an original contribution of this work. Fourth, we further discuss the implications of our work in the SoC design and its perspective with the new cryptographic primitives proposed in the ongoing National Institute of Standard and Technology Lightweight Cryptography competition. The results show that our improved communication-optimized attack is efficient, speeding up full key recovery by up to 400 times when compared to the traditional Prime+Probe technique. Moreover, the protection techniques are feasible and effectively mitigate the proposed improved attack.
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Rebeiro, Chester, and Debdeep Mukhopadhyay. "Micro-Architectural Analysis of Time-Driven Cache Attacks: Quest for the Ideal Implementation." IEEE Transactions on Computers 64, no. 3 (March 2015): 778–90. http://dx.doi.org/10.1109/tc.2013.212.

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Zeitschner, Jannik, and Amir Moradi. "PoMMES: Prevention of Micro-architectural Leakages in Masked Embedded Software." IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, no. 3 (July 18, 2024): 342–76. http://dx.doi.org/10.46586/tches.v2024.i3.342-376.

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Software solutions to address computational challenges are ubiquitous in our daily lives. One specific application area where software is often used is in embedded systems, which, like other digital electronic devices, are vulnerable to side-channel analysis attacks. Although masking is the most common countermeasure and provides a solid theoretical foundation for ensuring security, recent research has revealed a crucial gap between theoretical and real-world security. This shortcoming stems from the micro-architectural effects of the underlying micro-processor. Common security models used to formally verify masking schemes such as the d-probing model fully ignore the micro-architectural leakages that lead to a set of instructions that unintentionally recombine the shares. Manual generation of masked assembly code that remains secure in the presence of such micro-architectural recombinations often involves trial and error, and is non-trivial even for experts.Motivated by this, we present PoMMES, which enables inexperienced software developers to automatically compile masked functions written in a high-level programming language into assembly code, while preserving the theoretically proven security in practice. Compared to the state of the art, based on a general model for microarchitectural effects, our scheme allows the generation of practically secure masked software at arbitrary security orders for in-order processors. The major contribution of PoMMES is its micro-architecture aware register allocation algorithm, which is one of the crucial steps during the compilation process. In addition to simulation-based assessments that we conducted by open-source tools dedicated to evaluating masked software implementations, we confirm the effectiveness of the PoMMES-generated codes through experimental analysis. We present the result of power consumption based leakage assessments of several case studies running on a Cortex M0+ micro-controller, which is commonly deployed in industry.
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Busi, Matteo, Job Noorman, Jo Van Bulck, Letterio Galletta, Pierpaolo Degano, Jan Tobias Mühlberg, and Frank Piessens. "Securing Interruptible Enclaved Execution on Small Microprocessors." ACM Transactions on Programming Languages and Systems 43, no. 3 (September 30, 2021): 1–77. http://dx.doi.org/10.1145/3470534.

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Computer systems often provide hardware support for isolation mechanisms such as privilege levels, virtual memory, or enclaved execution. Over the past years, several successful software-based side-channel attacks have been developed that break, or at least significantly weaken, the isolation that these mechanisms offer. Extending a processor with new architectural or micro-architectural features brings a risk of introducing new software-based side-channel attacks. This article studies the problem of extending a processor with new features without weakening the security of the isolation mechanisms that the processor offers. Our solution is heavily based on techniques from research on programming languages. More specifically, we propose to use the programming language concept of full abstraction as a general formal criterion for the security of a processor extension. We instantiate the proposed criterion to the concrete case of extending a microprocessor that supports enclaved execution with secure interruptibility. This is a very relevant instantiation, as several recent papers have shown that interruptibility of enclaves leads to a variety of software-based side-channel attacks. We propose a design for interruptible enclaves and prove that it satisfies our security criterion. We also implement the design on an open-source enclave-enabled microprocessor and evaluate the cost of our design in terms of performance and hardware size.
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Yu, Jiyong, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, and Christopher W. Fletcher. "Speculative taint tracking (STT)." Communications of the ACM 64, no. 12 (December 2021): 105–12. http://dx.doi.org/10.1145/3491201.

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Speculative execution attacks present an enormous security threat, capable of reading arbitrary program data under malicious speculation, and later exfiltrating that data over microarchitectural covert channels. This paper proposes speculative taint tracking (STT), a high security and high performance hardware mechanism to block these attacks. The main idea is that it is safe to execute and selectively forward the results of speculative instructions that read secrets, as long as we can prove that the forwarded results do not reach potential covert channels. The technical core of the paper is a new abstraction to help identify all micro-architectural covert channels, and an architecture to quickly identify when a covert channel is no longer a threat. We further conduct a detailed formal analysis on the scheme in a companion document. When evaluated on SPEC06 workloads, STT incurs 8.5% or 14.5% performance overhead relative to an insecure machine.
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Vu, Son Tuan, Albert Cohen, Arnaud De Grandmaison, Christophe Guillon, and Karine Heydemann. "Reconciling optimization with secure compilation." Proceedings of the ACM on Programming Languages 5, OOPSLA (October 20, 2021): 1–30. http://dx.doi.org/10.1145/3485519.

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Software protections against side-channel and physical attacks are essential to the development of secure applications. Such protections are meaningful at machine code or micro-architectural level, but they typically do not carry observable semantics at source level. This renders them susceptible to miscompilation, and security engineers embed input/output side-effects to prevent optimizing compilers from altering them. Yet these side-effects are error-prone and compiler-dependent. The current practice involves analyzing the generated machine code to make sure security or privacy properties are still enforced. These side-effects may also be too expensive in fine-grained protections such as control-flow integrity. We introduce observations of the program state that are intrinsic to the correct execution of security protections, along with means to specify and preserve observations across the compilation flow. Such observations complement the input/output semantics-preservation contract of compilers. We introduce an opacification mechanism to preserve and enforce a partial ordering of observations. This approach is compatible with a production compiler and does not incur any modification to its optimization passes. We validate the effectiveness and performance of our approach on a range of benchmarks, expressing the secure compilation of these applications in terms of observations to be made at specific program points.
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Alam, Manaar, Sarani Bhattacharya, Sayan Sinha, Chester Rebeiro, and Debdeep Mukhopadhyay. "IPA: an Instruction Profiling–Based Micro-architectural Side-Channel Attack on Block Ciphers." Journal of Hardware and Systems Security 3, no. 1 (December 12, 2018): 26–44. http://dx.doi.org/10.1007/s41635-018-0060-3.

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Dissertations / Theses on the topic "Micro-Architectural Attacks"

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Lu, Shiting. "Micro-architectural Attacks and Countermeasures." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-65733.

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Micro-architectural analysis (MA) is a fast evolving area of side-channel cryptanalysis. This new area focuses on the effects of common processor components and their functionalities on the security of software cryptosystems. The main characteristic of micro-architectural attacks, which sets them aside from classical side-channel attacks, is the simple fact that they exploit the micro-architectural behavior of modern computer systems. Attackers could get running information through malicious software, then get some sensitive information through off-line analysis. This kind of attack has the following features: 1.) side channel information are acquired through software measurement on target machine with no need to use sophisticated devices. 2.) non-privilege process could get the running information of the privilege process. 3.) people can mount both a remote attack and local attack. This thesis mainly focuses one kinds of these attacks, data cache based timing attacks(CBTA). First, the main principle of CBTA is introduced, and several kinds of CBTA technique are discussed. Moreover, theoretical model is given under some attacks. Second, various countermeasures are described and their advantages and disadvantages are pointed out. Based on these discussions, the author proposes two anti-attack measures using hardware modification. Aiming at access-driven attacks, a XOR address remapping technique is proposed, which could obfuscate the mapping relationship between cache line and memory block. Aiming at timing-driven attacks, the IPMG mechanism is proposed innovatively. This mechanism could generate cache miss dynamically through observing the historic miss rate. These two mechanisms are realized on the MIPS processor and their effectiveness is verified on the FPGA board. At last, performance penalty and hardware cost are evaluated. The result shows that the proposed solution is effective with very low performance penalty and area cost
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Inci, Mehmet Sinan. "Micro-architectural Threats to Modern Computing Systems." Digital WPI, 2019. https://digitalcommons.wpi.edu/etd-dissertations/528.

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With the abundance of cheap computing power and high-speed internet, cloud and mobile computing replaced traditional computers. As computing models evolved, newer CPUs were fitted with additional cores and larger caches to accommodate run multiple processes concurrently. In direct relation to these changes, shared hardware resources emerged and became a source of side-channel leakage. Although side-channel attacks have been known for a long time, these changes made them practical on shared hardware systems. In addition to side-channels, concurrent execution also opened the door to practical quality of service attacks (QoS). The goal of this dissertation is to identify side-channel leakages and architectural bottlenecks on modern computing systems and introduce exploits. To that end, we introduce side-channel attacks on cloud systems to recover sensitive information such as code execution, software identity as well as cryptographic secrets. Moreover, we introduce a hard to detect QoS attack that can cause over 90+\% slowdown. We demonstrate our attack by designing an Android app that causes degradation via memory bus locking. While practical and quite powerful, mounting side-channel attacks is akin to listening on a private conversation in a crowded train station. Significant manual labor is required to de-noise and synchronizes the leakage trace and extract features. With this motivation, we apply machine learning (ML) to automate and scale the data analysis. We show that classical machine learning methods, as well as more complicated convolutional neural networks (CNN), can be trained to extract useful information from side-channel leakage trace. Finally, we propose the DeepCloak framework as a countermeasure against side-channel attacks. We argue that by exploiting adversarial learning (AL), an inherent weakness of ML, as a defensive tool against side-channel attacks, we can cloak side-channel trace of a process. With DeepCloak, we show that it is possible to trick highly accurate (99+\% accuracy) CNN classifiers. Moreover, we investigate defenses against AL to determine if an attacker can protect itself from DeepCloak by applying adversarial re-training and defensive distillation. We show that even in the presence of an intelligent adversary that employs such techniques, DeepCloak still succeeds.
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Forcioli, Quentin. "Modeling of micro-architecture for security with gem5." Electronic Thesis or Diss., Institut polytechnique de Paris, 2024. http://www.theses.fr/2024IPPAT033.

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Les systèmes embarqués sont la cible d’une grande variété d’attaques, tant au niveau logiciel que matériel. Parmi celles-ci, les attaques micro-architecturales sont particulièrement difficiles à étudier. En effet, en tirant parti des comportements spécifiques des systèmes sur puce (System-on-Chip (SoC)), ces attaques permettent à un attaquant de prendre le contrôle d’un système ou de ressources protégées, en contournant les mécanismes d’isolation entre processus. Ces attaques peuvent cibler toutes les parties d’un SoC : CPU, caches, mémoire, accélérateurs (FPGA, GPU,), interfaces, etc. L’environnement d’exécution de confiance (TEE), au cur de la sécurité des SoC modernes, impliqué dans la sécurisation d’applications bancaire, est lui aussi la cible d’attaques micro-architecturales. Dans cette thèse, j’adopte une approche basée la simulation pour la sécurité: au travers d’une plate-forme virtuelle basée sur gem5, je reproduis et étudie les attaques microarchitecturales contre les SoCs. Pour ce faire, j’ai amélioré le support de gem5 pour les TEEs, rendant possible l’utilisation d’un TEE open-source (OP-TEE) et le débogueur GDB présent dans gem5 pour permettre ainsi l’étude des scénarios d’attaque, tirant partie du simulateur. Avec cette interface, j’ai créé TEE-Time, un outil qui analyse les faiblesses cache-timing. Grâce à TEE-Time, j’ai trouvé des vulnérabilités dans des implémentations cryptographiques standard de RSA dans OP-TEE. Je les ais validées par des attaques cache-timing simulées avec gem5. Pour étendre ces attaques à un système réel, j’ai développé une plate-forme virtuelle reproduisant la carte RockPi4. Pour simuler son SoC RK3399 designé par Rockchip, j’ai développé les PyDevices des outils de prototypage-rapide utilisant l’interface Python de gem5. A travers la simulation d’attaque cache, j’ai découvert que le RK3399 utilisait AutoLock, un protocole de cache spécifique à ARM. En incorporant AutoLock dans gem5, j’ai simulé un scénario d’attaque ciblant le RSA d’OP-TEE sur le RK3399. En exécutant cette même attaque sans aucune modification sur un RockPi4, j’ai réussi à faire fuir en moyenne ∼30% des bits de la clé RSA, faisant ainsi le lien entre attaques cache et leur exploitation dans un vrai système
Embedded systems are the target of a wide variety of attacks, both software and hardware level. Microarchitectural attacks are particularly difficult to study. By taking advantage of the specific behaviors of systems-on-achip, these attacks enable an attacker to take control of a system or protected resources, bypassing process isolation mechanisms. These attacks can target all element in an SoC: CPU, caches, memory, accelerators (FPGA, GPU), interfaces, etc. The Trusted Execution Environment (TEE), key element of SoC security and involved in securing banking applications, is also the target of micro-architectural attacks. In this thesis, I adopt a simulation-based approach to security: through a virtual platform based on gem5, I reproduce and study micro-architectural attacks against TEEs. To achieve this, I improved gem5’s support for TEEs, allowing the use of an open-source TEE (OP-TEE) I also augmented the GDB debugger present in gem5 to allow the study of attack scenarios, leveraging the simulator environment. With this interface, I created TEE-Time, a tool to analyze cache-timing weaknesses. Thanks to TEE-Time, I found vulnerabilities in standard RSA implementations in OP-TEE, I validated this vulnerabilities with cache timing attacks simulated using my virtual platform. To further validate these attacks on a real system, I developed a virtual platform reproducing the RockPi4 board. To simulate the Rockchip RK3399 SoC on the RockPi4, I developed PyDevices fast-prototyping tools for system devices using gem5’s Python interface. Through cache timing simulation, I discovered that the RK3399 uses AutoLock, an ARM-specific cache protocol. Compiling AutoLock into gem5, I ran my attack scenario targeting OP-TEE’s RSA implementation on the RK3399 simulation. By executing this same attack without any modification on a RockPi4, I managed to leak an average of 30% of the RSA key bits, thus making the link between cache attacks and their exploitation in a real system
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Book chapters on the topic "Micro-Architectural Attacks"

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Ducousso, Soline, Sébastien Bardin, and Marie-Laure Potet. "Adversarial Reachability for Program-level Security Analysis." In Programming Languages and Systems, 59–89. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-30044-8_3.

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AbstractMany program analysis tools and techniques have been developed to assess program vulnerability. Yet, they are based on the standard concept of reachability and represent an attacker able to craft smart legitimate input, while in practice attackers can be much more powerful, using for instance micro-architectural exploits or fault injection methods. We introduce adversarial reachability, a framework allowing to reason about such advanced attackers and check whether a system is vulnerable or immune to a particular attacker. As equipping the attacker with new capacities significantly increases the state space of the program under analysis, we present a new symbolic exploration algorithm, namely adversarial symbolic execution, injecting faults in a forkless manner to prevent path explosion, together with optimizations dedicated to reduce the number of injections to consider while keeping the same attacker power. Experiments on representative benchmarks from fault injection show that our method significantly reduces the number of adversarial paths to explore, allowing to scale up to 10 faults where prior work timeout for 3 faults. In addition, we analyze the well-tested WooKey bootloader, and demonstrate the ability of our analysis to find attacks and evaluate countermeasures in real-life security scenarios. We were especially able to find an attack not mentioned in a previous patch.
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Mandal, Upasana, Rupali Kalundia, Nimish Mishra, Shubhi Shukla, Sarani Bhattacharya, and Debdeep Mukhopadhyay. "“There’s Always Another Counter”: Detecting Micro-Architectural Attacks in a Probabilistically Interleaved Malicious/Benign Setting." In Lecture Notes in Computer Science, 201–20. Cham: Springer Nature Switzerland, 2024. https://doi.org/10.1007/978-3-031-80408-3_13.

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Alam, Manaar, Sarani Bhattacharya, and Debdeep Mukhopadhyay. "Tackling the Time-Defence: An Instruction Count Based Micro-architectural Side-Channel Attack on Block Ciphers." In Security, Privacy, and Applied Cryptography Engineering, 30–52. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-71501-8_3.

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"Micro-architectural attacks and countermeasures on public-key implementations." In Frontiers in Hardware Security and Trust; Theory, design and practice, 143–71. Institution of Engineering and Technology, 2020. http://dx.doi.org/10.1049/pbcs066e_ch7.

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Conference papers on the topic "Micro-Architectural Attacks"

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"SECURING OPENSSL AGAINST MICRO-ARCHITECTURAL ATTACKS." In International Conference on Security and Cryptography. SciTePress - Science and and Technology Publications, 2007. http://dx.doi.org/10.5220/0002118801890196.

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Shen, Chaoqun, Congcong Chen, and Jiliang Zhang. "Micro-architectural Cache Side-Channel Attacks and Countermeasures." In ASPDAC '21: 26th Asia and South Pacific Design Automation Conference. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3394885.3431638.

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Nelson, Casey, Joseph Izraelevitz, R. Iris Bahar, and Tamara Silbergleit Lehman. "Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing." In 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED). IEEE, 2022. http://dx.doi.org/10.1109/seed55351.2022.00023.

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Wei, Shijia, Aydin Aysu, Michael Orshansky, Andreas Gerstlauer, and Mohit Tiwari. "Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems." In 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2019. http://dx.doi.org/10.1109/hst.2019.8740838.

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Tan, Ya, Jizeng Wei, and Wei Guo. "The Micro-architectural Support Countermeasures against the Branch Prediction Analysis Attack." In 2014 IEEE 13th International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom). IEEE, 2014. http://dx.doi.org/10.1109/trustcom.2014.38.

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