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Journal articles on the topic 'Metal-semiconductor field effect transistor (MESFET)'

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Published: 9 March 2023

Last updated: 10 March 2023

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1

Zhu, Shunwei, Hujun Jia, Xingyu Wang, Yuan Liang, Yibo Tong, Tao Li, and Yintang Yang. "Improved MRD 4H-SiC MESFET with High Power Added Efficiency." Micromachines 10, no. 7 (July 17, 2019): 479. http://dx.doi.org/10.3390/mi10070479.

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An improved multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (IMRD 4H-SiC MESFET) with high power added efficiency is proposed and studied by co-simulation of advanced design system (ADS) and technology computer aided design (TCAD) Sentaurus software in this paper. Based on multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (MRD 4H-SiC MESFET), the recessed area of MRD MESFET on both sides of the gate is optimized, the direct current (DC), radio frequency (RF) parameters and efficiency of the device is balanced, and the IMRD MESFET with a best power-added efficiency (PAE) is finally obtained. The results show that the PAE of the IMRD MESFET is 68.33%, which is 28.66% higher than the MRD MESFET, and DC and RF performance have not dropped significantly. Compared with the MRD MESFET, the IMRD MESFET has a broader prospect in the field of microwave radio frequency.

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Jia, Hujun, Mei Hu, and Shunwei Zhu. "An Improved UU-MESFET with High Power Added Efficiency." Micromachines 9, no. 11 (November 5, 2018): 573. http://dx.doi.org/10.3390/mi9110573.

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An improved ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (IUU-MESFET) is proposed in this paper. The structure is obtained by modifying the ultrahigh upper gate height h of the ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (UU-MESFET) structure, and the h is 0.1 μm and 0.2 μm for the IUU-MESFET and UU-MESFET, respectively. Compared with the UU-MESFET, the IUU-MESFET structure has a greater threshold voltage and trans-conductance, and smaller breakdown voltage and saturation drain current, and when the ultrahigh upper gate height h is 0.1 μm, the relationship between these parameters is balanced, so as to solve the contradictory relationship that these parameters cannot be improved simultaneously. Therefore, the power added efficiency (PAE) of the IUU-MESFET structure is increased from 60.16% to 70.99% compared with the UU-MESFET, and advanced by 18%.

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3

FJELDLY, TOR A., and MICHAEL S. SHUR. "SIMULATION AND MODELING OF COMPOUND SEMICONDUCTOR DEVICES." International Journal of High Speed Electronics and Systems 06, no. 01 (March 1995): 237–84. http://dx.doi.org/10.1142/s0129156495000079.

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We review the simulation and modeling techniques used for popular compound semiconductor devices such as the Heterostructure Field Effect Transistor (HFET), the Metal Semiconductor Field Effect Transistor (MESFET), and the Heterostructure Bipolar Transistor (HBT). Starting with the basic transport theory and the numerical simulation techniques based on this theory, we proceed to give examples of Monte Carlo simulations and of 2D balance equation simulations for investigating fundamental device properties and for exploring new design concepts. Next, we present analytical HFET and MESFET models suitable for circuit simulations. These models are based on the so-called universal FET modeling concept, and accurately reproduce FET I-V and C-V characteristics. Finally, we review basic simulation and modeling issues for HBTs.

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4

Hasan, Md Sakib, Samira Shamsir, Mst Shamim Ara Shawkat, Frances Garcia, and Syed K. Islam. "Multivariate Regression Polynomial: A Versatile and Efficient Method for DC Modeling of Different Transistors (MOSFET, MESFET, HBT, HEMT and G4FET)." International Journal of High Speed Electronics and Systems 27, no. 03n04 (September 2018): 1840016. http://dx.doi.org/10.1142/s0129156418400165.

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This work presents multivariate regression polynomial as a versatile and efficient method for DC modeling of modern transistors with very different underlying physics including MOSFET (metal-oxide-semiconductor field-effect transistor), MESFET (metal–semiconductor field-effect transistor), HBT (heterojunction bipolar transistor), HEMT (High-electron-mobility transistor) and a novel silicon-on-insulator four-gate transistors (G4FET). A set of available data from analytic solution, TCAD simulation, and experimental measurements for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. The developed model expresses the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of training data set. The continuity of the resulting polynomial and its first and second order derivatives make it particularly suitable for implementation in a circuit simulator. The model also provides a method for further simplification based on prior knowledge of the underlying physical mechanism and shows excellent predictive capability for different kinds of devices. This can be very useful for modeling deep-submicron emerging devices for which any closed-form analytical solution is not yet available.

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5

Estakhrian Haghighi, Amir Reza, and Mojtaba Mohamadi. "The Silicon Plates in Buried Oxide for Enhancement of the Breakdown Voltage in SOI MESFET." Applied Mechanics and Materials 538 (April 2014): 58–61. http://dx.doi.org/10.4028/www.scientific.net/amm.538.58.

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This paper introduces a novel SOI MESFET which enhancement breakdown voltage (VBR) by modifying electric field distribution. To achieve high enhancement of the VBR utilized three Silicon plates in buried oxide of the silicon on insulator metal semiconductor field effect transistor (SOI MESFET). This change in the SOI MESFET structure leads to controlled electric field distribution , increase VBR and Output Resistance (RO). The numerical simulation results show that the VBR of the Silicon Plates SOI MESFET (SP-SOI MESFET) structure improves by 50% compared with that of the conventional SOI MESFET (C-SOI MESFET) structure. As a result, the SP-SOI MESFET structure has superior electrical performances in comparison with the conventional structure.

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6

Lau, W. M., Ji Lijiu, K. Lowe, W. Tang, and L. Young. "Hysteresis in GaAs metal-semiconductor field-effect transistors I–V characteristics." Canadian Journal of Physics 63, no. 6 (June 1, 1985): 748–52. http://dx.doi.org/10.1139/p85-119.

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The hysteresis loops observed in the drain current vs. voltage characteristics of metal-semiconductor field-effect transistors (MESFET's) fabricated on semi-insulating GaAs by ion implantation were investigated as a function of the sweep frequency and of the temperature. A model was developed to correlate the extent of the looping to the characteristics of the deep-level traps in the channel. Experimental results were compared with the channel deep-level transient spectroscopic results on the same MESFET.

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7

Sitch, J. "Comparison of field-effect transistor logic families for a GaAs depletion-mode metal semiconductor field-effect transistor." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 882–84. http://dx.doi.org/10.1139/p87-137.

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Normally-on or depletion-mode field-effect transistors (MESFET) form the basis of the most mature and robust GaAs active-circuit technology. Because of the negative threshold voltage, depletion-mode metal semiconductor field-effect transistors (D-MEFSET) need level shifters to enable the output of one transistor to switch the input of the next. Buffered FET logic (BFL) is the most popular approach leading to gates that are fast and have good output-drive capability, but they occupy a lot of space and consume a lot of power. Capacitor – FET logic (CFL) has about one quarter of the power dissipation of BFL and occupies a similar area of GaAs. CFL is as fast as BFL, but the output-drive capability is inferior.The aim of the work described here is to develop a family of CFL gates that are at least as fast as BFL under all loading conditions while maintaining the power advantage of CFL. Bootstrapping the load increases the speed, but the output drive remains unsatisfactory. A super-buffered arrangement results in the lowest power and good output drive but with a slight reduction in speed compared to BFL. A combination of super buffering and load bootstrapping results in a design that meets all requirements. For example, a CFL gate with 12 mW dissipation gives a delay of 49 ps for a fan-out of unity and a loading factor of 13 ps per fan-out. This is compared with the BFL values of 60 ps with 12 ps per fan-out and 40 mW for a gate with comparable area and input capacitance.The super CFL gates have been used in the design of a 2.4 Gb∙s−1 4: 1 multiplexer, which has been successfully fabricated using a standard depletion-mode foundry process. The total power is approximately two thirds of that which would have been dissipated by a BFL realization.

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8

Jia, Hujun, Yuan Liang, Tao Li, Yibo Tong, Shunwei Zhu, Xingyu Wang, Tonghui Zeng, and Yintang Yang. "Improved DRUS 4H-SiC MESFET with High Power Added Efficiency." Micromachines 11, no. 1 (December 27, 2019): 35. http://dx.doi.org/10.3390/mi11010035.

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A 4H-SiC metal semiconductor field effect transistor (MESFET) with layered doping and undoped space regions (LDUS-MESFET) is proposed and simulated by ADS and ISE-TCAD software in this paper. The structure (LDUS-MESFET) introduced layered doping under the lower gate of the channel, while optimizing the thickness of the undoped region. Compared with the double-recessed 4H-SiC MESFET with partly undoped space region (DRUS-MESFET), the power added efficiency of the LDUS-MESFET is increased by 85.8%, and the saturation current is increased by 27.4%. Although the breakdown voltage of the device has decreased, the decrease is within an acceptable range. Meanwhile, the LDUS-MESFET has a smaller gate-source capacitance and a large transconductance. Therefore, the LDUS-MESFET can better balance DC and AC characteristics and improve power added efficiency (PAE).

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9

Yoshida, Seikoh, and Joe Suzuki. "High-Temperature Reliability of GaN Electronic Devices." MRS Internet Journal of Nitride Semiconductor Research 5, S1 (2000): 369–75. http://dx.doi.org/10.1557/s109257830000452x.

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High-quality GaN was grown using gas-source molecular-beam epitaxy (GSMBE). The mobility of undoped GaN was 350 cm2/Vsec and the carrier concentration was 6×1016 cm−3 at room temperature. A GaN metal semiconductor field-effect transistor (MESFET) and an n-p-n GaN bipolar junction transistor (BJT) were fabricated for high-temperature operation. The high-temperature reliability of the GaN MESFET was also investigated. That is, the lifetime of the FET at 673 K was examined by continuous current injection at 673 K. We confirmed that the FET performance did not change at 673 K for over 1010 h. The aging performance of the BJT at 573 K was examined during continuous current injection at 573 K for over 850 h. The BJT performance did not change at 573 K. The current gain was about 10. No degradation of the metal-semiconductor interface was observed by secondary ion-mass spectrometry (SIMS) and transmission electron microscopy (TEM). It was also confirmed by using Si-ion implantation that the contact resistivity of the GaN surface and electrode materials could be lowered to 7×10−6 ohmcm2.

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10

Zhang, Xian Jun, and Na You. "Dependence of the Breakdown Voltage of 4H-SiC MESFET’s on the Field Plate and Step-Channel." Applied Mechanics and Materials 668-669 (October 2014): 803–7. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.803.

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The breakdown mechanism of the 4H-SiC metal-semiconductor field effect transistor (4H-SiC MESFET) at a large drain bias is explored and the dependence of breakdown voltage on the field-plate and the step-channel is investigated by simulation. The results revealed that the breakdown occurs at the corner of the gate near to the drain. The channel step and the field-plate length have sensitive effect on the breakdown voltage. The breakdown characteristics are improved since the electric field peak is lowered at breakdown point in the step-channel and field-plate structures. The largest breakdown voltage can be achieved by optimizing the field-plate length.

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11

Shi, Wei Li, Chen Yang Xue, Zhen Xin Tan, Jun Liu, and Wen Dong Zhang. "Channel Direction Effect on the GaAs Mesfet Performances for MEMS Accelerometer Application." Advanced Materials Research 291-294 (July 2011): 3121–25. http://dx.doi.org/10.4028/www.scientific.net/amr.291-294.3121.

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An experimental investigation has been carried out with clarifying the external mechanical stress effect on GaAs metal-semiconductor field-effect transistor (MESFET) I-V characteristic curve which as the sensitive element of micro-accelerometer in different condition. In this paper, we research different channel directions to explore the output characteristics of the GaAs MESFET which fabricated at the root of the cantilever. We design three channel directions which angled with the cantilever as 0 degree, 45 degree, 90 degree. We find that when the Channel direction parallel to the cantilever direction, ∆U has the maximum value of 12.13mv. The sensitivity of 0 degree is 0.04mv/g higher than the 90 degree. The dynamic result indicates that the channel direction parallel to the cantilever direction is the optimized design structure.

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12

Magerlein, J. H., D. J. Webb, A. Callegari, J. D. Feder, T. Fryxell, H. C. Guthrie, Peter D. Hoh, et al. "Characterization of GaAs self‐aligned refractory‐gate metal‐semiconductor field‐effect transistor (MESFET) integrated circuits." Journal of Applied Physics 61, no. 8 (April 15, 1987): 3080–92. http://dx.doi.org/10.1063/1.337808.

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13

SHUR, M. S., T. A. FJELDLY, T. YTTERDAL, and K. LEE. "UNIFIED GaAs MESFET MODEL FOR CIRCUIT SIMULATIONS." International Journal of High Speed Electronics and Systems 03, no. 02 (June 1992): 201–33. http://dx.doi.org/10.1142/s0129156492000084.

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We describe a new, unified model for MEtal Semiconductor Field Effect Transistors (MESFETs) which covers all ranges of operation, including the subthreshold regime. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics are described by continuous, analytical expressions with relatively few, physically based parameters. The model includes effects such as velocity saturation, parasitic series resistances, the dependence of the threshold voltage on drain bias, finite output conductance in saturation, and temperature dependence of the device parameters. We also describe a parameter extraction routine which allows the model parameters to be derived in a straightforward fashion from experimental data. The model has been incorporated into our new circuit simulator AIM-Spice. The new device characterization is applied with good results to a typical ion-implanted GaAs MESFET and a delta-doped MESFET.

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14

Jia, Hujun, Yibo Tong, Tao Li, Shunwei Zhu, Yuan Liang, Xingyu Wang, Tonghui Zeng, and Yintang Yang. "An Improved 4H-SiC MESFET with a Partially Low Doped Channel." Micromachines 10, no. 9 (August 23, 2019): 555. http://dx.doi.org/10.3390/mi10090555.

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An improved 4H-SiC metal semiconductor field effect transistor (MESFET) based on the double-recessed MESFET (DR-MESFET) for high power added efficiency (PAE) is designed and simulated in this paper and its mechanism is explored by co-simulation of ADS and ISE-TCAD software. This structure has a partially low doped channel (PLDC) under the gate, which increases the PAE of the device by decreasing the absolute value of the threshold voltage (Vt), gate-source capacitance (Cgs) and saturation current (Id). The simulated results show that with the increase of H, the PAE of the device increases and then decreases when the value of NPLDC is low enough. The doping concentration and thickness of the PLDC are respectively optimized to be NPLDC = 1 × 1015 cm−3 and H = 0.15 μm to obtain the best PAE. The maximum PAE obtained from the PLDC-MESFET is 43.67%, while the PAE of the DR-MESFET is 23.43%; the optimized PAE is increased by 86.38%.

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15

Roy, Langis, Malcolm G. Stubbs, and James S. Wight. "A GaAs monolithic amplifier with extremely low power consumption." Canadian Journal of Physics 69, no. 3-4 (March 1, 1991): 177–79. http://dx.doi.org/10.1139/p91-028.

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The design and performance of a high-gain, monolithic, broadband amplifier with extremely low power consumption are described. The amplifier, fabricated using a 0.5 μm GaAs depletion-mode MESFET (metal semiconductor field effect transistor) process, utilizes very small gate width devices to achieve a measured gain of 19 dB and a 0.1 to 2.1 GHz bandwidth with only 63 mW dc power dissipation. This is the lowest power consumption broadband MMIC (monolithic microwave integrated circuit) reported to date and is intended for mobile radio applications.

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16

Hamma, Issam, Hichem Farh, Toufik Ziar, Yasmina Said, and Azizi Cherifa. "Modelisation and Simulation of Cgs.op and Cgd.op Capacities of GaAs MESFETs OPFET." Solid State Phenomena 297 (September 2019): 105–19. http://dx.doi.org/10.4028/www.scientific.net/ssp.297.105.

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An analytical of new theoretical model has been developed to study the Capacitance characteristics for an optically controlled Gallium Arsenic Metal Semiconductor Field Effect Transistor MESFET (OPFET) doped uniformly. The model takes the effects of photoconductive and photovoltaic into account that determine the device characteristics in the illuminated condition. It has been presented here for an analysis of extrinsic and intrinsic parameters such as, gate capacitances including both of the gate-source capacitances gate-drain capacitances under dark and illumination condition. The numerical results have also been compared with the reported data experience in the literature and a good agreement is observed.

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17

Lee, Jae-Hoon, and Jung-Hee Lee. "Growth and Device Performance of AlGaN/GaN Heterostructure with AlSiC Precoverage on Silicon Substrate." Advances in Materials Science and Engineering 2014 (2014): 1–6. http://dx.doi.org/10.1155/2014/290646.

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A crack-free AlGaN/GaN heterostructure was grown on 4-inch Si (111) substrate with initial dot-like AlSiC precoverage layer. It is believed that introducing the AlSiC layer between AlN wetting layer and Si substrate is more effective in obtaining a compressively stressed film growth than conventional Al precoverage on Si surface. The metal semiconductor field effect transistor (MESFET), fabricated on the AlGaN/GaN heterostructure grown with the AlSiC layer, exhibited normally on characteristics, such as threshold voltage of −2.3 V, maximum drain current of 370 mA/mm, and transconductance of 124 mS/mm.

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18

Kodama, Satoshi, Tomofumi Furuta, Atsushi Kanda, Masahiro Muraguchi, Hiroshi Ito, and Tadao Ishibashi. "Layered-Oxide-Isolation (LOXI) Metal-Semiconductor Field Effect Transistor (MESFET) for Low Parasitic Source-Drain Capacitance." Japanese Journal of Applied Physics 37, Part 2, No. 2B (February 15, 1998): L209—L211. http://dx.doi.org/10.1143/jjap.37.l209.

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19

Liu, Wenyuan, Lin Zhu, Feng Feng, Wei Zhang, Qi-Jun Zhang, Qian Lin, and Gaohua Liu. "A Time Delay Neural Network Based Technique for Nonlinear Microwave Device Modeling." Micromachines 11, no. 9 (August 31, 2020): 831. http://dx.doi.org/10.3390/mi11090831.

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This paper presents a nonlinear microwave device modeling technique that is based on time delay neural network (TDNN). The proposed technique can accurately model the nonlinear microwave devices when compared to static neural network modeling method. A new formulation is developed to allow for the proposed TDNN model to be trained with DC, small-signal, and large signal data, which can enhance the generalization of the device model. An algorithm is formulated to train the proposed TDNN model efficiently. This proposed technique is verified by GaAs metal-semiconductor-field-effect transistor (MESFET), and GaAs high-electron mobility transistor (HEMT) examples. These two examples demonstrate that the proposed TDNN is an efficient and valid approach for modeling various types of nonlinear microwave devices.

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20

YANG, JINMAN, ASHA BALIJEPALLI, TREVOR J. THORNTON, JAMES VANDERSAND, BENJAMIN J. BLALOCK, MICHAEL E. WOOD, and MOHAMMAD M. MOJARRADI. "SILICON-BASED INTEGRATED MOSFETS AND MESFETS: A NEW PARADIGM FOR LOW POWER, MIXED SIGNAL, MONOLITHIC SYSTEMS USING COMMERCIALLY AVAILABLE SOI." International Journal of High Speed Electronics and Systems 16, no. 02 (June 2006): 723–32. http://dx.doi.org/10.1142/s0129156406003977.

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Metal Semiconductor Field Effect Transistors fabricated using compound semiconductor materials have important applications in high-speed/low-noise communication systems. However, their integration densities are low compared to silicon technologies, and it is difficult to combine them with conventional CMOS for single-chip, mixed-signal circuit applications. In this paper we describe how silicon-on-insulator MESFETs can be fabricated alongside conventional MOSFETs using a commercially available silicon-on-insulator foundry. The process flow for the integrated MOSFETS and MESFETs is presented. Measurements from MESFETs fabricated using a commercial foundry demonstrate good depletion-mode device operation. The measured data confirms a square-law behavior for the saturated drain current, which can be reproduced using readily available MESFET models for Spice circuit simulation. The Spice model is applied to a simple differential-pair amplifier and the modeled results compared to measured data.

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Fushinobu, K., A. Majumdar, and K. Hijikata. "Heat Generation and Transport in Submicron Semiconductor Devices." Journal of Heat Transfer 117, no. 1 (February 1, 1995): 25–31. http://dx.doi.org/10.1115/1.2822317.

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The reduction of semiconductor device size to the submicrometer range leads to unique electrical and thermal phenomena. The presence of high electric fields (order of 107 V/m) energizes the electrons and throws them far from equilibrium with the lattice. This makes heat generation a nonequilibrium process. For gallium arsenide (GaAs), energy is first transferred from the energized electrons to optical phonons due to strong polar coupling. Since optical phonons do not conduct heat, they must transfer their energy to acoustic phonons for lattice heat conduction. Based on the two-step mechanism with corresponding time scales, a new model is developed to study the process of nonequilibrium heat generation and transport in a GaAs metal semiconductor field effect transistor (MESFET) with a gate length of 0.2 μm. When 3 V is applied to the device, the electron temperature rise is predicted to be more than 1000 K. The effect of lattice heating on electrical characteristics of the device shows that the current is reduced due to decrease in electron mobility. The package thermal conductance is observed to have strong effects on the transient response of the device.

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22

FOBELETS, K., P. W. DING, Y. SHADROKH, and J. E. VELAZQUEZ-PEREZ. "ANALOG AND DIGITAL PERFORMANCE OF THE SCREEN-GRID FIELD EFFECT TRANSISTOR (SGRFET)." International Journal of High Speed Electronics and Systems 18, no. 04 (December 2008): 783–92. http://dx.doi.org/10.1142/s012915640800576x.

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The Screen-Grid Field Effect Transistor (SGrFET) is a planar MOSFET-type device with a gating configuration consisting of metal cylindrical fingers inside the channel perpendicular to the current flow. The SGrFET operates in a MESFET mode using oxide insulated gates. The multi-gate configuration offers advantages for both analog and digital applications, whilst the gate cylinder holes can be exploited for bio-applications. In this manuscript TCAD results are presented on the analog and digital performance of the Screen-Grid Field Effect Transistor. The results are compared to the operation of an SOI-MOSFET and a finFET.

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McKinnon, W. R., and S. P. McAlister. "Sidegating in GaAs metal semiconductor field effect transistors (MESFETs): role of stationary Gunn domains." Canadian Journal of Physics 70, no. 10-11 (October 1, 1992): 1064–69. http://dx.doi.org/10.1139/p92-171.

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We study GaAs 0.8 μm MESFETs that show a threshold for sidegating. In these devices, the current from the sidegate saturates near the threshold voltage, supporting the idea that sidegating is produced when a stationary Gunn domain forms under the channel in the semi-insulating substrate. We compare the metal semiconductor field effect transistor to sidegated resistors and show that the same mechanism applies there, but supplemented by another mechanism, probably associated with the surface.

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Rao, M. Hema Lata, and Neti V. L. Narasimha Murty. "The Role of Substrate Compensation on DC Characteristics of 4H-SiC MESFET with Buffer Layer: A Combined Two-Dimensional Simulations and Analytical Study." Materials Science Forum 778-780 (February 2014): 887–90. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.887.

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An analytical model of 4H-SiC metal semiconductor field effect transistor (MESFET) is proposed with buffer layer on high purity semi-insulating (HPSI) 4H-SiC substrate compensated by multiple deep level traps. The contribution of deep level traps (DLT) is projected and verified using two-dimensional simulations (Silvaco®). The modeled DC characteristics are compared with two-dimensional simulations performed on the same device as considered in the analytical model.The 4H-SiC MESFET is simulated with and without the effect of buffer layer and the electron concentration profiles in different regions are observed from two-dimensional simulations.The electron concentration profiles obtained at channel-substrate interface clearly shows that when the buffer layer is not present, the channel electrons get trapped by the deep level traps used for substrate compensation. It is also observed that the inclusion of buffer layer minimizes the extent of electron trapping by screening out the active channel from the substrate. However, the trapping phenomena take place in both the cases.We believe that the proposed model of 4H-SiC MESFET which includes the substrate compensation through multiple deep level traps may be useful for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

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Zerrouk, Ilham, Mohamed Amellal, Amine Amharech, Mohamed Ramdani, and Hassane Kabbaj. "Theoretical and experimental analysis of electromagnetic coupling into microwave circuit." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 1 (February 1, 2019): 181. http://dx.doi.org/10.11591/ijece.v9i1.pp181-189.

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<span lang="EN-US">In this paper, our work is devoted to a time domain analysis of field-to-line coupling model. The latter is designed with a uniform microstrip multiconductor transmission line (MTL), connected with a mixed load which can be linear as a resistance, nonlinear like a diode or complex nonlinear as a Metal Semiconductor Field-Effect Transistor (MESFET). The finite difference time-domain technique (FDTD) is used to compute the expression of voltage and current at the line. The primary advantage of this method over many existing methods is that nonlinear terminations may be readily incorporated into the algorithm and the analysis. The numerical predictions using the proposed method show a good agreement with the GHz Transverse Electro Magnetic (GTEM) measurement.</span>

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Zheng, Chun-Yi, Wen-Jung Chiang, Yeong-Lin Lai, Edward Y. Chang, Shen-Li Chen, and K. B. Wang. "Characteristics of GaAs Power MESFETs with Double Silicon Ion Implantations for Wireless Communication Applications." Open Materials Science Journal 10, no. 1 (June 15, 2016): 29–36. http://dx.doi.org/10.2174/1874088x01610010029.

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GaAs power metal-semiconductor field-effect transistors (MESFETs) were fabricated using direct double silicon (Si) ion implantation technology for wireless communication applications. A 150-µm MESFET had a saturation drain current of 238 mA/mm after Si3N4passivation. A 15-mm MESFET, when measured under a class-AB condition with a biased drain voltage of 3.4 V and a quiescent drain current of 600 mA, delivered a maximum output power (Pout) of 31.1 dBm and a maximum power-added efficiency (PAE) of 58.0% at a frequency of 1.88 GHz. The MESFET exhibited aPoutof 29.2 dBm with a PAE of 45.0% at the 1-dB gain compression point. The MESFET, when measured under a deep class-B condition with a biased drain voltage of 4.7 V and a quiescent drain current of 50 mA, achieved a maximumPoutof 33.1 dBm and a maximum PAE of 55.9% at 1.88 GHz. The MESFET operating at 4.7 V and 1.88 GHz exhibited aP1dBof 31.8 dBm and an associated PAE of 47.1% at the 1-dB gain compression point. When tested by IS-95 code-division multiple access (CDMA) standard signals and biased at 4.7 V under the deep class-B condition, the MESFET with aPoutof 28 dBm demonstrated an adjacent channel power rejection (ACPR) of –31.2 dBc at +1.25 MHz apart from the 1.88 GHz center frequency and –45.7 dBc at +2.25 MHz.

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Ger, Muh-Ling, and Richard B. Brown. "Sputtered WSix for micromechanical structures." Journal of Materials Research 10, no. 7 (July 1995): 1710–20. http://dx.doi.org/10.1557/jmr.1995.1710.

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Tungsten silicide (WSix) thin tilms have been investigated for use as integrated circuit interconnect and self-aligned MESFET (metal-semiconductor field-effect transistor) gates because of their low resistivity and thermal and chemical stability. These same characteristics make them interesting materials for prospective use in micromechanical structures. However, little information on residual stresses, elastic moduli, or other micromechanical properties has been available for refractory metal silicide thin films. This paper presents the morphology and stress characteristics of cosputtered WSix thin films, including crystal structure variations and orientation-dependent stresses, as a function of the deposition pressure. The compositions of WSix thin films were analyzed by Rutherford backscattering spectrometry (RBS). The biaxial elastic modulus and thermal coefficient of expansion were found for the sputtered films. Stress-measurement methods and annealing are discussed. Released diaphragms of different sizes and shapes, having controlled residual stress, have been fabricated.

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Abib, Ghalid Idir, Eric Bergeault, Souheil Bensmida, and Reda Mohellebi. "Power amplifier optimization using base band and multiharmonic source/load-pull characterization with digital predistortion." International Journal of Microwave and Wireless Technologies 1, no. 4 (June 19, 2009): 255–60. http://dx.doi.org/10.1017/s1759078709990274.

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In this paper, different techniques are combined in a unique characterization system dedicated to power transistor linearity improvement. Successive optimizations are performed using source-pull/load-pull techniques at fundamental, harmonic, and base-band frequencies associated with an instantaneous memoryless base-band predistortion procedure. Measurement results performed at 1.575 GHz on a metal semiconductor field effect transistor (MESFET) power device biased in class-AB under a quadrature phase shift keying (QPSK)-modulated signal excitation show that fundamental frequency load-pull increases the output power and power-added efficiency (PAE) by 2 dB and 16 percentage points, respectively. The fundamental frequency source-pull measurements lead to an adjacent channel power ratio (ACPR) variation equal to 3 dB. For harmonic load-pull (at 2f0), it has been found that some impedances greatly improve linearity but output power and PAE decrease. Source-pull characterization at the second harmonic frequency allows one to find a trade-off between output power, efficiency, and linearity. Moreover, the influence of base-band impedance on ACPR and error vector magnitude (EVM) is found to be 15 dB and 5.5 percentage points, respectively. Finally, instantaneous memoryless base-band predistortion improves ACPR and EVM values by 5 dB and 1 point, respectively.

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Adjaye, John, and Michael S. Mazzola. "Physics of Hysteresis in MESFET Drain I-V Characteristics: Simulation Approach." Materials Science Forum 645-648 (April 2010): 945–48. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.945.

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The two-dimensional device simulator, MediciTM, was used to simulate 4H silicon carbide (4H-SiC) n-channel power metal semiconductor field effect transistors (MESFETs) with 0.5 µm gate length with and without p-type buffer layer between the n-channel and the semi-insulating (SI) substrate. The devices, which have previously been fabricated and characterized experimentally, have ion-implanted n+ source and drain ohmic contact regions. The simulations were performed with transient 30 V amplitude symmetrical triangular pulse with 30 s pulse width. Simulations show that hysteresis in drain I-V curves of MESFETs is due to substrate traps and source/drain implant damage traps. The hysteresis is caused by trapping and emission of channel electrons by the traps as VDS rises from 0 V to VDS(max) and as VDS falls from VDS(max) back to 0 V. This leads to difference in trap occupation, and hence difference in channel electron concentration as VDS rises and falls. This finally leads to difference in drain-source current (IDS) at a given VDS for a given VGS as VDS rises and falls, giving rise to the hysteresis in the I-V curves.

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30

Shih, Yih-Cheng, and E. L. Wilkie. "Microstructure studies of tungsten silicide schottky contacts on Gaas." Proceedings, annual meeting, Electron Microscopy Society of America 45 (August 1987): 328–29. http://dx.doi.org/10.1017/s0424820100126445.

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Tungsten silicides (WSix) have been successfully used as the gate materials in self-aligned GaAs metal-semiconductor-field- effect transistors (MESFET). Thermal stability of the WSix/GaAs Schottky contact is of major concern since the n+ implanted source/drain regions must be annealed at high temperatures (∼ 800°C). WSi0.6 was considered the best composition to achieve good device performance due to its low stress and excellent thermal stability of the WSix/GaAs interface. The film adhesion and the uniformity in barrier heights and ideality factors of the WSi0.6 films have been improved by depositing a thin layer of pure W as the first layer on GaAs prior to WSi0.6 deposition. Recently WSi0.1 has been used successfully as the gate material in 1x10 μm GaAs FET's on the GaAs substrates which were sputter-cleaned prior to deposition. These GaAs FET's exhibited uniform threshold voltages across a 51 mm wafer with good film adhesion after annealing at 800°C for 10 min.

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31

Dheenan, Ashok V., Joe F. McGlone, Nidhin Kurian Kalarickal, Hsien-Lien Huang, Mark Brenner, Jinwoo Hwang, Steven A. Ringel, and Siddharth Rajan. "β-Ga₂O₃ MESFETs with insulating Mg-doped buffer grown by plasma-assisted molecular beam epitaxy." Applied Physics Letters 121, no. 11 (September 12, 2022): 113503. http://dx.doi.org/10.1063/5.0103978.

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In this work, we develop in situ Mg doping techniques in plasma-assisted molecular beam epitaxy (PAMBE) of [Formula: see text]-Ga2O3 to compensate Si dopants at the substrate epilayer growth interface and eliminate parasitic leakage paths. Both abrupt and uniform Mg doping profiles over a wide range of concentrations were achieved in [Formula: see text]-Ga2O3 epilayers grown by PAMBE. Capacitance–voltage characteristics of Si and Mg co-doped samples confirmed the compensating effect of the Mg dopants. Mg delta-doping was then integrated into a β-Ga2O3 metal-semiconductor field effect transistor structure and shown to be effective in eliminating source leakage. The results presented here show that Mg doping is a promising way to engineer insulating buffer layers for β-Ga2O3 lateral devices grown by PAMBE.

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32

Frenzel, Heiko, Alexander Lajn, Holger von Wenckstern, Michael Lorenz, Friedrich Schein, Zhipeng Zhang, and Marius Grundmann. "MESFET Electronics: Recent Progress on ZnO-Based Metal-Semiconductor Field-Effect Transistors and Their Application in Transparent Integrated Circuits (Adv. Mater. 47/2010)." Advanced Materials 22, no. 47 (December 13, 2010): 5323. http://dx.doi.org/10.1002/adma.201090157.

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33

RUMYANTSEV, SERGEY L., MICHAEL S. SHUR, REMIS GASKA, MICHAEL E. LEVINSHTEIN, M. ASIF KHAN, GRIGORY SIMIN, and J. W. YANG. "LOW FREQUENCY NOISE IN GALLIUM NITRIDE FIELD EFFECT TRANSISTORS." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 449–58. http://dx.doi.org/10.1142/s012915640200137x.

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We report on experimental study of the low frequency noise in GaN-based Field Effect Transistors. In both GaN Metal Semiconductor Field Effect Transistors (MESFETs) and AlGaN/GaN Heterostructure Field Effect Transistors (HFETs), the main noise sources are located in the channel. Gate voltage dependence of noise in MESFETs complies with the Hooge formula and indicates the bulk origin of noise. The dependencies of the Hooge parameter, α, on sheet electron concentration ns in HFETs are extracted from measured drain current fluctuations taking into account the contact resistance, and the resistance of the ungated regions of the transistors. At low channel concentrations α is inversely proportional to ns (α ~ 1/ns). This dependence as well as the temperature dependence of noise might be explained by electron tunneling from the 2D gas into the traps in the bulk GaN or AlGaN.

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34

TREW, R. J., and M. W. SHIN. "HIGH FREQUENCY, HIGH TEMPERATURE FIELD-EFFECT TRANSISTORS FABRICATED FROM WIDE BAND GAP SEMICONDUCTORS." International Journal of High Speed Electronics and Systems 06, no. 01 (March 1995): 211–36. http://dx.doi.org/10.1142/s0129156495000067.

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Electronic and optical devices fabricated from wide band gap semiconductors have many properties ideal for high temperature, high frequency, high power, and radiation hard applications. Progress in wide band gap semiconductor materials growth has been impressive and high quality epitaxial layers are becoming available. Useful devices, particularly those fabricated from SiC, are rapidly approaching the commercialization stage. In particular, MESFETs (MEtal Semiconductor Field-Effect Transistors) fabricated from wide band gap semiconductors have the potential to be useful in microwave power amplifier and oscillator applications. In this work the microwave performance of MESFETs fabricated from SiC, GaN and semiconducting diamond is investigated with a theoretical simulator and the results compared to experimental measurements. Excellent agreement between the simulated and measured data is obtained. It is demonstrated that microwave power amplifiers fabricated from these semiconductors offer superior performance, particularly at elevated temperatures compared to similar components fabricated from the commonly employed GaAs MESFETs.

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35

Cha, Ho Young, Y. C. Choi, Lester F. Eastman, Michael G. Spencer, L. Ardaravičius, A. Matulionis, and O. Kiprijanovič. "Important Role of Parasitic Regions in Electrical Characteristics of SiC MESFETs." Materials Science Forum 483-485 (May 2005): 861–64. http://dx.doi.org/10.4028/www.scientific.net/msf.483-485.861.

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Because SiC does not have velocity overshooting behaviour, the current density of SiC metal-semiconductor field-effect transistors (MESFETs) is restricted by low drift velocity in the parasitic region between source and gate where the applied electric field is low. In addition, the extension of the depletion region toward the drain side at high drain voltages increases the effective channel length and, as a result, lowers the cut-off frequency due to the increased transit time.

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36

Ro, Han-Sol, Sung Ho Kang, and Sungyeop Jung. "The Effect of Gate Work Function and Electrode Gap on Wide Band-Gap Sn-Doped α-Ga2O3 Metal–Semiconductor Field-Effect Transistors." Materials 15, no. 3 (January 25, 2022): 913. http://dx.doi.org/10.3390/ma15030913.

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We present technology computer aided design (TCAD) results for wide band-gap Sn-doped α-Ga2O3 metal–semiconductor field-effect transistors (MESFETs). In particular, the effect of gate work function and electrode gap length on the electrical characteristics is demonstrated for a thorough understanding of the behavior of such devices. The gate work function significantly affects the reverse bias drain current under the gate-current dominant regime, whereas a gate-source/drain gap larger than 0.1 µm has a negligible effect on the drain current.

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37

LEPKOWSKI, WILLIAM, SETH J. WILK, M. REZA GHAJAR, ANURADHA PARSI, and TREVOR J. THORNTON. "SILICON-ON-INSULATOR MESFETS AT THE 45NM NODE." International Journal of High Speed Electronics and Systems 21, no. 01 (March 2012): 1250012. http://dx.doi.org/10.1142/s0129156412500127.

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Metal-semiconductor field-effect-transistors (MESFETs) have been fabricated using a commercially available 45nm silicon-on-insulator (SOI) CMOS foundry with no changes to the process flow. Depending upon the layout dimensions, these n-channel, depletion mode devices can be designed for high current drive (IDSAT≥ 100mA/mm ), high operating frequency (fmax> 35 GHz ) or enhanced breakdown voltage (VBD> 25 V ). The design flexibility provided by the SOI MESFETs, coupled with the high performance of ULSI CMOS at the 45nm node will enable a variety of analog, RF and mixed signal applications.

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38

Zhuang, Xiao Feng, Qing Kai Zeng, Bing Ren, Zhen Hua Wang, Yue Lu Zhang, Li Ya Shen, Mei Bi, et al. "A Threshold Voltage Simulation of Hydrogen-Terminated Diamond MESFETs." Advanced Materials Research 482-484 (February 2012): 1093–96. http://dx.doi.org/10.4028/www.scientific.net/amr.482-484.1093.

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In this paper, the threshold voltage of diamond film-based metal-semiconductor field effect transistors (MESFETs) has been simulated using Silvaco TCAD tools. The drain current (Id) versus gate voltage (Vg) relationship, and the distribution of acceptors in diamond surface conduction layer were also investigated. From the simulation results, it was found that the gate length contributed the most to the threshold voltage, while the doping depth almost had no impact on the threshold voltage value.

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39

Lee, Ching-Ting, Jen-Hou Huang, and Chang-Da Tsai. "Nonalloyed GaAs metal-semiconductor field effect transistor." Solid-State Electronics 44, no. 1 (January 2000): 143–46. http://dx.doi.org/10.1016/s0038-1101(99)00222-1.

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40

Natori, Kenji. "Ballistic metal‐oxide‐semiconductor field effect transistor." Journal of Applied Physics 76, no. 8 (October 15, 1994): 4879–90. http://dx.doi.org/10.1063/1.357263.

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41

Moore, Karen, and Robert J. Trew. "Radio-Frequency Power Transistors Based on 6H- and 4H-SiC." MRS Bulletin 22, no. 3 (March 1997): 50–56. http://dx.doi.org/10.1557/s0883769400032760.

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In recent years, SiC has received a great deal of attention as a nearly ideal material for the fabrication of high-speed, high-power transistors. The high electric breakdown field of 3.8 × 106 V/cm, high saturated electron drift velocity of 2 × 107 cm/s, and high thermal conductivity of 4.9 W/cm K indicate SiC's potential for high-power, high-frequency operation. A wide bandgap should also allow SiC field-effect transistors (FETs) to have high radio-frequency (rf) output power at high temperatures.These material qualities have been verified through outstanding device performance. Recent results for SiC metal-semiconductor field-effect transistors (MESFETs) have included superior frequency and power performance, with power gain at frequencies as high as 40 GHz and power densities as high as 3.3 W/mm. This represents significantly higher operating frequencies and power densities than current Si rf power FET technology, and nearly three times the power density of GaAs MESFETs, which are currently used in many commercial rf power applications. Similarly, SiC static induction transistors (SITs) have much higher power densities than their Si counterparts and have recently been demonstrated in modules with as much as 470-W total pulsed output power. This article describes microwave device operation, discusses material properties needed for rf power generation, and summarizes state-of-the-art SiC high-frequency device performance. Emphasis is placed on MESFETs and SITs since they are currently the most mature SiC-based device technologies.

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42

McAlister, S. P., Z. M. Li, and D. J. Day. "Model of low-frequency noise and oscillations in GaAs metal-semiconductor-field effect transistors (MESFETs)." Canadian Journal of Physics 69, no. 3-4 (March 1, 1991): 207–11. http://dx.doi.org/10.1139/p91-034.

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We examine the theoretical and experimental aspects of low-frequency noise and oscillations in GaAs metal-semiconductor-field-effect transistors. We attribute the f−3/2 noise behaviour that is often observed in these devices to trap-modified diffusion in the semi-insulating substrate and review the derivation of analytical formulas for the spectrum. The low-frequency oscillations are correlated with the noise and we discuss the contribution to the noise from the random generation of slow domains in the substrate. We derive formulas to describe these oscillations in the drain current. Calculations using our model successfully imitate the experimental results for the noise and oscillations.

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43

Duane, Michael. "Metal–oxide–semiconductor field-effect transistor junction requirements." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 16, no. 1 (January 1998): 306. http://dx.doi.org/10.1116/1.589800.

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44

Okyay, Ali K., Abhijit J. Pethe, Duygu Kuzum, Salman Latif, David A. Miller, and Krishna C. Saraswat. "SiGe optoelectronic metal-oxide semiconductor field-effect transistor." Optics Letters 32, no. 14 (July 5, 2007): 2022. http://dx.doi.org/10.1364/ol.32.002022.

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45

Johnson, J. W., B. Luo, F. Ren, B. P. Gila, W. Krishnamoorthy, C. R. Abernathy, S. J. Pearton, et al. "Gd2O3/GaN metal-oxide-semiconductor field-effect transistor." Applied Physics Letters 77, no. 20 (November 13, 2000): 3230–32. http://dx.doi.org/10.1063/1.1326041.

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46

Lin, H. K., and I. M. Abdel-Motaleb. "Small signal nonquasistatic models for GaAs field effect transistors for implementation in SPICE. Part 2: Metal semiconductor field effect transistors (MESFETs)." IEE Proceedings G Circuits, Devices and Systems 138, no. 6 (1991): 749. http://dx.doi.org/10.1049/ip-g-2.1991.0123.

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47

El-Sayed, Osman L., S. El-Ghazaly, and G. Salmer. "On the potential interest of sub-0.25-μm metal-semiconductor field-effect transistors." Canadian Journal of Physics 63, no. 6 (June 1, 1985): 727–31. http://dx.doi.org/10.1139/p85-115.

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The potential performance improvement achieved by reducing the gate length of GaAs MESFET's below 0.25 μm is investigated using a novel two-dimensional nonlocal numerical model. The charge, potential, and electron energy distributions in three devices having respectively 0.5-, 0.3-, and 0.15-μm gates are analyzed to provide an insight into the transport phenomena at hand. The I-V characteristics and the small-signal parameters are evaluated and the effect of gate length assessed. It is shown that no improvement in cutoff frequency is achieved below 0.2 μm while the effect of parasitic capacitance and gate-access resistance becomes more detrimental.

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48

Kim, Il Hwan, Jong Duk Lee, Chang Woo Oh, Jae Woo Park, and Byung Gook Park. "Metal–oxide–semiconductor field effect transistor-controlled field emission display." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 21, no. 1 (2003): 519. http://dx.doi.org/10.1116/1.1524134.

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49

Ashworth, Jayne M., and Norbert Arnold. "The Gate-Bias Dependency of Breakdown Location in GaAs Metal Semiconductor Field Effect Transistors (MESFETs)." Japanese Journal of Applied Physics 30, Part 1, No. 12B (December 30, 1991): 3822–27. http://dx.doi.org/10.1143/jjap.30.3822.

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50

Imai, Jim, and Ruben Flores. "Low‐temperature metal‐oxide‐semiconductor field‐effect transistor preamplifier." Review of Scientific Instruments 64, no. 10 (October 1993): 3024–25. http://dx.doi.org/10.1063/1.1144353.

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