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1
Frenzel, Heiko. "ZnO-based metal-semiconductor field-effect transistors." Doctoral thesis, Universitätsbibliothek Leipzig, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:15-qucosa-61957.
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Die vorliegende Arbeit befasst sich mit der Entwicklung, Herstellung und Untersuchung von ZnO-basierten Feldeffekttransistoren (FET). Dabei werden im ersten Teil Eigenschaften von ein- und mehrschichtigen Isolatoren mit hohen Dielektrizitätskonstanten betrachtet, die mittels gepulster Laserabscheidung (PLD) dargestellt wurden. Die elektrischen und kapazitiven Eigenschaften dieser Isolatoren innerhalb von Metall-Isolator-Metall (MIM) bzw. Metall-Isolator-Halbleiter (MIS) Übergängen wurden untersucht. Letzterer wurde schließlich als Gate-Struktur in Metall-Isolator-Halbleiter-FET (MISFET) mit unten (backgate) bzw. oben liegendem Gate (topgate) genutzt. Der zweite Teil konzentriert sich auf Metal-Halbleiter-FET (MESFET), die einen Schottky-Kontakt alsGate nutzen. Dieser wurde mittels reaktiver Kathodenzerstäubung (Sputtern) von Ag, Pt, Pd oder
Au unter Einflußvon Sauerstoff hergestellt. ZnO-MESFET stellen eine vielversprechende Alternative zu den bisher in der Oxid-basierten Elektronik verwendeten MISFET dar. Durch die Variation des
verwendeten Gate-Metalls, Dotierung, Dicke und Struktur des Kanals und Kontakstruktur, wurde ein Herstellungsstandard gefunden, der zu weiteren Untersuchungen herangezogen wurde. So wurde die
Degradation der MESFET unter Belastung durch dauerhaft angelegte Spannung, Einfluss von Licht und erhöhten Temperaturen sowie lange Lagerung getestet. Weiterhin wurden ZnO-MESFET auf industriell
genutztem Glasssubstrat hergestellt und untersucht, um die Möglichkeit einer großflächigen Anwendung in Anzeigeelementen aufzuzeigen. Einfache integrierte Schaltungen, wie Inverter und
ein NOR-Gatter, wurden realisiert. Dazu wurden Inverter mit sogenannten Pegelschiebern verwendet, welche die Ausgangsspannung des Inverters so verschieben, dass eine logische Aneinanderreihungvon Invertern möglich wird. Schließlich wurden volltransparente MESFET und Inverter, basierend auf neuartigen transparenten gleichrichtenden Kontakten demonstriert.
2
Turner, Gary Chandler. "Zinc Oxide MESFET Transistors." Thesis, University of Canterbury. Electrical and Computer Engineering, 2009. http://hdl.handle.net/10092/3439.
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Zinc oxide is a familiar ingredient in common household items including sunscreen and medicines. It
is, however, also a semiconductor material. As such, it is possible to use zinc oxide (ZnO) to make
semiconductor devices such as diodes and transistors. Being transparent to visible light in its
crystalline form means that it has the potential to be the starting material for so-called 'transparent
electronics', where the entire device is transparent. Transparent transistors have the potential to
improve the performance of the electronics currently used in LCD display screens.
Most common semiconductor devices require the material to be selectively doped with specific
impurities that can make the material into one of two electronically distinct types – p- or n-type.
Unfortunately, making reliable p-type ZnO has been elusive to date, despite considerable efforts
worldwide. This lack of p-type material has hindered development of transistors based on this
material.
One alternative is a Schottky junction, which can be used as the active element in a type of transistor
known as a metal-semiconductor field effect transistor, MESFET. Schottky junctions are traditionally
made from noble metal layers deposited onto semiconductors. Recent work at the Canterbury
University has shown that partially oxidised metals may in fact be a better choice, at least to zinc
oxide.
This thesis describes the development of a fabrication process for metal-semiconductor field effect
transistors using a silver oxide gate on epitaxially grown zinc oxide single crystals. Devices were
successfully produced and electrically characterised. The measurements show that the technology has
significant potential.
3
Abbott, Derek. "GaAs MESFET Photodetectors for imaging arrays /." Title page, contents and abstract only, 1995. http://web4.library.adelaide.edu.au/theses/09PH/09pha1312.pdf.
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BRAGA, DANIELE. "Charge transport properties of organic semiconductors: application to fiels effect transistors." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2009. http://hdl.handle.net/10281/8009.
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In order to go deeper in the knowledge of the fundamentals of Organic Field Effect Transistors (OFETs), we have characterized different typologies of OFETs using rubrene single crystals. The latter are highly ordered organic semiconductors with which high mobility transistors can be fabricated. First we have obtained a detailed picture about the properties of a rubrene single crystal, by analyzing the current-voltage (I-V) characteristics of symmetric diodes with the Space Charge Limited Current (SCLC) theory. A low density of defects and a low density of intrinsic thermally generated carriers have been found to characterize this material. On this basis, we have analyzed metal-semiconductor-field-effect-transistors (MESFETs). These non-conventional devices have been proved to be efficient organic FETs, in which the process of charge carrier injection from the ohmic source contact is controlled by the voltage applied to a non-ohmic gate electrode. Finally, metal-insulator-semiconductor field effect transistors (MISFETs) have been considered. The (I-V) trend below the threshold voltage is not exponential, as predicted by the inorganic theory; instead, it is linear with the gate voltage and it follows a pseudo-exponential behaviour only in a narrow transition region. An alternative semi-analytical description has been provided here by taking into account the effect of a localized trap level on the distribution of free charges. The presence of this discrete trap level was highlighted by the previously conducted SCLC analysis.
5
Utard, Christian. "Les oscillateurs microondes faible bruit de fond a base de mesfet gaas, tegfet gaalas et transistor bipolaire silicium : modelisation, caracterisation et comparaison." Toulouse 3, 1988. http://www.theses.fr/1988TOU30078.
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On presente une methode simplifiee de modelisation fort signal des mesfet et tegfet et transistors bipolaires. Ces trois types de transistors sont utilises dans un montage oscillateur dont les caracteristiques ont ete determines de trois facons differentes, analytique par simulation electrique temporelle et par mesures experimentales. On presente enfin une etude en bruit bf et bruit mf des transistors et des oscillateurs afin de determiner le composant le plus performant. Nous proposons trois facons de determiner le coefficient de conversion bruit bf - bruit mf, par des mesures directes; indirectes et par simulation temporelle
6
Ahmed, Muhammad Mansoor. "Optimisation of submicron low-noise GaAs MESFETs." Thesis, University of Cambridge, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.242966.
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Takshi, Arash. "Organic metal-semiconductor field-effect transistor (OMESFET)." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/31531.
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Organic electronics offers the possibility of producing ultra-low-cost and large-area electronics using printing methods. Two challenges limiting the utility of printed electronic circuits are the high operating voltage and the relatively poor performance of printed transistors. It is shown that voltages can be reduced by replacing the capacitive gate used in Organic Field-Effect Transistors (OFETs) with a Schottky contact, creating a thin-film Organic Metal-Semiconductor Field-Effect Transistor (OMESFET). This geometry solves the voltage issue, and promises to be useful in situations where low voltage operation is important, but good performance is not essential. In cases where high voltage is acceptable or required, it is shown that OFET performance can be greatly improved by employing a Schottky contact as a second gate. The relatively thick insulating layer between the gate and the semiconductor in OFETs makes it necessary to employ a large change of gate voltage (~40 V) to control the drain current. In order to reduce the voltage to less than 5 V a very thin (<10 nm) insulating layer and/or high-k dielectric materials can be used, but these solutions are not compatible with current printing technology. Simulations and implementations of OMESFET devices demonstrate low voltage operation (<5 V) and improved sub-threshold swing compared to the OFET. However, these benefits are achieved at the expense of mobility. In order to achieve good performance in an OFET, including threshold voltage, current ratio and output resistance, the semiconductor thickness has to be less than 50 nm, whereas the thickness of a printed semiconductor is typically larger than 200 nm. The addition of a top Schottky contact on the OFET creates a depletion region thereby reducing the effective thickness of the semiconductor, and resulting in enhanced transistor performance. Simulations and experimental results show improvements in the threshold voltage, the current ratio, and the output resistance of a dual gate transistor, when compared to those in an OFET of the same thickness. The transistors introduced in this work demonstrate means of improving the performance of thick-film OFETs and of achieving substantially lower operation voltage in organic transistors.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
8
Mogniotte, Jean-François. "Conception d'un circuit intégré en SiC appliqué aux convertisseur de moyenne puissance." Thesis, Lyon, INSA, 2014. http://www.theses.fr/2014ISAL0004/document.
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L’émergence d’interrupteurs de puissance en SiC permet d’envisager des convertisseurs de puissance capables de fonctionner au sein des environnements sévères tels que la haute tension (> 10 kV ) et la haute température (> 300 °C). Aucune solution de commande spécifique à ces environnements n’existe pour le moment. Le développement de fonctions élémentaires en SiC (comparateur, oscillateur) est une étape préliminaire à la réalisation d’un premier démonstrateur. Plusieurs laboratoires ont développé des fonctions basées sur des transistors bipolaires, MOSFETs ou JFETs. Cependant les recherches ont principalement portées sur la conception de fonctions logiques et non sur l’intégration de drivers de puissance. Le laboratoire AMPERE (INSA de Lyon) et le Centre National de Microélectronique de Barcelone (Espagne) ont conçu un MESFET latéral double grille en SiC. Ce composant élémentaire sera à la base des différentes fonctions intégrées envisagées. L’objectif de ces recherches est la réalisation d’un convertisseur élévateur de tension "boost" monolithique et de sa commande en SiC. La démarche scientifique a consisté à définir dans un premier temps un modèle de simulation SPICE du MESFET SiC à partir de caractérisations électriques statique et dynamique. En se basant sur ce modèle, des circuits analogiques tels que des amplificateurs, oscillateurs, paires différentielles, trigger de Schmitt ont été conçus pour élaborer le circuit de commande (driver). La conception de ces fonctions s’avère complexe puisqu’il n’existe pas de MESFETs de type P et une polarisation négative de -15 V est nécessaire au blocage des MESFETs SiC. Une structure constituée d’un pont redresseur, d’un boost régulé avec sa commande basée sur ces différentes fonctions a été réalisée et simulée sous SPICE. L’ensemble de cette structure a été fabriqué au CNM de Barcelone sur un même substrat SiC semi-isolant. L’intégration des éléments passifs n’a pas été envisagée de façon monolithique (mais pourrait être considérée pour les inductances et capacités dans la mesure où les valeurs des composants intégrés sont compatibles avec les processus de réalisation). Le convertisseur a été dimensionné pour délivrer une de puissance de 2.2 W pour une surface de 0.27 cm2, soit 8.14 W/cm2. Les caractérisations électriques des différents composants latéraux (résistances, diodes, transistors) valident la conception, le dimensionnement et le procédé de fabrication de ces structures élémentaires, mais aussi de la majorité des fonctions analogiques. Les résultats obtenus permettent d’envisager la réalisation d’un driver monolithique de composants Grand Gap. La perspective des travaux porte désormais sur la réalisation complète du démonstrateur et sur l’étude de son comportement en environnement sévère notamment en haute température (> 300 °C). Des analyses des mécanismes de dégradation et de fiabilité des convertisseurs intégrés devront alors être envisagéesThe new SiC power switches is able to consider power converters, which could operate in harsh environments as in High Voltage (> 10kV) and High Temperature (> 300 °C). Currently, they are no specific solutions for controlling these devices in harsh environments. The development of elementary functions in SiC is a preliminary step toward the realization of a first demonstrator for these fields of applications. AMPERE laboratory (France) and the National Center of Microelectronic of Barcelona (Spain) have elaborated an elementary electrical compound, which is a lateral dual gate MESFET in Silicon Carbide (SiC). The purpose of this research is to conceive a monolithic power converter and its driver in SiC. The scientific approach has consisted of defining in a first time a SPICE model of the elementary MESFET from electric characterizations (fitting). Analog functions as : comparator, ring oscillator, Schmitt’s trigger . . . have been designed thanks to this SPICE’s model. A device based on a bridge rectifier, a regulated "boost" and its driver has been established and simulated with the SPICE Simulator. The converter has been sized for supplying 2.2 W for an area of 0.27 cm2. This device has been fabricated at CNM of Barcelona on semi-insulating SiC substrate. The electrical characterizations of the lateral compounds (resistors, diodes, MESFETs) checked the design, the "sizing" and the manufacturing process of these elementary devices and analog functions. The experimental results is able to considerer a monolithic driver in Wide Band Gap. The prospects of this research is now to realize a fully integrated power converter in SiC and study its behavior in harsh environments (especially in high temperature > 300 °C). Analysis of degradation mechanisms and reliability of the power converters would be so considerer in the future
9
Xia, Zhanbo. "Materials and Device Engineering for High Performance β-Ga2O3-based Electronics." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1587688595358557.
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Shi, Xuejie. "Compact modeling of double-gate metal-oxide-semiconductor field-effect transistor /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202006%20SHI.
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Sun, Shan. "Power metal-oxide-semiconductor field-effect transistor with strained silicon and silicon germanium channel." Doctoral diss., University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4631.
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With the development of modern electronics, the demand for high quality power supplies has become more urgent than ever. For power MOSFETs, maintaining the trend of reducing on-state resistance (conduction loss) without sacrificing switching performance is a severe challenge. In this work, our research is focused on implementing strained silicon and silicon germanium in power MOFETs to enhance carrier mobility, thus achieving the goal of reducing specific on-state resistance. We propose an N-channel super-lattice trench MOSFET, a P-channel sidewall channel trench MOSFET and P-Channel LDMOS with strained Si/SiGe channels. A set of fabrication processes highly compatible with conventional Si technology is developed to fabricate proposed devices. The mobility enhancement is observed to be 20%, 40% and 35% respectively for N-channel, P-channel trench MOSFET and LDMOS respectively and the on-state resistance is reduced by 10%, 20% and 22% without sacrificing other device performance parameters.ID: 030423174; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2010.; Includes bibliographical references (p. 85-91).
Ph.D.
Doctorate
Department of Electrical Engineering
Engineering and Computer Science
12
Khan, Shamsul Arefin. "Deep sub-micron MOS transistor design and manufacturing sensitivity analysis /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Bjeletich, Peter John. "Characterization of heteroepitaxial silicon germanium carbon layers for metal oxide semiconductor field effect transistor (MOSFET) applications /." For electronic version search Digital dissertations database. Restricted to UC campuses. Access is free to UC campus dissertations, 2004. http://uclibs.org/PID/11984.
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Thesis (Ph. D.)--University of California, Davis, 2005.Degree granted in Electrical Engineering. Dissertation completed in 2004; degree granted in 2005. Also available via the World Wide Web. (Restricted to UC campuses)
14
Ma, Wei. "Linearity Analysis of Single and Double-Gate Silicon-On-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistor." Ohio University / OhioLINK, 2004. http://www.ohiolink.edu/etd/view.cgi?ohiou1103138153.
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Ely, Kevin Jon. "Piezoelectric effects in GaAs MESFET's." Diss., Virginia Tech, 1993. http://hdl.handle.net/10919/40029.
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Gallium arsenide MESFETS require protective passivation at several steps in their fabrication. A common film used for device passivation is silicon nitride. This passivation film is deposited on gallium arsenide substrates by chemical vapor deposition techniques and possesses high intrinsic stress. The stresses arise from the difference in the gallium arsenide and silicon nitride material properties, such as coefficient of expansion, density, modulus, and deposition temperature. The stress has been shown to cause electrical performance shifts in GaAs MESFET structures due to the piezoelectric nature of the gallium arsenide lattice.
This work develops a framework of mathematical models and experimental techniques by which the intrinsic stresses in the film and the GaAs substrate can be evaluated. Specifically, this work details the stress field and the electrical performance shifts in fully planarized self aligned gate GaAs MESFETS. The devices were 10 micron gate periphery FET devices with a 0.4 micron etched gate length. The test devices included both enhancement mode and depletion mode structures. The major contributors to the stress in GaAs devices was found to be the intrinsic stress effects of the silicon nitride passivation film. An externally applied stress, such as that applied to a package base that a typical GaAs device would be mounted into for actual service, was found to be insufficient to cause significant shifts in the device performance. The package body effectively reduces the transfer of stress to the device body and thereby minimizes the piezoelectric effect. The intrinsic stress effects are due to the deposition of the film itself. This intrinsic stress was found to have a significant effect on the device electrical characteristics. The stress was found to permanently shift the threshold voltage and current in 10 micron self aligned gate MESFETS. The shift was measured at 26 millivolts per 100 MPa film stress for depletion mode devices and 23 millivolts per 100 MPa for enhancement mode devices. For the maximum measured biaxial stress of -0.54 MPa in the gallium arsenide, the total measured shift was 140 millivolts. The level of shift is similar to that reported by earlier researchers. This piezoelectric shift has been modeled, with model predictions within 50/0 of the experimental values for the DFET devices and 11 % for the EFET devices.Ph. D.
16
Chen, Qiang. "Scaling limits and opportunities of double-gate MOSFETS." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15011.
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Saluru, Sarat K. "Projection of TaSiOx/In0.53Ga0.47As Tri-gate transistor performance for future Low-Power Electronic Applications." Thesis, Virginia Tech, 2017. http://hdl.handle.net/10919/78028.
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The aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistor over the past 50 years has resulted in an exponential increase in device density, which consequentially has increased computation power rapidly. This has pronounced the necessity to scale the device's supply voltage (VDD) in to order to maintain low-power device operation. However, the scaling of VDD can degrade drive current significantly due to the low carrier mobility of Si. To overcome the key challenges of dimensional and voltage scaling required for low-power electronic operation without degradation of device characteristics, the adoption of alternate channel materials with low bandgap with superior transport properties will play a crucial role to improve the computation ability of the standard integrated circuit (IC). The requirement of high-mobility channel materials allows the industry to harness the potential of III-V semiconductors and germanium. However, the adoption of such high mobility materials as bulk substrates remains cost-prohibitive even today. Hence, another key challenge lies in the heterogeneous integration of epitaxial high-mobility channel materials on the established cost-effective Si platform. Furthermore, dimensional scaling of the device has led to a change in architecture from the conventional planar MOSFET to be modified to a 3-D Tri-gate architecture which provides fully depleted characteristics by increasing the inversion layer area and hence, providing superior electrostatic control of the device channel to address short channel effects such as subthreshold slope (SS) and drain induced barrier lowering (DIBL). The Tri-gate configuration provides a steeper SS effectively reducing leakage current (IOFF), thereby decreasing dynamic power consumption and increasing device performance. Recently, Tantalum silicate (TaSiOx) a high-k dielectric has been shown to exhibit superior interfacial quality on multiple III-V materials. However, there is still ambiguity as to the potential of short-channel devices incorporating alternate channel (III-V) materials which is the basis of this research, to demonstrate the feasibility of future high-mobility n-channel InGaAs material integration on Si for high- speed, low-power, high performance CMOS logic applications.Master of Science
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Pratapgarhwala, Mustansir M. "Characterization of Transistor Matching in Silicon-Germanium Heterojunction Bipolar Transistors." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7536.
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Transistor mismatch is a crucial design issue in high precision analog circuits, and is investigated here for the first time in SiGe HBTs. The goal of this work is to study the effects of mismatch under extreme conditions including radiation, high temperature, and low temperature.
One portion of this work reports collector current mismatch data as a function of emitter geometry both before and after 63 MeV proton exposure for first-generation SiGe HBTs with a peak cut-off frequency of 60 GHz. However, minimal changes in device-to-device mismatch after radiation exposure were experienced.
Another part of the study involved measuring similar devices at different temperatures ranging from 298K to 377K. As a general trend, it was observed that device-to-device mismatch improved with increasing temperature.
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Adjaye, John. "Influence of source/drain residual implant lattice damage traps on silicon carbide metal semiconductor field effect transistor drain I-V characteristics." Diss., Mississippi State : Mississippi State University, 2007. http://sun.library.msstate.edu/ETD-db/theses/available/etd-09242007-081525.
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Ndoye, Coumba. "Characterization of Dopant Diffusion in Bulk and lower dimensional Silicon Structures." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/46321.
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The semiconductor industry scaling has mainly been driven by Mooreâ s law, which states that the number of transistors on a single chip should double every year and a half to two years. Beyond 2011, when the channel length of the Metal Oxide Field effect transistor (MOSFET) approaches 16 nm, the scaling of the planar MOSFET is predicted to reach its limit. Consequently, a departure from the current planar MOSFET on bulk silicon substrate is required to push the scaling limit further while maintaining electrostatic control of the gate over the channel. Alternative device structures that allow better control of the gate over the channel such as reducing short channel effects, and minimizing second order effects are currently being investigated.
Such novel device architectures such as Fully-Depleted (FD) planar Silicon On Insulator (SOI) MOSFETS, Triple gate SOI MOSFET and Gate-All-Around Nanowire (NW) MOSFET utilize Silicon on Insulator (SOI) substrates to benefit from the bulk isolation and reduce second order effects due to parasitic effects from the bulk. The doping of the source and drain regions and the redistribution of the dopants in the channel greatly impact the electrical characteristics of the fabricated device. Thus, in nano-scale and reduced dimension transistors, a tight control of doping levels and formation of pn junctions is required. Therefore, deeper understanding of the lateral component of the diffusion mechanisms and interface effects in these lower dimensional structures compared to the bulk is necessary.
This work focuses on studying the dopant diffusion mechanisms in Silicon nanomembranes (2D), nanoribbons (â 1.Xâ D), and nanowires (1D). This study also attempts to benchmark the 1D and 2D diffusion against the well-known bulk (3D) diffusion mechanisms.Master of Science
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Nadimi, Ebrahim. "Quantum Mechanical and Atomic Level ab initio Calculation of Electron Transport through Ultrathin Gate Dielectrics of Metal-Oxide-Semiconductor Field Effect Transistors." Doctoral thesis, Universitätsbibliothek Chemnitz, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-200800477.
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The low dimensions of the state-of-the-art nanoscale transistors exhibit increasing quantum mechanical effects, which are no longer negligible. Gate tunneling current is one of such effects, that is responsible for high power consumption and high working temperature in microprocessors. This in turn put limits on further down scaling of devices. Therefore modeling and calculation of tunneling current is of a great interest. This work provides a review of existing models for the calculation of the gate tunneling current in MOSFETs. The quantum mechanical effects are studied with a model, based on a self-consistent solution of the Schrödinger and Poisson equations within the effective mass approximation. The calculation of the tunneling current is focused on models based on the calculation of carrier’s lifetime on quasi-bound states (QBSs). A new method for the determination of carrier’s lifetime is suggested and then the tunneling current is calculated for different samples and compared to measurements. The model is also applied to the extraction of the “tunneling effective mass” of electrons in ultrathin oxynitride gate dielectrics. Ultrathin gate dielectrics (tox<2 nm) consist of only few atomic layers. Therefore, atomic scale deformations at interfaces and within the dielectric could have great influences on the performance of the dielectric layer and consequently on the tunneling current. On the other hand the specific material parameters would be changed due to atomic level deformations at interfaces. A combination of DFT and NEGF formalisms has been applied to the tunneling problem in the second part of this work. Such atomic level ab initio models take atomic level distortions automatically into account. An atomic scale model interface for the Si/SiO2 interface has been constructed and the tunneling currents through Si/SiO2/Si stack structures are calculated. The influence of single and double oxygen vacancies on the tunneling current is investigated. Atomic level distortions caused by a tensile or compression strains on SiO2 layer as well as their influence on the tunneling current are also investigatedDie vorliegende Arbeit beschäftigt sich mit der Berechnung von Tunnelströmen in MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Zu diesem Zweck wurde ein quantenmechanisches Modell, das auf der selbstkonsistenten Lösung der Schrödinger- und Poisson-Gleichungen basiert, entwickelt. Die Gleichungen sind im Rahmen der EMA gelöst worden. Die Lösung der Schrödinger-Gleichung unter offenen Randbedingungen führt zur Berechnung von Ladungsverteilung und Lebensdauer der Ladungsträger in den QBSs. Der Tunnelstrom wurde dann aus diesen Informationen ermittelt. Der Tunnelstrom wurde in verschiedenen Proben mit unterschiedlichen Oxynitrid Gatedielektrika berechnet und mit gemessenen Daten verglichen. Der Vergleich zeigte, dass die effektive Masse sich sowohl mit der Schichtdicke als auch mit dem Stickstoffgehalt ändert. Im zweiten Teil der vorliegenden Arbeit wurde ein atomistisches Modell zur Berechnung des Tunnelstroms verwendet, welche auf der DFT und NEGF basiert. Zuerst wurde ein atomistisches Modell für ein Si/SiO2-Schichtsystem konstruiert. Dann wurde der Tunnelstrom für verschiedene Si/SiO2/Si-Schichtsysteme berechnet. Das Modell ermöglicht die Untersuchung atom-skaliger Verzerrungen und ihren Einfluss auf den Tunnelstrom. Außerdem wurde der Einfluss einer einzelnen und zwei unterschiedlich positionierter neutraler Sauerstoffleerstellen auf den Tunnelstrom berechnet. Zug- und Druckspannungen auf SiO2 führen zur Deformationen in den chemischen Bindungen und ändern den Tunnelstrom. Auch solche Einflüsse sind anhand des atomistischen Modells berechnet worden
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Liu, Wei. "Electro-thermal simulations and measurements of silicon carbide power transistors." Doctoral thesis, Stockholm, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-86.
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Kobayashi, Takuma. "Study on Defects in SiC MOS Structures and Mobility-Limiting Factors of MOSFETs." Kyoto University, 2018. http://hdl.handle.net/2433/232043.
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Aminbeidokhti, Amirhossein. "Measurement and Analysis of Electron Mobility in GaN Power HEMTs." Thesis, Griffith University, 2016. http://hdl.handle.net/10072/368007.
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High-electron-mobility transistor (HEMT) is a promising device for power applications because of their high breakdown voltage, high electron mobility in two-dimensional electron gas (2DEG) area, fast switching capability, high-temperature operating capabilities, compatibility with standard electronic circuits, and low production cost.
In contrast to the gate in metal–oxide–semiconductor field-effect transistor (MOSFET), which extends from source to drain, the gate in HEMT splits the device into two main sections: field-effect (section under the gate) and resistive (section outside the gate). Resistances of the 2DEG outside the gate sections are constant and modelled by fixed resistors. However, the 2DEG resistance under the gate section is dependent to the gate voltage, which can be modelled by channel resistance of a field-effect transistor (FET). Since these resistances depend on the mobility of electrons in the 2DEG, it is important to separate the electron mobility in the resistive and field-effect sections. Therefore, existence of the resistive section in the HEMT structure leads to requiring new methods for the HEMT mobility measurement. Also, since there is no model for the HEMT in SPICE, novel models are required for the SPICE simulation of the HEMT. In order to solve these issues:Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
Griffith School of Engineering
Science, Environment, Engineering and Technology
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Makineni, Anil Kumar. "Construction and realisation of measurement system in a radiation field of 10 standard suns." Thesis, Mittuniversitetet, Institutionen för informationsteknologi och medier, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-17209.
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A measurement system is to be presented, which is used to obtain the I-V characteristics of a solar cell and to track its temperature during irra-diation before mounting it into a complete array/module. This project presents both the design and implementation of an Electronic load for testing the solar cell under field conditions of 10000 W/m^2, which is able to provide current versus voltage and power versus voltage charac-teristics of a solar cell using a software based model developed in Lab-VIEW. An efficient water cooling method which includes a heat pipe array system is also suggested. This thesis presents the maximum power tracking of a solar cell and the corresponding voltage and current values. In addition, the design of the clamp system provides an easy means of replacing the solar cell during testing.Keywords: Solar cell, Metal Oxide Semiconductor Field Effect Transistor (MOSFET), I-V characteristics, cooling system, solar cell clamp system, LabVIEW, Graphical User Interface (GUI).
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Raszmann, Emma Barbara. "Series-Connection of Silicon Carbide MOSFET Modules using Active Gate-Drivers with dv/dt Control." Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/95938.
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This work investigates the voltage scaling feasibility of several low voltage SiC MOSFET modules operated as a single series-connected switch using active gate control. Both multilevel and two-level topologies are capable of achieving higher blocking voltages in high-power converter applications. Compared to multilevel topologies, two-level switching topologies are of interest due to less complex circuitry, higher density, and simpler control techniques. In this work, to balance the voltage between series-connected MOSFETs, device turn-off speeds are dynamically controlled on active gate-drivers using active gate control. The implementation of the active gate control technique (specifically, turn-off dv/dt control) is described in this thesis. Experimental results of the voltage balancing behavior across eight 1.7 kV rated SiC MOSFET devices in series (6 kV total dc bus voltage) with the selected active dv/dt control scheme are demonstrated. Finally, the voltage balancing performance and switching behavior of series-connected SiC MOSFET devices are discussed.Master of Science
According to ABB, 40% of the world's power demand is supplied by electrical energy. Specifically, in 2018, the world's electrical demand has grown by 4% since 2010. The growing need for electric energy makes it increasingly essential for systems that can efficiently and reliably convert and control energy levels for various end applications, such as electric motors, electric vehicles, data centers, and renewable energy systems. Power electronics are systems by which electrical energy is converted to different levels of power (voltage and current) depending on the end application. The use of power electronics systems is critical for controlling the flow of electrical energy in all applications of electric energy generation, transmission, and distribution. Advances in power electronics technologies, such as new control techniques and manufacturability of power semiconductor devices, are enabling improvements to the overall performance of electrical energy conversion systems. Power semiconductor devices, which are used as switches or rectifiers in various power electronic converters, are a critical building block of power electronic systems. In order to enable higher output power capability for converter systems, power semiconductor switches are required to sustain higher levels of voltage and current. Wide bandgap semiconductor devices are a particular new category of power semiconductors that have superior material properties compared to traditional devices such as Silicon (Si) Insulated-Gate Bipolar Junction Transistors (IGBTs). In particular, wide bandgap devices such as Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have better ruggedness and thermal capabilities. These properties provide wide bandgap semiconductor devices to operate at higher temperatures and switching frequencies, which is beneficial for maximizing the overall efficiency and volume of power electronic converters. This work investigates a method of scaling up voltage in particular for medium-voltage power conversion, which can be applied for a variety of application areas. SiC MOSFET devices are becoming more attractive for utilization in medium-voltage high-power converter systems due to the need to further improve the efficiency and density of these systems. Rather than using individual high voltage rated semiconductor devices, this thesis demonstrates the effectiveness of using several low voltage rated semiconductor devices connected in series in order to operate them as a single switch. Using low voltage devices as a single series-connected switch rather than a using single high voltage switch can lead to achieving a lower total on-state resistance, expectedly maximizing the overall efficiency of converter systems for which the series-connected semiconductor switches would be applied. In particular, this thesis focuses on the implementation of a newer approach of compensating for the natural unbalance in voltage between series-connected devices. An active gate control method is used for monitoring and regulating the switching speed of several devices operated in series in this work. The objective of this thesis is to investigate the feasibility of this method in order to achieve up to 6 kV total dc bus voltage using eight series-connected SiC MOSFET devices.
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Jouvet, Nicolas. "Intégration hybride de transistors à un électron sur un noeud technologique CMOS." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00863770.
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Cette étude porte sur l'intégration hybride de transistors à un électron (single-electron transistor, SET) dans un noeud technologique CMOS. Les SETs présentent de forts potentiels, en particulier en termes d'économies d'énergies, mais ne peuvent complètement remplacer le CMOS dans les circuits électriques. Cependant, la combinaison des composants SETs et MOS permet de pallier à ce problème, ouvrant la voie à des circuits à très faible puissance dissipée, et à haute densité d'intégration. Cette thèse se propose d'employer pour la réalisation de SETs dans le back-end-of-line (BEOL), c'est-à-dire dans l'oxyde encapsulant les CMOS, le procédé de fabrication nanodamascène, mis au point par C. Dubuc.
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Chicot, Gauthier. "Effet de champs dans le diamant dopé au bore." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-01062250.
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Alors que la demande en électronique haute puissance et haute fréquence ne fait qu'augmenter, les semi-conducteurs classiques montrent leurs limites. Des approches basées soit sur des nouvelles architectures ou sur des matériaux à large bande interdite devraient permettre de les dépasser. Le diamant, avec ses propriétés exceptionnelles, semble être le semi-conducteur ultime pour répondre à ces attentes. Néanmoins, il souffre aussi de certaines limitations, en particulier d'une forte énergie d'ionisation du dopant de type p (bore) qui se traduit par une faible concentration de porteurs libres à la température ambiante. Des solutions innovantes s'appuyant sur un gaz 2D et /ou l'effet de champ ont été imaginées pour résoudre ce problème. Ce travail est axé sur deux de ces solutions : i) le diamant delta dopé au bore qui consiste en une couche fortement dopée entre deux couches intrinsèques, afin d'obtenir une conduction combinant une grande mobilité avec une grande concentration de porteurs et ii) le transistor à effet de champ métal oxide semiconducteur( MOSFET ), où l'état " on " et l'état " off " du canal sont obtenus grâce au contrôle électrostatique de la courbure de bandes à l' interface de diamant/oxyde. Pour ces deux structures, beaucoup de défis technologiques doivent être surmontés avant de pouvoir fabriquer un transistor. La dépendance en température de la densité surfacique de trous et de la mobilité de plusieurs couche de diamant delta dopées au bore a été étudiée expérimentalement et théoriquement sur une large gamme de température (6 K
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Sadik, Diane-Perle. "On Reliability of SiC Power Devices in Power Electronics." Doctoral thesis, KTH, Elkraftteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-207763.
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Silicon Carbide (SiC) is a wide-bandgap (WBG) semiconductor materialwhich has several advantages such as higher maximum electric field, lowerON-state resistance, higher switching speeds, and higher maximum allowablejunction operation temperature compared to Silicon (Si). In the 1.2 kV - 1.7kV voltage range, power devices in SiC are foreseen to replace Si Insulatedgatebipolar transistors (IGBTs) for applications targeting high efficiency,high operation temperatures and/or volume reductions. In particular, theSiC Metal-oxide semiconductor field-effect transistor (MOSFET) – which isvoltage controlled and normally-OFF – is the device of choice due to the easeof its implementation in designs using Si IGBTs.In this work the reliability of SiC devices, in particular that of the SiCMOSFET, has been investigated. First, the possibility of paralleling two discreteSiC MOSFETs is investigated and validated through static and dynamictests. Parallel-connection was found to be unproblematic. Secondly, drifts ofthe threshold voltage and forward voltage of the body diode of the SiC MOSFETare investigated through long-term tests. Also these reliability aspectswere found to be unproblematic. Thirdly, the impact of the package on thechip reliability is discussed through a modeling of the parasitic inductancesof a standard module and the impact of those inductances on the gate oxide.The model shows imbalances in stray inductances and parasitic elementsthat are problematic for high-speed switching. A long-term test on the impactof humidity on junction terminations of SiC MOSFETs dies and SiCSchottky dies encapsulated in the same standard package reveals early degradationfor some modules situated outdoors. Then, the short-circuit behaviorof three different types (bipolar junction transistor, junction field-effect transistor,and MOSFET) of 1.2 kV SiC switching devices is investigated throughexperiments and simulations. The necessity to turn OFF the device quicklyduring a fault is supported with a detailed electro-thermal analysis for eachdevice. Design guidelines towards a rugged and fast short-circuit protectionare derived. For each device, a short-circuit protection driver was designed,built and validated experimentally. The possibility of designing diode-lessconverters with SiC MOSFETs is investigated with focus on surge currenttests through the body diode. The discovered fault mechanism is the triggeringof the npn parasitic bipolar transistor. Finally, a life-cycle cost analysis(LCCA) has been performed revealing that the introduction of SiC MOSFETsin already existing IGBT designs is economically interesting. In fact,the initial investment is saved later on due to a higher efficiency. Moreover,the reliability is improved, which is beneficial from a risk-management pointof-view. The total investment over 20 years is approximately 30 % lower fora converter with SiC MOSFETs although the initial converter cost is 30 %higher.Kiselkarbid (SiC) är ett bredbandgapsmaterial (WBG) som har flera fördelar,såsom högre maximal elektrisk fältstyrka, lägre ON-state resitans, högreswitch-hastighet och högre maximalt tillåten arbetstemperatur jämförtmed kisel (Si). I spänningsområdet 1,2-1,7 kV förutses att effekthalvledarkomponenteri SiC kommer att ersätta Si Insulated-gate bipolar transistorer(IGBT:er) i tillämpningar där hög verkningsgrad, hög arbetstemperatur ellervolymreduktioner eftersträvas. Förstahandsvalet är en SiC Metal-oxidesemiconductor field-effect transistor (MOSFET) som är spänningsstyrd ochnormally-OFF, egenskaper som möjliggör enkel implementering i konstruktionersom använder Si IGBTer.I detta arbete undersöks tillförlitligheten av SiC komponenter, specielltSiC MOSFET:en. Först undersöks möjligheten att parallellkoppla tvådiskretaSiC MOSFET:ar genom statiska och dynamiska prov. Parallellkopplingbefanns vara oproblematisk. Sedan undersöks drift av tröskelspänning ochbody-diodens framspänning genom långtidsprov. Ocksådessa tillförlitlighetsaspekterbefanns vara oproblematiska. Därefter undersöks kapslingens inverkanpåchip:et genom modellering av parasitiska induktanser hos en standardmoduloch inverkan av dessa induktanser pågate-oxiden. Modellen påvisaren obalans mellan de parasitiska induktanserna, något som kan varaproblematiskt för snabb switchning. Ett långtidstest av inverkan från fuktpåkant-termineringar för SiC-MOSFET:ar och SiC-Schottky-dioder i sammastandardmodul avslöjar tidiga tecken pådegradering för vissa moduler somvarit utomhus. Därefter undersöks kortslutningsbeteende för tre typer (bipolärtransistor,junction-field-effect transistor och MOSFET) av 1.2 kV effekthalvledarswitchargenom experiment och simuleringar. Behovet att stänga avkomponenten snabbt stöds av detaljerade elektrotermiska simuleringar för allatre komponenter. Konstruktionsriktlinjer för ett robust och snabbt kortslutningsskyddtas fram. För var och en av komponenterna byggs en drivkrets medkortslutningsskydd som valideras experimentellt. Möjligheten att konstrueradiodlösa omvandlare med SiC MOSFET:ar undersöks med fokus påstötströmmargenom body-dioden. Den upptäckta felmekanismen är ett oönskat tillslagav den parasitiska npn-transistorn. Slutligen utförs en livscykelanalys(LCCA) som avslöjar att introduktionen av SiC MOSFET:ar i existerandeIGBT-konstruktioner är ekonomiskt intressant. Den initiala investeringensparas in senare pågrund av en högre verkningsgrad. Dessutom förbättrastillförlitligheten, vilket är fördelaktigt ur ett riskhanteringsperspektiv. Dentotala investeringen över 20 år är ungefär 30 % lägre för en omvandlare medSiC MOSFET:ar även om initialkostnaden är 30 % högre.
QC 20170524
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Valentin, François. "Optimisation du silicium amorphe hydrogéné préparé par décharge luminescente à basse fréquence pour l'utilisation dans divers dispositifs de type diode Schottky." Grenoble 1, 1987. http://www.theses.fr/1987GRE10173.
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Goguenheim, Didier. "CONTRIBUTION A L'ETUDE DE LA FIABILITE DES OXYDES MINCES DANS LES STRUCTURES MOS." Habilitation à diriger des recherches, Université de Provence - Aix-Marseille I, 2006. http://tel.archives-ouvertes.fr/tel-00421746.
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Ce manuscrit expose des travaux effectués entre 1994 et 2004 sur la fiabilité des composants à base de structures MOS et la fiabilité des oxydes ultra-minces de SiO2 (<10nm) utilisés comme isolant de grille dans ces composants. Nous avons établi un lien entre courants de fuite dans l'oxyde (SILC) et injection de porteurs chauds, principalement les trous chauds, dans les oxydes de 3.8 et 4.7nm. La dépendance en champ et en température du SILC soutient un modèle d'effet tunnel assisté par des défauts neutres barycentriques dans l'oxyde, même si une composante partielle de type Schottky est identifiable. Pour les claquages de type Soft-breakdown relevés, nous avons proposé un modèle simple, fondé sur un rétrécissement local de l'épaisseur d'oxyde. Le phénomène LVSILC, typique de la structure MOS en déplétion, est mis en évidence suite à des stress à tension constante pour des oxydes entre 2.5 et 1.2 nm. Nous proposons de l'interpréter comme un effet tunnel assisté par des niveaux proches des bandes de conduction ou de valence de la densité d'états d'interface. Les mécanismes de génération sont principalement déterminés par l'énergie des porteurs injectés (y compris dans le cas d'injections de porteurs chauds), et génèrent une loi d'accélération en VG pour le vieillissement en mode tunnel direct. On établit une loi générale, donnant la probabilité de création de défauts en fonction des paramètres qui déterminent l'énergie des porteurs injectés. Nos études sur les porteurs chauds nous ont aussi amené à étudier la fiabilité de transistor MOSFET lors de contraintes dynamiques (AC), caractéristiques des séquences de polarisation en mode normal de fonctionnement. Le résultat pratique de ce travail est la mise en oeuvre d'une méthodologie s'inspirant de l'hypothèse quasi-statique pour la prévision des durées de vie AC. Cette méthodologie, éprouvée et comparée aux résultats de mesure dans un certains nombre de cas où sa validité est reconnue, est appliquée au cas plus complexe du transistor de passage NMOS. L'accord reste satisfaisant, mais nous avons également mis en évidence les limitations de cette technique lors de séquences faisant intervenir des relaxations, des périodes de dépiégegage ou des dégradations bi-directionnelles.
Concernant le lien entre les étapes du procédé et la fiabilité, nous avons étudié l'influence d'une étape d'implantation ionique à haute énergie, qui induit un dégât dans le volume du semi-conducteur détecté électriquement par C(V), mais aussi des courants de fuite similaires au SILC (IILC Implantation Induced Leakage Current). Nous avons mis au point une méthodologie optimisée de détection du Wafer Charging, utilisant des injections très courtes de porteurs chauds (au pic de courant électronique) dans le transistor PMOS. Cette méthode s'est révélée plus sensible et plus révélatrice que les injections pratiquées en régime Fowler-Nordheim ou la simple étude paramétrique pour détecter les défauts latents issus du charging dans les oxydes minces. Enfin, nous avons identifié par DLTS les défauts issus d'une contamination au Fer dans le Silicium (paire Fe-B et Fer interstitiel Fei) et avons observé la re-transformation spontanée du Fei en paire Fe-B en quelques heures.
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Pelloquin, Sylvain. "LaAlO3 amorphe déposé par épitaxie par jets moléculaires sur silicium comme alternative pour la grille high-κ des transistors CMOS." Phd thesis, INSA de Lyon, 2011. http://tel.archives-ouvertes.fr/tel-00694351.
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Depuis l'invention du transistor MOS à effet de champ dans les années 60, l'exploitation de cette brique élémentaire a permis une évolution exponentielle du domaine de la microélectronique, avec une course effrénée vers la miniaturisation des dispositifs électroniques CMOS. Dans ce contexte, l'introduction des oxydes "high-κ" (notamment HfO2) a permis de franchir la barrière sub-nanométrique de l'EOT (Equivalent Oxide Thickness) pour l'oxyde de grille. Les travaux actuels concernent notamment la recherche de matériaux "high-κ" et de procédés qui permettraient d'avoir une interface abrupte, thermodynamiquement stable avec le silicium, pouvant conduire à des EOTs de l'ordre de 5Å. L'objectif de cette thèse, était d'explorer le potentiel de l'oxyde LaAlO3 amorphe déposé sur silicium par des techniques d'Épitaxie par Jets Moléculaires, en combinant des études sur les propriétés physico-chimiques et électriques de ce système. Le travail de thèse a d'abord consisté à définir des procédures d'élaboration sur Si de couches très minces (≈4nm), robustes et reproductibles, afin de fiabiliser les mesures électriques, puis à optimiser la qualité électrique des hétérostructures en ajustant les paramètres de dépôt à partir de corrélations entre résultats électriques et propriétés physico-chimiques (densité, stœchiométrie, environnement chimique...) et enfin à valider un procédé d'intégration du matériau dans la réalisation de MOSFET. La stabilité et la reproductibilité des mesures ont été atteintes grâce à une préparation de surface du substrat adaptée et grâce à l'introduction d'oxygène atomique pendant le dépôt de LaAlO3, permettant ainsi une homogénéisation des couches et une réduction des courants de fuite. Après optimisation des paramètres de dépôt, les meilleures structures présentent des EOTs de 8-9Å, une constante diélectrique de 16 et des courants de fuite de l'ordre de 10-2A/cm². Les caractérisations physico-chimiques fines des couches par XPS ont révélé des inhomogénéités de composition qui peuvent expliquer que le κ mesuré soit inférieur aux valeurs de LaAlO3 cristallin (20-25). Bien que les interfaces LAO/Si soient abruptes après le dépôt et que LaAlO3 soit thermodynamiquement stable vis-à-vis du silicium, le système LAO amorphe /Si s'est révélé instable pour des recuits post-dépôt effectués à des températures supérieures à 700°C. Un procédé de fabrication de MOSFETs aux dimensions relâchées a été défini pour tester les filières high-κ. Les premières étapes du procédé ont été validées pour LaAlO3.
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Zabihi, Sasan. "Flexible high voltage pulsed power supply for plasma applications." Thesis, Queensland University of Technology, 2011. https://eprints.qut.edu.au/48137/1/Sasan_Zabihi_Sheykhrajeh_Thesis.pdf.
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Demands for delivering high instantaneous power in a compressed form (pulse shape) have widely increased during recent decades. The flexible shapes with variable pulse specifications offered by pulsed power have made it a practical and effective supply method for an extensive range of applications. In particular, the release of basic subatomic particles (i.e. electron, proton and neutron) in an atom (ionization process) and the synthesizing of molecules to form ions or other molecules are among those reactions that necessitate large amount of instantaneous power. In addition to the decomposition process, there have recently been requests for pulsed power in other areas such as in the combination of molecules (i.e. fusion, material joining), gessoes radiations (i.e. electron beams, laser, and radar), explosions (i.e. concrete recycling), wastewater, exhausted gas, and material surface treatments. These pulses are widely employed in the silent discharge process in all types of materials (including gas, fluid and solid); in some cases, to form the plasma and consequently accelerate the associated process.
Due to this fast growing demand for pulsed power in industrial and environmental applications, the exigency of having more efficient and flexible pulse modulators is now receiving greater consideration. Sensitive applications, such as plasma fusion and laser guns also require more precisely produced repetitive pulses with a higher quality. Many research studies are being conducted in different areas that need a flexible pulse modulator to vary pulse features to investigate the influence of these variations on the application. In addition, there is the need to prevent the waste of a considerable amount of energy caused by the arc phenomena that frequently occur after the plasma process. The control over power flow during the supply process is a critical skill that enables the pulse supply to halt the supply process at any stage.
Different pulse modulators which utilise different accumulation techniques including Marx Generators (MG), Magnetic Pulse Compressors (MPC), Pulse Forming Networks (PFN) and Multistage Blumlein Lines (MBL) are currently employed to supply a wide range of applications. Gas/Magnetic switching technologies (such as spark gap and hydrogen thyratron) have conventionally been used as switching devices in pulse modulator structures because of their high voltage ratings and considerably low rising times. However, they also suffer from serious drawbacks such as, their low efficiency, reliability and repetition rate, and also their short life span. Being bulky, heavy and expensive are the other disadvantages associated with these devices. Recently developed solid-state switching technology is an appropriate substitution for these switching devices due to the benefits they bring to the pulse supplies. Besides being compact, efficient, reasonable and reliable, and having a long life span, their high frequency switching skill allows repetitive operation of pulsed power supply. The main concerns in using solid-state transistors are the voltage rating and the rising time of available switches that, in some cases, cannot satisfy the application’s requirements. However, there are several power electronics configurations and techniques that make solid-state utilisation feasible for high voltage pulse generation. Therefore, the design and development of novel methods and topologies with higher efficiency and flexibility for pulsed power generators have been considered as the main scope of this research work. This aim is pursued through several innovative proposals that can be classified under the following two principal objectives.
• To innovate and develop novel solid-state based topologies for pulsed power generation
• To improve available technologies that have the potential to accommodate solid-state technology by revising, reconfiguring and adjusting their structure and control algorithms.
The quest to distinguish novel topologies for a proper pulsed power production was begun with a deep and through review of conventional pulse generators and useful power electronics topologies. As a result of this study, it appears that efficiency and flexibility are the most significant demands of plasma applications that have not been met by state-of-the-art methods. Many solid-state based configurations were considered and simulated in order to evaluate their potential to be utilised in the pulsed power area. Parts of this literature review are documented in Chapter 1 of this thesis.
Current source topologies demonstrate valuable advantages in supplying the loads with capacitive characteristics such as plasma applications. To investigate the influence of switching transients associated with solid-state devices on rise time of pulses, simulation based studies have been undertaken. A variable current source is considered to pump different current levels to a capacitive load, and it was evident that dissimilar dv/dts are produced at the output. Thereby, transient effects on pulse rising time are denied regarding the evidence acquired from this examination. A detailed report of this study is given in Chapter 6 of this thesis.
This study inspired the design of a solid-state based topology that take advantage of both current and voltage sources. A series of switch-resistor-capacitor units at the output splits the produced voltage to lower levels, so it can be shared by the switches. A smart but complicated switching strategy is also designed to discharge the residual energy after each supply cycle. To prevent reverse power flow and to reduce the complexity of the control algorithm in this system, the resistors in common paths of units are substituted with diode rectifiers (switch-diode-capacitor). This modification not only gives the feasibility of stopping the load supply process to the supplier at any stage (and consequently saving energy), but also enables the converter to operate in a two-stroke mode with asymmetrical capacitors. The components’ determination and exchanging energy calculations are accomplished with respect to application specifications and demands. Both topologies were simply modelled and simulation studies have been carried out with the simplified models. Experimental assessments were also executed on implemented hardware and the approaches verified the initial analysis. Reports on details of both converters are thoroughly discussed in Chapters 2 and 3 of the thesis.
Conventional MGs have been recently modified to use solid-state transistors (i.e. Insulated gate bipolar transistors) instead of magnetic/gas switching devices. Resistive insulators previously used in their structures are substituted by diode rectifiers to adjust MGs for a proper voltage sharing. However, despite utilizing solid-state technology in MGs configurations, further design and control amendments can still be made to achieve an improved performance with fewer components. Considering a number of charging techniques, resonant phenomenon is adopted in a proposal to charge the capacitors. In addition to charging the capacitors at twice the input voltage, triggering switches at the moment at which the conducted current through switches is zero significantly reduces the switching losses. Another configuration is also introduced in this research for Marx topology based on commutation circuits that use a current source to charge the capacitors. According to this design, diode-capacitor units, each including two Marx stages, are connected in cascade through solid-state devices and aggregate the voltages across the capacitors to produce a high voltage pulse. The polarity of voltage across one capacitor in each unit is reversed in an intermediate mode by connecting the commutation circuit to the capacitor. The insulation of input side from load side is provided in this topology by disconnecting the load from the current source during the supply process. Furthermore, the number of required fast switching devices in both designs is reduced to half of the number used in a conventional MG; they are replaced with slower switches (such as Thyristors) that need simpler driving modules. In addition, the contributing switches in discharging paths are decreased to half; this decrease leads to a reduction in conduction losses. Associated models are simulated, and hardware tests are performed to verify the validity of proposed topologies. Chapters 4, 5 and 7 of the thesis present all relevant analysis and approaches according to these topologies.
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Baudot, Sophie. "MOSFETs contraints sur SOI : analyse des déformations par diffraction des rayons X et étude des propriétés électriques." Phd thesis, Grenoble, 2010. http://tel.archives-ouvertes.fr/tel-00557963.
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L'introduction d'une contrainte mécanique dans le canal de MOSFETs sur SOI est indispensable pour les noeuds technologiques sub-22 nm. Son efficacité dépend de la géométrie et des règles de dessin du dispositif. L'impact des étapes du procédé de fabrication des transistors (gravure des zones actives, formation de la grille métallique, implantation des Source/Drain (S/D)) sur la contrainte du silicium contraint sur isolant (sSOI) a été mesuré par diffraction des rayons X en incidence rasante (GIXRD). Parallèlement, le gain en performances de MOSFETs sur sSOI a été quantifié par rapport au SOI (100% de gain en mobilité pour des nMOS longs et larges (L=W=10 μm), 35% de gain en courant de drain à saturation (IDsat) pour des nMOS courts et étroits (L=25 nm, W=77 nm)). Des structures contraintes innovantes ont aussi été étudiées. Un gain en IDsat de 37% (18%) pour des pMOS sur SOI (sSOI) avec des S/D en SiGe est démontré par rapport au sSOI avec des S/D en Si, pour une longueur de grille de 60 nm et des films de 15 nm d'épaisseur. Des mesures GIXRD, couplées à des simulations mécaniques, ont permis d'étudier et d'optimiser des structures originales avec transfert de contrainte d'une couche enterrée précontrainte (en SiGe ou en nitrure) vers le canal.
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Christoforou, Georges. "Conception de préamplificateurs intégrés pour fonctionnement à basse température et sous rayonnement intense." Université Joseph Fourier (Grenoble), 1998. http://www.theses.fr/1998GRE10031.
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Le grand nombre de voies d'acquisition des signaux issus du calorimetre electromagnetique du detecteur atlas (machine lhc) pose un probleme de cablage et des solutions prevoyant le placement de la partie amont de la chaine electronique d'acquisition dans le meme milieu que l'element froid de detection ont ete envisagees. L'electronique amont doit donc etre resistante aux radiations (2 10#1#4n/cm#2, 0. 5mrad), fonctionner a la temperature de l'argon liquide (89k), avoir un faible niveau de bruit, une non-linearite inferieure a 1%, consommer peu et etre rapide (40mhz). Dans le cadre de ce projet nous avons explore les possibilites offertes par les differentes technologies. Nous avons retenu les technologies asga qui resistent aux radiations et fonctionnent jusqu'a des temperatures cryogeniques. Nous avons mis en evidence au moyen de caracterisations (a basse temperature) le fait que les technologies asga sont capables de fonctionner dans un tel environnement. Les amplificateurs concus presentent une amelioration de leurs performances quand ils fonctionnent a basse temperature (reduction du bruit, reduction de la puissance dissipee augmentation du gain) rencontrant les contraintes posees par la calorimetrie dans atlas, faible niveau de bruit, faible puissance dissipee, grande dynamique de sortie et bonne non-linearite integrale, mais ne sont pas encore capables d'assurer un niveau de fiabilite de fabrication suffisant. Nous abordons egalement le probleme de la simulation des mesfet a basse temperature. Les modeles manquant, nous avons employe pour la simulation des parametres spice extraits a la temperature de l'azote liquide. Finalement, nous avons approfondi la simulation du bruit des circuits analogiques et mis en evidence les problemes existant ainsi que les precautions a prendre afin de rendre la simulation spice du bruit plus fiable.
36
Canfield, Philip C. "A P-well GaAs MESFET technology." Thesis, 1990. http://hdl.handle.net/1957/36995.
Full textAbstract:
The semiconductor gallium arsenide (GaAs) has many potential
advantages over the more widely used semiconductor silicon (Si).
These include higher low field mobility, semi-insulating substrates,
a direct band-gap, and greater radiation hardness. All these
advantages offer distinct opportunities for implementation of new
circuit functions or extension of the operating conditions of similar
circuits in silicon based technology. However, full exploitation of
these advantages has not been realized. This study examines the
limitations imposed on conventional GaAs metal-semiconductor field
effect transistor (MESFET) technology by deviations of the semi-insulating
substrate material from ideal behavior. The interaction
of the active device with defects in the semi-insulating GaAs
substrate is examined and the resulting deviations in MESFET
performance from ideal behavior are analyzed.
A p-well MESFET technology is successfully implemented which
acts to shield the active device from defects in the substrate.
Improvements in the operating characteristics include elimination of
drain current transients with long time constants, elimination of the
frequency dependence of g[subscript ds] at low frequencies, and the elimination of
sidegating. These results demonstrate that control of the channel to
substrate junction results in a dramatic improvement in the
functionality of the GaAs MESFET. The p-well MESFET RF
characteristics are examined for different p-well doping levels.
Performance comparable with the conventional GaAs MESFET technology
is demonstrated. Results indicate that optimization of the p-well
MESFET doping levels will result in devices with uniform
characteristics from DC to the highest operating frequency.Graduation date: 1991
37
Yan, Kai-tuan Kelvin. "Wide bandwidth GaAs MESFET amplifier." Thesis, 1992. http://hdl.handle.net/1957/37380.
Full text
38
Balakrishnan, V. R. "Some Studies On Interface States In GaAs MESFET's & HJFET's." Thesis, 1997. http://etd.iisc.ernet.in/handle/2005/2141.
Full text
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Lin, Angela A. "Two dimensional numerical simulation of a non-isothermal GaAs MESFET." Thesis, 1992. http://hdl.handle.net/1957/37014.
Full textAbstract:
The low thermal conductivity of gallium arsenide compared to silicon
results in self-heating effects in GaAs MESFETs that limit the electrical
performance of such devices for high power applications. To date, analytical
thermal models of self heating in GaAs MESFETs are based on the assumption
of a uniformly heated channel. This thesis presents a two dimensional analysis
of the electrothermal effect of this device based on the two dimensional
power density distribution in the channel under various bias conditions. The
numerical simulation is performed using the finite difference technique. The
results of the simulation of an isothermal MESFET without heat effects is
compared with various one dimensional analytical models in the literature.
Electro thermal effects into the two-dimensional isothermal MESFET model
allowed close examination of the temperature profile within the MESFET. The
large gradient in power distribution results in a localized heat source within the
channel which increases the overall channel temperature, which shows that the
assumption of a uniformly heated channel is erroneous, and may lead to an
underestimation of the maximum channel temperature.Graduation date: 1992
40
Vogt, Sofie. "Realization and Characterization of Metal-Semiconductor Field-Effect Transistors based on Amorphous Zinc Tin Oxide." 2019. https://ul.qucosa.de/id/qucosa%3A71690.
Full textAbstract:
Im ersten Teil der vorliegenden Arbeit werden die physikalischen Eigenschaften, insbesondere die elektrische Leitfähigkeit, von Zink-Zinn-Oxid Dünnschichten sowie darauf basierenden Schottky-Dioden in Abhängigkeit von der Kationenkomposition bestimmt. Zur Herstellung dieser Dünnschichten wurde ein Verfahren genutzt, welches die Herstellung von kontinuierlichen Kompositiongradienten im Rahmen eines gepulsten Laserabscheidungsprozesses bei Raumtemperatur ermöglicht. Erster Schwerpunkt der Diskussion ist die Abhängigkeit elektrischer Eigenschaften der Dünnschichten sowie die Diodeneigenschaften vom Kationenverhältnis. Des Weiteren wird die Langzeitstabilität der Schottky-Dioden und der Einfluss der Sauerstoffzufuhr während der Kontaktherstellung auf die Eigenschaften der Schottky-Dioden herausgestellt. DieErgebnissetiefenaufgelösterRöntgenphotoelektronenspektroskopiewerden diskutiert und ein Mechanismus, welcher zu einer Verbesserung der Schottky-Dioden über die Zeit führt, wird vorgestellt. Die Erkenntnisse über die optimale Kationenkomposition und den Einfluss des Sauerstoffs auf die Eigenschaften von Schottky-Dioden wurden genutzt, um Metall-Halbleiter-Feldeffekttransistoren herzustellen, welche im zweiten Teil der vorliegenden Arbeit beschrieben werden. In einem ersten Schritt wurden hierfür die Abscheidebedingungen in der Sputterkammer optimiert und eine neue Abscheiderezeptur für die Herstellung von Feldeffekttransistoren eingeführt. Auch hier finden alle Abscheidungen bei Raumtemperatur statt. Die Abscheidung mittels Sputtern wurde gewählt, da diese Abscheidemethode größere industrielle Relevanz als die gepulste Laserabscheidung hat. Metall-Halbleiter-Feldeffekttransistoren mit zwei verschiedenen Gate-Typen werden vorgestellt und jeweils der Einfluss der Kanalschichtdicke auf die Transistoreigenschaften untersucht. Der Einfluss des durch die Herstellung erzeugten Sauerstoffreservoirs in dem Schottky-Gate Kontakt auf die Eigenschaften der Feldeffekttransistoren wird ebenso gezeigt wie der Einfluss eines thermischen Ausheizprozesses auf die Schaltgeschwindigkeit der Feldeffekttransistoren. Außerdem werden einfache Inverter, welche auf zwei gleichartigen Feldeffekttransistoren basieren, vorgestellt. Ebenfalls werden SchottkyDioden Feldeffekttransistoren Logik basierte Inverter vorgestellt und charakterisiert. AbschließendwerdenRingoszillatoren,aufgebautausmehrereninReihegeschaltetenSchottkyDiodenFeldeffekttransistorenLogikbasiertenInverternvorgestellt. DerEinflussderKanalschichtdicke und der Gate-Geometrie auf die Oszillationsfrequenz wird diskutiert.:Contents
1 Introduction
2 Theoretical Descriptions
2.1 The Amorphous Semiconductor Zinc Tin Oxide
2.2 Schottky Barrier Diodes
2.3 Field-Effect Transistors
2.4 Inverter
2.5 Inverter Chain and Ring Oscillator
3 Methods
3.1 Growth and Structuring Techniques
3.1.1 Pulsed Laser Deposition
3.1.2 Sputtering Deposition
3.1.3 Photolithography
3.2 Characterization Techniques
3.2.1 Hall Effect Measurements
3.2.2 XRD and XRR Measurements
3.2.3 Static and Dynamic Current-Voltage Measurements
3.2.4 Further Characterization Techniques
4 Physical Properties of Amorphous Zinc Tin Oxide
4.1 Characterization of Pulsed Laser Deposited Zinc Tin Oxide Thin Films Having a Continuous Composition Spread
4.2 Properties of Schottky Barrier Diodes in Dependence on the Cation Composition
4.3 Long Term Stability of Schottky Barrier Diodes
4.4 ImportantRoleofOxygenfortheFormationofHighlyRectifyingContacts
4.5 Processes Governing the Long Term Stability
5 Demonstration and Characterization of Zinc Tin Oxide Based Devices
5.1 Implementation of a New Sputtering Recipe
5.1.1 CharacterizationandElectricalOptimizationoftheZincTinOxide Thin Films
.1.2 Optimization of the Gate Contact
5.2 Devices with PtOx/Pt Gate Contact
5.2.1 Variation of the Channel Thickness
5.2.2 Influence of the Oxygen Reservoir on the Performance and Long Term Stability of Devices
5.2.3 Tuning of the Electron Mobility
5.2.4 Frequency Dependent Switching of Transistors
5.3 Devices with i-ZTO/PtOx/Pt Gate Contact
5.3.1 Transistors with Varying Channel Thickness
5.3.2 Simple Inverter
5.3.3 SDFL Inverter
5.3.4 Inverter Chain
5.3.5 Ring Oscillators
5.4 Comparison to Literature
6 Summary and Outlook
Abbreviations
List of Symbols
Bibliography
List of Own and Contributed Articles
AppendixIn the first part of the present work the physical properties, especially the electrical properties, of zinc tin oxide thin films as well as Schottky diodes based thereon are determined as a function of the cation composition. For film growth, a room temperature pulsed laser deposition process was used, which allows the realization of a continuous composition gradient within one sample. First focus of the discussion is the dependence of electrical properties of thin films as well as diode properties on the cation ratio. Furthermore, the long-term stability of the Schottky diodes and the influence of the oxygen supply during contact fabrication on the properties of the Schottky diodes are highlighted. The results of depth-resolved Xray photoelectron spectroscopy measurements are discussed and a mechanism leading to an improvement of the Schottky diodes over time is elucidated. The findings on the optimal cation composition and the influence of oxygen on the properties of Schottky diodes were used to produce metal-semiconductor field-effect transistors, which are described in the second part of this thesis. In a first step, the deposition conditions in the sputter chamber were optimized and a new deposition recipe for the fabrication of field effect transistors was developed. Here, too, all depositions take place at room temperature. Sputter deposition was chosen because this deposition method has greater industrial relevance than pulsed laser deposition. Metal-semiconductor field-effect-transistors with two different gate types are presented and the influence of the channel layer thickness on the transistor properties is investigated. The influence of the oxygen reservoir in the Schottky gate contact on the properties of the field-effect-transistors is shown as well as the influence of a thermal annealing process on the switching speed of the field-effect-transistors. In addition, simple inverters based on two identical field-effect-transistors are demonstrated. Also Schottky diode field-effect-transistor logic based inverters are presented and characterized. Finally, ring oscillators consisting of several series-connected Schottky diode field-effecttransistor logic based inverters are presented. The influence of channel layer thickness and gate geometry on the oscillation frequency is discussed.:Contents 1 Introduction 2 Theoretical Descriptions 2.1 The Amorphous Semiconductor Zinc Tin Oxide 2.2 Schottky Barrier Diodes 2.3 Field-Effect Transistors 2.4 Inverter 2.5 Inverter Chain and Ring Oscillator 3 Methods 3.1 Growth and Structuring Techniques 3.1.1 Pulsed Laser Deposition 3.1.2 Sputtering Deposition 3.1.3 Photolithography 3.2 Characterization Techniques 3.2.1 Hall Effect Measurements 3.2.2 XRD and XRR Measurements 3.2.3 Static and Dynamic Current-Voltage Measurements 3.2.4 Further Characterization Techniques 4 Physical Properties of Amorphous Zinc Tin Oxide 4.1 Characterization of Pulsed Laser Deposited Zinc Tin Oxide Thin Films Having a Continuous Composition Spread 4.2 Properties of Schottky Barrier Diodes in Dependence on the Cation Composition 4.3 Long Term Stability of Schottky Barrier Diodes 4.4 ImportantRoleofOxygenfortheFormationofHighlyRectifyingContacts 4.5 Processes Governing the Long Term Stability 5 Demonstration and Characterization of Zinc Tin Oxide Based Devices 5.1 Implementation of a New Sputtering Recipe 5.1.1 CharacterizationandElectricalOptimizationoftheZincTinOxide Thin Films .1.2 Optimization of the Gate Contact 5.2 Devices with PtOx/Pt Gate Contact 5.2.1 Variation of the Channel Thickness 5.2.2 Influence of the Oxygen Reservoir on the Performance and Long Term Stability of Devices 5.2.3 Tuning of the Electron Mobility 5.2.4 Frequency Dependent Switching of Transistors 5.3 Devices with i-ZTO/PtOx/Pt Gate Contact 5.3.1 Transistors with Varying Channel Thickness 5.3.2 Simple Inverter 5.3.3 SDFL Inverter 5.3.4 Inverter Chain 5.3.5 Ring Oscillators 5.4 Comparison to Literature 6 Summary and Outlook Abbreviations List of Symbols Bibliography List of Own and Contributed Articles Appendix
41
Langoni, Diego Weatherspoon Mark H. "Gallium arsenide MESFET small-signal modeling using backpropagation & RBF neural networks." Diss., 2005. http://etd.lib.fsu.edu/theses/available/etd-11212005-171421.
Full textAbstract:
Thesis (M.S.)--Florida State University, 2005.Advisor: Mark H. Weatherspoon, Florida State University, College of Engineering, Dept. of Electrical and Computer Engineering. Title and description from dissertation home page (viewed Jan. 26, 2006). Document formatted into pages; contains x, 107 pages. Includes bibliographical references.
42
Huster, Carl R. "A parallel/vector Monte Carlo MESFET model for shared memory machines." Thesis, 1992. http://hdl.handle.net/1957/37306.
Full textAbstract:
The parallelization and vectorization of Monte Carlo algorithms for modelling
charge transport in semiconductor devices are considered. The standard ensemble
Monte Carlo simulation of a three parabolic band model for GaAs is first
presented as partial verification of the simulation. The model includes scattering
due to acoustic, polar-optical and intervalley phonons. This ensemble simulation
is extended to a full device simulation by the addition of real-space positions, and
solution for the electrostatic potential from the charge density distribution using
Poisson's equation. Poisson's equation was solved using the cloud-in-cell scheme
for charge assignment, finite differences for spatial discretization, and simultaneous
over-relaxation for solution. The particle movement (acceleration and scattering)
and the solution of Poisson's are both separately parallelized. The parallelization
techniques used in both parts are based on the use of semaphores for the protection
of shared resources and processor synchronization. The speed increase results for
parallelization with and without vectorization on the Ardent Titan II are presented.
The results show saturation due to memory access limitations at a speed increase of
approximately 3.3 times the serial case when four processors are used. Vectorization
alone provides a speed increase of approximately 1.6 times when compared with the
nonvectorized serial case. It is concluded that the speed increase achieved with
the Titan II is limited by memory access considerations and that this limitation is
likely to plague shared memory machines for the forseeable future. For the program
presented here, vectorization is concluded to provide a better speed increase
per day of development time than parallelization. However, when vectorization is
used in conjunction with parallelization, the speed increase due to vectorization is
negligible.Graduation date: 1993
43
ZHENG, JIAN-GUAN, and 鄭建銓. "The studies of polyacetylene metal-semiconductor field-effect transistors (MESFETs)." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/41035203929646670243.
Full text
44
Yan, Kai-tuan Kelvin. "Noise measurements, models and analysis in GaAs MESFETs circuit design." Thesis, 1996. http://hdl.handle.net/1957/34642.
Full text
45
Lee, Mankoo. "Analysis and modeling of GaAs MESFET's for linear integrated circuit design." Thesis, 1990. http://hdl.handle.net/1957/37482.
Full textAbstract:
A complete Gallium Arsenide Metal Semiconconductor
Field Effect Transistor (GaAs MESFET) model including deep-level
trap effects has been developed, which is far more
accurate than previous equivalent circuit models, for high-speed
applications in linear integrated circuit design.
A new self-backgating GaAs MESFET model, which can
simulate low frequency anomalies, is presented by including
deep-level trap effects which cause transconductance
reduction and the output conductance and the saturation
drain current to increase with the applied signal frequency.
This model has been incorporated into PSPICE and includes a
time dependent I-V curve model, a capacitance model, a
subthreshold current model, an RC network describing the
effective substrate-induced capacitance and resistance, and
a switching resistance providing device symmetry.
An analytical approach is used to derive capacitances
which depend on Vgs and Vds and is one which also includes
the channel/substrate junction modulation by the self
backgating effect. A subthreshold current model is
analytically derived by the mobile charge density from the
parabolic potential distribution in the cut-off region. Sparameter
errors between previous models and measured data
in conventional GaAs MESFET's have been reduced by including
a transit time delay in the transconductances, gm and gds,
by the second order Bessel polynomial approximation. As a
convenient extraction method, a new circuit configuration is
also proposed for extracting simulated S-parameters which
accurately predict measured data. Also, a large-signal GaAs
MESFET model for performing nonlinear microwave circuit
simulations is described.
As a linear IC design vehicle for demonstrating the
utility of the model, a 3-stage GaAs operational amplifier
has been designed and also has been fabricated with results
of a 35 dB open-loop gain at high frequencies and a 4 GHz
gain bandwidth product by a conventional half micron MESFET
technology. Using this new model, the low frequency
anomalies of the GaAs amplifier such as a gain roll-off, a
phase notch, and an output current lag are more accurately
predicted than with any other previous model.
This new self-backgating GaAs MESFET model, which
provides accurate voltage dependent capacitances, frequency
dependent output conductance, and transit time delay
dependent transconductances, can be used to simulate low
frequency effects in GaAs linear integrated circuit design.Graduation date: 1991
46
Martinez, Hector Abel Weatherspoon Mark H. "Small-signal and noise temperature modeling of microwave MESFETS using artificial neural networks." Diss., 2005. http://etd.lib.fsu.edu/theses/available/etd-07112005-103752/.
Full textAbstract:
Thesis (M. S.)--Florida State University, 2005.Advisor: Dr. Mark H. Weatherspoon, Florida State University, College of Engineering, Dept. of Electrical and Computer Engineering. Title and description from dissertation home page (viewed Sept. 19, 2005). Document formatted into pages; contains viii, 70 pages. Includes bibliographical references.
47
(9115403), Rahul Padavagodu ramamurthy. "VERTICAL TRIGATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR IN 4H - SILICON CARBIDE." Thesis, 2020.
Find full textAbstract:
Advances in modern technology and recent demand for high power applications have motivated great interest in power electronics. Power semiconductor devices are key components that have enabled significant advances in power electronic systems. Historically, silicon has been the material of choice for power semiconductor devices such as diodes, transistors and thyristors. However, silicon devices are now reaching their fundamental limits, and a transition to wide bandgap semiconductors is critical to make further progress in the field. Among them, SiC (silicon carbide) has attracted increasing attention as a power semiconductor to replace silicon due to its superior properties and technological maturity. In fact, SiC power MOSFETs have been commercially available since 2011, and are actively replacing their silicon counterparts at blocking voltages above 1 kV. At these voltages, the specific on-resistance of SiC MOSFETs is 200-300x lower than that of silicon devices. However, conventional vertical SiC MOSFETs are still far from their theoretical performance at blocking voltages below 2 kV. In this regime, the channel resistance is the dominant limitation due to the relatively low channel mobility at the SiO2/4H-SiC MOS interface.
In this thesis, the first successful demonstration of a novel power device in 4H-SiC called the trigate power DMOSFET (double diffused metal oxide semiconductor field effect transistor) is presented. This device reduces the channel resistance by a factor of 3-5× compared with the state-of-art commercial power DMOSFETs, without requiring an increase in the channel mobility. The trigate structure is applied to a power MOSFET for the first time along with a self-aligned short channel process. This new structure utilizes both the conventional horizontal surface as well as the sidewalls of a trench to increase the effective width of the channel without increasing the device area. Conceptual design, optimization, process development and electrical results are presented. The trigate power MOSFET with a trench depth of 1 μm designed for a blocking voltage of 650 V has a specific on-resistance of 1.98 mΩcm2 and a channel resistance of 0.67 mΩcm2.This corresponds to a ∼2× reduction in the total specific on-resistance, and a 3.3× reduction in the specific channel resistance as compared to a conventional DMOSFET with the same blocking voltage rating. This demonstration is a landmark that could help SiC technology compete successfully in the lower blocking voltage regime below 600 V, and access for the first time a completely new segment in the power electronics application space.
48
WANG, DUN-ZHENG, and 王敦正. "The study and fabrication of inP metal-insulator-semiconductor field-effect transistor." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/46883366304183689390.
Full text
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Cheng, Hsiang-Hsun, and 鄭香郇. "Studies on the Characteristics of Oligomeric Furan Metal Oxide Semiconductor Field-Effect Transistor." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/83343163687690264799.
Full textAbstract:
碩士大同工學院
化學工程研究所
87
The characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with oligomeric furan as semiconducting layer were investigated. In this study, the field-effect transistors (FETs) with oligomelic furan film as p-type semiconductor was fabricated. The mobility and Ion/Ioff current ratio of FETs decreases with an increasing time. Evaporating distance, evaporaing temperature and evapoating time could influence the characteristics of MOSFETs. The highest mobility (5.010-2 cm2V-1s-1) was obtained for transistors prepared at Tsub = 80 oC.
50
Chiuan, Jiang Shin, and 姜信銓. "Studies on the charge mechanism of oligoaniline metal-oxide-semiconductor field-effect transistor." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/04643710414946788985.
Full textAbstract:
碩士大同大學
化學工程研究所
89
In this study, the charge transport mechanism of organic field-effect transistor fabricated with phenyl-capped aniline tetramer by vacuum evaporation has been investigated. The influences of the trap density, contact resistance, gate bias dependence, grain size and temperature-dependence on the mobility of the transistor have been investigated. The result shows that the trap density of device is influenced by the threshold voltage, field-effect mobility and aging time of devices. It is found that the metal-semiconductor junction of oligoaniline MOSFETs is not ohmic constant by estimating the contact resistance and TLM (transmission line model) measurement. The contact resistance, about 10 8 ~ 10 9 , which is independent of the aging time. On the other hand, the mobility increases with increasing gate voltage. In addition, through the result of the temperature effect of the mobility, it shows that the mobility of oligoaniline MOSFETs is thermally activated. The device with smaller grain size is thermally activated and the device with larger grain size is temperature independent below 213 K. Finally, it shows that the charge transport mechanisms of the oligoaniline transistors are similar to the MTR (Multiple Trapping and Release) model through the results of the gate bias dependent mobility and temperature effect of the transistors.