Relevant bibliographies by topics / Metal oxide semiconductors – Design and construction

Academic literature on the topic 'Metal oxide semiconductors – Design and construction'

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Published: 4 June 2021
Last updated: 19 February 2022

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Journal articles on the topic "Metal oxide semiconductors – Design and construction"

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Maity, Heranmoy. "A New Approach to Design and Implementation of 2-Input XOR Gate Using 4-Transistor." Micro and Nanosystems 12, no. 3 (December 1, 2020): 240–42. http://dx.doi.org/10.2174/1876402912666200309120205.

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Aim: This paper proposed the design and implementation of a 2-input XOR gate using 4- transistor. Method : The XOR gate can be designed using NOT gate and 2:1 multiplexer. The NOT gate is designed using two metal–oxide–semiconductor field-effect transistors MOSFETs and an approximate 2:1 multiplexer. The 2:1 multiplexer is designed using two MOSFETs. So, an XOR gate can be designed using four transistors. Results: The proposed work theoretically and experimentally describes the 2-input XOR gate using 4- transistor. The proposed work was verified using Xilinx (ISE Design Suite).
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Li, Le, Xiaofei Ma, Yin Xiao, and Yong Wang. "Construction and Application of Graphene Oxide-Bovine Serum Albumin Modified Extended Gate Field Effect Transistor Chiral Sensor." Sensors 21, no. 11 (June 7, 2021): 3921. http://dx.doi.org/10.3390/s21113921.

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Chirality is an essential natural attribute of organisms. Chiral molecules exhibit differences in biochemical processes, pharmacodynamics, and toxicological properties, and their enantioselective recognition plays an important role in explaining life science processes and guiding drug design. Herein, we developed an ultra-sensitive enantiomer recognition platform based on an extended-gate metal-oxide semiconductor field-effect-transistor (Nafion–GO@BSA–EG-MOSFET) that achieved effective chiral resolution of ultra-sensitive Lysine (Lys) and α-Methylbenzylamine (α-Met) enantiodiscrimination at the femtomole level. Bovine serum albumin (BSA) was immobilized on the surface of graphene oxide (GO) through amide bond coupling to prepare the GO@BSA complex. GO@BSA was drop-cast on deposited Au surfaces with a Nafion solution to afford the extended-gate sensing unit. Effective recognition of chiral enantiomers of mandelic acid (MA), tartaric acid (TA), tryptophan (Trp), Lys and α-Met was realized. Moreover, the introduction of GO reduced non-specific adsorption, and the chiral resolution concentration of α-Met reached the level of picomole in a 5-fold diluted fetal bovine serum (FBS). Finally, the chiral recognition mechanism of the as-fabricated sensor was proposed.
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Sotner, Roman, Jan Jerabek, Ladislav Polak, Roman Prokop, and Vilem Kledrowetz. "Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example." Electronics 8, no. 5 (May 22, 2019): 568. http://dx.doi.org/10.3390/electronics8050568.

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This paper introduces new integrated analog cells fabricated in a C035 I3T25 0.35-μm ON Semiconductor process suitable for a modular design of advanced active elements with multiple terminals and controllable features. We developed and realized five analog cells on a single integrated circuit (IC), namely a voltage differencing differential buffer, a voltage multiplier with current output in full complementary metal–oxide–semiconductor (CMOS) form, a voltage multiplier with current output with a bipolar core, a current-controlled current conveyor of the second generation with four current outputs, and a single-input and single-output adjustable current amplifier. These cells (sub-blocks of the manufactured IC device), designed to operate in a bandwidth of up to tens of MHz, can be used as a construction set for building a variety of advanced active elements, offering up to four independently adjustable internal parameters. The performances of all individual cells were verified by extensive laboratory measurements, and the obtained results were compared to simulations in the Cadence IC6 tool. The definition and assembly of a newly specified advanced active element, namely a current-controlled voltage differencing current conveyor transconductance amplifier (CC-VDCCTA), is shown as an example of modular interconnection of the selected cells. This device was implemented in a newly synthesized topology of an electronically linearly tunable quadrature oscillator. Features of this active element were verified by simulations and experimental measurements.
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Demkov, Alexander A., Xiaodong Zhang, and Heather Loechelt. "Theoretical Investigation of Ultrathin Gate Dielectrics." VLSI Design 13, no. 1-4 (January 1, 2001): 135–43. http://dx.doi.org/10.1155/2001/98032.

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We describe a theoretical methodology for screening potential gate dielectric materials. A recently proposed method for constructing realistic structural models of the Si-dielectric interface is used to generate the Si-SiO2-Si and Si-SiON-SiO2-Si model metal-oxide-semiconductor (MOS) structures. We discuss methods to estimate the valence band discontinuity at the corresponding interface. We use Landauer's ballistic transport approach to investigate the low bias leakage through these ultrathin dielectric layers.
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Breslin, Catherine, and Adrian O'Lenskie. "Neuromorphic hardware databases for exploring structure–function relationships in the brain." Philosophical Transactions of the Royal Society of London. Series B: Biological Sciences 356, no. 1412 (August 29, 2001): 1249–58. http://dx.doi.org/10.1098/rstb.2001.0904.

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Neuromorphic hardware is the term used to describe full custom–designed integrated circuits, or silicon ‘chips’, that are the product of neuromorphic engineering—a methodology for the synthesis of biologically inspired elements and systems, such as individual neurons, retinae, cochleas, oculomotor systems and central pattern generators. We focus on the implementation of neurons and networks of neurons, designed to illuminate structure–function relationships. Neuromorphic hardware can be constructed with either digital or analogue circuitry or with mixed–signal circuitry—a hybrid of the two. Currently, most examples of this type of hardware are constructed using analogue circuits, in complementary metal–oxide–semiconductor technology. The correspondence between these circuits and neurons, or networks of neurons, can exist at a number of levels. At the lowest level, this correspondence is between membrane ion channels and field–effect transistors. At higher levels, the correspondence is between whole conductances and firing behaviour, and filters and amplifiers, devices found in conventional integrated circuit design. Similarly, neuromorphic engineers can choose to design Hodgkin–Huxley model neurons, or reduced models, such as integrate–and–fire neurons. In addition to the choice of level, there is also choice within the design technique itself; for example, resistive and capacitive properties of the neuronal membrane can be constructed with extrinsic devices, or using the intrinsic properties of the materials from which the transistors themselves are composed. So, silicon neurons can be built, with dendritic, somatic and axonal structures, and endowed with ionic, synaptic and morphological properties. Examples of the structure–function relationships already explored using neuromorphic hardware include correlation detection and direction selectivity. Establishing a database for this hardware is valuable for two reasons: first, independently of neuroscientific motivations, the field of neuromorphic engineering would benefit greatly from a resource in which circuit designs could be stored in a form appropriate for reuse and re–fabrication. Analogue designers would benefit particularly from such a database, as there are no equivalents to the algorithmic design methods available to designers of digital circuits. Second, and more importantly for the purpose of this theme issue, is the possibility of a database of silicon neuron designs replicating specific neuronal types and morphologies. In the future, it may be possible to use an automated process to translate morphometric data directly into circuit design compatible formats. The question that needs to be addressed is: what could a neuromorphic hardware database contribute to the wider neuroscientific community that a conventional database could not? One answer is that neuromorphic hardware is expected to provide analogue sensory–motor systems for interfacing the computational power of symbolic, digital systems with the external, analogue environment. It is also expected to contribute to ongoing work in neural–silicon interfaces and prosthetics. Finally, there is a possibility that the use of evolving circuits, using reconfigurable hardware and genetic algorithms, will create an explosion in the number of designs available to the neuroscience community. All this creates the need for a database to be established, and it would be advantageous to set about this while the field is relatively young. This paper outlines a framework for the construction of a neuromorphic hardware database, for use in the biological exploration of structure–function relationships.
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Sun, Peng. "Gas Sensors Based on Oxide Semiconductors with Porous Nanostructures." Proceedings 14, no. 1 (June 19, 2019): 13. http://dx.doi.org/10.3390/proceedings2019014013.

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Gas sensor as a device composed of sensing material coupled with signal transducer, has been acknowledged as an analytical tool for detection and quantification of inflammable, explosive or toxic gases. The gas sensors based on nanostructured oxide semiconductor endowed with excellent sensing properties have exhibited great potential application in the fields of environmental monitoring, resource exploration, medical welfare, etc. It is well known that the sensing mechanism of sensor employing oxide semiconductors is mainly that the interactions between the surface adsorbed oxygen species and target gases lead to a change in the electrical conductivity. Therefore, the gas sensing properties of oxide semiconductors are closely related with their composition, crystalline size, and microstructure. In this regard, design and preparation of oxides with novel architectures will be increasingly important in the construction of high performance gas sensors. Due to high specific surface area, low density, and good surface permeability, porous nanostructures oxide semiconductor sensing materials have attracted growing interest in recent years. In our work, we successfully prepared various porous nanostructures oxides and their composites to the construction of high performances gas sensors with enhanced sensitivity, selectivity, as well as lowered detection limit. The subsequent gas sensing measurements explicitly revealed that these oxides and composites manifested superior sensing behaviors (like much higher sensitivity and faster response speed), which can be ascribed to the porous architectures and the synergistic effects.
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Argazzi, Roberto, Neyde Yukie Murakami Iha, Hervé Zabri, Fabrice Odobel, and Carlo Alberto Bignozzi. "Design of molecular dyes for application in photoelectrochemical and electrochromic devices based on nanocrystalline metal oxide semiconductors." Coordination Chemistry Reviews 248, no. 13-14 (July 2004): 1299–316. http://dx.doi.org/10.1016/j.ccr.2004.03.026.

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Pargoletti, Eleonora, and Giuseppe Cappelletti. "Breakthroughs in the Design of Novel Carbon-Based Metal Oxides Nanocomposites for VOCs Gas Sensing." Nanomaterials 10, no. 8 (July 29, 2020): 1485. http://dx.doi.org/10.3390/nano10081485.

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Nowadays, the detection of volatile organic compounds (VOCs) at trace levels (down to ppb) is feasible by exploiting ultra-sensitive and highly selective chemoresistors, especially in the field of medical diagnosis. By coupling metal oxide semiconductors (MOS e.g., SnO2, ZnO, WO3, CuO, TiO2 and Fe2O3) with innovative carbon-based materials (graphene, graphene oxide, reduced graphene oxide, single-wall and multi-wall carbon nanotubes), outstanding performances in terms of sensitivity, selectivity, limits of detection, response and recovery times towards specific gaseous targets (such as ethanol, acetone, formaldehyde and aromatic compounds) can be easily achieved. Notably, carbonaceous species, highly interconnected to MOS nanoparticles, enhance the sensor responses by (i) increasing the surface area and the pore content, (ii) favoring the electron migration, the transfer efficiency (spillover effect) and gas diffusion rate, (iii) promoting the active sites concomitantly limiting the nanopowders agglomeration; and (iv) forming nano-heterojunctions. Herein, the aim of the present review is to highlight the above-mentioned hybrid features in order to engineer novel flexible, miniaturized and low working temperature sensors, able to detect specific VOC biomarkers of a human’s disease.
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Anusha, N., and T. Sasilatha. "Performance Analysis of Wide AND OR Structures Using Keeper Architectures in Various Complementary Metal Oxide Semiconductors Technologies." Journal of Computational and Theoretical Nanoscience 13, no. 10 (October 1, 2016): 6999–7008. http://dx.doi.org/10.1166/jctn.2016.5660.

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Power dissipation and area are the important constraints in VLSI design. Various techniques are employed in reducing the power dissipation of the logic circuits. Dynamic CMOS circuits are one of the techniques in VLSI to lower the power dissipation. All gates can be designed using dynamic CMOS to lower the power dissipation. In this paper wide AND OR gates are implemented using Dynamic circuits, where keeper architecture is employed in order to prevent leakage current and to ensure that correct output is obtained. The performance analysis of Wide AND OR structures implemented in dynamic CMOS with mandatory keeper architectures in ultra submicron range are analyzed. A comparative analysis of Power dissipation and area of the keeper architectures employed in dynamic CMOS in different lower nanometer such as 120 nm, 90 nm, 70 nm and 50 nm is analyzed.
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Pathan, Abrarkhan M., Dhawal H. Agrawal, Pina M. Bhatt, Hitarthi H. Patel, and U. S. Joshi. "Design and Construction of Low Temperature Attachment for Commercial AFM." Solid State Phenomena 209 (November 2013): 137–42. http://dx.doi.org/10.4028/www.scientific.net/ssp.209.137.

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With the rapid advancements in the field of nanoscience and nanotechnology, scanning probe microscopy has become an integral part of a typical R&D lab. Atomic force microscope (AFM) has become a familiar name in this category. The AFM measures the forces acting between a fine tip and a sample. The tip is attached to the free end of a cantilever and is brought very close to a surface. Attractive or repulsive forces resulting from interactions between the tip and the surface will cause a positive or negative bending of the cantilever. The bending is detected by means of a laser beam, which is reflected from the backside of the cantilever. Atomic force microscopy is currently applied to various environments (air, liquid, vacuum) and types of materials such as metal semiconductors, soft biological samples, conductive and non-conductive materials. With this technique size measurements or even manipulations of nano-objects may be performed. An experimental setup has been designed and built such that a commercially available Atomic Force Microscope (AFM) (Nanosurf AG, Easyscan 2) can be operated at cryogenic temperature under vacuum and in a vibration-free environment. The design also takes care of portability and flexibility of AFM i.e. it is very small, light weight and AFM can be used in both ambient and cryogenic conditions. The whole set up was assembled in-house at a fairly low cost. It is used to study the surface structure of nanomaterials. Important perovskite manganite Pr0.7Ca0.3MnO3thin films were studied and results such as morphology, RMS area and line roughness as well as the particle size have been estimated at cryogenic temperature.
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Dissertations / Theses on the topic "Metal oxide semiconductors – Design and construction"

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Wilson, Jeffrey. "Analysis of power requirements inside of NMOS integrated circuits." Full text open access at:, 1986. http://content.ohsu.edu/u?/etd,134.

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Dowlatabadi, Ahmad Baghai. "A high speed, high resolution, self-clocked voltage comparator in a standard digital CMOS process." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/14794.

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Johnson, Timothy E. "MOSSTAT An interactive static rule checker for MOS VLSI designs." Full text open access at:, 1986. http://content.ohsu.edu/u?/etd,109.

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Bond, Steven Winfred. "Through-silicon circuit optical communications links." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15390.

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Tang, Wei 1976. "High-speed parallel optical receivers." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103298.

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Parallel optical interconnects (POI) have attracted a great deal of attention in the past two decades as the system bandwidth continues to increase. Optical interconnects are known to have more advantages than their electrical counterparts in many aspects such as crosstalk, bandwidth distance product, power consumption, and RC time delay. The parallelization of several optical links is also an effective method to increase the aggregate data rate while keeping the component count manageable and to reduce the unit cost of optics, electronics, and packaging at lower line rate.
Parallel optical transceiver modules running at several gigabits per second are commercially available nowadays. Parallel optical receivers are one of the key components of parallel interconnected systems. In this work, we describe how a low-power parallel CMOS preamplifier IC and a deskew IC have been designed and fabricated through the IBM 0.13mum CMOS technology. The performances of three different transimpedance amplifier (TIA) topologies are compared experimentally. The best of the three TIAs shows a differential gain of 56.2dBO, 2.6GHz bandwidth, and less than -16dBm sensitivity with a bit-error-rate (BER) less than 10-12. The TIA consumes 2.5mW of power from a 1.2V supply while the channel power is 22mW with a 400mV pp differential output swing.
A novel method of accurately measuring the crosstalk power penalty with an on-chip PRBS generator is proposed and its implementation is described. The use of an on-chip PRBS generator to drive the dummy channels eliminates the data pattern dependence between the aggressors and the victim. The inevitable channel skew associated with parallel channels can be removed by a phase-locked loop (PLL) based deskew method. We investigated the skew compensation range of this method theoretically and our experimental results confirm our conclusion.
Various practical design and test techniques such as photodiode modeling, AC coupling, low-pass filtering and continuous skew generation, and their implementations, are discussed and implemented in this thesis.
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Hill, Matthew Roland Chemistry Faculty of Science UNSW. "The single source chemical vapour deposition of alkaline earth metal oxide thin films." Awarded by:University of New South Wales. School of Chemistry, 2006. http://handle.unsw.edu.au/1959.4/32903.

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Metal oxide thin films are dynamic materials that have revolutionised the nature of semiconductor and electronic thin film devices. Recently, progress has stagnated in some aspects due to the increasingly complex deposition apparatus required, and the dearth of suitable precursor complexes of certain ???difficult??? metals. This thesis seeks to address both of these issues. The application of a precursor complex, Mg6(O2CNEt2)12 to the SSCVD of MgO thin films delivered the highest quality films ever reported with this technique. The resultant films were found to be of purely (111) orientation. Due to the nature of the precursor, the chemical reactions occurring at the surface during SSCVD growth result in a high growth rate, low flux environment and films of (111) orientation have been achieved without the amorphous underlayer. This finding has important implications for buffer layers in perovskite thin film devices. The unprecedented precursor chemistry has been used as a basis for the extremely high quality material produced, along with the unusual, yet beneficial structural morphology it possesses. A new range of barium complexes with single encapsulating ligands have been prepared for use in chemical vapour deposition (CVD) of BaTiO3 thin films. A novel pathway to an unprecedented class of barium carbamates is reported, and also new dianionic bis ??-ketoesterates and their barium, strontium, and calcium analogues were synthesised. High resolution mass spectrometry showed the barium bis ??-ketoesterate derivatives to be monomeric, and preliminary testing indicated some volatility in these species. Insights were gained into the likely successful pathways to building a volatile heterobimetallic precursor complex containing an alkaline earth metal. The knowledge of intimate mixing in heterobimetallic precursor complexes was extended by some novel chemistry to develop the first mixed Zn/Mg carbamato cluster complexes. These complexes were found to be excellent SSCVD precursors for ZnxMg1-xO thin films. Thin films were deposited with these precursors and exhibited a single preferred orientation, with a constant amount of magnesium throughout the bulk of the films. Investigation of the light emission properties of the films revealed significant improvements in the structural order commensurate with the incorporation of magnesium, and the formation of the ZnxMg1-xO alloy.
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Deshpande, Sandeep. "A cost quality model for CMOS IC design." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12042009-020251/.

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Moreno, Debra Ann. "Design, synthesis, and characterization of monomeric group 2 element Bis(alkoxide) compounds ; Part II, Synthesis and characterization of some group 2 element imidophosphonate compounds." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/30267.

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Xiao, Haiqiao. "Design of Radio-Frequency Filters and Oscillators in Deep-Submicron CMOS Technology." PDXScholar, 2008. https://pdxscholar.library.pdx.edu/open_access_etds/5233.

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Radio-frequency filters and oscillators are widely used in wireless communication and high-speed digital systems, and they are mostly built on passive integrated inductors, which occupy a relative large silicon area. This research attempted to implement filters and oscillators operating at 1-5 GHz using transistors only, to reduce the circuits’ area. The filters and oscillators are designed using active inductors, based on the gyrator principle; they are fabricated in standard digital CMOS technology to be compatible with logic circuits and further lower the cost. To obtain the highest operating frequency, only parasitic capacitors were used. Two new active-inductor circuits are derived from this research, labeled allNMOS and all-NMOS-II. The all-NMOS active inductor was used to design high-Q bandpass filters and oscillators, which were fabricated in TSMC’s 0.18-µm digital CMOS process. The highest center frequency measured was 5.7 GHz at 0.20-µm gate length and the maximum repeatably measured Q was 665. 2.4-GHz circuits were also designed and fabricated in 0.40-µm gate length. The all-NMOS-II circuit has superior linearity and signal fidelity, which are robust against process and temperature variations, due to its novel structure. It was used in signal drivers and will be fabricated in commercial products. Small-signal analysis was conducted for each of the active-inductor, filter and oscillator circuits, and the calculated performance matches those from simulations. The noise performance of the active inductor, active-inductor filter and oscillator was also analyzed and the calculated results agree with simulations. The difference between simulation and measured results is about 10% due to modeling and parasitic extraction error. The all-NMOS active-inductor circuit was granted a US patent. The US patent for all-NMOS-II circuit is pending. This research generated three conference papers and two journal papers.
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Ng, Chik-wai, and 吳植偉. "Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45896926.

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Books on the topic "Metal oxide semiconductors – Design and construction"

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Peluso, Vincenzo. Design of low-voltage low-power CMOS Delta-Sigma A/D converters. Boston: Kluwer Academic Publishers, 1999.

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High voltage MOS device design: Injection enhancement and negative gate capacitance. Konstanz: Hartung-Gorre Verlag, 2005.

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Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. New York: IEEE Press, 2005.

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1960-, Li Harry W., and Boyce David E. 1940-, eds. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1997.

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Baker, R. Jacob. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1998.

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Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. Piscataway, NJ: IEEE Press, 2008.

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Schumicki, G. Prozesstechnologie: Fertigungsverfahren für integrierte MOS-Schaltungen. Berlin: Springer-Verlag, 1991.

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Switched-current design and implementation of oversampling A/D converters. Boston: Kluwer Academic Publishers, 1997.

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Craninckx, J. Wireless CMOS frequency synthesizer design. Boston: Kluwer Academic Publishers, 1998.

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1960-, Li Harry W., Boyce David E. 1940-, and Institute of Electrical and Electronics Engineers, eds. CMOS circuit design, layout, and simulation. New Delhi: Prentice-Hall of India, 2004.

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Book chapters on the topic "Metal oxide semiconductors – Design and construction"

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Lei, Dian, and Xiao Gong. "Ge0.83Sn0.17 P-Channel Metal-Oxide-Semiconductor Field- Effect Transistors: Impact of Sulfur Passivation on Gate Stack Quality." In Design, Simulation and Construction of Field Effect Transistors. InTech, 2018. http://dx.doi.org/10.5772/intechopen.74532.

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Conference papers on the topic "Metal oxide semiconductors – Design and construction"

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Lee, Chang-Chun, Pei-Chen Huang, and Chi-Wei Wang. "Performance Variation of Nano-Scaled Devices in 3D-IC Packaging Architecture Induced by TSV Residual Stress." In ASME 2019 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/imece2019-10450.

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Abstract Through-silicon via (TSV) technique, is widely adopted as the vertical interconnection technology of three-dimensional integrated circuit packaging architecture. However, fabrication process-induced residual stress occurred in TSV during annealing and introduced the subsequent thermal–mechanical stress into silicon-based interposer. Aforementioned residual stress will affect the performance and electric stability of p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) located around TSV. Accordingly, this study is focused on the influences of TSV layout with intrinsic residual stress on concerned pMOSFET performance. Process-oriented finite element analysis (FEA) is performed to simulate stress distribution of pMOSFET when concerned device channel region was affected by TSV residual stress and embedded SiGe alloy. To conquer the difficulty of FEA construction on TSV and pMOSFET with significant scale mismatch in same FEA model, the global–local submodeling technology is adopted to manage the balance between model complexity and numerical convergence. The residual stress magnitude effect of different designed TSV diameter on concerned channel stress components is extracted to estimate its influence on pMOSFET with scaled gate width. The presented results indicated that increased TSV residual stress could obviously reduce performance of concerned device. It should be noted that the S/D stressor remarkably dominated mobility gain of strained pMOSFET.
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Diver, Richard B., James E. Miller, Mark D. Allendorf, Nathan P. Siegel, and Roy E. Hogan. "Solar Thermochemical Water-Splitting Ferrite-Cycle Heat Engines." In ASME 2006 International Solar Energy Conference. ASMEDC, 2006. http://dx.doi.org/10.1115/isec2006-99147.

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Thermochemical cycles are a type of heat engine that utilize high-temperature heat to produce chemical work. Like their mechanical work-producing counterparts, their efficiency depends on operating temperature and on the irreversibilities of their internal processes. With this in mind, we have invented innovative design concepts for two-step solar-driven thermochemical heat engines based on iron oxide and iron oxide mixed with other metal oxides (ferrites). These concepts utilize two sets of moving beds of ferrite reactant material in close proximity and moving in opposite directions to overcome a major impediment to achieving high efficiency – thermal recuperation between solids in efficient counter-current arrangements. They also provide inherent separation of the product hydrogen and oxygen and are an excellent match with high-concentration solar flux. However, they also impose unique requirements on the ferrite reactants and materials of construction as well as an understanding of the chemical and cycle thermodynamics. In this paper, the Counter-Rotating-Ring Receiver/Reactor/Recuperator (CR5) solar thermochemical heat engine concept is introduced and its basic operating principals are described. Preliminary thermal efficiency estimates are presented and discussed. Our results and development approach are also outlined.
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Gillet, Jean-Numa, Yann Chalopin, and Sebastian Volz. "Atomic-Scale Three-Dimensional Phononic Crystals With a Lower Thermal Conductivity Than the Einstein Limit of Bulk Silicon." In ASME 2008 Heat Transfer Summer Conference collocated with the Fluids Engineering, Energy Sustainability, and 3rd Energy Nanotechnology Conferences. ASMEDC, 2008. http://dx.doi.org/10.1115/ht2008-56403.

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Extensive research about superlattices with a very low thermal conductivity was performed to design thermoelectric materials. Indeed, the thermoelectric figure of merit ZT varies with the inverse of the thermal conductivity but is directly proportional to the power factor. Unfortunately, as nanowires, superlattices reduce heat transfer in only one main direction. Moreover, they often show dislocations owing to lattice mismatches. Therefore, fabrication of nanomaterials with a ZT larger than the alloy limit usually fails with the superlattices. Self-assembly is a major epitaxial technology to fabricate ultradense arrays of germaniums quantum dots (QD) in a silicon matrix for many promising electronic and photonic applications as quantum computing. We theoretically demonstrate that high-density three-dimensional (3-D) periodic arrays of small self-assembled Ge nanoparticles (i.e. the QDs), with a size of some nanometers, in Si can show a very low thermal conductivity in the three spatial directions. This property can be considered to design thermoelectric devices, which are compatible with the complementary metal-oxide-semiconductor (CMOS) technologies. To obtain a computationally manageable model of these nanomaterials, we simulate their thermal behavior with atomic-scale 3-D phononic crystals. A phononic-crystal period (supercell) consists of diamond-like Si cells. At each supercell center, we substitute Si atoms by Ge atoms in a given number of cells to form a box-like Ge nanoparticle. The phononic-crystal dispersion curves, which are computed by classical lattice dynamics, are flat compared to those of bulk Si. In an example phononic crystal, the thermal conductivity can be reduced below the value of only 0.95 W/mK or by a factor of at least 165 compared to bulk silicon at 300 K. Close to the melting point of silicon, we obtain a larger decrease of the thermal conductivity below the value of 0.5 W/mK, which is twice smaller than the classical Einstein Limit of single crystalline Si. In this paper, we use an incoherent-scattering approach for the nanoparticles. Therefore, we expect an even larger decrease of the phononic-crystal thermal conductivity when multiple-scattering effects, as multiple reflections and diffusions of the phonons between the Ge nanoparticles, will be considered in a more realistic model. As a consequence of our simulations, a large ZT could be achieved in 3-D ultradense self-assembled Ge nanoparticle arrays in Si. Indeed, these nanomaterials with a very small thermal conductivity are crystalline semiconductors with a power factor that can be optimized by doping using CMOS-compatible technologies, which is not possible with other recently-proposed nanomaterials.
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Reports on the topic "Metal oxide semiconductors – Design and construction"

1

Albert F. Zeller. Design and construction of a radiation resistant quadrupole using metal oxide insulated CICC. Office of Scientific and Technical Information (OSTI), December 2012. http://dx.doi.org/10.2172/1058846.

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