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1
Sotner, Roman, Jan Jerabek, Ladislav Polak, Roman Prokop, and Vilem Kledrowetz. "Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example." Electronics 8, no. 5 (May 22, 2019): 568. http://dx.doi.org/10.3390/electronics8050568.
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This paper introduces new integrated analog cells fabricated in a C035 I3T25 0.35-μm ON Semiconductor process suitable for a modular design of advanced active elements with multiple terminals and controllable features. We developed and realized five analog cells on a single integrated circuit (IC), namely a voltage differencing differential buffer, a voltage multiplier with current output in full complementary metal–oxide–semiconductor (CMOS) form, a voltage multiplier with current output with a bipolar core, a current-controlled current conveyor of the second generation with four current outputs, and a single-input and single-output adjustable current amplifier. These cells (sub-blocks of the manufactured IC device), designed to operate in a bandwidth of up to tens of MHz, can be used as a construction set for building a variety of advanced active elements, offering up to four independently adjustable internal parameters. The performances of all individual cells were verified by extensive laboratory measurements, and the obtained results were compared to simulations in the Cadence IC6 tool. The definition and assembly of a newly specified advanced active element, namely a current-controlled voltage differencing current conveyor transconductance amplifier (CC-VDCCTA), is shown as an example of modular interconnection of the selected cells. This device was implemented in a newly synthesized topology of an electronically linearly tunable quadrature oscillator. Features of this active element were verified by simulations and experimental measurements.
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Breslin, Catherine, and Adrian O'Lenskie. "Neuromorphic hardware databases for exploring structure–function relationships in the brain." Philosophical Transactions of the Royal Society of London. Series B: Biological Sciences 356, no. 1412 (August 29, 2001): 1249–58. http://dx.doi.org/10.1098/rstb.2001.0904.
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Neuromorphic hardware is the term used to describe full custom–designed integrated circuits, or silicon ‘chips’, that are the product of neuromorphic engineering—a methodology for the synthesis of biologically inspired elements and systems, such as individual neurons, retinae, cochleas, oculomotor systems and central pattern generators. We focus on the implementation of neurons and networks of neurons, designed to illuminate structure–function relationships. Neuromorphic hardware can be constructed with either digital or analogue circuitry or with mixed–signal circuitry—a hybrid of the two. Currently, most examples of this type of hardware are constructed using analogue circuits, in complementary metal–oxide–semiconductor technology. The correspondence between these circuits and neurons, or networks of neurons, can exist at a number of levels. At the lowest level, this correspondence is between membrane ion channels and field–effect transistors. At higher levels, the correspondence is between whole conductances and firing behaviour, and filters and amplifiers, devices found in conventional integrated circuit design. Similarly, neuromorphic engineers can choose to design Hodgkin–Huxley model neurons, or reduced models, such as integrate–and–fire neurons. In addition to the choice of level, there is also choice within the design technique itself; for example, resistive and capacitive properties of the neuronal membrane can be constructed with extrinsic devices, or using the intrinsic properties of the materials from which the transistors themselves are composed. So, silicon neurons can be built, with dendritic, somatic and axonal structures, and endowed with ionic, synaptic and morphological properties. Examples of the structure–function relationships already explored using neuromorphic hardware include correlation detection and direction selectivity. Establishing a database for this hardware is valuable for two reasons: first, independently of neuroscientific motivations, the field of neuromorphic engineering would benefit greatly from a resource in which circuit designs could be stored in a form appropriate for reuse and re–fabrication. Analogue designers would benefit particularly from such a database, as there are no equivalents to the algorithmic design methods available to designers of digital circuits. Second, and more importantly for the purpose of this theme issue, is the possibility of a database of silicon neuron designs replicating specific neuronal types and morphologies. In the future, it may be possible to use an automated process to translate morphometric data directly into circuit design compatible formats. The question that needs to be addressed is: what could a neuromorphic hardware database contribute to the wider neuroscientific community that a conventional database could not? One answer is that neuromorphic hardware is expected to provide analogue sensory–motor systems for interfacing the computational power of symbolic, digital systems with the external, analogue environment. It is also expected to contribute to ongoing work in neural–silicon interfaces and prosthetics. Finally, there is a possibility that the use of evolving circuits, using reconfigurable hardware and genetic algorithms, will create an explosion in the number of designs available to the neuroscience community. All this creates the need for a database to be established, and it would be advantageous to set about this while the field is relatively young. This paper outlines a framework for the construction of a neuromorphic hardware database, for use in the biological exploration of structure–function relationships.
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Anusha, N., and T. Sasilatha. "Performance Analysis of Wide AND OR Structures Using Keeper Architectures in Various Complementary Metal Oxide Semiconductors Technologies." Journal of Computational and Theoretical Nanoscience 13, no. 10 (October 1, 2016): 6999–7008. http://dx.doi.org/10.1166/jctn.2016.5660.
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Power dissipation and area are the important constraints in VLSI design. Various techniques are employed in reducing the power dissipation of the logic circuits. Dynamic CMOS circuits are one of the techniques in VLSI to lower the power dissipation. All gates can be designed using dynamic CMOS to lower the power dissipation. In this paper wide AND OR gates are implemented using Dynamic circuits, where keeper architecture is employed in order to prevent leakage current and to ensure that correct output is obtained. The performance analysis of Wide AND OR structures implemented in dynamic CMOS with mandatory keeper architectures in ultra submicron range are analyzed. A comparative analysis of Power dissipation and area of the keeper architectures employed in dynamic CMOS in different lower nanometer such as 120 nm, 90 nm, 70 nm and 50 nm is analyzed.
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Rajendran, Selvakumar, Arvind Chakrapani, Srihari Kannan, and Abdul Quaiyum Ansari. "A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 14, no. 4 (June 17, 2021): 377–97. http://dx.doi.org/10.2174/2352096514666210127140831.
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Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in μm and nm technology. The current mirror (CM) is a basic building block used to enhance performance characteristics by constructing complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technologybased current mirror (CM) circuits are discussed with their advantages and disadvantages accompanied by the performance analysis of different parameters. It also briefs various techniques which are employed for improvising the current mirror performance like gain boosting and bandwidth extension. Besides, this paper lists the CMs that use different types of MOS devices like Floating Gate MOS, Bulk-driven MOS, and Quasi-Floating Gate MOS. As a result, the paper performs a detailed review of CMOS Current mirrors and their techniques. Results: Basic CM circuits that can act as building blocks in the VLSI circuits are simulated using 0.25 μm, BSIM and Level 1 technology. In addition, various devices based CMs are investigated and compared. Conclusion: The comprehensive discussion shows that the current mirror plays a significant role in analog/mixed-signal circuits design to realize complex systems for low-power biomedical and wireless applications.
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Kalagadda, B., N. Muthyala, and K. K. Korlapati. "Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques." Journal of Engineering Research [TJER] 14, no. 1 (March 1, 2017): 74. http://dx.doi.org/10.24200/tjer.vol14iss1pp74-84.
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Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation.
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Wang, Xiaochun, Meicheng Fu, Heng Yang, Jiali Liao, and Xiujian Li. "Temperature and Pulse-Energy Range Suitable for Femtosecond Pulse Transmission in Si Nanowire Waveguide." Applied Sciences 10, no. 23 (November 26, 2020): 8429. http://dx.doi.org/10.3390/app10238429.
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We experimentally measured the femtosecond pulse transmission through a silicon-on-insulator (SOI) nanowire waveguide under different temperatures and input pulse energy with a cross-correlation frequency-resolved optical gating (XFROG) measurement setup. The experimental results demonstrated that the temperature and pulse energy dependence of the Si photonic nanowire waveguide (SPNW) is interesting rather than just monotonous or linear, and that the suitable temperature and pulse-energy range is as suggested in this experiment, which will be valuable for analyzing the practical design of the operating regimes and the fine dispersion engineering of various ultrafast photonic applications based on the SPNWs. The research results will contribute to developing the SPNWs with photonic elements and networks compatible with mature complementary metal–oxide–semiconductors (CMOS).
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Mizuno, Tomohisa, Naoki Mizoguchi, Kotaro Tanimoto, Tomoaki Yamauchi, Mitsuo Hasegawa, Toshiyuki Sameshima, and Tsutomu Tezuka. "New Source Heterojunction Structures with Relaxed/Strained Semiconductors for Quasi-Ballistic Complementary Metal–Oxide–Semiconductor Transistors: Relaxation Technique of Strained Substrates and Design of Sub-10 nm Devices." Japanese Journal of Applied Physics 49, no. 4 (April 20, 2010): 04DC13. http://dx.doi.org/10.1143/jjap.49.04dc13.
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Chang, Wen-Teng, Hsu-Jung Hsu, and Po-Heng Pao. "Vertical Field Emission Air-Channel Diodes and Transistors." Micromachines 10, no. 12 (December 6, 2019): 858. http://dx.doi.org/10.3390/mi10120858.
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Vacuum channel transistors are potential candidates for low-loss and high-speed electronic devices beyond complementary metal-oxide-semiconductors (CMOS). When the nanoscale transport distance is smaller than the mean free path (MFP) in atmospheric pressure, a transistor can work in air owing to the immunity of carrier collision. The nature of a vacuum channel allows devices to function in a high-temperature radiation environment. This research intended to investigate gate location in a vertical vacuum channel transistor. The influence of scattering under different ambient pressure levels was evaluated using a transport distance of about 60 nm, around the range of MFP in air. The finite element model suggests that gate electrodes should be near emitters in vertical vacuum channel transistors because the electrodes exhibit high-drive currents and low-subthreshold swings. The particle trajectory model indicates that collected electron flow (electric current) performs like a typical metal oxide semiconductor field effect-transistor (MOSFET), and that gate voltage plays a role in enhancing emission electrons. The results of the measurement on vertical diodes show that current and voltage under reduced pressure and filled with CO2 are different from those under atmospheric pressure. This result implies that this design can be used for gas and pressure sensing.
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Heyns, M., and W. Tsai. "Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials." MRS Bulletin 34, no. 7 (July 2009): 485–92. http://dx.doi.org/10.1557/mrs2009.136.
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AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transistor design. The introduction of deposited high-κ gate dielectrics and metal gates as replacements for the thermally grown SiO2 and poly-Si electrode was a major challenge that has been met in the transition toward the 32 nm technology node since it replaced the heart of the metal oxide semiconductor structure. For the next generation of technology nodes, even bigger hurdles will need to be overcome, since new device structures and high-mobility channel materials such as Ge and III–V compounds might be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 16 nm CMOS node and beyond. The basic properties of these high-mobility channel materials and their impact on the device performance have to be fully understood to allow process integration and full-scale manufacturing. In addition to thermal stability, compatibility with other materials, electronic transport properties, and especially the passivation of electronically active defects at the interface with a high-κ dielectric, are enormous challenges. Many encouraging results have been obtained, but the stringent demands in terms of electrical performance and oxide thickness scaling needed for highly scaled CMOS devices are not yet fully met. Other areas where breakthroughs will be needed are the formation of low-resistivity contacts, especially on III–V materials, and III–V materials suited for pMOS channels. An overview of the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices is given in this issue of MRS Bulletin.
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Banerjee, Writam. "Challenges and Applications of Emerging Nonvolatile Memory Devices." Electronics 9, no. 6 (June 22, 2020): 1029. http://dx.doi.org/10.3390/electronics9061029.
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Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.
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Ren, Xiaojiao, Ming Zhang, Nicolas Llaser, and Yiqi Zhuang. "On-Chip Measurement of Quality Factor Implemented in 0.35μm CMOS." Journal of Circuits, Systems and Computers 25, no. 08 (May 17, 2016): 1650087. http://dx.doi.org/10.1142/s0218126616500870.
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Based on time-domain quality factor (Q-factor) measurement principle, we have proposed an architecture which has the potential to be integrated on-chip. Thanks to the proposed original reconfigurable structure, the main measurement error from the offset of the operational transconductance amplifier (OTA) used can be cancelled automatically during the measurement operation, leading to a high accuracy Q-factor measurement. The digital control circuit plays an important role in the automatic passage between the two configurations designed, i.e., peak detector and comparator. The main advantages of the proposed time-domain Q-factor measurement lay on the possibility of being integrated next to the Micro Electro Mechanical System (MEMS) resonator to be measured, the miniaturization of the whole measuring system as well as the enhancement of the measurement performance, and to guide the design of such architecture, a theoretical analysis linking the required accuracy and the given Q-factor to the circuit parameters have been given in this paper. The proposed circuit is designed and simulated in a 0.35[Formula: see text][Formula: see text]m Complementary Metal Oxide Semiconductors (CMOS) technology. The post-layout simulation results show that the operating frequency can reach up to 200[Formula: see text]kHz with an accuracy of 0.4%.
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Kajal and Vijay Kumar Sharma. "An Investigation for the Negative-Bias Temperature Instability Aware CMOS Logic." Micro and Nanosystems 13 (January 25, 2021). http://dx.doi.org/10.2174/1876402913666210125144339.
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Background: Scaling of the dimensions of semiconductor device plays a very important role in the advancement of very large-scale integration (VLSI) technology. There are many advantages of scaling in VLSI technology such as increment in the speed of the device and less area requirement of the device. Aggressive device scaling causes some limitations in the form of short channel effects which produce large leakage current. Large leakage current harms the characteristics of the device and affects the reliability of the device. Objective: The most important and popular reliability issue in deep submicron (DSM) regime is negative-bias temperature instability (NBTI). NBTI effect increases the threshold voltage of p-channel metal oxide semiconductor (PMOS) device over the time and affects the different characteristics of the device. As a result, circuit delay exceeds the design specification and there may be timing violations or logic failure. Different performance parameters are observed under NBTI effect for different logic gates. Methods: This paper presents an impact of NBTI at 22nm Berkeley short-channel IGFET model4 (BSIM4) predictive technology model (PTM) for complementary metal oxide semiconductor (CMOS) logic gates. Reliability simulations are utilised to evaluate the amount of gradual damage in PMOS device due to NBTI effect. Results : The impact of NBTI degradation is checked for various CMOS logic gates using Mentor Graphics’s Eldo circuit simulator. Output voltage and drain current are reducing over the time under NBTI effect. Conclusion: NBTI degradation increases the threshold voltage of PMOS device over the time and affects the different characteristics of the device.
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"The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology." International Journal of Engineering and Advanced Technology 9, no. 1 (October 30, 2019): 43–49. http://dx.doi.org/10.35940/ijeat.a1027.109119.
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Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors
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"The Mixed Logic Style based Low Power and High Speed One-bit Binary adder for SOI Designs AT 32NM Technology." International Journal of Recent Technology and Engineering 8, no. 4 (November 30, 2019): 361–66. http://dx.doi.org/10.35940/ijrte.d6903.118419.
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Binary adders are the fundamental building blocks to construct Data Processing arithmetic units. A novel one-bit full adder is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the one-bit full adder like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual Voltage Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity and by improving the driving capability. This Mixed logic style provides 83.53% average power consumption and Propagation Delay of 14.02% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of the Full adder logic at different voltages. The 32nm model file is used for MOS transistors
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Naz, Syed Farah, Sadat Riyaz, and Vijay Kumar Sharma. "A Review of QCA Nanotechnology as an Alternate to CMOS." Current Nanoscience 17 (March 1, 2021). http://dx.doi.org/10.2174/1573413717666210301111822.
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Background: The human ken and understanding about esoteric phenomenon develops the period from space to the sub-atomic level. The passion to further explore the unexplored domains and dimensions boosts the human advancement in a cyclic way. A significant part of such passion follows in the electronics industry. Moore’s law is reaching the practical limitations because of further scaling of metal oxide semiconductor (MOS) devices. The need of a more dexterous and effective technology approach is demanded. Quantum-dot cellular automata (QCA) is an emerging technology which avoids the physical limitations of the MOS device. QCA is a dynamic computational transistor paradigm that addresses device density, power, operating frequency and interconnection problems. It requires an extensive study to know the fundamentals of logic implementation. Objective: Immense research and experiments due same vigor led to the evolving nanotechnology and a feasible alternative to complementary metal oxide semiconductor (CMOS) technology. A comprehensive study is presented in the paper to enhance the basics of QCA technology and the way of implementation of the logic circuits. Different existing circuits using QCA technology are discussed and compared for different parameters. Methods: Scaling the devices can reduce the power consumption of the MOS device. Quantum dots are nanostructures made from semi-conductive conventional materials. It is possible to model these constructions as 3-dimensional (3D) quantum energy wells. Logical operations and data movement are performed using Columbic interaction between nearby QCA cells instead of current flow. Results: The focus of this review paper is to study the trends which have been proposed and compared the designs for various digital circuits. The performance of different circuits such as XOR, adder, reversible gates and flip-flops are provided. Different logic circuits are compared on the parameters such as cell count, area and latency. At least 10 QCA cells are used for the XOR gate with 1 clock latency. Minimum 44 QCA cells are required to make a full adder with 1.25 clock latency.
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Torres, Florent, Eric Kerhervé, Andreia Cathelin, and Magali De Matos. "A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications." International Journal of Microwave and Wireless Technologies, August 25, 2020, 1–18. http://dx.doi.org/10.1017/s1759078720001087.
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Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.
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TR, Mrs Lakshmidevi, Mr K. N. Jeevan Reddy, Mr Ashrith Rao, Mr Dhanush Kashyap S, and Ms Chandini K. "Comparison of 4-Bit SAR ADC Using Different Logic Styles in 90nm Technology." International Journal of Advanced Research in Science, Communication and Technology, August 6, 2021, 100–108. http://dx.doi.org/10.48175/ijarsct-1817.
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In recent years, we have come across a growing need for the design of low power, long battery life Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC). ADCs are the major component of all the systems which need to process an analogue signal obtained from measuring real world parameters and hence they need to be efficient enough depending on the application and power constraint of the device. Speed is also an important parameter as it is used in many real time applications. The basic components of the SAR ADC can be implemented using circuits of various logics available for the logic gates, adders, comparators utilised in it. This paper presents the working of 4-bit successive approximation register analog-to-digital converters (SAR ADC) in three different logics namely, Complementary Metal Oxide Semiconductors (CMOS), Transmission Gates (TG), and Double Pass Transistors (DPL) logics, which were used in the basic components of each major block of the ADC. The aim of this paper here is to compare the various parameters such as area, power consumption and delay between the three different technologies chosen above. The SAR ADCs were implemented for this purpose in 90nm Technology using the Cadence Virtuoso Design Tool building schematics and layouts for the same and calculating the various parameters required for the above-mentioned comparison.
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Chang, Jane P. "Innovative Curriculum on Electronic Materials Processing and Engingeering." MRS Proceedings 684 (2001). http://dx.doi.org/10.1557/proc-684-gg5.2.
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Recognizing that the traditional engineering education training is often inadequate in preparing the students for the challanges presented by this industry's dynamic environment and insufficient to meet the empoyer's criteria in hiring new engineers, a new curriculum on Semiconductor Manufacturing is instituted in the Chemical Engineering Department at UCLA to train the students in various scientific and technologica areas that are pertinenet to the microelectronics industries. This paper describes this new mutidisciplinary curriculum that provides knowledge and skills in semiconductor manufacturing through a series ofcourses that emphasize on the application of fundamenta engineeering disciplines in solid-state physics, materials science of semiconductors, and chemical processing. The curriculum comprises three major components:(1)a comprehensive course curriculum in semiconductor manufacturing; (2) a laboratory for hands-on training in semiconductor device fabrication; (3) design of experiments. The capstone laboratory course is designed to strengthen students’ training in “unit operatins” used in semicounductor manufacturing and allow them to practice engineering principles using the state-of-the-art experimental setup. It comprises the most comprehensive training(seven photolithographic steps and numero0us chemical processes)in fabricating and testing complementary metal-oxide-semiconductor (CMOS) devices. This curriculum is recentyaccredited by the Accreditation Board for Engineering and Technology(ABET).
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Li, Kai, Chao Teng, Shuang Wang, and Qianhao Min. "Recent Advances in TiO2-Based Heterojunctions for Photocatalytic CO2 Reduction With Water Oxidation: A Review." Frontiers in Chemistry 9 (April 15, 2021). http://dx.doi.org/10.3389/fchem.2021.637501.
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Photocatalytic conversion of CO2 into solar fuels has gained increasing attention due to its great potential for alleviating the energy and environmental crisis at the same time. The low-cost TiO2 with suitable band structure and high resistibility to light corrosion has proven to be very promising for photoreduction of CO2 using water as the source of electrons and protons. However, the narrow spectral response range (ultraviolet region only) as well as the rapid recombination of photo-induced electron-hole pairs within pristine TiO2 results in the low utilization of solar energy and limited photocatalytic efficiency. Besides, its low selectivity toward photoreduction products of CO2 should also be improved. Combination of TiO2 with other photoelectric active materials, such as metal oxide/sulfide semiconductors, metal nanoparticles and carbon-based nanostructures, for the construction of well-defined heterostructures can enhance the quantum efficiency significantly by promoting visible light adsorption, facilitating charge transfer and suppressing the recombination of charge carriers, resulting in the enhanced photocatalytic performance of the composite photocatalytic system. In addition, the adsorption and activation of CO2 on these heterojunctions are also promoted, therefore enhancing the turnover frequency (TOF) of CO2 molecules, so as to the improved selectivity of photoreduction products. This review focus on the recent advances of photocatalytic CO2 reduction via TiO2-based heterojunctions with water oxidation. The rational design, fabrication, photocatalytic performance and CO2 photoreduction mechanisms of typical TiO2-based heterojunctions, including semiconductor-semiconductor (S-S), semiconductor-metal (S-M), semiconductor-carbon group (S-C) and multicomponent heterojunction are reviewed and discussed. Moreover, the TiO2-based phase heterojunction and facet heterojunction are also summarized and analyzed. In the end, the current challenges and future prospects of the TiO2-based heterostructures for photoreduction of CO2 with high efficiency, even for practical application are discussed.
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Rahimi, Ronak, and D. Korakakis. "Charge transport in ambipolar pentacene thin film transistors." MRS Proceedings 1286 (2011). http://dx.doi.org/10.1557/opl.2011.239.
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ABSTRACTAmbipolar organic transistors are technologically interesting because of their potential applications in light-emitting field-effect transistors [1] and complementary-metal-oxide-semiconductor (CMOS) devices by providing ease of design, low cost of fabrication, and flexibility [2]. Although common organic semiconductors show either n- or p-type charge transport characteristic, organic transistors with ambipolar characteristics have been reported recently. In this work, we show that ambipolar transport can be achieved within a single transistor channel using LiF gate dielectric in the transistors with pentacene active layer. This ambipolar behavior can be controlled by the applied source-drain and gate biases. It was found that at low source-drain biases multistep hopping is the dominant conduction mechanism, while in high voltage regimes I-V data fits in Fowler-Nordheim (F-N) tunneling model. From the slope of the F-N plots, the dependency between field enhancement factor and the transition point in conduction mechanism upon gate bias has been extracted. The transition points show more dependency on gate voltage for negative biases compared to the positive biases. While sweeping negative gate voltages from -5 to -20 V, the source-drain voltages change from about 27 to 17 V. On the other hand, for positive gate voltages from 5 to 20 V, the value of the transition point stays at approximately 36 V. In order to further understand the transport mechanisms, new structures with an interface layer between dielectric and active layer have been fabricated and characterized. As expected, a significant decrease in the amount of the source-drain current has been observed after introducing the interface layer.