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Dissertations / Theses on the topic 'Metal oxide semiconductors, Complementary Design and construction'

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Published: 4 June 2021
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1

Bond, Steven Winfred. "Through-silicon circuit optical communications links." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15390.

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2

Tang, Wei 1976. "High-speed parallel optical receivers." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103298.

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Parallel optical interconnects (POI) have attracted a great deal of attention in the past two decades as the system bandwidth continues to increase. Optical interconnects are known to have more advantages than their electrical counterparts in many aspects such as crosstalk, bandwidth distance product, power consumption, and RC time delay. The parallelization of several optical links is also an effective method to increase the aggregate data rate while keeping the component count manageable and to reduce the unit cost of optics, electronics, and packaging at lower line rate.
Parallel optical transceiver modules running at several gigabits per second are commercially available nowadays. Parallel optical receivers are one of the key components of parallel interconnected systems. In this work, we describe how a low-power parallel CMOS preamplifier IC and a deskew IC have been designed and fabricated through the IBM 0.13mum CMOS technology. The performances of three different transimpedance amplifier (TIA) topologies are compared experimentally. The best of the three TIAs shows a differential gain of 56.2dBO, 2.6GHz bandwidth, and less than -16dBm sensitivity with a bit-error-rate (BER) less than 10-12. The TIA consumes 2.5mW of power from a 1.2V supply while the channel power is 22mW with a 400mV pp differential output swing.
A novel method of accurately measuring the crosstalk power penalty with an on-chip PRBS generator is proposed and its implementation is described. The use of an on-chip PRBS generator to drive the dummy channels eliminates the data pattern dependence between the aggressors and the victim. The inevitable channel skew associated with parallel channels can be removed by a phase-locked loop (PLL) based deskew method. We investigated the skew compensation range of this method theoretically and our experimental results confirm our conclusion.
Various practical design and test techniques such as photodiode modeling, AC coupling, low-pass filtering and continuous skew generation, and their implementations, are discussed and implemented in this thesis.
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3

Deshpande, Sandeep. "A cost quality model for CMOS IC design." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12042009-020251/.

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4

Xiao, Haiqiao. "Design of Radio-Frequency Filters and Oscillators in Deep-Submicron CMOS Technology." PDXScholar, 2008. https://pdxscholar.library.pdx.edu/open_access_etds/5233.

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Radio-frequency filters and oscillators are widely used in wireless communication and high-speed digital systems, and they are mostly built on passive integrated inductors, which occupy a relative large silicon area. This research attempted to implement filters and oscillators operating at 1-5 GHz using transistors only, to reduce the circuits’ area. The filters and oscillators are designed using active inductors, based on the gyrator principle; they are fabricated in standard digital CMOS technology to be compatible with logic circuits and further lower the cost. To obtain the highest operating frequency, only parasitic capacitors were used. Two new active-inductor circuits are derived from this research, labeled allNMOS and all-NMOS-II. The all-NMOS active inductor was used to design high-Q bandpass filters and oscillators, which were fabricated in TSMC’s 0.18-µm digital CMOS process. The highest center frequency measured was 5.7 GHz at 0.20-µm gate length and the maximum repeatably measured Q was 665. 2.4-GHz circuits were also designed and fabricated in 0.40-µm gate length. The all-NMOS-II circuit has superior linearity and signal fidelity, which are robust against process and temperature variations, due to its novel structure. It was used in signal drivers and will be fabricated in commercial products. Small-signal analysis was conducted for each of the active-inductor, filter and oscillator circuits, and the calculated performance matches those from simulations. The noise performance of the active inductor, active-inductor filter and oscillator was also analyzed and the calculated results agree with simulations. The difference between simulation and measured results is about 10% due to modeling and parasitic extraction error. The all-NMOS active-inductor circuit was granted a US patent. The US patent for all-NMOS-II circuit is pending. This research generated three conference papers and two journal papers.
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5

Ng, Chik-wai, and 吳植偉. "Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45896926.

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6

Mule, Anthony Victor. "Volume grating coupler-based optical interconnect technologies for polylithic gigascale integrat." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/9447.

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7

Blalock, Benjamin Joseph. "A 1-volt CMOS wide dynamic Range operational amplifier." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/15441.

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8

Bhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.

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9

Dong, Zhiwei. "Low-power, low-distortion constant transconductance Gm-C filters." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/25400.

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10

Mony, Madeleine. "Reprogrammable optical phase array." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103276.

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The evolving needs of network carriers are changing the design of optical networks. In order to reduce cost, latency, and power consumption, electrical switches are being replaced with optical switching fabrics at the core of the networks. An example of such a network is an Agile All-Photonic Network (AAPN).
This thesis presents a novel device that was designed to operate as an optical switch within the context of an AAPN network. The device is a Reprogrammable Optical Phase Array (ROPA), and the design consists of applying multiple electric fields of different magnitudes across an electro-optic material in order to create a diffractive optical element. The configuration of the electric fields can change to modify the properties of the diffractive device.
Such a device has a wide range of potential applications, and two different ROPA designs are presented. Both designs are optimized to function as 1xN optical switches. The switches are wavelength tunable and have switching times on the order of microseconds. The ROPA devices consist of two parts: a bulk electro-optic crystal, and a high-voltage CMOS chip for the electrical control of the device. The design, simulation, fabrication and testing of both the electrical and optical components of the devices are presented.
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11

Kumar, Ajay. "A novel Q tuning technique for high-Q high-frequency IF bandpass filter." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15904.

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12

Gibson, Jr Allen. "Design and simulation of CMOS active mixers." Master's thesis, University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4765.

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This paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage range from the most commonly known mixer design, to implemented design techniques that are used to increase the mixers important design properties as the demand of CMOS technology and the overall RF system rises. All mixer topologies were designed and simulated using TSMC 0.18 micrometer] CMOS technology in Advanced Design Systems, a simulator used specifically for RF designs.
ID: 030646192; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (M.S.E.E.)--University of Central Florida, 2011.; Includes bibliographical references.
M.S.E.E.
Masters
Electrical Engineering and Computing
Engineering and Computer Science
Electrical Engineering
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13

Long, Ethan Schuyler. "The Role of Temperature in Testing Deep Submicron CMOS ASICs." PDXScholar, 2003. https://pdxscholar.library.pdx.edu/open_access_etds/34.

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Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.
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14

Shin, Eung Seo. "Automated Generation of Round-robin Arbitration and Crossbar Switch Logic." Diss., Available online, Georgia Institute of Technology, (2003), 2003. http://etd.gatech.edu/theses/available/etd-11232003-150424/.

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15

Hass, Joanna R. "Structural characterization of epitaxial graphene on silicon carbide." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26654.

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Thesis (Ph.D)--Physics, Georgia Institute of Technology, 2009.
Committee Co-Chair: Conrad, Edward; Committee Co-Chair: First, Phillip; Committee Member: Carter, Brent; Committee Member: de Heer, Walter; Committee Member: Zangwill, Andrew. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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16

Song, Indal. "Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector for Optical Interconnects." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4902.

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Trends toward increased integration and miniaturization of optical system components have created pressure to consolidate widely disparate analog and digital functions onto fewer and fewer chips with a goal of eventually built into a single mixed-signal chip. Yet, because of those performance requirements, the frontend circuit has traditionally used III-V compound semiconductor technologies, but the low-level of integration with other digital ICs limits the sustainability of such end products for short-distance applications. On the other hand, their CMOS counter parts, despite having such advantages as low power consumption, high yield that lowers the cost of fabrication, and a higher degree of integration, have not performed well enough to survive in such a noisy environment without sacrificing other important attributes. In this research, a high-speed CMOS preamplifier was designed and fabricated through TSMC 0.18/spl mu/m mixed-signal non-epi CMOS technology, and a 20/spl mu/m diameter InGaAs thin-film Inverted-MSM photodetector with a responsivity of 0.15A/W at a wavelength of 1550/spl mu/m was post-integrated onto the circuit. The circuit has a overall transimpedance gain of 60dB/spl Omega/, and bit-error-rate data and eye-diagram measurement results taken as high as 10Gbit/s are reported in this dissertation.
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17

Amarnath, Avinash. "A Self-Configurable Architecture on an Irregular Reconfigurable Fabric." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/634.

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Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale level. We argue that a bottom-up self-assembled fabric of nodes will be easier and cheaper to manufacture, however, one has to make compromises with regards to the device regularity, homogeneity, and reliability. The goal of this thesis is to evaluate the performance and cost of a self-configurable computing architecture composed of simple reconfigurable nodes for unstructured and unknown fabrics. We built a software and hardware framework for this purpose. The framework enables creating an irregular network of compute nodes where each node can be configured as a simple 2-input, 4-bit logic gate. The compute nodes are organized hierarchically by sending a packet through a top anchor node that recruits compute nodes with a chemically-inspired algorithm. The nodes are then self-configured by means of a gate-level netlist describing any digital logic circuit. A topology-agnostic optimization algorithm inspired by simulated annealing is then initiated to self-optimize the circuit for latency. Latency comparisons between non-optimized, brute-force optimized and our optimization algorithm are made. We further implement the architecture in VHDL and evaluate hardware cost, area, and energy consumption. The simple on-chip topology-agnostic optimization algorithm we propose results in a significant (up to 50\%) performance improvement compared to the non-optimized circuits. Our findings are of particular interest for emerging nano and molecular-scale circuits.
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18

Park, Yunseo. "Direct Conversion RF Front-End Implementation for Ultra-Wideband (UWB) and GSM/WCDMA Dual-Band Applications in Silicon-Based Technologies." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7563.

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This dissertation focuses on wideband circuit design and implementation issues up to 10GHz based on the direct conversion architecture in the CMOS and SiGe BiCMOS technologies. The dissertation consists of two parts: One, implementation of a RF front-end receiver for an ultra-wideband system and, two, implementation of a local oscillation (LO) signal for a GSM/WCDMA multiband application. For emerging ultra-wideband (UWB) applications, the key active components in the RF front-end receiver were designed and implemented in 0.18um SiGe BiCMOS process. The design of LNA, which is the critical circuit block for both systems, was analyzed in terms of noise, linearity and group delay variation over an extemely wide bandwidth. Measurements are demonstrated for an energy-thrifty UWB receiver based on an MB-OFDM system covering the full FCC-allowed UWB frequency range. For multiband applications such as a GSM/WCDMA dual-band application, the design of wideband VCO and various frequency generation blocks are investigated as alternatives for implementation of direct conversion architecture. In order to reduce DC-offset and LO pulling phenomena that degrade performance in a typical direct conversion scheme, an innovative fractional LO signal generator was implemented in a standard CMOS process. A simple analysis is provided for the loop dynamics and operating range of the design as well as for the measured results of the factional LO signal generator.
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19

Ukirde, Vaishali. "Trapping of hydrogen in Hf-based high κ dielectric thin films for advanced CMOS applications." Thesis, University of North Texas, 2007. https://digital.library.unt.edu/ark:/67531/metadc5114/.

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In recent years, advanced high κ gate dielectrics are under serious consideration to replace SiO2 and SiON in semiconductor industry. Hafnium-based dielectrics such as hafnium oxides, oxynitrides and Hf-based silicates/nitrided silicates are emerging as some of the most promising alternatives to SiO2/SiON gate dielectrics in complementary metal oxide semiconductor (CMOS) devices. Extensive efforts have been taken to understand the effects of hydrogen impurities in semiconductors and its behavior such as incorporation, diffusion, trapping and release with the aim of controlling and using it to optimize the performance of electronic device structures. In this dissertation, a systematic study of hydrogen trapping and the role of carbon impurities in various alternate gate dielectric candidates, HfO2/Si, HfxSi1-xO2/Si, HfON/Si and HfON(C)/Si is presented. It has been shown that processing of high κ dielectrics may lead to some crystallization issues. Rutherford backscattering spectroscopy (RBS) for measuring oxygen deficiencies, elastic recoil detection analysis (ERDA) for quantifying hydrogen and nuclear reaction analysis (NRA) for quantifying carbon, X-ray diffraction (XRD) for measuring degree of crystallinity and X-ray photoelectron spectroscopy (XPS) were used to characterize these thin dielectric materials. ERDA data are used to characterize the evolution of hydrogen during annealing in hydrogen ambient in combination with preprocessing in oxygen and nitrogen.
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20

Chan, Chi Hang. "A study on comparator and offset calibration techniques in high speed Nyquist ADCs." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2493284.

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21

Sarivisetti, Gayathri. "Design and Optimization of Components in a 45nm CMOS Phase Locked Loop." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5397/.

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A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.
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22

Liu, Yidong. "CMOS RF cituits sic] variability and reliability resilient design, modeling, and simulation." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4969.

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Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.; The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (Vsubscript T) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (Vsubscript T]) shift and 25% to electron mobility (mu subscript n]) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation.
ID: 029809399; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 90-105).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
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23

Vakili-Amini, Babak. "A Mixed-Signal Low-Noise Sigma-Delta Interface IC for Integrated Sub-Micro-Gravity Capacitive SOI Accelerometers." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10437.

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This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data scheme is deployed with the ability of low-frequency noise reduction through the use of correlated double sampling (CDS) scheme. In this work, the measured resolution of the closed-loop CMOS-SOI accelerometer system, in the presence of high background accelerations, is in the micro-g (g: gravity) range. In this design, a second-order SC modulator is cascaded with the accelerometer and the front-end amplifier. The accelerometer operates in air and is designed for non-peaking response with a BW-3dB of 500 Hz. A 22 dB improvement in noise and hence dynamic range is achieved with a sampling clock of 40 kHz corresponding to a low oversampling ratio (OSR) of 40. The interface IC consumed a current of 1.5 mA from a supply of 3 V.
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24

Wu, Ting. "Design of terabits/s CMOS crossbar switch chip /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20WU.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.
Includes bibliographical references (leaves 100-105). Also available in electronic version. Access restricted to campus users.
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25

Srirattana, Nuttapong. "High-Efficiency Linear RF Power Amplifiers Development." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6899.

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Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.
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26

Correll, Jeffrey. "The design and implementation of an 8 bit CMOS microprocessor /." Online version of thesis, 1992. http://hdl.handle.net/1850/11649.

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27

Kwon, Ohsang. "On high performance multiplier design using dynamic CMOS circuits /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004310.

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28

Li, Xiaoyong. "Low noise design techniques for radio frequency integrated circuits /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/6013.

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29

Sayre, Edward P. "The design, fabrication, and test of a CMOS operational amplifier /." Online version of thesis, 1990. http://hdl.handle.net/1850/11226.

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30

Khan, Shamsul Arefin. "Deep sub-micron MOS transistor design and manufacturing sensitivity analysis /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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31

Liu, Kou-chen. "Si1-xGex/Si vertical MOSFETs and sidewall strained Si devices : design and fabrication /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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32

Chan, Wan Tim. "CMOS-compatible zero-mask one time programmable (OTP) memory design /." View abstract or full-text, 2008. http://library.ust.hk/cgi/db/thesis.pl?ECED%202008%20CHANW.

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33

Kanitkar, Hrishikesh. "Subthreshold circuits : design, implementation and application /." Online version of thesis, 2009. http://hdl.handle.net/1850/8926.

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34

Venkataraman, Sunitha. "Systematic Analysis of the Small-Signal and Broadband Noise Performance of Highly Scaled Silicon-Based Field-Effect Transistors." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/16232.

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The objective of this work is to provide a comprehensive analysis of the small-signal and broadband noise performance of highly scaled silicon-based field-effect transistors (FETs), and develop high-frequency noise models for robust radio frequency (RF) circuit design. An analytical RF noise model is developed and implemented for scaled Si-CMOS devices, using a direct extraction procedure based on the linear two-port noise theory. This research also focuses on investigating the applicability of modern CMOS technologies for extreme environment electronics. A thorough analysis of the DC, small-signal AC, and broadband noise performance of 0.18 um and 130 nm Si-CMOS devices operating at cryogenic temperatures is presented. The room temperature RF noise model is extended to model the high-frequency noise performance of scaled MOSFETs at temperatures down to 77 K and 10 K. Significant performance enhancement at cryogenic temperatures is demonstrated, indicating the suitability of scaled CMOS technologies for low temperature electronics. The hot-carrier reliability of MOSFETs at cryogenic temperatures is investigated and the worst-case gate voltage stress condition is determined. The degradation due to hot-carrier-induced interface-state creation is identified as the dominant degradation mechanism at room temperature down to 77 K. The effect of high-energy proton radiation on the DC, AC, and RF noise performance of 130 nm CMOS devices is studied. The performance degradation is investigated up to an equivalent total dose of 1 Mrad, which represents the worst case condition for many earth-orbiting and planetary missions. The geometric scaling of MOSFETs has been augmented by the introduction of novel FET designs, such as the Si/SiGe MODFETs. A comprehensive characterization and modeling of the small-signal and high-frequency noise performance of highly scaled Si/SiGe n-MODFETs is presented. The effect of gate shot noise is incorporated in the broadband noise model. SiGe MODFETs offer the potential for high-speed and low-voltage operation at high frequencies and hence are attractive devices for future RF and mixed-signal applications. This work advances the state-of-the-art in the understanding and analysis of the RF performance of highly scaled Si-CMOS devices as well as emerging technologies, such as Si/SiGe MODFETs. The key contribution of this dissertation is to provide a robust framework for the systematic characterization, analysis and modeling of the small-signal and RF noise performance of scaled Si-MOSFETs and Si/SiGe MODFETs both for mainstream and extreme-environment applications.
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35

Layton, Kent D. "Low-voltage analog CMOS architectures and design methods /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2141.pdf.

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36

Yee, Gin Sun. "Dynamic logic design and synthesis using clock-delayed domino /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6039.

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37

Balachandran, Ganesh Kumar. "A switched-current filter in digital-CMOS technology with low charge-injection errors." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15405.

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38

Guan, Bingzhong. "Automatic layout generation of static CMOS combinational cells and blocks /." Thesis, Connect to this title online; UW restricted, 1996. http://hdl.handle.net/1773/6059.

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39

Amarchinta, Sumanth. "High performance subthreshold standard cell design and cell placement optimization /." Online version of thesis, 2009. http://hdl.handle.net/1850/10740.

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40

Baker, Eric Albert. "The design of a CMOS sensor camera system for a nanosatellite." Thesis, Stellenbosch : University of Stellenbosch, 2006. http://hdl.handle.net/10019/493.

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41

Tsui, Hau Yiu. "A 5 GHz integrated low-power CMOS RF front-end IC design /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20TSUI.

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42

Wang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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43

Wang, Dan. "Design and integration of a single-chip low-power single-conversion CMOS cable TV tuner /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20WANG.

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Khlif, Wassim. "Design of tunable low-noise amplifier in 0.13 [symbol for Greek letter mu]m CMOS technology for multistandard RF transceivers." Link to electronic thesis, 2007. http://www.wpi.edu/Pubs/ETD/Available/etd-050407-145957/.

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Leung, Chi Tak. "Design of 1-V CMOS RF phase-locked loops and frequency synthesizers /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20LEUNG.

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Tennakoon, Hiran Kasturiratne. "Efficient and accurate gate sizing with piecewise convex delay models /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/5999.

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Ng, Wai Hon. "Design of CMOS wide-band switched-capacitor bandpass filters /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20NG.

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Zhang, Xibo. "RF integrated circuit design options : from technology to layout /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20ZHANG.

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Abstract:
Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.
Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.
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Mills, Richard P. III. "Design and optimization of RF test structures for mm-wave circuit design." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/42922.

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Xuan, Xiangdong. "Analysis and design of reliable mixed-signal CMOS circuits." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-08032004-185515/unrestricted/xuan%5Fxiangdong%5F200412%5Fphd.pdf.

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Abstract:
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
Singh, Adit, Committee Member ; Chatterjee, Abhijit, Committee Chairl May, Gary, Committee Member ; Keezer, David, Committee Member ; Swaminathan, Madhavan, Committee Member. Vita. Includes bibliographical references.
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