To see the other types of publications on this topic, follow the link: Memory transistors.
Journal articles on the topic 'Memory transistors'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 journal articles for your research on the topic 'Memory transistors.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.
1
Al-shawi, Amjad, Maysoon Alias, Paul Sayers, and Mohammed Fadhil Mabrook. "Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors." Micromachines 10, no. 10 (September 25, 2019): 643. http://dx.doi.org/10.3390/mi10100643.
Full textAbstract:
To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts in the threshold voltage of the transfer characteristics as well as the hysteresis in the output characteristics were attributed to the charging and discharging of the floating gate. The counter-clockwise direction of hysteresis indicates that the process of charging and discharging the floating gate take place through the semiconductor/insulator interface. A clear shift in the threshold voltage was observed when different voltage pulses were applied to the gate. The non-volatile behaviour of the memory transistors was investigated in terms of charge retention. The memory transistors exhibited a large memory window (~30 V), and high charge density of (9.15 × 1011 cm−2).
2
Xie, Fangqing, Maryna N. Kavalenka, Moritz Röger, Daniel Albrecht, Hendrik Hölscher, Jürgen Leuthold, and Thomas Schimmel. "Copper atomic-scale transistors." Beilstein Journal of Nanotechnology 8 (March 1, 2017): 530–38. http://dx.doi.org/10.3762/bjnano.8.57.
Full textAbstract:
We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.
3
Srinivasarao, B. N., and K. Chandrabhushana Rao. "Design and Analysis of Area Efficient 128 Bytes SRAM Architecture." Journal of VLSI Design and Signal Processing 8, no. 1 (March 30, 2022): 19–26. http://dx.doi.org/10.46610/jovdsp.2022.v08i01.004.
Full textAbstract:
SRAM Memory architecture design and implementation is a challenging task for memory applications. Practical architecture was developed and used successfully using various double ended SRAM cells like 6 and 4 transistors. But for single ended SRAM cell like 5 transistors or any other number of transistors there is no specific architecture for practical applications. Conventional SRAM architecture has SRAM cell, write driver circuit along with bit inverter, Pre-charge circuit and sense amplifier which consists more, number of transistors required to handle single bit storage. In this paper SRAM architecture is implemented for single ended SRAM cell that is three transistor SRAM cell. Area is reduced by 60% with average power consumption 3.05µW and speed with 20.87GHz. Finally,28 bytes memory structure is implemented and verified its operation.
4
Kim, Woojo, Jimin Kwon, and Sungjune Jung. "3D Integration of Flexible and Printed Electronics: Integrated Circuits, Memories, and Sensors." Journal of Flexible and Printed Electronics 2, no. 2 (December 2023): 199–210. http://dx.doi.org/10.56767/jfpe.2023.2.2.199.
Full textAbstract:
Printing technologies have received a lot of attention and expectations for producing flexible and wearable electronics. However, the low transistor density of the printed devices has been a major obstacle to commercialization. In this review, a three-dimensional (3D) integration of organic flexible and printed electronics is described. First, layout-to-bitmap conversion and design rules for printed transistors, arrays, and integrated circuits are introduced. Then, printed 3D transistors, digital integrated circuits, and memories are described. Finally, 3D integration of printed active-matrix arrays and sensors is highlighted. This approach is a breakthrough technology that not only reduces the area occupied by a single transistor, memory, and sensor, but also increases the efficiency of routing, effectively reducing the area of the entire devices. In addition, monolithic 3D integration through the printing can stack transistor, memory, and sensor by simply repeating the additive process.
5
Kim, Ji-Hun, Hyeon-Jun Kim, Ki-Jun Kim, Tae-Hun Shim, Jin-Pyo Hong, and Jea-gun Park. "3-Terminal Igzo FET Based 2T0C DRAM Combined Bit-Line Structure." ECS Meeting Abstracts MA2023-02, no. 30 (December 22, 2023): 1561. http://dx.doi.org/10.1149/ma2023-02301561mtgabs.
Full textAbstract:
The IGZO (InGaZnO)-based two-transistor zero-capacitor(2T0C) DRAM has attracted much attention as an alternative memory to overcome the scale-down limit of current 1T1C DRAM due to its low power consumption and monolithic 3D stacking capability. In particular, its low power consumption and the feasibility of low temperature process make it highly implementable for 3D DRAM. For operating the 2T0C DRAM, four metal lines are necessary, i.e., write word line and write bit line (WBL) for operating write transistor (WTR), and read word line and read bit line (RBL) for operating read transistor (RTR). In this study, we propose a 3-terminal 2T0C DRAM to enhance its memory characteristics, where RBL was combined with WBL, enabling 2T0C memory operation with only three metal lines as shown in Fig. 1(b). In addition, we investigated the dependency of retenetion time of the proposed 2T0C DRAM on channel length. In particular we evaluated the dependency of the sneak current of 2T0C DRAM on off-current of transistor. For the fabrication of 3-terminal IGZO 2T0C DRAM, a top gate IGZO transistor was fabricated using RF sputtering and two transistors were connected by storage node and bit line bridge as shown in Fig. 1(d).The storage node was formed by connecting the gate of RTR to drain of WTR. And source electrodes of both transistors were coupled. To determine the voltage values for memory operation, the transfer curve of each transistor was characterized and the threshold voltages for both RTR and WTR were around 1 V. The write and read voltages were set to 3 and 2 V, respectively. The retention time was measured by performing periodic read operations after writing and measuring the RTR currents. In addition, the retention time of transistors for varying channel length and gate capacitance was characterized. The retention time was defined as the time to be taken for decreasing the currents by 90 %. Furthermore, the disturbance of 2T0C DRAM with 2x2 array structure was investigated. The RTR currents of selected cells were measured depending on the memory state of adjacent cells. It was found that the retention times of transistors with 10- and 100-um RTR channel lengths were approximately 15 and 30 seconds, respectively. It was observed that the memory state was not changed from “0“ to “1“ by disturbant currents, but, RTR currents of “0“ state cell increased slightly when an adjacent cell was turned on. However, as shown in Fig.1(i) and (j), when off-currents of transistor of 2T0C DRAM decreased from 20 nA to 200 pA, it was confirmed the sneak current of 2T0C decreased. Finally, several technical apporaches how to suppress the disturbant currents will be presented in detail. Acknowledgement This research was supported by BrainKorea21 Four. Figure 1
6
Brtník, Bohumil. "Assembling a Formula for Current Transferring by Using a Summary Graph and Transformation Graphs." Journal of Electrical Engineering 64, no. 5 (September 1, 2013): 334–36. http://dx.doi.org/10.2478/jee-2013-0050.
Full textAbstract:
Abstract This paper deals with the symbolic solution of the switched current circuits. As is described, the full graph method of the solution can be used for finding relationships expressing current transfer, too. The summa MC-graph is constructed using two-graphs method in two-phase switching. By comparing the matrix form with results of the Mason’s formula are derived relations for current transfers in all phases. There are discussed various options described transistor memory cells - with loss and lossless transistors and normal transistor current mirror. Evaluation of the graph is simplified if we consider the lossless transistors or if the y21 -parameter of one transistor is alpha multiple of second ones.
7
Lee, Edward, Daehyun Kim, Jinwoo Kim, Sung Kyu Lim, and Saibal Mukhopadhyay. "A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process." ACM Journal on Emerging Technologies in Computing Systems 18, no. 1 (January 31, 2022): 1–20. http://dx.doi.org/10.1145/3466681.
Full textAbstract:
We present a ReRAM memory compiler for monolithic 3D (M3D) integrated circuits (IC). We develop ReRAM architectures for M3D ICs using 1T-1R bit cells and single and multiple tiers of transistors for access and peripheral circuits. The compiler includes an automated flow for generation of subarrays of different dimensions and larger arrays of a target capacity by integrating multiple subarrays. The compiler is demonstrated using an M3D process design kit (PDK) based on a Carbon Nanotube Transistor technology. The PDK includes multiple layers of transistors and back-end-of-the-line integrated ReRAM. Simulations show the compiled ReRAM macros with multiple tiers of transistors reduces footprint and improves performance over the macros with single-tier transistors. The compiler creates layout views that are exported into library exchange format or graphic data system for full-array assembly and schematic/symbol views to extract per-bit read/write energy and read latency. Comparison of the proposed M3D subarray architectures with baseline 2D subarrays, generated with a custom-designed set of bit cells and peripherals, demonstrate up to 48% area reduction and 13% latency improvement.
8
Choi, Young Jin, Jihyun Kim, Min Je Kim, Hwa Sook Ryu, Han Young Woo, Jeong Ho Cho, and Joohoon Kang. "Hysteresis Behavior of the Donor–Acceptor-Type Ambipolar Semiconductor for Non-Volatile Memory Applications." Micromachines 12, no. 3 (March 12, 2021): 301. http://dx.doi.org/10.3390/mi12030301.
Full textAbstract:
Donor–acceptor-type organic semiconductor molecules are of great interest for potential organic field-effect transistor applications with ambipolar characteristics and non-volatile memory applications. Here, we synthesized an organic semiconductor, PDPPT-TT, and directly utilized it in both field-effect transistor and non-volatile memory applications. As-synthesized PDPPT-TT was simply spin-coated on a substrate for the device fabrications. The PDPPT-TT based field-effect transistor showed ambipolar electrical transfer characteristics. Furthermore, a gold nanoparticle-embedded dielectric layer was used as a charge trapping layer for the non-volatile memory device applications. The non-volatile memory device showed clear memory window formation as applied gate voltage increases, and electrical stability was evaluated by performing retention and cycling tests. In summary, we demonstrate that a donor–acceptor-type organic semiconductor molecule shows great potential for ambipolar field-effect transistors and non-volatile memory device applications as an important class of materials.
9
Qiu, Haiyang, Dandan Hao, Hui Li, Yepeng Shi, Yao Dong, Guoxia Liu, and Fukai Shan. "Transparent and biocompatible In2O3 artificial synapses with lactose–citric acid electrolyte for neuromorphic computing." Applied Physics Letters 121, no. 18 (October 31, 2022): 183301. http://dx.doi.org/10.1063/5.0124219.
Full textAbstract:
Electrolyte-gated synaptic transistors are promising for artificial neural morphological devices. However, few literatures have been reported regarding the manufacturing of electrolyte-gated synaptic transistors with low cost and biocompatible components. Here, the fully transparent synaptic transistors based on water-induced In2O3 thin films have been integrated by sol–gel method at low temperature, and lactose dissolved in citric acid solution is used as the gate electrolyte. The migration of the ions at the interface plays a crucial role in the potentiation and depression of the synaptic weight. In this work, the biological synaptic functions, including excitatory postsynaptic current, paired-pulse facilitation, high-pass filtering characteristics, short-term memory, and long-term memory, are mimicked. Meanwhile, based on the potentiation/depression behaviors of the synaptic transistor, a three-layer artificial neural network is applied for pattern recognition, and the recognition accuracy is as high as 94.6%. This study offers a possibility to realize fully transparent synaptic devices with biocompatible components at low temperature.
10
Gul, Waqas, Maitham Shams, and Dhamin Al-Khalili. "SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview." Micromachines 13, no. 8 (August 17, 2022): 1332. http://dx.doi.org/10.3390/mi13081332.
Full textAbstract:
Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell’s stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell’s reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions.
11
Arimoto, Yoshihiro, and Hiroshi Ishiwara. "Current Status of Ferroelectric Random-Access Memory." MRS Bulletin 29, no. 11 (November 2004): 823–28. http://dx.doi.org/10.1557/mrs2004.235.
Full textAbstract:
AbstractThe current status of ferroelectric random-access memory (FeRAM) technology is reviewed in this article. Presented first is the status of conventional FeRAM, in which the memory cells are composed of ferroelectric capacitors to store the data and cell-selection transistors to access the selected capacitors. Discussed next are recent developments in the field. Pb(Zrx, Ti1–x)O3 (PZT) and SrBi2Ta2O9 (SBT) films are being used to produce 0.13 mμ and 0.18 μm FeRAM cells, respectively, with a stacked capacitor configuration; these cells are easily embedded into logic circuits. A new class of FeRAM called 6T4C—containing static RAM (SRAM) cells composed of six transistors (6T) and four ferroelectric capacitors (4C)—has been commercially produced. This type of FeRAM features a nondestructive readout operation, unlimited read/write cycling, and a fast access time of less than 10 ns. Lastly, the status of field-effect-transistor (FET)-type FeRAM is reviewed, emphasizing that the data retention time of a ferroelectric-gate FET has been improved to more than a month in recent studies.
12
Yu, Li-Zhen, Hung-Chun Chen, and Ching-Ting Lee. "Memory mechanisms of vertical organic memory transistors." Applied Physics Letters 96, no. 23 (June 7, 2010): 233301. http://dx.doi.org/10.1063/1.3449120.
Full text
13
Saman, Bander, P. Gogna, El-Sayed Hasaneen, J. Chandy, E. Heller, and F. C. Jain. "Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation." International Journal of High Speed Electronics and Systems 26, no. 03 (June 27, 2017): 1740009. http://dx.doi.org/10.1142/s0129156417400092.
Full textAbstract:
This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.
14
Chiquet, Philippe, Jérémy Postel-Pellerin, Célia Tuninetti, Sarra Souiki-Figuigui, and Pascal Masson. "Enhancement of flash memory endurance using short pulsed program/erase signals." ACTA IMEKO 5, no. 4 (December 30, 2016): 29. http://dx.doi.org/10.21014/acta_imeko.v5i4.422.
Full textAbstract:
The present paper proposes to investigate the effect of short pulsed Program/Erase signals on the functioning of Flash memory transistors. Usually, electrical operations related to said devices involve the application of single long pulses to various terminals of the transistor to induce various tunneling effects allowing the variation of the floating gate charge. According to the literature, the oxide degradation occurring after a number of electrical operations, leading to loss of performance and reliability, can be reduced by replacing DC stress by AC stress or by reducing the time spent under polarization by the MOS-based devices. After a brief presentation of the functioning of the Flash memory transistors tested in this work, the experimental setup used to replace standard electric signals with short pulses will be described. Electrical results showing the benefits of programming and erasing non-volatile memories with short pulses will then be presented.
15
Xie, Dongyu, Xiaoci Liang, Di Geng, Qian Wu, and Chuan Liu. "An Enhanced Synaptic Plasticity of Electrolyte-Gated Transistors through the Tungsten Doping of an Oxide Semiconductor." Electronics 13, no. 8 (April 13, 2024): 1485. http://dx.doi.org/10.3390/electronics13081485.
Full textAbstract:
Oxide electrolyte-gated transistors have shown the ability to emulate various synaptic functions, but they still require a high gate voltage to form long-term plasticity. Here, we studied electrolyte-gated transistors based on InOx with tungsten doping (W-InOx). When the tungsten-to-indium ratio increased from 0% to 7.6%, the memory window of the transfer curve increased from 0.2 V to 2 V over a small sweep range of −2 V to 2.5 V. Under 50 pulses with a duty cycle of 2%, the conductance of the transistor increased from 40-fold to 30,000-fold. Furthermore, the W-InOx transistor exhibited improved paired pulse facilitation and successfully passed the Pavlovian test after training. The formation of WO3 within InOx and its ion intercalation into the channel may account for the enhanced synaptic plasticity.
16
Fuller, Elliot J., Scott T. Keene, Armantas Melianas, Zhongrui Wang, Sapan Agarwal, Yiyang Li, Yaakov Tuchman, et al. "Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing." Science 364, no. 6440 (April 25, 2019): 570–74. http://dx.doi.org/10.1126/science.aaw5581.
Full textAbstract:
Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and readout of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10-nanoampere read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array based on a polymer redox transistor connected to a conductive-bridge memory (CBM). Selective and linear programming of a redox transistor array is executed in parallel by overcoming the bridging threshold voltage of the CBMs. Synaptic weight readout with currents <10 nanoamperes is achieved by diluting the conductive polymer with an insulator to decrease the conductance. The redox transistors endure >1 billion write-read operations and support >1-megahertz write-read frequencies.
17
Rumberg, Brandon, Spencer Clites, Haifa Abulaiha, Alexander DiLello, and David Graham. "Continuous-Time Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Arrays." Journal of Low Power Electronics and Applications 11, no. 1 (January 13, 2021): 4. http://dx.doi.org/10.3390/jlpea11010004.
Full textAbstract:
Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well. Such programmable analog systems are often designed for battery-powered and resource-constrained applications, which require the memory cells to program quickly and with low infrastructural overhead. To meet these needs, we present a four-transistor analog floating-gate memory cell that offers both voltage and current outputs and has linear programming characteristics. Furthermore, we present a simple programming circuit that forces the memory cell to converge to targets with 13.0 bit resolution. Finally, we demonstrate how to use the FG memory cell and the programmer circuit in array configurations. We show how to program an array in either a serial or parallel fashion and demonstrate the effectiveness of the array programming with an application of a bandpass filter array.
18
Lee, Sora, Xiaotian Zhang, Thomas McKnight, Bhavesh Ramkorun, Huaiyu Wang, Venkatraman Gopalan, Joan M. Redwing, and Thomas N. Jackson. "Low-temperature processed beta-phase In2Se3 ferroelectric semiconductor thin film transistors." 2D Materials 9, no. 2 (March 23, 2022): 025023. http://dx.doi.org/10.1088/2053-1583/ac5b17.
Full textAbstract:
Abstract As scaling becomes increasingly difficult, there is growing interest in vertical or three-dimensional stacking of transistors and especially memory. Ferroelectric semiconductor field effect transistors can be key enablers to improve energy efficiency and overall chip and memory performance. In this work, low-temperature processed, back-end-of-the-line compatible transistors were demonstrated by depositing a layered chalcogenide ferroelectric semiconductor, beta-phase In2Se3, at temperature as low as 400 °C. Top gate n-channel In2Se3 thin film transistors were fabricated with field-effect mobility ∼1 cm2 V−1 s−1, and simple polarization switching based memory results are presented.
19
Neudeck, Philip G., David J. Spry, Michael J. Krasowski, Liangyu Chen, Lawrence C. Greer, Carl W. Chang, Dorothy Lukco, Glenn M. Beheim, and Norman F. Prokop. "Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2021, HiTEC (April 1, 2021): 000064–68. http://dx.doi.org/10.4071/2380-4491.2021.hitec.000064.
Full textAbstract:
Abstract At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 μm to 2 μm) coupled with enlarged die size (from 3 × 3 mm to 5 × 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.
20
Gherendi, Florin, Daniela Dobrin, and Magdalena Nistor. "Transparent Structures for ZnO Thin Film Paper Transistors Fabricated by Pulsed Electron Beam Deposition." Micromachines 15, no. 2 (February 12, 2024): 265. http://dx.doi.org/10.3390/mi15020265.
Full textAbstract:
Thin film transistors on paper are increasingly in demand for emerging applications, such as flexible displays and sensors for wearable and disposable devices, making paper a promising substrate for green electronics and the circular economy. ZnO self-assembled thin film transistors on a paper substrate, also using paper as a gate dielectric, were fabricated by pulsed electron beam deposition (PED) at room temperature. These self-assembled ZnO thin film transistor source–channel–drain structures were obtained in a single deposition process using 200 and 300 µm metal wires as obstacles in the path of the ablation plasma. These transistors exhibited a memory effect, with two distinct states, “on” and “off”, and with a field-effect mobility of about 25 cm2/Vs in both states. For the “on” state, a threshold voltage (Vth on = −1.75 V) and subthreshold swing (S = 1.1 V/decade) were determined, while, in the “off” state, Vth off = +1.8 V and S = 1.34 V/decade were obtained. A 1.6 μA maximum drain current was obtained in the “off” state, and 11.5 μA was obtained in the “on” state of the transistor. Due to ZnO’s non-toxicity, such self-assembled transistors are promising as components for flexible, disposable smart labels and other various green paper-based electronics.
21
Grudanov, Oleksandr. "Stability Parameters of Register File Bit Cell with Low Power Consumption Priority." Electronics and Control Systems 3, no. 77 (September 27, 2023): 40–46. http://dx.doi.org/10.18372/1990-5548.77.17963.
Full textAbstract:
This research is dedicated to a transistor sizing method of an 8-transistor register file static random access memory bit cell aiming to create two-port register files and two-port static random access memory with reduced supply voltage to reduce power consumption. This method can also be applied to 6-transistor single-port static random access memory bit cells. The method is based on the analysis of butterfly curves and the search for such values of the sizes of transistors and margin of their threshold voltages, in which, for a given critical minimal supply voltage, the condition for the existence of one intersection and one touch of its curves is achieved for the butterfly curves. The obtained samples of the register files bit cell in silicon and its critical voltage were compared to the results of circuit simulation in the write and read mode depending on the supply voltage. Experimental register files chip samples were successfully tested in silicon at a voltage of 0.75 V.
22
Thomas, Stuart. "Transistors and memory get together." Nature Electronics 4, no. 5 (May 2021): 321. http://dx.doi.org/10.1038/s41928-021-00596-8.
Full text
23
Novembre, Christophe, David Guérin, Kamal Lmimouni, Christian Gamrat, and Dominique Vuillaume. "Gold nanoparticle-pentacene memory transistors." Applied Physics Letters 92, no. 10 (March 10, 2008): 103314. http://dx.doi.org/10.1063/1.2896602.
Full text
24
Sedaghat, Mahsa, and Mahdi Salimi. "Evaluation and Comparison of CMOS logic circuits with CNTFET." Journal of Research in Science, Engineering and Technology 3, no. 04 (September 13, 2019): 1–9. http://dx.doi.org/10.24200/jrset.vol3iss04pp1-9.
Full textAbstract:
In this paper, a comparison between CMOS and MOSFET base circuits HSPICE is done with software. 0.13 CMOS transistor model for simulation and CNTFET Model of Stanford University used. In simulations amounts of power, circuit delay and PDP is calculated and these values were compared at the end. And tried to CNTFET applications of transistors in circuit design, including memory and logic circuits Ternary be expressed.
25
Chen, Zhuo, Huilong Zhu, Guilei Wang, Qi Wang, Zhongrui Xiao, Yongkui Zhang, Jinbiao Liu, et al. "Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing." Nanomaterials 13, no. 11 (June 1, 2023): 1786. http://dx.doi.org/10.3390/nano13111786.
Full textAbstract:
Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.
26
Qi, Hongxia, and Ying Wu. "Synaptic plasticity of TiO2 nanowire transistor." Microelectronics International 37, no. 3 (January 16, 2020): 125–30. http://dx.doi.org/10.1108/mi-08-2019-0053.
Full textAbstract:
Purpose The emulation of synapses is essential to neuromorphic computing systems. Despite remarkable progress has been made in the two-terminal device (memristor), three-terminal transistors evoke greater attention because of the controlled conductance between the source and drain. The purpose of this paper is to investigate the synaptic plasticity of the TiO2 nanowire transistor. Design/methodology/approach TiO2 nanowire transistor was assembled by dielectrophoresis, and the synaptic plasticity such as paired-pulse facilitation, learning behaviors and high-pass filter were studied. Findings Facilitation index decreases with the increasing pulse interval. A bigger response current is obtained at the pulses with higher amplitude and smaller intervals, which is similar to the consolidated memory at the deeply and frequently learning. The increased current at the higher stimulus frequency demonstrates a promising application in the high-pass filter. Originality/value TiO2 nanowire transistors possess broad application prospects in the future neural network.
27
Salahuddin, Shairfe Muhammad, and Volkan Kursun. "Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability." Journal of Circuits, Systems and Computers 25, no. 01 (November 15, 2015): 1640009. http://dx.doi.org/10.1142/s0218126616400090.
Full textAbstract:
A novel six-transistor static random-access memory (6T SRAM) cell is proposed in this paper for enhancing the data stability and write ability as compared to the conventional memory circuits. Asymmetrically gate overlapped / underlapped FinFETs are employed as bitline access transistors in the proposed SRAM cell. The strength of the asymmetrical bitline access transistors are weakened during read operations. Furthermore, voltage transfer characteristics (VTCs) of cross-coupled inverters have narrower transition regions in the new SRAM cell as compared to the conventional SRAM cells. The proposed SRAM cell thereby provides stronger read data stability as compared to the conventional symmetrical SRAM cells. The strength of bitline access transistors are enhanced during write operations as the direction of current flow is reversed in the new asymmetrical SRAM cell. The power supply voltage of a selected word floats during write operations. The write voltage margin is thereby significantly increased with the proposed SRAM cell as compared to the conventional SRAM cells. The read data stability and write ability are both enhanced by up to 51.7% and 65.5%, respectively, with the proposed SRAM cell as compared to the conventional symmetrical six-FinFET SRAM cells in a 15[Formula: see text]nm FinFET technology.
28
Hellkamp, Daniel, and Kundan Nepal. "True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors." Journal of Circuits, Systems and Computers 28, no. 05 (May 2019): 1950085. http://dx.doi.org/10.1142/s0218126619500853.
Full textAbstract:
Carbon nanotube-based transistors (CNTFETs) have been shown to exhibit ambipolar field-effect transistor behavior, allowing circuit designers to easily choose between [Formula: see text]- and [Formula: see text]-conduction channels by applying correct voltages at a polarity gate. In this paper, we explore this ambipolar behavior of the CNTFET to design both binary and ternary content addressable memory (AM) cells. Using SPICE simulation, we show the designs of a traditional ternary CAM (TCAM) and a true three-valued TCAM (T3-CAM) functionality of the proposed cells and show that the ambipolar design can lead to a savings of up to 31% in terms of transistor count over a traditional design. We also explore issues related to matchline leakage, cell stability and design in the presence of metallic tubes.
29
Seon, Kim, Kim, and Jeon. "Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel." Electronics 8, no. 9 (September 4, 2019): 988. http://dx.doi.org/10.3390/electronics8090988.
Full textAbstract:
Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physics at the same time. In this work, we derived new analytical current-voltage model for GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain boundary effect. Based on the derived formula, the compact I-V model for various operating regions and threshold voltage was proposed for the first time. The proposed model was compared with the measured data and good agreements were observed.
30
Kumari, Nibha, and Prof Vandana Niranjan. "Low-Power 6T SRAM Cell using 22nm CMOS Technology." Indian Journal of VLSI Design 2, no. 2 (September 30, 2022): 5–10. http://dx.doi.org/10.54105/ijvlsid.b1210.092222.
Full textAbstract:
Static Random-Access Memory (SRAM) occupies approximately 90% of total area on a chip due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell becomes a power-hungry block on a chip and it becomes more prominent at lower technologies from both dynamic and static perspective. Static power consumption is due to leakage current associated with the transistors that are off and dynamic power consumption is due to charging and discharging of the circuit capacitance. As gate length or channel length decreases gate oxide thickness also scales down. Scaling down of conventional transistor results in huge tunneling of electron from gate into channel leading to higher leakage power consumption. So, transistor with metal gate, high-k dielectric and strained-Si is used which shows better result in terms of low-power consumption, better performance with acceptable delay. Among various topologies of SRAM cell 6T is considered as a suitable choice for low power applications.
31
Huang, Jing, Pengfei Tan, Fang Wang, and Bo Li. "Ferroelectric Memory Based on Topological Domain Structures: A Phase Field Simulation." Crystals 12, no. 6 (May 29, 2022): 786. http://dx.doi.org/10.3390/cryst12060786.
Full textAbstract:
The low storage density of ferroelectric thin film memory currently limits the further application of ferroelectric memory. Topologies based on controllable ferroelectric domain structures offer opportunities to develop microelectronic devices such as high-density memories. This study uses ferroelectric topology domains in a ferroelectric field-effect transistor (FeFET) structure for memory. The electrical behavior of FeFET and its flip properties under strain and electric fields are investigated using a phase-field model combined with the device equations of field-effect transistors. When the dimensionless electric field changes from −0.10 to 0.10, the memory window drops from 2.49 V to 0.6 V and the on-state current drops from 2.511 mA to 1.951 mA; the off-state current grows from 1.532 mA to 1.877 mA. External tensile stress increases the memory window and off-state current, while compressive stress decreases it. This study shows that a ferroelectric topology can be used as memory and could significantly increase the storage density of ferroelectric memory.
32
Jin, Risheng, Keli Shi, Beibei Qiu, and Shihua Huang. "Photoinduced-reset and multilevel storage transistor memories based on antimony-doped tin oxide nanoparticles floating gate." Nanotechnology 33, no. 2 (October 22, 2021): 025201. http://dx.doi.org/10.1088/1361-6528/ac2dc5.
Full textAbstract:
Abstract Recently, antimony-doped tin oxide nanoparticles (ATO NPs) have been widely used in the fields of electronics, photonics, photovoltaics, sensing, and other fields because of their good conductivity, easy synthesis, excellent chemical stability, high mechanical strength, good dispersion and low cost. Herein, for the first time, a novel nonvolatile transistor memory device is fabricated using ATO NPs as charge trapping sites to enhance the memory performance. The resulting organic nano-floating gate memory (NFGM) device exhibits outstanding memory properties, including tremendous memory window (∼85 V), superhigh memory on/off ratio (∼109), long data retention (over 10 years) and eminent multilevel storage behavior, which are among the optimal performances in NFGM devices based on organic field effect transistors. Additionally, the device displays photoinduced-reset characteristic with low energy consumption erasing operation. This study provides novel avenues for the manufacture of simple and low-cost data storage devices with outstanding memory performance, multilevel storage behavior and suitability as platforms for integrated circuits.
33
Jeon, Juhee, Kyoungah Cho, and Sangsig Kim. "Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors." Micromachines 14, no. 6 (May 28, 2023): 1138. http://dx.doi.org/10.3390/mi14061138.
Full textAbstract:
Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated. Cell reliability is closely related to device malfunction. Hence, in this study, we propose a 1T DRAM consisting of an FBFET with a p+–n–p–n+ silicon nanowire and investigate the memory operation and disturbance in a 3 × 3 array structure through mixed-mode simulations. The 1T DRAM exhibits a write speed of 2.5 ns, a sense margin of 90 μA/μm, and a retention time of approximately 1 s. Moreover, the energy consumption is 5.0 × 10−15 J/bit for the write ‘1’ operation and 0 J/bit for the hold operation. Furthermore, the 1T DRAM shows nondestructive read characteristics, reliable 3 × 3 array operation without any write disturbance, and feasibility in a massive array with an access time of a few nanoseconds.
34
Boampong, Amos Amoako, Jae-Hyeok Cho, Yoonseuk Choi, and Min-Hoi Kim. "Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure." Journal of Nanoscience and Nanotechnology 21, no. 3 (March 1, 2021): 1766–71. http://dx.doi.org/10.1166/jnn.2021.18923.
Full textAbstract:
We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO. The voltage applied to the counter bottom-gate electrode causes variations in the turn-on voltage position, which controlled the memory on- and off-current in retention characteristics. Specifically, due to the full depletion of semiconductor by the high negative counter gate bias, the memory off-current in reading operation is dramatically reduced by 104. The application of a high negative counter field to the dual-gate solution-processed ferroelectric memory gives a high memory on- and off-current ratio useful for the production of high performance multi-bit memory devices.
35
Yurasik G. A., Kulishov A. A., Givargizov M. E., and Postnikov V. A. "Dedicated to the memory of V.D. Aleksandrov Effect of annealing in an inert atmosphere on the electrical properties of crystalline pentacene films." Technical Physics Letters 48, no. 15 (2022): 30. http://dx.doi.org/10.21883/tpl.2022.15.55278.18983.
Full textAbstract:
The results of a study of the effect of annealing at 150^oC in an inert atmosphere (Ar + 5% H2) on the electrical properties of organic field-effect transistors based on pentacene are presented. Crystalline pentacene films with a thickness of 95±5 nm were obtained using thermal vacuum deposition. The transfer and output characteristics of field-effect transistors before and after annealing for 15 hours are investigated. It was found that as a result of heat treatment, the hole mobility in the saturation regime increased by an average of 30%, and the threshold voltage decreased approximately two times. According to the data of atomic force microscopy, annealing led to a more than twofold decrease in the surface roughness of pentacene films, as well as to a noticeable enlargement of grains, which led to a decrease in the concentration of traps for hole electric transport in the channel of the field-effect transistor. Keywords: pentacene, vacuum thermal deposition, crystalline films, organic field-effect transistors, hole mobility, annealing in an inert atmosphere.
36
Seo, Yeongkyo, and Kon-Woo Kwon. "Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application." Electronics 12, no. 20 (October 12, 2023): 4223. http://dx.doi.org/10.3390/electronics12204223.
Full textAbstract:
This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin.
37
Shim, Hyunseok, Kyoseung Sim, Faheem Ershad, Pinyi Yang, Anish Thukral, Zhoulyu Rao, Hae-Jin Kim, et al. "Stretchable elastic synaptic transistors for neurologically integrated soft engineering systems." Science Advances 5, no. 10 (October 2019): eaax4961. http://dx.doi.org/10.1126/sciadv.aax4961.
Full textAbstract:
Artificial synaptic devices that can be stretched similar to those appearing in soft-bodied animals, such as earthworms, could be seamlessly integrated onto soft machines toward enabled neurological functions. Here, we report a stretchable synaptic transistor fully based on elastomeric electronic materials, which exhibits a full set of synaptic characteristics. These characteristics retained even the rubbery synapse that is stretched by 50%. By implementing stretchable synaptic transistor with mechanoreceptor in an array format, we developed a deformable sensory skin, where the mechanoreceptors interface the external stimulations and generate presynaptic pulses and then the synaptic transistors render postsynaptic potentials. Furthermore, we demonstrated a soft adaptive neurorobot that is able to perform adaptive locomotion based on robotic memory in a programmable manner upon physically tapping the skin. Our rubbery synaptic transistor and neurologically integrated devices pave the way toward enabled neurological functions in soft machines and other applications.
38
Duraivel, A. N., B. Paulchamy, and K. Mahendrakan. "Proficient Technique for High Performance Very Large-Scale Integration System to Amend Clock Gated Dual Edge Triggered Sense Amplifier Flip-Flop with Less Dissipation of Power Leakage." Journal of Nanoelectronics and Optoelectronics 16, no. 4 (April 1, 2021): 602–11. http://dx.doi.org/10.1166/jno.2021.2984.
Full textAbstract:
Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting the individual clock signal status. Therefore, at these times of clock signal transfer, the state of the memory unit and the state of the whole electrical structure change. It’s only during signal transfer that the key to a flip-flop being correctly operated. Two transitions from 0 and 1 are followed by a clock pulse, and 1 to 0. The pulse shift is defined by the positive and negative sides of the pulse. The data on or off the clock cycle edges are recorded by a single-edge trigger flip flop (SETFF), but the flip flop with the double-edge sensor amplifier (DETSAFF). Another common technique for dynamic energy consumption reduced when the device is idle is the clock gating. In this document. Sleep is used to reduce the power of the leakage Here are the following: High threshold voltages sleep transistors are used. Among the supply voltage and VDD the sleep pMOS transistor and the pull-up system and between the network and the ground GND a sleep NMOs Transistor is located. With sleep transistors, CG-SAFF can save up to 30% of its power during zero input switching operation. For different sequential device architecture, the proposed flip-flop may be used.
39
Natarajamoorthy, Mathan, Jayashri Subbiah, Nurul Ezaila Alias, and Michael Loong Peng Tan. "Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design." Journal of Nanotechnology 2020 (April 30, 2020): 1–7. http://dx.doi.org/10.1155/2020/7608279.
Full textAbstract:
The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.
40
Gong, Xiao, Kaizhen Han, Chen Sun, Zijie Zheng, Qiwen Kong, Yuye Kang, Chengkuan Wang, et al. "Beol-Compatible Ingazno-Based Devices for 3D Integrated Circuits." ECS Meeting Abstracts MA2022-02, no. 32 (October 9, 2022): 1186. http://dx.doi.org/10.1149/ma2022-02321186mtgabs.
Full textAbstract:
Due to its attractive materials and electrical properties, indium-gallium-zinc-oxide (IGZO) has been extensively researched in many emerging technologies, especially for three-dimensional (3D) monolithic integration and back-end-of-line (BEOL) compatible applications [1]. On the pathway toward the realization of high-performance 3D monolithic integrated chips (ICs), a wide range of building blocks with different functionalities are required. 3D monolithic ICs also demand optimization in device performance and circuit architecture design. In this paper, we discuss our recent research development in IGZO-based techniques at both device and circuit levels. This includes nanowire structure for IGZO-based transistors, as well as the BEOL-compatible ferroelectric ternary content-addressable memory (TCAM) and embedded dynamic random-access-memory (eDRAM) for compute-in-memory (CiM) using IGZO-based transistors. A novel digital etch technique for amorphous IGZO (α-IGZO) material as well as the formation of α-IGZO nanowires were realized, enabling high performance α-IGZO nanowire field-effect transistors (NWFETs) with ultra-scaled nanowire width (W NW) [2]. The scanning electron microscopy (SEM) images of α-IGZO nanowire before and after the digital etch show that the nanowire structure as well as W NW reduction after digital etch can be clearly observed. The smallest α-IGZO nanowire after digital etch has a W NW of ~20 nm. By leveraging the ultra-scaled nanowire structure, the NWFET with the smallest W NW achieves decent subthreshold swing of 80 mV/decade as well as high peak extrinsic transconductance (G m,ext) of 612 μS/μm at a drain to source voltage (V DS) = 2 V (456 μS/μm at V DS = 1 V). As compared with previous works in literature, our IGZO NWFET achieves one of the highest peak G m among all IGZO-based FETs. α-IGZO ferroelectric FETs (Fe-FETs) with a metal-ferroelectric-metal-oxide-semiconductor (MFMIS) structure were further realized based on the α-IGZO transistor process modules. The smallest L CH is as small as 40 nm. The cross-sectional transmission electron microscopy (TEM) image of the device shows sharp interface. The α-IGZO Fe-FETs achieve a large memory window of 2.9 V, high endurance of 108 cycles, high conductance ratio, and small cycle-to-cycle variation. By leveraging the low temperature processed α-IGZO Fe-FETs with good electrical characteristics, a BEOL-compatible ferroelectric TCAM circuit with 2 Fe-FETs connected in parallel was realized [3], showing an extremely large sensing margin. In addition, such α-IGZO Fe-FET TCAM reduces the transistor number from 16 to 2 as compared to traditional SRAM-based TCAM. Smaller cell size and higher energy efficiency can also be obtained. IGZO transistors can play an important role in in-memory computing as well. SEM image of the eDRAM CiM cell shows utilization of IGZO transistors. The smallest device has L CH of 45 nm [4]. The IGZO transistor-based eDRAM CiM with differential cell structure achieves low leakage current, low variation, low charge loss sensitivity, and the control-friendly charge-domain computing without DC power. By evaluating the key figure-of-merits, including precision, power efficiency, computing density, retention time, and robustness, it can be concluded that our IGZO transistor-based eDRAM CiM is promising for low-power and scalable compute-in-eDRAM design. Acknowledgments: This work is supported by Singapore Ministry of Education (Tier 2: MOE2018-T2-2-154, Tier 1: R-263-000-D65-114). References: [1] K. Normura et al., Nature, 432 (7016), 488-492, 2004. [2] K. Han et al., VLSI, 2021, p. T10-1. [3] C. Sun et al., VLSI, 2021, p. T7-4. [4] J. Liu et al., IEDM, 2021, p. 462.
41
Shih, Wen-Chieh, Chih-Hao Cheng, Joseph Ya-min Lee, and Fu-Chien Chiu. "Charge-Trapping Devices Using Multilayered Dielectrics for Nonvolatile Memory Applications." Advances in Materials Science and Engineering 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/548329.
Full textAbstract:
Charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications. The device structure is Al/Y2O3/Ta2O5/SiO2/Si (MYTOS). The MYTOS field effect transistors were fabricated using Ta2O5as the charge storage layer and Y2O3as the blocking layer. The electrical characteristics of memory window, program/erase characteristics, and data retention were examined. The memory window is about 1.6 V. Using a pulse voltage of 6 V, a threshold voltage shift of ~1 V can be achieved within 10 ns. The MYTOS transistors can retain a memory window of 0.81 V for 10 years.
42
Song, Chong-Myeong, and Hyuk-Jun Kwon. "Ferroelectrics Based on HfO2 Film." Electronics 10, no. 22 (November 11, 2021): 2759. http://dx.doi.org/10.3390/electronics10222759.
Full textAbstract:
The discovery of ferroelectricity in HfO2 thin film, which is compatible with the CMOS process, has revived interest in ferroelectric memory devices. HfO2 has been found to exhibit high ferroelectricity at a few nanometers thickness, and studies have rapidly progressed in the past decade. Ferroelectricity can be induced in HfO2 by various deposition methods and heat treatment processes. By combining ferroelectric materials with field-effect transistors, devices that combine logic and memory functions can be implemented. Ferroelectric HfO2-based devices show high potential, but there are some challenges to overcome in endurance and characterization. In this paper, we discuss the fabrication and characteristics of ferroelectric HfO2 film and various applications, including negative capacitance (NC)), Ferroelectric random-access memory (FeRAM), Ferroelectric tunnel junction (FTJ), and Ferroelectric Field-effect Transistor (FeFET).
43
Zhu, Zhiheng, Yunlong Guo, and Yunqi Liu. "Application of organic field-effect transistors in memory." Materials Chemistry Frontiers 4, no. 10 (2020): 2845–62. http://dx.doi.org/10.1039/d0qm00330a.
Full textAbstract:
Functional organic field-effect transistors (OFETs) have developed rapidly, especially OFETs with memory function. We make a comprehensive summary of the background, memory mechanism, structure construction and memory applications based on OFETs.
44
Cheremisinov, D. I., and L. D. Cheremisinova. "Logical gates recognition in a flat transistor circuit." Informatics 18, no. 4 (December 31, 2021): 96–107. http://dx.doi.org/10.37661/1816-0301-2021-18-4-96-107.
Full textAbstract:
O b j e c t i v e s. With the increasing complexity of verification and simulation of modern VLSI, containing hundreds of millions of transistors, the means of extracting the hierarchical description at the level of logical elements froma flat description of circuits at the transistor level are becoming the main tools for computer-aided design and verification. Decompilation tools for transistor circuits can not only significantly reduce the time to perform VLSI topology check, but also provide the basis for generating test cases, logical reengineering of integrated circuits and reverse engineering to detect untrusted attachments.The objective of the work is to solve the problem of extracting the structure of the functional level from a flat circuit of the transistor level by recognizing in it subcircuits that implement logical elements.M e t h o d s. Graph based methods are proposed for solving some key problems arising at the stage of structural recognition of CMOS gates in a transistor circuit: partitioning a graph into connectivity components corresponding to transistor subcircuits; recognition of subcircuits that are logical elements, and functions implemented by them; forming a library of recognized gates and constructing two-level transistor circuit. The original flat and resulting two-level transistor circuits are presented in SPICE format.Re s u l t s. The proposed methods are implemented in C++ as a part of a transistor circuit decompilation programfor the case without any predetermined cell library. All steps of the proposed methods of structural CMOS gates recognition are performed in a linear time from the number of transistors in the initial circuit.Co n c l u s i o n. The decompilation program has been tested on practical transistor-level circuits. Experiments indicate that the present tool is fast enough to process circuits with more than a hundred thousand transistors in a few minutes on a personal computer. Currently, the authors are developing methods for recognizing more complex elements in a transistor circuit, such as memory elements.
45
Zhao, Yuhang, and Jie Jiang. "Recent Progress on Neuromorphic Synapse Electronics: From Emerging Materials, Devices, to Neural Networks." Journal of Nanoscience and Nanotechnology 18, no. 12 (December 1, 2018): 8003–15. http://dx.doi.org/10.1166/jnn.2018.16428.
Full textAbstract:
To realize intelligent functions in electronic devices like a human brain, it is important to develop the electronic devices that can imitate biological neurons and synapses (synaptic electronics). In this paper, we review the critical learning mechanisms for synaptic plasticity. Different electronic devices were developed to mimic biological synapses, such as atomic switch, phase change memory, ferroelectric memory, and electric-double-layer transistors. More importantly, several groups have realized the artificial neuromorphic network using multi-gate transistor architecture. The leap from synapse to neuron to neural network, thus, has been systematically realized using thin films and nanomaterials. The emerging synaptic electronics can have a broader applications and brighter future in the next-generation intelligent nano-electronics.
46
Sharma, Neha, and Rajeevan Chandel. "Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS." International Journal of Modeling, Simulation, and Scientific Computing 12, no. 04 (March 9, 2021): 2150029. http://dx.doi.org/10.1142/s179396232150029x.
Full textAbstract:
With technology scaling, stability, power dissipation, and device variability, the impact of process, voltage and temperature (PVT) variations has become dominant for static random access memory (SRAM) analysis for productivity and failure. In this paper, ten-transistors (10T) and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors (FGMOS). Power centric parameters viz. read power, write power, hold power and delay are the performance analysis metrics. Further, the stochastic parameter variation to study the variability tolerance of the redesigned cell, PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell. Stability has been illustrated with the conventional butterfly method giving read static noise margin (RSNM) and write static noise margin (WSNM) metrics for read stability and write ability, respectively. A comparative analysis with standard six-transistor SRAM cell is carried out. HSPICE simulative analysis has been carried out for 32[Formula: see text]nm technology node. The redesigned FGMOS SRAM cells provide improved performance. Also, these are robust and reliability efficient with comparable stability.
47
Kavitha, Shanmugam, Chandrasekaran Kumar, Hady H. Fayek, and Eugen Rusu. "Design and Implementation of CNFET SRAM Cells by Using Multi-Threshold Technique." Electronics 12, no. 7 (March 29, 2023): 1611. http://dx.doi.org/10.3390/electronics12071611.
Full textAbstract:
This paper presents a CNFET (Carbon Nano-tube FET) based MT (Multi-Threshold)-SRAM (Static Random Access Memory) design based on the leakage reduction mechanism. A multi-threshold logic is employed for reducing the leakage current during read/write operations. Here, the multi-threshold technique is used to insert the high threshold sleep control to the low threshold circuit. The insertion is performed in a serial manner. The high threshold transistors are very useful for deriving the low sub-threshold current. Meanwhile, the low threshold transistors are promising for improving the circuit performance. The high-low threshold transistor pairs are used to change the channel length by modifying the oxide thickness of the transistors. The overall implementation of the Multi-threshold-based SRAM cells are implemented with the help of CNFET in-order to avoid the short channel effect, mobility degradation which is occurred while considering the channel length below 32 nm in CMOS (Complementary Metal Oxide Semiconductor) devices. The paper clearly represents the performance improvement of the proposed SRAM cells with above-mentioned technologies.
48
Lee, Dong-Hee, Hamin Park, and Won-Ju Cho. "Nanowire-Enhanced Fully Transparent and Flexible Indium Gallium Zinc Oxide Transistors with Chitosan Hydrogel Gate Dielectric: A Pathway to Improved Synaptic Properties." Gels 9, no. 12 (November 27, 2023): 931. http://dx.doi.org/10.3390/gels9120931.
Full textAbstract:
In this study, a transparent and flexible synaptic transistor was fabricated based on a random-network nanowire (NW) channel made of indium gallium zinc oxide. This device employs a biocompatible chitosan-based hydrogel as an electrolytic gate dielectric. The NW structure, with its high surface-to-volume ratio, facilitated a more effective modulation of the channel conductance induced by protonic-ion polarization. A comparative analysis of the synaptic properties of NW- and film-type devices revealed the distinctive features of the NW-type configuration. In particular, the NW-type synaptic transistors exhibited a significantly larger hysteresis window under identical gate-bias conditions. Notably, these transistors demonstrated enhanced paired-pulse facilitation properties, synaptic weight modulation, and transition from short- to long-term memory. The NW-type devices displayed gradual potentiation and depression of the channel conductance and thus achieved a broader dynamic range, improved linearity, and reduced power consumption compared with their film-type counterparts. Remarkably, the NW-type synaptic transistors exhibited impressive recognition accuracy outcomes in Modified National Institute of Standards and Technology pattern-recognition simulations. This characteristic enhances the efficiency of practical artificial intelligence (AI) processes. Consequently, the proposed NW-type synaptic transistor is expected to emerge as a superior candidate for use in high-efficiency artificial neural network systems, thus making it a promising technology for next-generation AI semiconductor applications.
49
Jang, Jiung, Yeonsu Kang, Danyoung Cha, Junyoung Bae, and Sungsik Lee. "Thin-Film Optical Devices Based on Transparent Conducting Oxides: Physical Mechanisms and Applications." Crystals 9, no. 4 (April 3, 2019): 192. http://dx.doi.org/10.3390/cryst9040192.
Full textAbstract:
This paper provides a review of optical devices based on a wide band-gap transparent conducting oxide (TCO) while discussing related physical mechanisms and potential applications. Intentionally using a light-induced metastability mechanism of oxygen defects in TCOs, it is allowed to detect even visible lights, eluding to a persistent photoconductivity (PPC) as an optical memory action. So, this PPC phenomenon is naturally useful for TCO-based optical memory applications, e.g., optical synaptic transistors, as well as photo-sensors along with an electrical controllability of a recovery speed with gate pulse or bias. Besides the role of TCO channel layer in thin-film transistor structure, a defective gate insulator can be another approach for a memory operation with assistance for gate bias and illuminations. In this respect, TCOs can be promising materials for a low-cost transparent optoelectronic application.
50
Gudlavalleti, R. H., B. Saman, R. Mays, Evan Heller, J. Chandy, and F. Jain. "A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory." International Journal of High Speed Electronics and Systems 29, no. 01n04 (March 2020): 2040010. http://dx.doi.org/10.1142/s0129156420400108.
Full textAbstract:
This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.