Academic literature on the topic 'Memory transistors'
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Journal articles on the topic "Memory transistors"
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Al-shawi, Amjad, Maysoon Alias, Paul Sayers, and Mohammed Fadhil Mabrook. "Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors." Micromachines 10, no. 10 (September 25, 2019): 643. http://dx.doi.org/10.3390/mi10100643.
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To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts in the threshold voltage of the transfer characteristics as well as the hysteresis in the output characteristics were attributed to the charging and discharging of the floating gate. The counter-clockwise direction of hysteresis indicates that the process of charging and discharging the floating gate take place through the semiconductor/insulator interface. A clear shift in the threshold voltage was observed when different voltage pulses were applied to the gate. The non-volatile behaviour of the memory transistors was investigated in terms of charge retention. The memory transistors exhibited a large memory window (~30 V), and high charge density of (9.15 × 1011 cm−2).
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Xie, Fangqing, Maryna N. Kavalenka, Moritz Röger, Daniel Albrecht, Hendrik Hölscher, Jürgen Leuthold, and Thomas Schimmel. "Copper atomic-scale transistors." Beilstein Journal of Nanotechnology 8 (March 1, 2017): 530–38. http://dx.doi.org/10.3762/bjnano.8.57.
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We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.
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Srinivasarao, B. N., and K. Chandrabhushana Rao. "Design and Analysis of Area Efficient 128 Bytes SRAM Architecture." Journal of VLSI Design and Signal Processing 8, no. 1 (March 30, 2022): 19–26. http://dx.doi.org/10.46610/jovdsp.2022.v08i01.004.
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SRAM Memory architecture design and implementation is a challenging task for memory applications. Practical architecture was developed and used successfully using various double ended SRAM cells like 6 and 4 transistors. But for single ended SRAM cell like 5 transistors or any other number of transistors there is no specific architecture for practical applications. Conventional SRAM architecture has SRAM cell, write driver circuit along with bit inverter, Pre-charge circuit and sense amplifier which consists more, number of transistors required to handle single bit storage. In this paper SRAM architecture is implemented for single ended SRAM cell that is three transistor SRAM cell. Area is reduced by 60% with average power consumption 3.05µW and speed with 20.87GHz. Finally,28 bytes memory structure is implemented and verified its operation.
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Kim, Woojo, Jimin Kwon, and Sungjune Jung. "3D Integration of Flexible and Printed Electronics: Integrated Circuits, Memories, and Sensors." Journal of Flexible and Printed Electronics 2, no. 2 (December 2023): 199–210. http://dx.doi.org/10.56767/jfpe.2023.2.2.199.
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Printing technologies have received a lot of attention and expectations for producing flexible and wearable electronics. However, the low transistor density of the printed devices has been a major obstacle to commercialization. In this review, a three-dimensional (3D) integration of organic flexible and printed electronics is described. First, layout-to-bitmap conversion and design rules for printed transistors, arrays, and integrated circuits are introduced. Then, printed 3D transistors, digital integrated circuits, and memories are described. Finally, 3D integration of printed active-matrix arrays and sensors is highlighted. This approach is a breakthrough technology that not only reduces the area occupied by a single transistor, memory, and sensor, but also increases the efficiency of routing, effectively reducing the area of the entire devices. In addition, monolithic 3D integration through the printing can stack transistor, memory, and sensor by simply repeating the additive process.
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Kim, Ji-Hun, Hyeon-Jun Kim, Ki-Jun Kim, Tae-Hun Shim, Jin-Pyo Hong, and Jea-gun Park. "3-Terminal Igzo FET Based 2T0C DRAM Combined Bit-Line Structure." ECS Meeting Abstracts MA2023-02, no. 30 (December 22, 2023): 1561. http://dx.doi.org/10.1149/ma2023-02301561mtgabs.
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The IGZO (InGaZnO)-based two-transistor zero-capacitor(2T0C) DRAM has attracted much attention as an alternative memory to overcome the scale-down limit of current 1T1C DRAM due to its low power consumption and monolithic 3D stacking capability. In particular, its low power consumption and the feasibility of low temperature process make it highly implementable for 3D DRAM. For operating the 2T0C DRAM, four metal lines are necessary, i.e., write word line and write bit line (WBL) for operating write transistor (WTR), and read word line and read bit line (RBL) for operating read transistor (RTR). In this study, we propose a 3-terminal 2T0C DRAM to enhance its memory characteristics, where RBL was combined with WBL, enabling 2T0C memory operation with only three metal lines as shown in Fig. 1(b). In addition, we investigated the dependency of retenetion time of the proposed 2T0C DRAM on channel length. In particular we evaluated the dependency of the sneak current of 2T0C DRAM on off-current of transistor. For the fabrication of 3-terminal IGZO 2T0C DRAM, a top gate IGZO transistor was fabricated using RF sputtering and two transistors were connected by storage node and bit line bridge as shown in Fig. 1(d).The storage node was formed by connecting the gate of RTR to drain of WTR. And source electrodes of both transistors were coupled. To determine the voltage values for memory operation, the transfer curve of each transistor was characterized and the threshold voltages for both RTR and WTR were around 1 V. The write and read voltages were set to 3 and 2 V, respectively. The retention time was measured by performing periodic read operations after writing and measuring the RTR currents. In addition, the retention time of transistors for varying channel length and gate capacitance was characterized. The retention time was defined as the time to be taken for decreasing the currents by 90 %. Furthermore, the disturbance of 2T0C DRAM with 2x2 array structure was investigated. The RTR currents of selected cells were measured depending on the memory state of adjacent cells. It was found that the retention times of transistors with 10- and 100-um RTR channel lengths were approximately 15 and 30 seconds, respectively. It was observed that the memory state was not changed from “0“ to “1“ by disturbant currents, but, RTR currents of “0“ state cell increased slightly when an adjacent cell was turned on. However, as shown in Fig.1(i) and (j), when off-currents of transistor of 2T0C DRAM decreased from 20 nA to 200 pA, it was confirmed the sneak current of 2T0C decreased. Finally, several technical apporaches how to suppress the disturbant currents will be presented in detail. Acknowledgement This research was supported by BrainKorea21 Four. Figure 1
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Brtník, Bohumil. "Assembling a Formula for Current Transferring by Using a Summary Graph and Transformation Graphs." Journal of Electrical Engineering 64, no. 5 (September 1, 2013): 334–36. http://dx.doi.org/10.2478/jee-2013-0050.
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Abstract This paper deals with the symbolic solution of the switched current circuits. As is described, the full graph method of the solution can be used for finding relationships expressing current transfer, too. The summa MC-graph is constructed using two-graphs method in two-phase switching. By comparing the matrix form with results of the Mason’s formula are derived relations for current transfers in all phases. There are discussed various options described transistor memory cells - with loss and lossless transistors and normal transistor current mirror. Evaluation of the graph is simplified if we consider the lossless transistors or if the y21 -parameter of one transistor is alpha multiple of second ones.
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Lee, Edward, Daehyun Kim, Jinwoo Kim, Sung Kyu Lim, and Saibal Mukhopadhyay. "A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process." ACM Journal on Emerging Technologies in Computing Systems 18, no. 1 (January 31, 2022): 1–20. http://dx.doi.org/10.1145/3466681.
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We present a ReRAM memory compiler for monolithic 3D (M3D) integrated circuits (IC). We develop ReRAM architectures for M3D ICs using 1T-1R bit cells and single and multiple tiers of transistors for access and peripheral circuits. The compiler includes an automated flow for generation of subarrays of different dimensions and larger arrays of a target capacity by integrating multiple subarrays. The compiler is demonstrated using an M3D process design kit (PDK) based on a Carbon Nanotube Transistor technology. The PDK includes multiple layers of transistors and back-end-of-the-line integrated ReRAM. Simulations show the compiled ReRAM macros with multiple tiers of transistors reduces footprint and improves performance over the macros with single-tier transistors. The compiler creates layout views that are exported into library exchange format or graphic data system for full-array assembly and schematic/symbol views to extract per-bit read/write energy and read latency. Comparison of the proposed M3D subarray architectures with baseline 2D subarrays, generated with a custom-designed set of bit cells and peripherals, demonstrate up to 48% area reduction and 13% latency improvement.
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Choi, Young Jin, Jihyun Kim, Min Je Kim, Hwa Sook Ryu, Han Young Woo, Jeong Ho Cho, and Joohoon Kang. "Hysteresis Behavior of the Donor–Acceptor-Type Ambipolar Semiconductor for Non-Volatile Memory Applications." Micromachines 12, no. 3 (March 12, 2021): 301. http://dx.doi.org/10.3390/mi12030301.
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Donor–acceptor-type organic semiconductor molecules are of great interest for potential organic field-effect transistor applications with ambipolar characteristics and non-volatile memory applications. Here, we synthesized an organic semiconductor, PDPPT-TT, and directly utilized it in both field-effect transistor and non-volatile memory applications. As-synthesized PDPPT-TT was simply spin-coated on a substrate for the device fabrications. The PDPPT-TT based field-effect transistor showed ambipolar electrical transfer characteristics. Furthermore, a gold nanoparticle-embedded dielectric layer was used as a charge trapping layer for the non-volatile memory device applications. The non-volatile memory device showed clear memory window formation as applied gate voltage increases, and electrical stability was evaluated by performing retention and cycling tests. In summary, we demonstrate that a donor–acceptor-type organic semiconductor molecule shows great potential for ambipolar field-effect transistors and non-volatile memory device applications as an important class of materials.
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Qiu, Haiyang, Dandan Hao, Hui Li, Yepeng Shi, Yao Dong, Guoxia Liu, and Fukai Shan. "Transparent and biocompatible In2O3 artificial synapses with lactose–citric acid electrolyte for neuromorphic computing." Applied Physics Letters 121, no. 18 (October 31, 2022): 183301. http://dx.doi.org/10.1063/5.0124219.
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Electrolyte-gated synaptic transistors are promising for artificial neural morphological devices. However, few literatures have been reported regarding the manufacturing of electrolyte-gated synaptic transistors with low cost and biocompatible components. Here, the fully transparent synaptic transistors based on water-induced In2O3 thin films have been integrated by sol–gel method at low temperature, and lactose dissolved in citric acid solution is used as the gate electrolyte. The migration of the ions at the interface plays a crucial role in the potentiation and depression of the synaptic weight. In this work, the biological synaptic functions, including excitatory postsynaptic current, paired-pulse facilitation, high-pass filtering characteristics, short-term memory, and long-term memory, are mimicked. Meanwhile, based on the potentiation/depression behaviors of the synaptic transistor, a three-layer artificial neural network is applied for pattern recognition, and the recognition accuracy is as high as 94.6%. This study offers a possibility to realize fully transparent synaptic devices with biocompatible components at low temperature.
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Gul, Waqas, Maitham Shams, and Dhamin Al-Khalili. "SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview." Micromachines 13, no. 8 (August 17, 2022): 1332. http://dx.doi.org/10.3390/mi13081332.
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Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell’s stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell’s reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions.
Dissertations / Theses on the topic "Memory transistors"
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Masani, Deekshitha. "Analysis of radiation induced errors in transistors in memory elements." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/theses/2791.
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From the first integrated circuit which has 16-transistor chip built by Heiman and Steven Hofstein in 1962 to the latest 39.54 billion MOSFET’s using 7nm FinFET technology as of 2019 the scaling of transistors is still challenging. The scaling always needs to satisfy the minimal power constraint, minimal area constraint and high speed as possible. As of 2020, the worlds smallest transistor is 1nm long build by a team at Lawrence Berkeley National Laboratory. Looking at the latest trends of 14nm, 7nm technologies present where a single die holds more than a billion transistors on it. Thinking of it, it is more challenging for dyeing a 1nm technology. The scaling keeps going on and if silicon does not satisfy the requirement, they switch to carbon nanotubes and molybdenum disulfide or some newer materials. The transistor sizing is reducing but the pressure of radiation effects on transistor is in quench of more and more efficient circuits to tolerate errors. The radiation errors which are of higher voltage are capable of hitting a node and flipping its value. However, it is not possible to have a perfect material to satisfy no error requirement for a circuit. But it is possible to maintain the value before causing the error and retain the value even after occurrence of the error. In the advanced technologies due to transistor scaling multiple simultaneous radiation induced errors are the issue. Different latch designs are proposed to fix this problem. Using the CMOS 90nm technology different latch designs are proposed which will recover the value even after the error strikes the latch. Initially the errors are generally Single event upsets (SEUs) which when the high radiation particle strikes only one transistor. Since the era of scaling, the multiple simultaneous radiation errors are common. The general errors are Double Node Upset (DNU) which occurs when the high radiation particle strikes the two transistors due to replacing one transistor by more than one after scaling. Existing designs of SEUs and DNUs accurately determine the error rates in a circuit. However, with reference to the dissertation of Dr. Adam Watkins, proposed HRDNUT latch in the paper “Analysis and mitigation of multiple radiation induced errors in modern circuits”, the circuits can retain its error value in 2.13ps. Two circuits are introduced to increase the speed in retaining the error value after the high energy particle strikes the node. Upon the evaluation of the past designs how the error is introduced inside the circuit is not clear. Some designs used a pass gate to actually introduce the error logic value but not in terms of voltage. The current thesis introduces a method to introduce error with reduced power and delay overhead compared to the previous circuits. Introducing the error in the circuits from the literature survey and comparing the delay and power with and without introducing the error is shown. Introducing the errors in the two new circuits are also shown and compared with when no errors are injected.
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Fakher, Sundes Juma. "Advanced study of pentacene-based organic memory structures." Thesis, Bangor University, 2014. https://research.bangor.ac.uk/portal/en/theses/advanced-study-of-pentacenebased-organic-memory-structures(5319a571-2c4c-4f90-a26c-fa5e7da82cfb).html.
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A systematic approach has been used to optimise the fabrication process of pentacene-based nonvolatile organic thin film memory transistors (OTFMTs) operating at low programming voltages. In the first part of this work, reliable, reproducible and hysteresis free organic metal-insulator-semiconductor (OMIS) devices and organic thin film transistors (OTFTs) were fabricated and characterised. All devices were based on poly(methyl methacrylate) (PMMA) and poly(vinyl phenol) (PVP) as the organic insulators. The second part of this work focused on optimising the evaporation parameters to fabricate high-performance pentacene-based devices. About 50 nm thickness of pentacene film with a deposition rate of 0.03 nm s-1 on ~ 300 nm of PMMA was found to produce large, uniform and condense grains leading to high quality devices. OTFTs with high mobility of 1.32 cm2 V−1 s−1, on/off current ratio of 106, and negligible hysteresis and leakage current were demonstrated. The effect of the environment on the OTFTs obehaviour was also investigated. The bias stress effect was also investigated in terms of threshold voltage shift ΔVT at various conditions and times. The results show ΔVT increases with the increase of stress voltage. A negligible hysteresis is evident between the forward and reverse direction of the transfer characteristics and the shape of the transfer characteristics does not change with the bias stress. Floating gate memory structures with thin layer of gold, gold nanoparticles (AuNPs) and single walled carbon nanotubes (SWCNTs) were fabricated and characterised during this investigation. Hysteresis in memory structures was a clear indication of the memory effect and charge storage in these devices. Also, the hysteresis was centred close to 0 V for SWCNTs-based structures, which indicate that a low operation voltage is needed to charge the devices. A memory window of about 40 V was observed for AuNPs-based memory devices based on PVP; while the memory windows for devices based on PMMA with thin layer of Au and AuNPs floating gates were 22 V and 32 V, respectively. The electrical properties of the OTFMTs were improved by the use of the Au nanoparticles as the floating gate compared with that of an Au thin film. Using appropriate negative or positive voltages, the floating gate was charged and discharged, resulting in a clear shift in the threshold voltage of the memory transistors. Negative and positive pulses of 1 V resulted in clear write and erase states, respectively. Additionally, these organic memory transistors exhibited rather high carrier mobility of about μ = 0.319 cm2 V-1 s-1. Furthermore the data retention and endurance measurements confirmed the non-volatile memory properties of the memory devices fabricated in this study.
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Almeida, Luciano Mendes. "Estudo de célula de memória dinâmica de apenas um transistor SOI de óxido enterrado ultrafino." Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-18072013-144946/.
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Neste trabalho foi analisado o comportamento de um transistor UTBOX (Ultra Thin Buried Oxide) FD SOI MOSFET (Fully Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) planar do tipo n, operando como uma célula de memória 1T-FBRAM (single transistor floating body random access memory). A memória em questão trata-se de uma evolução das memórias 1T1C-DRAM convencionais formada, porém, de apenas um transistor, sendo o próprio transistor o responsável pelo armazenamento da informação por meio do efeito de corpo flutuante. Assim, foram realizadas simulações numéricas bidimensionais, obtendo-se curvas dinâmicas e, a partir destas, foi possível extrair e analisar alguns dos principais parâmetros da memória tais como tensão de disparo no dreno, margem de sensibilidade, janela de leitura e tempo de retenção, além dos mecanismos atuantes em cada estado da memória (escrita, leitura e repouso). Foram estudadas as polarizações da célula de memória. Dentre as possíveis maneiras de programação do dado 1 desta tecnologia foram abordadas neste trabalho a programação pelos métodos GIDL (Gate Induced Drain Leakage) e BJT (Bipolar Junction Transistor). Pelo método de escrita por GIDL foi possível operar a célula de memória em alta velocidade sem dissipar potência expressiva. Mostrou-se que esse método é bastante promissor para a tecnologia low-power high-speed. E ainda, obteve-se maior estabilidade na operação de leitura quando esta é polarizada no ponto ZTC (Zero Temperature-Coefficient) devido ao nível de corrente do dado 0 ficar estável mesmo com a variação da temperatura. Pelo método de escrita por BJT, estudou-se a influência das espessuras do filme de silício e também do óxido enterrado, notou-se uma forte dependência da tensão mínima de dreno para a programação do dado 1 em função destas espessuras e também em função da temperatura. Conforme a espessura do filme de silício torna-se mais fina, a tensão de disparo aplicada ao dreno aumenta devido ao maior acoplamento. Porém, observou-se que o nível da tensão de disparo do dreno pode ser modulada através da tensão aplicada ao substrato, tornando possível operar a célula em uma tensão de disparo menor aumentando a vida útil do dispositivo. Quanto à temperatura, com o seu aumento observou-se que a tensão mínima de dreno necessária para disparar a escrita do dado 1 diminuiu favorecendo a programação da célula. Porém o tempo de retenção é prejudicado (torna-se menor) por causa do aumento da corrente de fuga na junção PN. Na análise sobre o impacto que a primeira e a segunda porta causam na margem de sensibilidade de corrente e no tempo de retenção, verificou-se que dependendo da tensão aplicada à porta durante a condição de armazenamento do dado, o tempo de retenção pode ser limitado ou pela geração ou pela recombinação dos portadores (lacunas). Notou-se que há um compromisso entre a obtenção da melhor margem de sensibilidade de corrente e o melhor tempo de retenção. Como o tempo retenção é um parâmetro mais crítico, mais atenção foi dada para a otimização deste. Concluiu-se nesta análise que a melhor polarização para reter o dado por mais tempo é a primeira interface estar em modo acumulação e a segunda em modo depleção. No estudo da polarização de dreno durante a operação de leitura, observou-se que quando aplicado alta tensão de dreno é obtido alta margem de sensibilidade, porém ao mesmo tempo esta polarização prejudica o dado 0 devido ao alto nível de geração de lacunas induzidas pela ionização por impacto, o qual diminui o tempo de retenção e destrói o dado 0 quando operações de múltiplas leituras são realizadas. Já para baixo nível de tensão de dreno durante a leitura notou-se que é possível realizar múltiplas operações de leitura sem perder o dado armazenado e também maior tempo de retenção foi obtido.In this study was analyzed the behavior of one transistor called UTBOX (Ultra Thin Buried Oxide) FD SOI MOSFET (Fully Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) working as a 1T-FBRAM (Single Transistor Floating Body Random Access Memory). This memory device is an evolution from conventional memories 1T1C-DRAM, however formed by only one transistor, the device itself is responsible for the storage of the information through the floating body effect. Thus two dimensional simulations were performed, where were obtained dynamic curves, and from these curves it was possible to extract and analyze some of the main parameters, such as, trigger drain voltage, sense margin current, read window, and the retention time, beyond the mechanisms in each state of memory (write, read and hold). Among the possible ways to program the data 1 in this technology were used the methods GIDL (Gate Induced Drain Leakage) and BJT (Bipolar Junction Transistor). By the GIDL method it was possible to operate the memory cell at high speed without spending significant power, showing that this method is very promising for low-power high-speed. Furthermore, greater stability was obtained in read operation when it is biased at point ZTC (zero-Temperature Coefficient) due to the current level of datum \'0\' remain stable even with temperature variation. By the BJT method, it was studied the influence of the silicon film thickness and the buried oxide thickness, and it was noted a strong dependence on minimum drain voltage for programming the data \'1\' as a function of both thicknesses. As the thickness of the silicon film becomes thinner, the trigger drain voltage increases due to stronger coupling. However, it was observed that the level of the trigger drain voltage can be modulated by the substrate bias in this way it is possible to operate the cell with lower voltage avoiding the damage and increasing the lifetime of the device. About the temperature, with its increase it was observed that the minimum drain voltage required to trigger the writing datum \'1\' decreased favoring the programming the cell. However the retention time is harmed (becomes smaller) due to the increment of leakage current in the PN junction. Analyzing the impact of the first and second gate on sense margin current and retention time, it was verified that depending on the voltage applied to the gate during the hold condition, the retention time may be limited by the generation or recombination of the carriers (holes). It was noted that there is a compromise between obtaining the best sense margin current and the best retention time. Since the retention is the most critical parameter, more attention should be given in order to obtain the optimization of this latter. It is concluded in this analysis that the best bias to retain the datum for longer time is the first interface being in accumulation mode and the second in depletion mode. In the study of biasing the drain during the read operation, it has been observed that the use of high drain voltage provides high sense margin, but at the same time, this polarization affect the data \'0\' due to high level of holes generation induced by impact ionization, which shortens the retention time and destroys the data \'0\' in multiple read operations. However, for low drain voltage during read operations it was possible to perform multiple read operations without losing the stored data and also higher retention time was obtained.
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Sasaki, Kátia Regina Akemi. "Propostas de melhorias de desempenho de célula de memória dinâmica utilizando um único transistor UTBOX SOI." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-26072013-173443/.
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Neste trabalho foi analisado o comportamento de um transistor UTBOX FD SOI MOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) planar do tipo N, em sua aplicação como uma célula de memória 1T-DRAM, dando ênfase no estudo das polarizações e propostas de melhorias de desempenho para viabilizar sua aplicação como uma célula de memória. Dessa forma, foram analisados os efeitos das diferentes polarizações (de porta, de dreno e de substrato), bem como a influência da concentração de uma região de extensão de fonte e dreno menos dopada (LDD Lightly Doped Drain), nos principais parâmetros da referida memória. Assim, foram analisados alguns parâmetros da memória tais como tensão de disparo no dreno, margem de sensibilidade, janela de leitura e tempo de retenção, além dos mecanismos atuantes em cada estado da memória (escrita, leitura e repouso). Por fim, foram propostas algumas melhorias de desempenho para o tempo de retenção. Foi observado que o aumento da temperatura facilita a escrita na memória diminuindo a mínima tensão no dreno (até 72% para temperatura de 25 a 300°C, ficando limitada a 0,8V) e o tempo necessários para a escrita (até 95%), porém reduz a margem de sensibilidade (até 90%) e o tempo de retenção (até 2 ordens de grandeza). Verificou-se também que, apesar da menor espessura do filme de silício e do óxido enterrado aumentar a tensão no dreno necessária para ativar o efeito BJT (efeito bipolar parasitário), um potencial positivo no substrato pode reduzir este requisito (61% para tensão de substrato variando de 0 V até 1,5 V). Além disso, foi visto que pode haver uma geração ou uma recombinação de portadores, dependendo da tensão na porta durante o repouso, degradando o bit \'0\' ou \'1\'. Já a otimização da polarização de substrato demonstrou ser limitada pelo compromisso de ser alta o suficiente para ativar o efeito de corpo flutuante durante a escrita, sem prejudicar a leitura do \'0\'. Os resultados também demonstraram que a margem de sensibilidade é menos dependente da tensão do substrato que o tempo de retenção, levando a este último parâmetro ser considerado mais crítico. Com relação à leitura, maiores tensões no dreno resultaram na presença do efeito BJT também neste estado, aumentando a margem de sensibilidade (60%) e diminuindo o tempo de retenção (66%) e o número de leituras possíveis sem atualização do dado (de mais de 30 para 22 leituras). No tópico da concentração das extensões de fonte e dreno, os dispositivos sem extensão de fonte e dreno apresentaram uma taxa de geração de lacunas menor (aproximadamente 12 ordens de grandeza), levando a um tempo de retenção muito maior (aproximadamente 3 ordens de grandeza) quando comparado ao dispositivo referência. Em seu estudo no escalamento, verificou-se uma diminuição no tempo de retenção para canais mais curtos (quase 2 ordens de grandeza), demonstrando ser um fator limitante para as futuras gerações das memórias 1T-DRAM. Apesar disso, quando comparados com os dispositivos convencionais com extensão de fonte e dreno (com extensão), seu tempo de retenção aumentou (quase 1 ordem de grandeza), permitindo a utilização de menores comprimentos de canal (30nm contra 50nm do dispositivo com extensão) e polarizações de substrato menores. Outra proposta de melhoria no tempo de retenção apresentada foi a utilização da polarização de substrato pulsada apenas durante a escrita do nível \'1\', o que resultou no aumento do tempo de retenção em 17%. Finalmente, estudou-se também a variação da banda proibida motivado pela utilização de novos materiais para o filme semicondutor. Observou-se que o aumento da banda proibida aumentou o tempo de retenção em até 5 ordens de grandeza, possibilitando retenções mais próximas das DRAMs convencionais atuais.In this work, it was analyzed the behavior of a planar UTBOX FD SOI NMOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor), as a 1T-DRAM (Single Transistor Dynamic Random Access Memory) cell, focusing on the best biases and other proposals for enabling the 1T-DRAM applications. Therefore, it was analyzed the effects of different biases (gate, drain and substrate), as well as the influence of the concentration of a less doped source/drain extension region on the main parameters of this kind of memory. Thus, it was analyzed some of the main memory parameters such as the trigger drain voltage, the sense margin, the read window and the retention time, as well as the mechanisms operating in each state of the memory (writing, reading and holding). Finally, it were proposed some performance enhancements for the retention time of this kind of memory. It was observed that the increase in temperature facilitates the memory write decreasing the minimum drain bias and time required for writing, but reduces the sense margin. It was also verified that, despite the thinner silicon film and buried oxide increase the drain voltage required to activate the BJT effect (parasitic bipolar effect), a positive potential on the substrate may reduce this requirement (61% for back gate bias varying from 0 to 1,5V), being an alternative for solving the problem and allowing the use of smaller devices as a memory cell. Furthermore, it was seen that there can be a carriers generation or recombination, depending on the gate voltage during the holding state, degrading the bit \'0\' or \'1\'. Moreover, the optimization of substrate bias proved to be limited by enabling the writing state, without degrading the reading of \'0\'. The results also demonstrated the sense margin is less dependent on the substrate voltage than the retention time, therefore, the retention time was considered as a more critical parameter. With respect to the reading state, there was the presence of BJT effect also in this state, increasing the margin of sensitivity (60%) and reducing the retention time (66%) and the number of possible readings without updating the data (over 30 for 22 readings) in cases of higher drain bias. On the topic of the concentration of the source and drain extensions, the devices with source and drain extensions presented a generation rate lower (about 12 orders of magnitude), resulting in a retention time far longer than the reference one (about 3 orders of magnitude). About its downscaling, the retention time decreased for shorter channel lengths (almost 2 orders of magnitude), which is a limiting factor for 1T-DRAM future generations. Nevertheless, when it was compared to the conventional devices with source and drain extensions, theirs retention time increased (almost 1 order of magnitude), allowing the use of shorter channel lengths (30nm against 50nm of reference device) and lower back gate biases. Another proposal presented to improve the retention time was the pulsed back gate only during the writing \'1\' state, which resulted in an increase on the retention time by 17%. Finally, we also studied the band gap influence motivated by the use of new materials for the semiconductor film. It was observed that higher band gaps increase the retention time by up to 5 orders of magnitude, allowing a retention time closer to the current conventional DRAMs.
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Fullem, Travis Z. "Radiation detection using single event upsets in memory chips." Diss., Online access via UMI:, 2006.
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Kirschner, Johannes [Verfasser], and Marcus [Gutachter] Halik. "Block Copolymer Hybrid Dielectrics in Organic Memory Transistors / Johannes Kirschner ; Gutachter: Marcus Halik." Erlangen : Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2017. http://d-nb.info/1152079026/34.
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CASULA, SILVIA. "Non-volatile organic memory devices: from design to applications." Doctoral thesis, Università degli Studi di Cagliari, 2015. http://hdl.handle.net/11584/266601.
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The research activity described in the attached dissertation focused on the development, fabrication and characterization of new non-volatile memory elements based on organic technology. During the last few decades, organic materials based devices have attracted considerable interest due to their great potential for future electronic systems. Low fabrication costs, high mechanical flexibility and versatility of the chemical structure, good scalability and easy processing are the unique advantages of organic electronics. As memory devices are essential elements of any kind of electronic system, the development of organic memory devices is fundamental in order to extend the application of organic materials to different electronic circuits. Research on organic electronic memories is currently at a rapid growth stage, since it is recognized that they may be an alternative or supplementary to the conventional memory technologies. Despite considerable progress in the advancement of novel memory technologies in recent years, some challenging tasks still need to be resolved.
The Ph.D. research activity of this thesis is related to the still -opened challenges in the organic memories technologies. In particular, it focused mainly on the study, development, fabrication and characterization of new non-volatile organic memory elements based on resistive switching. The activity has been carried out in the frame of the European project “HYbrid organic/inorganic Memory Elements for integration of electronic and photonic Circuitry” (HYMEC), which involved the University of Cagliari during the last three years. The project goal was to realize new hybrid inorganic/organic resistive memory devices with functionality far beyond the state of the art. A complementary activity on transistor-based organic memory devices has been also carried out and described in this thesis.
As regards resistive memory devices, the research activity included design, fabrication and testing of a novel non-volatile memory device based on the combination of an air-stable organic semiconductor and metal nanoparticles. This topic required the development of technology and procedures for easy and reliable production of devices as well as the definition of measurement protocols. The proposed structure was thoroughly characterized by morphological techniques, which allowed to interpret the resistive switching mechanisms in terms of formation and rupture of metallic filaments inside the organic layer assisted by the metal NPs. The obtained performances are the best reported so far in literature, and, to our knowledge, the statistics analysis is the largest ever reported for organic-based resistive memories. The developed technology was then successfully applied on flexible plastic substrates. The definition of technological processes for the reliable fabrication of high performance printed organic memory devices was also carried out: this work clearly demonstrates the real possibility of fabricating high performance printed memory elements. A significant effort was also devoted to the development of basic memory/sensor systems entirely fabricated on plastic substrates. The suitability of organic non-volatile memory devices for the detection and the storage of external parameters was demonstrated. The results definitely demonstrated the feasibility of the proposed technology for the fabrication of systems including organic memories for their final application in different industrial processes, including e-textile and smart packaging.
As regards transistor memory devices, highly flexible Organic Field-Effect Transistor (OFET)-based memory elements with excellent mechanical stability and high retention time were developed. As main innovation with respect to the state of the art, low voltage operation of the OFET-based memory was investigated. Such an activity was also related to the development of reliable measurement procedures
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Marron, Dominique. "Etude des transistors à grille flottante et application à la conception d'une mémoire reconfigurable intégrée sur tranche." Grenoble 1, 1989. http://www.theses.fr/1989GRE10080.
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Afin d'accroitre la complexite des composants electroniques, leur architecture utilise des elements redondants. On pallie ainsi les problemes de rendements. Cette these traite d'un element de reconfiguration, le transistor a grille flottante, et de sa programmation par un faisceau d'electrons. Les conditions de programmation, la tenue dans le temps de la charge deposee ainsi que les problemes pratiques rencontres sont etudies. Ce transistor est ensuite utilise dans la conception d'une memoire sram de 4. 5 mbit reconfigurable integree sur une tranche d=100. Les contraintes pratiques et l'architecture sont exposees de meme que la partie realisation et test. Cette etude est en fait une etude de faisabilite pour des circuits de type wsi industriels
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Couto, Andre Luis do. "Caracterização de memorias analogicas implementadas com transistores MOS floating gate." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260078.
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Orientador: Carlos Alberto dos Reis FilhoDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-07T11:14:24Z (GMT). No. of bitstreams: 1 Couto_AndreLuisdo_M.pdf: 2940356 bytes, checksum: 959908541a3bc46b7b7035eb035de186 (MD5) Previous issue date: 2005
Resumo: A integração de memórias e circuitos analógicos em um mesmo die oferece diversas vantagens: redução de espaço nas placas, maior confiabilidade, menor custo. Para tanto, prescindir-se de tecnologia específica à confecção de memórias e utilizar-se somente de tecnologia CMOS convencional é requisito para tal integração. Essa pode ser tanto mais eficiente quanto maior a capacidade de armazenagem de dados, ou seja, maior a densidade de informação. Para isso, memórias analógicas mostram-se bem mais adequadas, posto que em uma só célula (um ou dois transistores) podem ser armazenados dados que precisariam de diversas células de memórias digitais e, portanto, de maior área. Neste trabalho, transistores MOS com porta flutuante mostraram-se viáveis de serem confeccionados e resultados de caracterização como tipos de programação, retenção de dados e endurance foram obtidos. O trabalho apresenta as principais características dos FGMOS (Floating Gate MOS) e presta-se como referência à futuros trabalhos na área
Abstract:Monolithic integration of memories and analog circuits ,in the same die offers interesting advantages like: smaller application boards, higher robustness and mainly lower costs. Today, a profitable integration of these kind of circuit can only be possible using conventional CMOS technology, which allows efficiently extraordinary levels of integration. Thus, the possibility of integrating analog memories looks more suitable since one single cell (usually use one or two transistors) serves for storing the same data stored by few digital memory cells, therefore, they requiring less area. In this work, it was implemented different memory cells together with few devices using floating gate MOS transistors and manufactured by a conventional CMOS technology. Differemt sort of programrning', data retention, and endurance were characterized as well as the main characteristics of the FGMOS (Floating Gate MOS) were obtained. The results of their characterization reveal that is possible to make and' to program fIoating gate MOSFETS analog memories and must serve as starting-point and reference for new academic studies
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
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Cheong, Kuan Yew, and n/a. "Silicon Carbide as the Nonvolatile-Dynamic-Memory Material." Griffith University. School of Microelectronic Engineering, 2004. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050115.101233.
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This thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1][7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metaloxidesemiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10][15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridationoxidationnitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitancetransient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiCSiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiCSiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10][16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metaloxide semiconductor fieldeffecttransistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.
Books on the topic "Memory transistors"
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Vagts, Christopher Bryan. A single-transistor memory cell and sense amplifier for a gallium arsenide dynamic random access memory. Monterey, Calif: Naval Postgraduate School, 1992.
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Maeda, Shigenobu. Teishōhi denryoku kōsoku MOSFET gijutsu: Takesshō shirikon TFT fukagata SRAM to SOI debaisu. Tōkyō: Sipec, 2002.
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Gang, Yung-jin. Ultra low voltage DRAM current sense amplifier with body bias techniques. 1998.
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Huster, Carl R. A parallel/vector Monte Carlo MESFET model for shared memory machines. 1992.
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Vuillaume, D. Molecular electronics based on self-assembled monolayers. Edited by A. V. Narlikar and Y. Y. Fu. Oxford University Press, 2017. http://dx.doi.org/10.1093/oxfordhb/9780199533060.013.9.
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This article considers molecular electronics based on self-assembled monolayers. It begins with a brief overview of the nanofabrication of molecular devices, followed by a discussion of the electronic properties of several basic devices, from simple molecules such as molecular tunnel junctions and molecular semiconducting wires, to more complex ones such as molecular rectifying diodes. It also describes molecular switches and memories, focusing on three approaches called ‘conformational memory’, ‘charge-based memory’ and ‘RTD-based memory’ (RTD is resonant tunnelling diode). It shows that memory can be implemented from resonant tunnelling diodes following cell architecture already used for semiconductor devices. The article concludes with a review of molecular transistors.
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Launay, Jean-Pierre, and Michel Verdaguer. The mastered electron: molecular electronics and spintronics, molecular machines. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198814597.003.0005.
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After a historical account of the evolution which led to the concept of Molecular Electronics, the “Hybrid Molecular Electronics” approach (that is, molecules connected to nanosized metallic electrodes) is discussed. The different types of transport (one-step, two-step with different forms of tunnelling) are described, including the case where the molecule is paramagnetic (Kondo resonance). Several molecular achievements are presented: wires, diodes, memory cells, field-effect transistors, switches, using molecules, but also carbon nanotubes. A spin-off result is the possibility of imaging Molecular Orbitals. The emerging field of molecular spintronics is presented. Besides hybrid devices, examples are given of electronic functionalities using ensembles of molecules, either in solution (logical functions) or in the solid state (memory elements). The relation with the domain of Quantum Computing is presented, including the particular domain of Quantum Hamiltonian Computing. The chapter finishes by an introduction to molecular machines, with the problem of the directional control of their motion.
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Forrest, Stephen R. Organic Electronics. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198529729.001.0001.
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Organic electronics is a platform for very low cost and high performance optoelectronic and electronic devices that cover large areas, are lightweight, and can be both flexible and conformable to irregularly shaped surfaces such as foldable smart phones. Organics are at the core of the global organic light emitting device (OLED) display industry, and also having use in efficient lighting sources, solar cells, and thin film transistors useful in medical and a range of other sensing, memory and logic applications. This book introduces the theoretical foundations and practical realization of devices in organic electronics. It is a product of both one and two semester courses that have been taught over a period of more than two decades. The target audiences are students at all levels of graduate studies, highly motivated senior undergraduates, and practicing engineers and scientists. The book is divided into two sections. Part I, Foundations, lays down the fundamental principles of the field of organic electronics. It is assumed that the reader has an elementary knowledge of quantum mechanics, and electricity and magnetism. Background knowledge of organic chemistry is not required. Part II, Applications, focuses on organic electronic devices. It begins with a discussion of organic thin film deposition and patterning, followed by chapters on organic light emitters, detectors, and thin film transistors. The last chapter describes several devices and phenomena that are not covered in the previous chapters, since they lie outside of the current mainstream of the field, but are nevertheless important.
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Advanced Technologies for Next Generation Integrated Circuits. Institution of Engineering & Technology, 2020.
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Launay, Jean-Pierre, and Michel Verdaguer. Electrons in Molecules. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198814597.001.0001.
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The book treats in a unified way electronic properties of molecules (magnetic, electrical, photophysical), culminating with the mastering of electrons, i.e. molecular electronics and spintronics and molecular machines. Chapter 1 recalls basic concepts. Chapter 2 describes the magnetic properties due to localized electrons. This includes phenomena such as spin cross-over, exchange interaction from dihydrogen to extended molecular magnetic systems, and magnetic anisotropy with single-molecule magnets. Chapter 3 is devoted to the electrical properties due to moving electrons. One considers first electron transfer in discrete molecular systems, in particular in mixed valence compounds. Then, extended molecular solids, in particular molecular conductors, are described by band theory. Special attention is paid to structural distortions (Peierls instability) and interelectronic repulsions in narrow-band systems. Chapter 4 treats photophysical properties, mainly electron transfer in the excited state and its applications to photodiodes, organic light emitting diodes, photovoltaic cells and water photolysis. Energy transfer is also treated. Photomagnetism (how a photonic excitation modifies magnetic properties) is introduced. Finally, Chapter 5 combines the previous knowledge for three advanced subjects: first molecular electronics in its hybrid form (molecules connected to electrodes acting as wires, diodes, memory elements, field-effect transistors) or in the quantum computation approach. Then, molecular spintronics, using, besides the charge, the spin of the electron. Finally the theme of molecular machines is presented, with the problem of the directionality control of their motion.
Book chapters on the topic "Memory transistors"
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Julien, Levisse Alexandre Sébastien, Xifan Tang, and Pierre-Emmanuel Gaillardon. "Innovative Memory Architectures Using Functionality Enhanced Devices." In Emerging Computing: From Devices to Systems, 47–83. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7487-7_3.
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AbstractSince the introduction of the transistor, the semiconductor industry has always been able to propose an increasingly higher level of circuit performance while keeping cost constant by scaling the transistor’s area. This scaling process (named Moore’s law) has been followed since the 80s. However, it has been facing new constraints and challenges since 2012. Standard sub-30nm bulk CMOS technologies cannot provide sufficient performance while remaining industrially profitable. Thereby, various solutions, such as FinFETs (Auth et al. 2012) or Fully Depleted Silicon On Insulator (FDSOI) (Faynot et al. 2010) transistors have therefore been proposed. All these solutions enabled Moore’s law scaling to continue. However, when approaching sub-10nm technology nodes, the story starts again. Again, process costs and electrical issues reduce the profitability of such solutions, and new technologies such as Gate-All-Around (GAA) (Sacchetto et al. 2009) transistors are seen as future FinFET replacement candidates.
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Song, Young Suh, Youngjae Song, T. S. Arun Samuel, P. Vimala, Shubham Tayal, Ritam Dutta, Chandan Kumar Pandey, Abhishek Kumar Upadhyay, Ilho Myeong, and Shiromani Balmukund Rahi. "TFET-based Memory Cell Design with Top-Down Approach." In Tunneling Field Effect Transistors, 223–34. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003327035-12.
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Britavska, O., S. Zyryn, and I. Tolkach. "Nanoparticles in Gate Dielectric of Memory Transistors." In NATO Science for Peace and Security Series B: Physics and Biophysics, 339–44. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-4119-5_31.
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Tokumitsu, Eisuke. "Oxide-Channel Ferroelectric-Gate Thin Film Transistors with Nonvolatile Memory Function." In Topics in Applied Physics, 75–88. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-024-0841-6_4.
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Tokumitsu, Eisuke. "Oxide-Channel Ferroelectric-Gate Thin-Film Transistors with Nonvolatile Memory Function." In Topics in Applied Physics, 111–24. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1212-4_6.
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Das, Debaprasad, Avisek Sinha Roy, and Hafizur Rahaman. "Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors." In Progress in VLSI Design and Test, 233–42. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31494-0_27.
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Park, Byung-Eun. "Non-volatile Ferroelectric Memory Transistors Using PVDF and P(VDF-TrFE) Thin Films." In Topics in Applied Physics, 141–55. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-024-0841-6_7.
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Lu, Xubing. "High-k Dielectrics in Ferroelectric Gate Field Effect Transistors for Nonvolatile Memory Applications." In High-k Gate Dielectrics for CMOS Technology, 471–99. Weinheim, Germany: Wiley-VCH Verlag GmbH & Co. KGaA, 2012. http://dx.doi.org/10.1002/9783527646340.ch15.
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Jadon, Atibhi, and Shyam Akashe. "Memristive Power Optimization of Non-volatile Seven Transistors Static Random Access Memory Cell." In Springer Proceedings in Physics, 245–53. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2367-2_31.
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Li, Yiming, Chih-Hong Hwang, and Shao-Ming Yu. "Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors." In Computational Science – ICCS 2007, 227–34. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-72590-9_33.
Full textConference papers on the topic "Memory transistors"
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Ruprecht, Michael W., Shengmin Wen, and Rolf-P. Vollertsen. "Sample Preparation for Vertical Transistors in DRAM." In ISTFA 2002. ASM International, 2002. http://dx.doi.org/10.31399/asm.cp.istfa2002p0307.
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Abstract This paper describes a newly developed preparation technique for vertical transistors in DRAM. The recently developed concept of DRAM cells combining a deep trench storage capacitor and a vertical access transistor promises a significant reduction in cell size. In the vertical transistor concept two gates are used to access one storage cell, which creates a challenge for the analysis of gate oxide fails. A gate oxide breakdown is determined and localized in the memory array by electrical probing and photoemission microscopy. The preparation technique combines focused ion beam (FIB) milling and selective wet chemical etching to expose both gates of the transistor simultaneously. Gate oxide pinholes are decorated by the wet etch to allow efficient inspection in a secondary electron microscope (SEM).
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Fakher, S. J., D. Ashall, and M. F. Mabrook. "Low-voltage organic memory transistors." In 2011 IEEE 11th International Conference on Nanotechnology (IEEE-NANO). IEEE, 2011. http://dx.doi.org/10.1109/nano.2011.6144538.
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Chen, Yan-Ru, Chen-Jun Wu, K.-P. Chang, Chih-Ping Chen, Tzu-Hsuan Hsu, Yi-Hsuan Hsiao, F.-N. Tsai, et al. "Trapping-free string select transistors and ground select transistors for Vg-type 3D NAND Flash memory." In 2014 IEEE 6th International Memory Workshop (IMW). IEEE, 2014. http://dx.doi.org/10.1109/imw.2014.6849380.
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Jung, Ilwoo, Byoungdeok Choi, Bonggu Sung, Daejung Kim, Ilgweon Kim, Hyoungsub Kim, and Gyoyoung Jin. "Body Effect Measurement in DRAM Cell Transistor Using Memory Test System." In ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0085.
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Abstract Body effect is the key characteristic of DRAM cell transistor. Conventional method uses a TEG structure for body effect measurement. But this measurement is not accurate, because TEG structure has only several transistors and it is located outside of the DRAM die. This paper suggests a viable method for measuring DRAM cell transistor body effect. It uses a memory test system for fast, massive, nondestructive measurement. Newly developed method can measure 100,000 DRAM cell body effects in two minute, without sample damage. The test gives one median value and 100,000 individual values of body effects. Median value of measured body effects is equal to the TEG body effect. An individual DRAM cell body effect has a correlation with the fin height.
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Xia, Jiangnan, and Yuanyuan Hu. "Organic ferroelectric non-volatile memory transistors." In 2022 IEEE International Flexible Electronics Technology Conference (IFETC). IEEE, 2022. http://dx.doi.org/10.1109/ifetc53656.2022.9948506.
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Li, Shuo, David Guérin, and Kamal Lmimouni. "Flexible organic nano-floating memory with multilevel charge storage by combing charge store in nanoparticles and electrets (Conference Presentation)." In Organic Field-Effect Transistors XVII, edited by Oana D. Jurchescu and Iain McCulloch. SPIE, 2018. http://dx.doi.org/10.1117/12.2321087.
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Ersen, A., J. Wang, V. Ozguz, S. Esener, and S. H. Lee. "XOR and 1-bit memory cell arrays fabricated in laser recrystallized silicon/PLZT." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1991. http://dx.doi.org/10.1364/oam.1991.tht4.
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We report on the latest development in the integration of thin film silicon with PLZT for smart spatial light modulators (S-SLMs). PLZT is an electrooptic (EO) material that satisfies most of the requirements for a S-SLM. It exhibits a large quadratic EO effect requiring relatively small modulation voltages. Also modulation speeds as high as 180 MHz has been demonstrated in our laboratories. One way of integrating this material with silicon technology is to deposit polysilicon on PLZT wafers and then recrystallize silicon for subsequent device fabrication using a scanning laser beam. The major problem was the high leakage current of fabricated transistors due to grain boundaries and crystal imperfection after the laser recrystallization process. As a result of these defects, the transistor yield was limited to 20-30%, preventing us from fabricating large arrays. We have now developed our process to the point where the yield has become 85%. Based on these improvements, 8×8 XOR and 1-bit memory cells with up to ten transistors per unit cell have been fabricated.
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Toan, D. T., H. Sakai, T. Matsushima, and H. Murata. "Fullerene Memory Transistors with a Chargeable Polymer." In 2011 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2011. http://dx.doi.org/10.7567/ssdm.2011.p-10-19l.
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