Journal articles: 'Memory transistor'

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Xie, Fangqing, Maryna N. Kavalenka, Moritz Röger, Daniel Albrecht, Hendrik Hölscher, Jürgen Leuthold, and Thomas Schimmel. "Copper atomic-scale transistors." Beilstein Journal of Nanotechnology 8 (March 1, 2017): 530–38. http://dx.doi.org/10.3762/bjnano.8.57.

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We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

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Choi, Young Jin, Jihyun Kim, Min Je Kim, Hwa Sook Ryu, Han Young Woo, Jeong Ho Cho, and Joohoon Kang. "Hysteresis Behavior of the Donor–Acceptor-Type Ambipolar Semiconductor for Non-Volatile Memory Applications." Micromachines 12, no. 3 (March 12, 2021): 301. http://dx.doi.org/10.3390/mi12030301.

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Donor–acceptor-type organic semiconductor molecules are of great interest for potential organic field-effect transistor applications with ambipolar characteristics and non-volatile memory applications. Here, we synthesized an organic semiconductor, PDPPT-TT, and directly utilized it in both field-effect transistor and non-volatile memory applications. As-synthesized PDPPT-TT was simply spin-coated on a substrate for the device fabrications. The PDPPT-TT based field-effect transistor showed ambipolar electrical transfer characteristics. Furthermore, a gold nanoparticle-embedded dielectric layer was used as a charge trapping layer for the non-volatile memory device applications. The non-volatile memory device showed clear memory window formation as applied gate voltage increases, and electrical stability was evaluated by performing retention and cycling tests. In summary, we demonstrate that a donor–acceptor-type organic semiconductor molecule shows great potential for ambipolar field-effect transistors and non-volatile memory device applications as an important class of materials.

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Kim, Woojo, Jimin Kwon, and Sungjune Jung. "3D Integration of Flexible and Printed Electronics: Integrated Circuits, Memories, and Sensors." Journal of Flexible and Printed Electronics 2, no. 2 (December 2023): 199–210. http://dx.doi.org/10.56767/jfpe.2023.2.2.199.

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Printing technologies have received a lot of attention and expectations for producing flexible and wearable electronics. However, the low transistor density of the printed devices has been a major obstacle to commercialization. In this review, a three-dimensional (3D) integration of organic flexible and printed electronics is described. First, layout-to-bitmap conversion and design rules for printed transistors, arrays, and integrated circuits are introduced. Then, printed 3D transistors, digital integrated circuits, and memories are described. Finally, 3D integration of printed active-matrix arrays and sensors is highlighted. This approach is a breakthrough technology that not only reduces the area occupied by a single transistor, memory, and sensor, but also increases the efficiency of routing, effectively reducing the area of the entire devices. In addition, monolithic 3D integration through the printing can stack transistor, memory, and sensor by simply repeating the additive process.

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Kim, Ji-Hun, Hyeon-Jun Kim, Ki-Jun Kim, Tae-Hun Shim, Jin-Pyo Hong, and Jea-gun Park. "3-Terminal Igzo FET Based 2T0C DRAM Combined Bit-Line Structure." ECS Meeting Abstracts MA2023-02, no. 30 (December 22, 2023): 1561. http://dx.doi.org/10.1149/ma2023-02301561mtgabs.

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The IGZO (InGaZnO)-based two-transistor zero-capacitor(2T0C) DRAM has attracted much attention as an alternative memory to overcome the scale-down limit of current 1T1C DRAM due to its low power consumption and monolithic 3D stacking capability. In particular, its low power consumption and the feasibility of low temperature process make it highly implementable for 3D DRAM. For operating the 2T0C DRAM, four metal lines are necessary, i.e., write word line and write bit line (WBL) for operating write transistor (WTR), and read word line and read bit line (RBL) for operating read transistor (RTR). In this study, we propose a 3-terminal 2T0C DRAM to enhance its memory characteristics, where RBL was combined with WBL, enabling 2T0C memory operation with only three metal lines as shown in Fig. 1(b). In addition, we investigated the dependency of retenetion time of the proposed 2T0C DRAM on channel length. In particular we evaluated the dependency of the sneak current of 2T0C DRAM on off-current of transistor. For the fabrication of 3-terminal IGZO 2T0C DRAM, a top gate IGZO transistor was fabricated using RF sputtering and two transistors were connected by storage node and bit line bridge as shown in Fig. 1(d).The storage node was formed by connecting the gate of RTR to drain of WTR. And source electrodes of both transistors were coupled. To determine the voltage values for memory operation, the transfer curve of each transistor was characterized and the threshold voltages for both RTR and WTR were around 1 V. The write and read voltages were set to 3 and 2 V, respectively. The retention time was measured by performing periodic read operations after writing and measuring the RTR currents. In addition, the retention time of transistors for varying channel length and gate capacitance was characterized. The retention time was defined as the time to be taken for decreasing the currents by 90 %. Furthermore, the disturbance of 2T0C DRAM with 2x2 array structure was investigated. The RTR currents of selected cells were measured depending on the memory state of adjacent cells. It was found that the retention times of transistors with 10- and 100-um RTR channel lengths were approximately 15 and 30 seconds, respectively. It was observed that the memory state was not changed from “0“ to “1“ by disturbant currents, but, RTR currents of “0“ state cell increased slightly when an adjacent cell was turned on. However, as shown in Fig.1(i) and (j), when off-currents of transistor of 2T0C DRAM decreased from 20 nA to 200 pA, it was confirmed the sneak current of 2T0C decreased. Finally, several technical apporaches how to suppress the disturbant currents will be presented in detail. Acknowledgement This research was supported by BrainKorea21 Four. Figure 1

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Al-shawi, Amjad, Maysoon Alias, Paul Sayers, and Mohammed Fadhil Mabrook. "Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors." Micromachines 10, no. 10 (September 25, 2019): 643. http://dx.doi.org/10.3390/mi10100643.

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To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts in the threshold voltage of the transfer characteristics as well as the hysteresis in the output characteristics were attributed to the charging and discharging of the floating gate. The counter-clockwise direction of hysteresis indicates that the process of charging and discharging the floating gate take place through the semiconductor/insulator interface. A clear shift in the threshold voltage was observed when different voltage pulses were applied to the gate. The non-volatile behaviour of the memory transistors was investigated in terms of charge retention. The memory transistors exhibited a large memory window (~30 V), and high charge density of (9.15 × 1011 cm−2).

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Brtník, Bohumil. "Assembling a Formula for Current Transferring by Using a Summary Graph and Transformation Graphs." Journal of Electrical Engineering 64, no. 5 (September 1, 2013): 334–36. http://dx.doi.org/10.2478/jee-2013-0050.

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Abstract This paper deals with the symbolic solution of the switched current circuits. As is described, the full graph method of the solution can be used for finding relationships expressing current transfer, too. The summa MC-graph is constructed using two-graphs method in two-phase switching. By comparing the matrix form with results of the Mason’s formula are derived relations for current transfers in all phases. There are discussed various options described transistor memory cells - with loss and lossless transistors and normal transistor current mirror. Evaluation of the graph is simplified if we consider the lossless transistors or if the y21 -parameter of one transistor is alpha multiple of second ones.

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Grudanov, Oleksandr. "Stability Parameters of Register File Bit Cell with Low Power Consumption Priority." Electronics and Control Systems 3, no. 77 (September 27, 2023): 40–46. http://dx.doi.org/10.18372/1990-5548.77.17963.

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This research is dedicated to a transistor sizing method of an 8-transistor register file static random access memory bit cell aiming to create two-port register files and two-port static random access memory with reduced supply voltage to reduce power consumption. This method can also be applied to 6-transistor single-port static random access memory bit cells. The method is based on the analysis of butterfly curves and the search for such values of the sizes of transistors and margin of their threshold voltages, in which, for a given critical minimal supply voltage, the condition for the existence of one intersection and one touch of its curves is achieved for the butterfly curves. The obtained samples of the register files bit cell in silicon and its critical voltage were compared to the results of circuit simulation in the write and read mode depending on the supply voltage. Experimental register files chip samples were successfully tested in silicon at a voltage of 0.75 V.

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Fuller, Elliot J., Scott T. Keene, Armantas Melianas, Zhongrui Wang, Sapan Agarwal, Yiyang Li, Yaakov Tuchman, et al. "Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing." Science 364, no. 6440 (April 25, 2019): 570–74. http://dx.doi.org/10.1126/science.aaw5581.

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Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and readout of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10-nanoampere read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array based on a polymer redox transistor connected to a conductive-bridge memory (CBM). Selective and linear programming of a redox transistor array is executed in parallel by overcoming the bridging threshold voltage of the CBMs. Synaptic weight readout with currents <10 nanoamperes is achieved by diluting the conductive polymer with an insulator to decrease the conductance. The redox transistors endure >1 billion write-read operations and support >1-megahertz write-read frequencies.

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Srinivasarao, B. N., and K. Chandrabhushana Rao. "Design and Analysis of Area Efficient 128 Bytes SRAM Architecture." Journal of VLSI Design and Signal Processing 8, no. 1 (March 30, 2022): 19–26. http://dx.doi.org/10.46610/jovdsp.2022.v08i01.004.

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SRAM Memory architecture design and implementation is a challenging task for memory applications. Practical architecture was developed and used successfully using various double ended SRAM cells like 6 and 4 transistors. But for single ended SRAM cell like 5 transistors or any other number of transistors there is no specific architecture for practical applications. Conventional SRAM architecture has SRAM cell, write driver circuit along with bit inverter, Pre-charge circuit and sense amplifier which consists more, number of transistors required to handle single bit storage. In this paper SRAM architecture is implemented for single ended SRAM cell that is three transistor SRAM cell. Area is reduced by 60% with average power consumption 3.05µW and speed with 20.87GHz. Finally,28 bytes memory structure is implemented and verified its operation.

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Seo, Yeongkyo, and Kon-Woo Kwon. "Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application." Electronics 12, no. 20 (October 12, 2023): 4223. http://dx.doi.org/10.3390/electronics12204223.

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This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin.

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Gul, Waqas, Maitham Shams, and Dhamin Al-Khalili. "SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview." Micromachines 13, no. 8 (August 17, 2022): 1332. http://dx.doi.org/10.3390/mi13081332.

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Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell’s stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell’s reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions.

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Li, Tingkai, Sheng Teng Hsu, Bruce D. Ulrich, and David R. Evans. "Semiconductive metal oxide ferroelectric memory transistor: A long-retention nonvolatile memory transistor." Applied Physics Letters 86, no. 12 (March 21, 2005): 123513. http://dx.doi.org/10.1063/1.1886252.

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Cheremisinov, D. I., and L. D. Cheremisinova. "Logical gates recognition in a flat transistor circuit." Informatics 18, no. 4 (December 31, 2021): 96–107. http://dx.doi.org/10.37661/1816-0301-2021-18-4-96-107.

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O b j e c t i v e s. With the increasing complexity of verification and simulation of modern VLSI, containing hundreds of millions of transistors, the means of extracting the hierarchical description at the level of logical elements froma flat description of circuits at the transistor level are becoming the main tools for computer-aided design and verification. Decompilation tools for transistor circuits can not only significantly reduce the time to perform VLSI topology check, but also provide the basis for generating test cases, logical reengineering of integrated circuits and reverse engineering to detect untrusted attachments.The objective of the work is to solve the problem of extracting the structure of the functional level from a flat circuit of the transistor level by recognizing in it subcircuits that implement logical elements.M e t h o d s. Graph based methods are proposed for solving some key problems arising at the stage of structural recognition of CMOS gates in a transistor circuit: partitioning a graph into connectivity components corresponding to transistor subcircuits; recognition of subcircuits that are logical elements, and functions implemented by them; forming a library of recognized gates and constructing two-level transistor circuit. The original flat and resulting two-level transistor circuits are presented in SPICE format.Re s u l t s. The proposed methods are implemented in C++ as a part of a transistor circuit decompilation programfor the case without any predetermined cell library. All steps of the proposed methods of structural CMOS gates recognition are performed in a linear time from the number of transistors in the initial circuit.Co n c l u s i o n. The decompilation program has been tested on practical transistor-level circuits. Experiments indicate that the present tool is fast enough to process circuits with more than a hundred thousand transistors in a few minutes on a personal computer. Currently, the authors are developing methods for recognizing more complex elements in a transistor circuit, such as memory elements.

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Qi, Hongxia, and Ying Wu. "Synaptic plasticity of TiO2 nanowire transistor." Microelectronics International 37, no. 3 (January 16, 2020): 125–30. http://dx.doi.org/10.1108/mi-08-2019-0053.

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Purpose The emulation of synapses is essential to neuromorphic computing systems. Despite remarkable progress has been made in the two-terminal device (memristor), three-terminal transistors evoke greater attention because of the controlled conductance between the source and drain. The purpose of this paper is to investigate the synaptic plasticity of the TiO2 nanowire transistor. Design/methodology/approach TiO2 nanowire transistor was assembled by dielectrophoresis, and the synaptic plasticity such as paired-pulse facilitation, learning behaviors and high-pass filter were studied. Findings Facilitation index decreases with the increasing pulse interval. A bigger response current is obtained at the pulses with higher amplitude and smaller intervals, which is similar to the consolidated memory at the deeply and frequently learning. The increased current at the higher stimulus frequency demonstrates a promising application in the high-pass filter. Originality/value TiO2 nanowire transistors possess broad application prospects in the future neural network.

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Xie, Dongyu, Xiaoci Liang, Di Geng, Qian Wu, and Chuan Liu. "An Enhanced Synaptic Plasticity of Electrolyte-Gated Transistors through the Tungsten Doping of an Oxide Semiconductor." Electronics 13, no. 8 (April 13, 2024): 1485. http://dx.doi.org/10.3390/electronics13081485.

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Oxide electrolyte-gated transistors have shown the ability to emulate various synaptic functions, but they still require a high gate voltage to form long-term plasticity. Here, we studied electrolyte-gated transistors based on InOx with tungsten doping (W-InOx). When the tungsten-to-indium ratio increased from 0% to 7.6%, the memory window of the transfer curve increased from 0.2 V to 2 V over a small sweep range of −2 V to 2.5 V. Under 50 pulses with a duty cycle of 2%, the conductance of the transistor increased from 40-fold to 30,000-fold. Furthermore, the W-InOx transistor exhibited improved paired pulse facilitation and successfully passed the Pavlovian test after training. The formation of WO3 within InOx and its ion intercalation into the channel may account for the enhanced synaptic plasticity.

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Fazio, Al. "Flash Memory Scaling." MRS Bulletin 29, no. 11 (November 2004): 814–17. http://dx.doi.org/10.1557/mrs2004.233.

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AbstractIn order to meet technology scaling in the field of solid-state memory and data storage, the mainstream transistor-based flash technologies will start evolving to incorporate material and structural innovations. Dielectric scaling in nonvolatile memories is approaching the point where new approaches will be required to meet the scaling requirements while simultaneously meeting the reliability and performance requirements of future products. High-dielectric-constant materials are being explored as possible candidates to replace the traditional SiO2 and ONO (oxide/nitride/oxide) films used today in memory cells. Likewise, planar-based memory cell scaling is approaching the point where scaling constraints force exploration of new materials and nonplanar, three-dimensional scaling alternatives. This article will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor floating-gate-based nonvolatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor-based flash memory cells can scale through at least the end of the decade (2010) using techniques that are available today or projected to be available in the near future. More complex, structural innovations will be required to achieve further scaling.

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Hellkamp, Daniel, and Kundan Nepal. "True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors." Journal of Circuits, Systems and Computers 28, no. 05 (May 2019): 1950085. http://dx.doi.org/10.1142/s0218126619500853.

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Carbon nanotube-based transistors (CNTFETs) have been shown to exhibit ambipolar field-effect transistor behavior, allowing circuit designers to easily choose between [Formula: see text]- and [Formula: see text]-conduction channels by applying correct voltages at a polarity gate. In this paper, we explore this ambipolar behavior of the CNTFET to design both binary and ternary content addressable memory (AM) cells. Using SPICE simulation, we show the designs of a traditional ternary CAM (TCAM) and a true three-valued TCAM (T3-CAM) functionality of the proposed cells and show that the ambipolar design can lead to a savings of up to 31% in terms of transistor count over a traditional design. We also explore issues related to matchline leakage, cell stability and design in the presence of metallic tubes.

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Lee, Dain, Yongsuk Choi, Euyheon Hwang, Moon Sung Kang, Seungwoo Lee, and Jeong Ho Cho. "Black phosphorus nonvolatile transistor memory." Nanoscale 8, no. 17 (2016): 9107–12. http://dx.doi.org/10.1039/c6nr02078j.

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Fuhrer, M. S., B. M. Kim, T. Dürkop, and T. Brintlinger. "High-Mobility Nanotube Transistor Memory." Nano Letters 2, no. 7 (July 2002): 755–59. http://dx.doi.org/10.1021/nl025577o.

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Kim, Soo-Jin, and Jang-Sik Lee. "Flexible Organic Transistor Memory Devices." Nano Letters 10, no. 8 (August 11, 2010): 2884–90. http://dx.doi.org/10.1021/nl1009662.

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Ni, Yao, Yongfei Wang, and Wentao Xu. "Flexible Transistor‐Structured Memory: Recent Process of Flexible Transistor‐Structured Memory (Small 9/2021)." Small 17, no. 9 (March 2021): 2170037. http://dx.doi.org/10.1002/smll.202170037.

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Boampong, Amos Amoako, Jae-Hyeok Cho, Yoonseuk Choi, and Min-Hoi Kim. "Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure." Journal of Nanoscience and Nanotechnology 21, no. 3 (March 1, 2021): 1766–71. http://dx.doi.org/10.1166/jnn.2021.18923.

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We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO. The voltage applied to the counter bottom-gate electrode causes variations in the turn-on voltage position, which controlled the memory on- and off-current in retention characteristics. Specifically, due to the full depletion of semiconductor by the high negative counter gate bias, the memory off-current in reading operation is dramatically reduced by 104. The application of a high negative counter field to the dual-gate solution-processed ferroelectric memory gives a high memory on- and off-current ratio useful for the production of high performance multi-bit memory devices.

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Jin, Risheng, Keli Shi, Beibei Qiu, and Shihua Huang. "Photoinduced-reset and multilevel storage transistor memories based on antimony-doped tin oxide nanoparticles floating gate." Nanotechnology 33, no. 2 (October 22, 2021): 025201. http://dx.doi.org/10.1088/1361-6528/ac2dc5.

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Abstract Recently, antimony-doped tin oxide nanoparticles (ATO NPs) have been widely used in the fields of electronics, photonics, photovoltaics, sensing, and other fields because of their good conductivity, easy synthesis, excellent chemical stability, high mechanical strength, good dispersion and low cost. Herein, for the first time, a novel nonvolatile transistor memory device is fabricated using ATO NPs as charge trapping sites to enhance the memory performance. The resulting organic nano-floating gate memory (NFGM) device exhibits outstanding memory properties, including tremendous memory window (∼85 V), superhigh memory on/off ratio (∼109), long data retention (over 10 years) and eminent multilevel storage behavior, which are among the optimal performances in NFGM devices based on organic field effect transistors. Additionally, the device displays photoinduced-reset characteristic with low energy consumption erasing operation. This study provides novel avenues for the manufacture of simple and low-cost data storage devices with outstanding memory performance, multilevel storage behavior and suitability as platforms for integrated circuits.

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Sedaghat, Mahsa, and Mahdi Salimi. "Evaluation and Comparison of CMOS logic circuits with CNTFET." Journal of Research in Science, Engineering and Technology 3, no. 04 (September 13, 2019): 1–9. http://dx.doi.org/10.24200/jrset.vol3iss04pp1-9.

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In this paper, a comparison between CMOS and MOSFET base circuits HSPICE is done with software. 0.13 CMOS transistor model for simulation and CNTFET Model of Stanford University used. In simulations amounts of power, circuit delay and PDP is calculated and these values were compared at the end. And tried to CNTFET applications of transistors in circuit design, including memory and logic circuits Ternary be expressed.

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Shim, Hyunseok, Kyoseung Sim, Faheem Ershad, Pinyi Yang, Anish Thukral, Zhoulyu Rao, Hae-Jin Kim, et al. "Stretchable elastic synaptic transistors for neurologically integrated soft engineering systems." Science Advances 5, no. 10 (October 2019): eaax4961. http://dx.doi.org/10.1126/sciadv.aax4961.

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Artificial synaptic devices that can be stretched similar to those appearing in soft-bodied animals, such as earthworms, could be seamlessly integrated onto soft machines toward enabled neurological functions. Here, we report a stretchable synaptic transistor fully based on elastomeric electronic materials, which exhibits a full set of synaptic characteristics. These characteristics retained even the rubbery synapse that is stretched by 50%. By implementing stretchable synaptic transistor with mechanoreceptor in an array format, we developed a deformable sensory skin, where the mechanoreceptors interface the external stimulations and generate presynaptic pulses and then the synaptic transistors render postsynaptic potentials. Furthermore, we demonstrated a soft adaptive neurorobot that is able to perform adaptive locomotion based on robotic memory in a programmable manner upon physically tapping the skin. Our rubbery synaptic transistor and neurologically integrated devices pave the way toward enabled neurological functions in soft machines and other applications.

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Shrivastava, Anurag, and Mohan Gupta. "Evaluation of the Core Processor Cache Memory Architecture's Performance." Journal of Futuristic Sciences and Applications 2, no. 1 (2019): 11–18. http://dx.doi.org/10.51976/jfsa.211903.

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In this study, memory architectures for single-bit caches are studied. Voltage differential sense amplifiers and charge transfer differential sense amplifiers are used to study a six-transistor static random-access memory. In a single-bit, six-transistor static random-access memory, it has been demonstrated that the voltage differential sensing amplifier uses the least power.

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Gudlavalleti, R. H., B. Saman, R. Mays, H. Salama, Evan Heller, J. Chandy, and F. Jain. "A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array." International Journal of High Speed Electronics and Systems 29, no. 01n04 (March 2020): 2040009. http://dx.doi.org/10.1142/s0129156420400091.

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Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

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Arimoto, Yoshihiro, and Hiroshi Ishiwara. "Current Status of Ferroelectric Random-Access Memory." MRS Bulletin 29, no. 11 (November 2004): 823–28. http://dx.doi.org/10.1557/mrs2004.235.

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AbstractThe current status of ferroelectric random-access memory (FeRAM) technology is reviewed in this article. Presented first is the status of conventional FeRAM, in which the memory cells are composed of ferroelectric capacitors to store the data and cell-selection transistors to access the selected capacitors. Discussed next are recent developments in the field. Pb(Zrx, Ti1–x)O3 (PZT) and SrBi2Ta2O9 (SBT) films are being used to produce 0.13 mμ and 0.18 μm FeRAM cells, respectively, with a stacked capacitor configuration; these cells are easily embedded into logic circuits. A new class of FeRAM called 6T4C—containing static RAM (SRAM) cells composed of six transistors (6T) and four ferroelectric capacitors (4C)—has been commercially produced. This type of FeRAM features a nondestructive readout operation, unlimited read/write cycling, and a fast access time of less than 10 ns. Lastly, the status of field-effect-transistor (FET)-type FeRAM is reviewed, emphasizing that the data retention time of a ferroelectric-gate FET has been improved to more than a month in recent studies.

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MATSUMOTO, KAZUHIKO. "ROOM-TEMPERATURE SINGLE ELECTRON DEVICES BY SCANNING PROBE PROCESS." International Journal of High Speed Electronics and Systems 10, no. 01 (March 2000): 83–91. http://dx.doi.org/10.1142/s0129156400000118.

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A single electron transistor (SET) and a single electron memory were fabricated using the improved pulse-mode AFM nano-oxidation process. A single electron transistor which works as an electrometer for detecting the potential of the memory node of the single electron memory showed clear Coulomb oscillation characteristics with the period of 2.1 V at room temperature. A single electron memory exhibited a hysteresis loop as the memory bias was scanned from 0 to 10 V and then back down to 0 V.

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Seon, Kim, Kim, and Jeon. "Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel." Electronics 8, no. 9 (September 4, 2019): 988. http://dx.doi.org/10.3390/electronics8090988.

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Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physics at the same time. In this work, we derived new analytical current-voltage model for GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain boundary effect. Based on the derived formula, the compact I-V model for various operating regions and threshold voltage was proposed for the first time. The proposed model was compared with the measured data and good agreements were observed.

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Kumari, Nibha, and Prof Vandana Niranjan. "Low-Power 6T SRAM Cell using 22nm CMOS Technology." Indian Journal of VLSI Design 2, no. 2 (September 30, 2022): 5–10. http://dx.doi.org/10.54105/ijvlsid.b1210.092222.

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Static Random-Access Memory (SRAM) occupies approximately 90% of total area on a chip due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell becomes a power-hungry block on a chip and it becomes more prominent at lower technologies from both dynamic and static perspective. Static power consumption is due to leakage current associated with the transistors that are off and dynamic power consumption is due to charging and discharging of the circuit capacitance. As gate length or channel length decreases gate oxide thickness also scales down. Scaling down of conventional transistor results in huge tunneling of electron from gate into channel leading to higher leakage power consumption. So, transistor with metal gate, high-k dielectric and strained-Si is used which shows better result in terms of low-power consumption, better performance with acceptable delay. Among various topologies of SRAM cell 6T is considered as a suitable choice for low power applications.

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Huang, Jing, Pengfei Tan, Fang Wang, and Bo Li. "Ferroelectric Memory Based on Topological Domain Structures: A Phase Field Simulation." Crystals 12, no. 6 (May 29, 2022): 786. http://dx.doi.org/10.3390/cryst12060786.

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The low storage density of ferroelectric thin film memory currently limits the further application of ferroelectric memory. Topologies based on controllable ferroelectric domain structures offer opportunities to develop microelectronic devices such as high-density memories. This study uses ferroelectric topology domains in a ferroelectric field-effect transistor (FeFET) structure for memory. The electrical behavior of FeFET and its flip properties under strain and electric fields are investigated using a phase-field model combined with the device equations of field-effect transistors. When the dimensionless electric field changes from −0.10 to 0.10, the memory window drops from 2.49 V to 0.6 V and the on-state current drops from 2.511 mA to 1.951 mA; the off-state current grows from 1.532 mA to 1.877 mA. External tensile stress increases the memory window and off-state current, while compressive stress decreases it. This study shows that a ferroelectric topology can be used as memory and could significantly increase the storage density of ferroelectric memory.

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Yin, Wan-Jun, Tao Wen, and Wei Zhang. "Design of Dynamic Random Access Memory Based on One Transistor One Diode Memory Cell." Journal of Nanoelectronics and Optoelectronics 16, no. 1 (January 1, 2021): 114–18. http://dx.doi.org/10.1166/jno.2021.2924.

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This paper presents the design analysis of Dynamic Random Access Memory (DRAM) with one transistor one diode (1T1D). The proposed structure consists of one transistor and one voltage controlled diode capacitor. The word and bit lines are connected with two voltage sources for the write operation. The source and drain of the NMOS is tied together to form the diode structure. The off-state leakage current is the main cause for the power dissipation of DRAM. Thus the improvement of power efficiency to the overall system is a critical task. The conventional DRAM cell contains one capacitor and one transistor. But the absence of capacitor in the proposed work is advantageous by means of compatibility, scalability, fabrication complexity, and cost. Tanner EDA working platform of 7 nm technology is used for the implementation of 1T1D DRAM cell in proposed work. This work achieve the power dissipation, read and write access time in the range of 2.647 mW, 0.04 μs and 0.021 μs respectively. Also, the parameter comparison is performed by changing the technologies from 10 nm to 20 nm for 1T1D DRAM cell design.

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Saman, Bander, P. Gogna, El-Sayed Hasaneen, J. Chandy, E. Heller, and F. C. Jain. "Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation." International Journal of High Speed Electronics and Systems 26, no. 03 (June 27, 2017): 1740009. http://dx.doi.org/10.1142/s0129156417400092.

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This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.

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Natarajamoorthy, Mathan, Jayashri Subbiah, Nurul Ezaila Alias, and Michael Loong Peng Tan. "Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design." Journal of Nanotechnology 2020 (April 30, 2020): 1–7. http://dx.doi.org/10.1155/2020/7608279.

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The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.

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Jang, Won Douk, Young Jun Yoon, Min Su Cho, Jun Hyeok Jung, Sang Ho Lee, Jaewon Jang, Jin-Hyuk Bae, and In Man Kang. "Design and Analysis of Metal-Oxide-Semiconductor Field-Effect Transistor-Based Capacitorless One-Transistor Embedded Dynamic Random-Access Memory with Double-Polysilicon Layer Using Grain Boundary for Hole Storage." Journal of Nanoscience and Nanotechnology 20, no. 11 (November 1, 2020): 6596–602. http://dx.doi.org/10.1166/jnn.2020.18767.

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In this work, a capacitorless one-transistor embedded dynamic random-access memory based on a metal-oxide-semiconductor field-effect transistor with a double-polysilicon layer structure has been proposed and investigated using technology computer-aided design simulation. By using the grain boundary for hole storage, a higher sensing margin of 4.35 /μA//μm is achieved compared to that without using the grain boundary. Furthermore, the proposed device achieves a superior retention time of 555.77 /μs, which is reasonable from the viewpoint of its application in embedded systems (>100 /μs), even at a high temperature of 358 K. For higher device reliability, the effect of the grain boundary on the capacitorless one-transistor embedded dynamic random-access memory is analyzed with different trap distributions. The proposed capacitorless one-transistor embedded dynamic random-access memory cell exhibited superior reliability in terms of retention time (>100 /μs).

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Rumberg, Brandon, Spencer Clites, Haifa Abulaiha, Alexander DiLello, and David Graham. "Continuous-Time Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Arrays." Journal of Low Power Electronics and Applications 11, no. 1 (January 13, 2021): 4. http://dx.doi.org/10.3390/jlpea11010004.

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Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well. Such programmable analog systems are often designed for battery-powered and resource-constrained applications, which require the memory cells to program quickly and with low infrastructural overhead. To meet these needs, we present a four-transistor analog floating-gate memory cell that offers both voltage and current outputs and has linear programming characteristics. Furthermore, we present a simple programming circuit that forces the memory cell to converge to targets with 13.0 bit resolution. Finally, we demonstrate how to use the FG memory cell and the programmer circuit in array configurations. We show how to program an array in either a serial or parallel fashion and demonstrate the effectiveness of the array programming with an application of a bandpass filter array.

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Wang, Peng-Fei, Xi Lin, Lei Liu, Qing-Qing Sun, Peng Zhou, Xiao-Yong Liu, Wei Liu, Yi Gong, and David Wei Zhang. "A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation." Science 341, no. 6146 (August 8, 2013): 640–43. http://dx.doi.org/10.1126/science.1240961.

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As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra–high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensity was observed when the transistor was exposed to light, so possible applications include image sensing with high density and performance.

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Qiu, Haiyang, Dandan Hao, Hui Li, Yepeng Shi, Yao Dong, Guoxia Liu, and Fukai Shan. "Transparent and biocompatible In₂O₃ artificial synapses with lactose–citric acid electrolyte for neuromorphic computing." Applied Physics Letters 121, no. 18 (October 31, 2022): 183301. http://dx.doi.org/10.1063/5.0124219.

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Electrolyte-gated synaptic transistors are promising for artificial neural morphological devices. However, few literatures have been reported regarding the manufacturing of electrolyte-gated synaptic transistors with low cost and biocompatible components. Here, the fully transparent synaptic transistors based on water-induced In2O3 thin films have been integrated by sol–gel method at low temperature, and lactose dissolved in citric acid solution is used as the gate electrolyte. The migration of the ions at the interface plays a crucial role in the potentiation and depression of the synaptic weight. In this work, the biological synaptic functions, including excitatory postsynaptic current, paired-pulse facilitation, high-pass filtering characteristics, short-term memory, and long-term memory, are mimicked. Meanwhile, based on the potentiation/depression behaviors of the synaptic transistor, a three-layer artificial neural network is applied for pattern recognition, and the recognition accuracy is as high as 94.6%. This study offers a possibility to realize fully transparent synaptic devices with biocompatible components at low temperature.

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Chiquet, Philippe, Jérémy Postel-Pellerin, Célia Tuninetti, Sarra Souiki-Figuigui, and Pascal Masson. "Enhancement of flash memory endurance using short pulsed program/erase signals." ACTA IMEKO 5, no. 4 (December 30, 2016): 29. http://dx.doi.org/10.21014/acta_imeko.v5i4.422.

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The present paper proposes to investigate the effect of short pulsed Program/Erase signals on the functioning of Flash memory transistors. Usually, electrical operations related to said devices involve the application of single long pulses to various terminals of the transistor to induce various tunneling effects allowing the variation of the floating gate charge. According to the literature, the oxide degradation occurring after a number of electrical operations, leading to loss of performance and reliability, can be reduced by replacing DC stress by AC stress or by reducing the time spent under polarization by the MOS-based devices. After a brief presentation of the functioning of the Flash memory transistors tested in this work, the experimental setup used to replace standard electric signals with short pulses will be described. Electrical results showing the benefits of programming and erasing non-volatile memories with short pulses will then be presented.

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Duraivel, A. N., B. Paulchamy, and K. Mahendrakan. "Proficient Technique for High Performance Very Large-Scale Integration System to Amend Clock Gated Dual Edge Triggered Sense Amplifier Flip-Flop with Less Dissipation of Power Leakage." Journal of Nanoelectronics and Optoelectronics 16, no. 4 (April 1, 2021): 602–11. http://dx.doi.org/10.1166/jno.2021.2984.

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Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting the individual clock signal status. Therefore, at these times of clock signal transfer, the state of the memory unit and the state of the whole electrical structure change. It’s only during signal transfer that the key to a flip-flop being correctly operated. Two transitions from 0 and 1 are followed by a clock pulse, and 1 to 0. The pulse shift is defined by the positive and negative sides of the pulse. The data on or off the clock cycle edges are recorded by a single-edge trigger flip flop (SETFF), but the flip flop with the double-edge sensor amplifier (DETSAFF). Another common technique for dynamic energy consumption reduced when the device is idle is the clock gating. In this document. Sleep is used to reduce the power of the leakage Here are the following: High threshold voltages sleep transistors are used. Among the supply voltage and VDD the sleep pMOS transistor and the pull-up system and between the network and the ground GND a sleep NMOs Transistor is located. With sleep transistors, CG-SAFF can save up to 30% of its power during zero input switching operation. For different sequential device architecture, the proposed flip-flop may be used.

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Pérez-Tomás, Amador, Anderson Lima, Quentin Billon, Ian Shirley, Gustau Catalan, and Mónica Lira-Cantú. "A Solar Transistor and Photoferroelectric Memory." Advanced Functional Materials 28, no. 17 (February 28, 2018): 1707099. http://dx.doi.org/10.1002/adfm.201707099.

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Liang, Lijuan, Wenjuan He, Rong Cao, Xianfu Wei, Sei Uemura, Toshihide Kamata, Kazuki Nakamura, Changshuai Ding, Xuying Liu, and Norihisa Kobayashi. "Non-Volatile Transistor Memory with a Polypeptide Dielectric." Molecules 25, no. 3 (January 23, 2020): 499. http://dx.doi.org/10.3390/molecules25030499.

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Organic nonvolatile transistor memory with synthetic polypeptide derivatives as dielectric was fabricated by a solution process. When only poly (γ-benzyl-l-glutamate) (PBLG) was used as dielectric, the device did not show obvious hysteresis in transfer curves. However, PBLG blended with PMMA led to a remarkable increase in memory window up to 20 V. The device performance was observed to remarkably depend on the blend ratio. This study suggests the crystal structure and the molecular alignment significantly affect the electrical performance in transistor-type memory devices, thereby provides an alternative to prepare nonvolatile memory with polymer dielectrics.

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Song, Chong-Myeong, and Hyuk-Jun Kwon. "Ferroelectrics Based on HfO2 Film." Electronics 10, no. 22 (November 11, 2021): 2759. http://dx.doi.org/10.3390/electronics10222759.

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The discovery of ferroelectricity in HfO2 thin film, which is compatible with the CMOS process, has revived interest in ferroelectric memory devices. HfO2 has been found to exhibit high ferroelectricity at a few nanometers thickness, and studies have rapidly progressed in the past decade. Ferroelectricity can be induced in HfO2 by various deposition methods and heat treatment processes. By combining ferroelectric materials with field-effect transistors, devices that combine logic and memory functions can be implemented. Ferroelectric HfO2-based devices show high potential, but there are some challenges to overcome in endurance and characterization. In this paper, we discuss the fabrication and characteristics of ferroelectric HfO2 film and various applications, including negative capacitance (NC)), Ferroelectric random-access memory (FeRAM), Ferroelectric tunnel junction (FTJ), and Ferroelectric Field-effect Transistor (FeFET).

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Xie, Hui, Hao Wu, and Chang Liu. "Non-Volatile Memory Based on ZnO Thin-Film Transistor with Self-Assembled Au Nanocrystals." Nanomaterials 14, no. 8 (April 14, 2024): 678. http://dx.doi.org/10.3390/nano14080678.

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Non-volatile memory based on thin-film transistor is crucial for system-on-panel and flexible electronic systems. Achieving high-performance and reliable thin-film transistor (TFT) memory still remains challenging. Here, for the first time, we present a ZnO TFT memory utilizing self-assembled Au nanocrystals with a low thermal budget, exhibiting excellent memory performance, including a program/erase window of 9.8 V, 29% charge loss extrapolated to 10 years, and remarkable endurance characteristics. Moreover, the memory exhibits favorable on-state characteristics with mobility, subthreshold swing, and current on–off ratio of 17.6 cm2V−1s−1, 0.71 V/dec, and 107, respectively. Our study shows that the fabricated TFT memory has great potential for practical applications.

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Gherendi, Florin, Daniela Dobrin, and Magdalena Nistor. "Transparent Structures for ZnO Thin Film Paper Transistors Fabricated by Pulsed Electron Beam Deposition." Micromachines 15, no. 2 (February 12, 2024): 265. http://dx.doi.org/10.3390/mi15020265.

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Thin film transistors on paper are increasingly in demand for emerging applications, such as flexible displays and sensors for wearable and disposable devices, making paper a promising substrate for green electronics and the circular economy. ZnO self-assembled thin film transistors on a paper substrate, also using paper as a gate dielectric, were fabricated by pulsed electron beam deposition (PED) at room temperature. These self-assembled ZnO thin film transistor source–channel–drain structures were obtained in a single deposition process using 200 and 300 µm metal wires as obstacles in the path of the ablation plasma. These transistors exhibited a memory effect, with two distinct states, “on” and “off”, and with a field-effect mobility of about 25 cm2/Vs in both states. For the “on” state, a threshold voltage (Vth on = −1.75 V) and subthreshold swing (S = 1.1 V/decade) were determined, while, in the “off” state, Vth off = +1.8 V and S = 1.34 V/decade were obtained. A 1.6 μA maximum drain current was obtained in the “off” state, and 11.5 μA was obtained in the “on” state of the transistor. Due to ZnO’s non-toxicity, such self-assembled transistors are promising as components for flexible, disposable smart labels and other various green paper-based electronics.

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ABDEL-HAFEEZ, SALEH M., and ANAS S. MATALKAH. "CMOS EIGHT-TRANSISTOR MEMORY CELL FOR LOW-DYNAMIC-POWER HIGH-SPEED EMBEDDED SRAM." Journal of Circuits, Systems and Computers 17, no. 05 (October 2008): 845–63. http://dx.doi.org/10.1142/s0218126608004599.

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Embedded SRAM design with high noise margin between read and write, low power, low supply voltages, and high speed become essential features in VLSI embedded applications. The complete embedded SRAM design of self-timing synchronization is proposed based on the CMOS eight-transistor (8T-Cell) memory cell circuit. The cell is based on the traditional six-transistor (6T-Cell) cross-coupled invertors with the addition of two NMOS transistors for separate read buffer circuit. The read buffer structure is based on pre-charging the read bit-line during the low value of read clock and evaluating the read bit-line during the high value of read clock, thereby maintaining one active line per column and eliminating the use of traditional sense amplifier with all its synchronization schemes. The simulation results show that the embedded SRAM of size 128-bit × 128-bit is operating at a maximum frequency of 200 MHz for Write and Read clock cycles with 1.62 V power supply, and measures a total average power consumption of 22.60 mW. All simulation results were conducted on 0.18 μm TSMC single poly and three layers of metals measuring a cell area of 2.2 × 3.0 μ m 2. The circuit is not meant to replace the SRAM with 6T-Cell transistor structure; however, it is attractive for applications related to high density with automation road-map design, such as graphic and network processor chips. In these applications, memory sizes are introduced in many different irregular geometries and uses all over the chip with storage sizes less than 20 k-bit, in addition, it is susceptible to large substrate noise as well as large coupling wire routing.

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Yil Suk, Yang, You In-kyu, Lee Won Jae, Yu Byoung Gon, and Cho Kyong-Ik. "Design of a Single-Transistor-Type Ferroelectric Field Effect Transistor Memory." Journal of the Korean Physical Society 40, no. 4 (April 1, 2002): 701. http://dx.doi.org/10.3938/jkps.40.701.

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Sun, Shuo, Hyochul Kim, Zhouchen Luo, Glenn S. Solomon, and Edo Waks. "A single-photon switch and transistor enabled by a solid-state quantum memory." Science 361, no. 6397 (July 5, 2018): 57–60. http://dx.doi.org/10.1126/science.aat3581.

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Single-photon switches and transistors generate strong photon-photon interactions that are essential for quantum circuits and networks. However, the deterministic control of an optical signal with a single photon requires strong interactions with a quantum memory, which has been challenging to achieve in a solid-state platform. We demonstrate a single-photon switch and transistor enabled by a solid-state quantum memory. Our device consists of a semiconductor spin qubit strongly coupled to a nanophotonic cavity. The spin qubit enables a single 63-picosecond gate photon to switch a signal field containing up to an average of 27.7 photons before the internal state of the device resets. Our results show that semiconductor nanophotonic devices can produce strong and controlled photon-photon interactions that could enable high-bandwidth photonic quantum information processing.

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Zhao, Yuhang, and Jie Jiang. "Recent Progress on Neuromorphic Synapse Electronics: From Emerging Materials, Devices, to Neural Networks." Journal of Nanoscience and Nanotechnology 18, no. 12 (December 1, 2018): 8003–15. http://dx.doi.org/10.1166/jnn.2018.16428.

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To realize intelligent functions in electronic devices like a human brain, it is important to develop the electronic devices that can imitate biological neurons and synapses (synaptic electronics). In this paper, we review the critical learning mechanisms for synaptic plasticity. Different electronic devices were developed to mimic biological synapses, such as atomic switch, phase change memory, ferroelectric memory, and electric-double-layer transistors. More importantly, several groups have realized the artificial neuromorphic network using multi-gate transistor architecture. The leap from synapse to neuron to neural network, thus, has been systematically realized using thin films and nanomaterials. The emerging synaptic electronics can have a broader applications and brighter future in the next-generation intelligent nano-electronics.

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Journal articles on the topic 'Memory transistor'

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