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Townsend, Kevin R., Osama G. Attia, Phillip H. Jones, and Joseph Zambreno. "A Scalable Unsegmented Multiport Memory for FPGA-Based Systems." International Journal of Reconfigurable Computing 2015 (2015): 1–12. http://dx.doi.org/10.1155/2015/826283.
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On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.
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C, Chandrashekar, and Dr Basavaraj I Neelgar. "Design and implementation of Dual-Port Memory." Journal of University of Shanghai for Science and Technology 23, no. 06 (June 26, 2021): 1716–22. http://dx.doi.org/10.51201/jusst/21/06478.
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Multiport memory cell using a dual-port memory cell provides required access to multi-processor-based applications. Simultaneous access can be provided using two-pass transistors, pair of bit lines, and a word line. Using specific word lines and bit lines of SRAM cell access can be provided by using dual ports memory. The single address of a memory cell can be accessed at a time during each clock pulse using single-port SRAM this drawback can be overcome by using dual-port RAM which supports concurrent read or writes access at different addresses. Efficiency is improved by using dual-port RAM. Each processor can be made to operate at different clock frequencies thereby dual-port RAM will not have any limitations of access between the two ports.
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Chen, Chien-In Henry. "Using PDM on Multiport Memory Allocation in Data Path." VLSI Design 1, no. 3 (January 1, 1994): 217–32. http://dx.doi.org/10.1155/1994/62462.
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A data path consists of memory elements (i.e. registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to memory synthesis have been proposed in the literature. However, only single port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. In this paper, an efficient method, Partitioned Dependence Matrix (PDM), is presented for memory synthesis which deals not only with single port memory synthesis but also multiport memory synthesis according to the design constraints. With suitable modifications, the proposed technique can also be applied to multiport memory synthesis in which the maximum number of read ports is different from the maximum number of write ports. Therefore, the entire design space is explored and has the capability to handle early architectural design exploration so that the quality of designs produced by an automatic synthesis tool is more adequate for production use in comparison to manual design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. A key element in our approach is the successful adoption of techniques originally developed for problems in test generation to the field of memory synthesis.
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CARBALLO, DANIEL J., INMACULADA PARDINES, and MARCOS SANCHEZ-ELEZ. "A RECONFIGURABLE MODULAR ARCHITECTURE TO EXPLOIT WORD-LEVEL PARALLELISM." Journal of Circuits, Systems and Computers 18, no. 07 (November 2009): 1227–41. http://dx.doi.org/10.1142/s0218126609005630.
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Contemporary memory system design aims to achieve high performance and low energy consumption at a reasonable cost. To balance these requirements, we propose a modular reconfigurable architecture to design memories over FPGAs. The proposed memory system can be reconfigured taking into account: the number of words, the word size of the data, the number of physical memory banks and the number of ports of the banks. Different operating modes have been defined, each one implying a certain configuration for the memory system. Simulations of these modes show the performance of our reconfigurable memory in terms of timing and power consumption.
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Rotem, Nadav, and Yosi Ben Asher. "Combining static and dynamic array detection for binary synthesis with multiple memory ports." Design Automation for Embedded Systems 15, no. 1 (November 30, 2010): 1–18. http://dx.doi.org/10.1007/s10617-010-9065-z.
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Ditmar, Johan, Steve McKeever, and Alex Wilson. "Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation." International Journal of Reconfigurable Computing 2008 (2008): 1–14. http://dx.doi.org/10.1155/2008/674340.
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This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs.
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Lin, Zhiting, Honglan Zhan, Xuan Li, Chunyu Peng, Wenjuan Lu, Xiulong Wu, and Junning Chen. "In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, no. 5 (May 2020): 1316–20. http://dx.doi.org/10.1109/tvlsi.2020.2976099.
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Deng, Jiang Ming, Te Fang Chen, and Shu Cheng. "MVB-Based Dynamic Supervision of Docks in Traffic Memory." Advanced Materials Research 403-408 (November 2011): 2728–31. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.2728.
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A high reliability of Traffic Memory(TM) working condition is of vital importance to information transfer in MVB. In order to avoid bus traffic overflows, the minimum possible time intervals or loading ratios of TM for a given number of ports were calculated. The longer supervision period it had, the more number of docks could be supervised. The number of docks supervised, during supervision intervals, was submitted to Normal distribution ( Ν(μ,σ2)). From the possibility distribution function it could σfind maximum possibility of the number of docks in working. From the disturbance rejection test of the fixed factor σ , a reasonable setting of sink-time supervision interval could be made to guarantee a high reliability for TM working condition.
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Mansoursamaei, Meead, Mahmoud Moradi, Rosa G. González-Ramírez, and Eduardo Lalla-Ruiz. "Machine Learning for Promoting Environmental Sustainability in Ports." Journal of Advanced Transportation 2023 (March 3, 2023): 1–17. http://dx.doi.org/10.1155/2023/2144733.
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Maritime transportation is one of the essential drivers of the global economy as it enables both lower transportation costs and intermodal operations across multiple forms of transportation. Maritime ports are essential interfaces that support cargo handling between sea and hinterland transportation. Besides, in this area, environmental protection is becoming extremely important. Global warming, air pollution, and greenhouse gas emissions are all having a detrimental influence on the environment and will most likely continue to do so for future generations. Hence, there is a growing need to promote environmental sustainability in maritime-based transportation. The application of machine learning (ML), as one of the main subdomains of artificial intelligence (AI), can be considered a component within the process of digital transformation to advance green activities in maritime port logistics. Thus, this article presents the results of a systematic literature review of the recent literature on machine learning for promoting environmentally sustainable maritime ports. It collects and analyses the articles whose contributions lie in the interplay between three main dimensions, i.e., machine learning, port-related operations, and environmental sustainability. Throughout a review protocol, this research is constituted on the major focuses of impact, problems, and techniques to discern the current state of the art as well as research directions. The research findings indicate that the articles using polynomial regression models are dominant in the literature, and the recurrent neural network (RNN) and long short-term memory (LSTM) are the most recent approaches. Moreover, in terms of environmental sustainability, emissions and energy consumption are the most studied problems. mAccording to the research gaps observed in the review, two broad directions for future research are identified: (i) altering attention on a greater diversity of machine learning approaches for promoting environmental sustainability in ports and (ii) leveraging new outlooks to perform more green practical works on port-related operations.
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Kumar, Sanjeev, and Alvaro Munoz. "Comparison of Memory Assignment Schemes for Switch Architectures with Shareable Parallel Memory Modules." Journal of Electrical and Computer Engineering 2010 (2010): 1–7. http://dx.doi.org/10.1155/2010/126591.
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Switching Architectures deploying shareable parallel memory modules are quite versatile in their ability to scale to higher capacity while retaining the advantage of sharing its entire memory resource among all input and output ports. The two main classes of such architectures, namely, the Shared Multibuffer-(SMB-) based switch and the Sliding-Window-(SW-) based packet switch, both deploy parallel memory modules that are physically separate but logically connected. Inspite of their similarity in regards to using shareable parallel memory modules, they differ in switching control and scheduling of packets to parallel memory modules. SMB switch uses centralized control whereas the SW switch uses a decentralized control for switching operations. In this paper, we present a new memory assignment scheme for the Sliding-Window (SW) switch for assigning packets to parallel memory modules that maximizes the parallel storage of packets to multiple memory modules. We compare the performance of a sliding-window switch deploying this new memory assignment scheme with that of an SMB switch architecture under conditions of identical traffic type and memory resources deployed. The simulation results show that the new memory assignment scheme for the sliding window switch maximizes parallel storage of packets input in a given switch cycle, and it does not require speed-up of memory modules. Furthermore, it provides a superior performance compared to that of the SMB switch under the constraints of fixed memory-bandwidth and memory resources.
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Priya, A., and P. Thenmozhi. "Implementation of an Efficient Design of Multi ported Memory on FPGA." International Journal of Advance Research and Innovation 7, no. 2 (2019): 67–71. http://dx.doi.org/10.51976/ijari.721910.
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The utilization of block RAMs (BRAMs) is a critical performance factor for multi ported memory designs on field programmable gate arrays (FPGAs). Not only does the excessive demand on BRAMs block the usage of BRAMs from other parts of a design, but the complex routing between BRAMs and logic also limits the operating frequency. This paper first introduces a brand new perspective and a more efficient way of using a conventional two reads one write (2R1W) memory as a 2R1W/4Rmemory. By exploiting the 2R1W/4R as the building block, this introduces a hierarchical design of 4R1W memory that25% fewer BRAMs than the previous approach of duplicating the 2R1W module. Memories with more read/write ports can be extended from the proposed 2R1W/4R memory and the hierarchical 4R1W memory. Compared with previous xor-based and live value table-based approaches, the proposed designs can, respectively, reduce BRAM usage for 4R2W memory designs with 8K-depth. For complex multiport designs, the proposed BRAM-efficient approaches can achieve higher clock frequencies by alleviating the complex routing in an FPGA.
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Yeongkyo Seo, Xuanyao Fong, Kon-Woo Kwon, and Kaushik Roy. "Spin-Hall Magnetic Random-Access Memory With Dual Read/Write Ports for On-Chip Caches." IEEE Magnetics Letters 6 (2015): 1–4. http://dx.doi.org/10.1109/lmag.2015.2422260.
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Cui, Junfei, Bingchun Liu, Yan Xu, and Xiaoling Guo. "Regional Collaborative Forecast of Cargo Throughput in China’s Circum-Bohai-Sea Region Based on LSTM Model." Computational Intelligence and Neuroscience 2022 (July 7, 2022): 1–13. http://dx.doi.org/10.1155/2022/5044926.
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Any developed port plays a dominant role both in domestic and international trade reflecting economic prosperity of the port and nearby regions in terms of its cargo throughput and port construction. An attempt is made in this study to use long-and short-term memory (LSTM) artificial neural network method to construct the port cargo throughput prediction model. Three ports namely, Tianjin Port, Dalian Port, and Tangshan Port from China’s Bohai Rim region are selected as research objects. The historical cargo throughput of each port for nearly ten years was used as the input index data for joint prediction. The cargo throughput of Bohai Port provides another way to improve the accuracy of port cargo throughput prediction. The prediction results show that the LSTM model can effectively predict the port cargo throughput; the cargo throughput forecasts between the three Bohai Rim ports have both an interactive relationship and differences.
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Kumar S., Druva, and Roopa M. "Design and analysis of multiple read port techniques using bank division with XOR method for multi-ported-memory on FPGA platform." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 6 (December 1, 2021): 4785. http://dx.doi.org/10.11591/ijece.v11i6.pp4785-4793.
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<span lang="EN-US">The multiple read and write operations are performed simultaneously by multi-ported memories and are used in advanced digital design applications on reprogrammable field-programmable gate arrays (FPGAs) to achieve higher bandwidth. The Memory modules are configured by block RAM (BRAMs), which utilizes more area and power on FPGA. In this manuscript, the techniques to increase the read ports for multi-ported memory modules are designed using the bank division with XOR (BDX) approach. The read port techniques like two read-one write (2R1W) memory, hybrid mode approach either 2R1W or 4R memory, and hierarchical BDX (HBDX) Approach using 2R1W/4R memory are designed on FPGA platform. The Proposed work utilizes only slices and look-up table (LUT's) rather than BRAMs while designing the memory modules on FPGA, which reduces the computational complexity and improves the system performance. The experimental results are analyzed on Artix-7 FPGA. The performance parameters like slices, LUT utilization, maximum frequency (Fmax), and hardware efficiency are analyzed by concerning different memory depths. The 4R1W memory design using the HBDX approach utilizes 4% slices and works at 449.697 MHz operating frequency on Artix-7 FPGA. The proposed work provides a better platform to choose the proper read port technique to design an efficient modular multiport memory architecture.</span>
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Dawamsyach, Fazar, Ikhwan Ruslianto, and Uray Ristian. "Implementation of IPS (Intrusion Prevention System) Fail2ban on Server for DDoS and Brute Force Attacks." CESS (Journal of Computer Engineering, System and Science) 8, no. 1 (January 21, 2023): 149. http://dx.doi.org/10.24114/cess.v8i1.40259.
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Server security is an important thing that must be considered so that the server can work well and serve users. Attacks on servers can threaten server performance and data security in it. According to the National Cyber and Crypto Agency 2020 report, ports 22 and 80 were the top ports with the most attacks. One of the attacks on port 22 is brute force and an attack on port 80 is Distributed Denial of Service (DDoS). To solve this problem, a study was conducted to implement fail2ban IPS (Intrusion Prevention System) to increase server security. The attacks tested focused on brute force attacks on port 22 and DDoS attacks on port 80 using the TCP protocol. The fail2ban system is equipped with a website interface and notifications via telegram. The test results show that DDoS attacks have more impact on CPU performance with the highest increase in CPU being 92%, while brute force attacks have more impact on server memory performance with the highest increase in memory by 100%. The increase in server performance results in slowed server performance. The system managed to prevent DDoS attacks with an average speed of 0.5 seconds while brute force attacks were 6.1 seconds. The system managed to prevent DDoS attacks with a total of 88 attacks and brute force attacks with a total of 864 attacks.
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Lin, Zhiting, Chunyu Peng, and Kun Wang. "A Novel Controllable BIST Circuit for embedded SRAM." Open Electrical & Electronic Engineering Journal 10, no. 1 (January 29, 2016): 1–10. http://dx.doi.org/10.2174/1874129001610010001.
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With increasingly stringent requirements for memory test, the complexity of the test algorithm is increasing. This will make BIST (Build-In-Self-Test) circuit more complex and the area of BIST circuit larger. This paper proposes a novel controllable BIST circuit. The controllable BIST circuit provides a cost-effective solution that supports a variety of March algorithms and SRAM embedded testing operation modes. It controls the test patterns with three additional input ports. And it indicates the algorithm progress, the test result and the number of fails with three output ports. To achieve test patterns generation, analy-sis and test results recording, the proposed BIST circuit contains five internal functional modules, which are Address Gener-ator, Control Generator, Data Generator, Data Comparator and Fail Accumulator. The test patterns of the proposed BIST cir-cuit are controlled by external signals. It is not only suitable for any existing march algorithms but also leaves room for ex-tension if needed.
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KANG, MOO-KYUNG, and CHONG-MIN KYUNG. "THREE-STAGE CLOS-NETWORK SWITCH ARCHITECTURE WITH BUFFERED CENTER STAGE FOR MULTI-CLASS TRAFFIC." Journal of Circuits, Systems and Computers 15, no. 02 (April 2006): 263–76. http://dx.doi.org/10.1142/s0218126606003088.
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Memory-space-memory (MSM) arrangement is a popular architecture to implement three-stage Clos-network switches with distributed arbitration. The scalability of this architecture, however, is limited by the round-trip communication delay between the first and the second stages. Moreover, virtual output queue does not completely remove the blocking in the buffered modules under multi-class traffic. In this paper, we propose a competition-free memory–memory–memory (CFM3) switch which is a three-stage Clos-network switch with buffered center stage. The CFM3 deploys buffered modules in all stages to simplify communication between stages. To reduce the blocking, each module is equipped with a set of buffers fully separated according to the destinations, classes of packets and the input ports of the module. Despite the buffered center stage, CFM3 is free from reordering problem due to simple control mechanism. Simulation result shows the delay of the proposed CFM3 switch closely approaches that of the ideal Output Queued switch under multi-class traffic when strict priority policy popularly used for class-based switch is deployed. The CFM3 achieves 100% throughput under uniformly distributed four-class traffic with strict priority policy while traditional MSM switch records about 77% throughput.
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Lin, Zhiting, Zhiyong Zhu, Honglan Zhan, Chunyu Peng, Xiulong Wu, Yuan Yao, Jianchao Niu, and Junning Chen. "Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports." IEEE Journal of Solid-State Circuits 56, no. 9 (September 2021): 2832–44. http://dx.doi.org/10.1109/jssc.2021.3061260.
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Lindenstrøm, Thomas, Joshua Woodworth, Jes Dietrich, Claus Aagaard, Peter Andersen, and Else Marie Agger. "Vaccine-Induced Th17 Cells Are Maintained Long-Term Postvaccination as a Distinct and Phenotypically Stable Memory Subset." Infection and Immunity 80, no. 10 (July 30, 2012): 3533–44. http://dx.doi.org/10.1128/iai.00550-12.
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ABSTRACTTh17 cells are increasingly being recognized as an important T helper subset for immune-mediated protection, especially against pathogens at mucosal ports of entry. In several cases, it would thus be highly relevant to induce Th17 memory by vaccination. Th17 cells are reported to exhibit high plasticity and may not stably maintain their differentiation program once induced, questioning the possibility of inducing durable Th17 memory. Accordingly, there is no consensus as to whether Th17 memory can be established unless influenced by continuous Th17 polarizing conditions. We have previously reported (T. Lindenstrøm, et al., J. Immunol. 182:8047–8055, 2009) that the cationic liposome adjuvant CAF01 can prime both Th1 and Th17 responses and promote robust, long-lived Th1 memory. Here, we demonstrate that subunit vaccination in mice with CAF01 leads to establishment of bona fide Th17 memory cells. Accordingly, Th17 memory cells exhibited lineage stability by retaining both phenotypic and functional properties for nearly 2 years. Antigen-specific, long-term Th17 memory cells were found to be mobilized from lung-draining lymph nodes to the lung following an aerosol challenge byMycobacterium tuberculosisnearly 2 years after their induction and proliferated at levels comparable to those of Th1 memory cells. During the infection, the vaccine-induced Th17 memory cells expanded in the lungs and adapted Th1 characteristics, implying that they represent a metastable population which exhibits plasticity when exposed to prolonged Th1 polarizing, inflammatory conditions such as those found in theM. tuberculosis-infected lung. In the absence of overt inflammation, however, stable bona fide Th17 memory can indeed be induced by parenteral immunization.
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Siddaraju, Druva Kumar, and Roopa Munibyrappa. "Design and performance analysis of efficient hybrid mode multi-ported memory modules on FPGA platform." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 2 (July 1, 2022): 115. http://dx.doi.org/10.11591/ijres.v11.i2.pp115-125.
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The multi-ported memories (MPMs) are essential and are part of the parallel computing system for high-performance features. The MPMs are commonly used in most processors and advanced system-on-chip (SoC) for faster computation and high-speed processing. In this manuscript, efficient MPMs are designed using the integration of hierarchical bank division with xor (HBDX) and bank division with remap table (BDRT) approaches. The BDRT approach is configured using remap table with a hash write controlling mechanism to avoid write conflicts. The different multiple read ports are designed using BDX, and HBDX approaches are discussed in detail. The results of 2W4R and 3W4R memory modules are analyzed in detail concerning chip area, operating frequency (MHz), block random access memories (BRAMs), and throughput (Gbps) for different memory depths on virtex-7 field programmable gate array (FPGA). The 2W4R utilizes 2.27% slices, operates at 268 MHz frequency by consuming 64 BRAMs for 16K memory depth. Similarly, the 3W4R uses 2.28% slices, operates at 250 MHz frequency by consuming 96 BRAMs for 16K Memory depth. The proposed designs are compared with existing MPM approaches with better chip utilization (Slices), frequency, and BRAMs on the same FPGA device.
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Chakravarti, Ranabir. "NAKHUDAS AND NAUVITTAKAS: SHIP-OWNING MERCHANTS IN THE WEST COAST OF INDIA (C. AD 1000-1500)." Journal of the Economic and Social History of the Orient 43, no. 1 (2000): 34–64. http://dx.doi.org/10.1163/156852000511231.
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AbstractAmong the diverse types of merchants active in India during the first half of the second millennium, the ship-owning merchants occupy a prominent position in the coastal areas of western India (especially at ports). These merchants are given distinct epithets nakhuda and nauvittaka, the two terms being occasionally used as interchangeable ones and also in their abbreviated forms in official documents. Known from the medieval Jewish letters of 'India Traders', copper plates, a bilingual inscription, Arabic accounts and epitaphs and Jaina carita (biographical) texts, nakudas and nauvittkas of different religious leanings (Jewish, Muslim and Hindu) illustrate remarkable co-operation and social amity and religious toleration, which underline their importance in the Indian Ocean maritime network prior to AD 1500. Possessing considerable wealth, these ship-owning merchants can be considered as elites in the ports of coastal western India and were also known for their patronage to religious and cultural activities. The paper is presented as a tribute to the memory of Professor Ashin Das Gupta who immensely enlightened us on the ship-owners of coastal western India between 1500-1800.
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Abbasi, Mahdi, Navid Mousavi, Milad Rafiee, Mohammad R. Khosravi, and Varun G. Menon. "A CRC-Based Classifier Micro-Engine for Efficient Flow Processing in SDN-Based Internet of Things." Mobile Information Systems 2020 (May 18, 2020): 1–8. http://dx.doi.org/10.1155/2020/7641073.
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In the Internet of things (IoT), network devices and mobile systems should exchange a considerable amount of data with negligible delays. For this purpose, the community has used the software-defined networking (SDN), which has provided high-speed flow-based communication mechanisms. To satisfy the requirements of SDN in the classification of communicated packets, high-throughput packet classification systems are needed. A hardware-based method of Internet packet classification that could be simultaneously high-speed and memory-aware has been proved to be able to fill the gap between the network speed and the processing speed of the systems on the network in traffics higher than 100 Gbps. The current architectures, however, have not been successful in achieving these two goals. This paper proposes the architecture of a processing micro-core for packet classification in high-speed, flow-based network systems. By using the hashing technique, this classifying micro-core fixes the length of the rules field. As a result, with a combination of SRAM and BRAM memory cells and implementation of two ports on Virtex®6 FPGAs, the memory usage of 14.5 bytes per rule and a throughput of 324 Mpps were achieved in our experiments. Also, the performance per memory of the proposed design is the highest as compared to its major counterparts and is able to simultaneously meet the speed and memory-usage criteria.
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Jacobsen, Jørgen Gausdal, Behruz Shaker Shiran, Tormod Skauge, Kenneth Stuart Sorbie, and Arne Skauge. "Qualification of New Methods for Measuring In Situ Rheology of Non-Newtonian Fluids in Porous Media." Polymers 12, no. 2 (February 14, 2020): 452. http://dx.doi.org/10.3390/polym12020452.
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Pressure drop (ΔP) versus volumetric injection rate (Q) data from linear core floods have typically been used to measure in situ rheology of non-Newtonian fluids in porous media. However, linear flow is characterized by steady-state conditions, in contrast to radial flow where both pressure and shear-forces have non-linear gradients. In this paper, we qualify recently developed methods for measuring in situ rheology in radial flow experiments, and then quantitatively investigate the robustness of these methods against pressure measurement error. Application of the new methods to experimental data also enabled accurate investigation of memory and rate effects during polymer flow through porous media. A radial polymer flow experiment using partially hydrolyzed polyacrylamide (HPAM) was performed on a Bentheimer sandstone disc where pressure ports distributed between a central injector and the perimeter production line enabled a detailed analysis of pressure variation with radial distance. It has been suggested that the observed shear-thinning behavior of HPAM solutions at low flux in porous media could be an experimental artifact due to the use of insufficiently accurate pressure transducers. Consequently, a generic simulation study was conducted where the level of pressure measurement error on in situ polymer rheology was quantitatively investigated. Results clearly demonstrate the robustness of the history match methods to pressure measurement error typical for radial flow experiments, where negligible deviations from the reference rheology was observed. It was not until the error level was increased to five-fold of typical conditions that significant deviation from the reference rheology emerged. Based on results from pore network modelling, Chauveteau (1981) demonstrated that polymer flow in porous media may at some rate be influenced by the prior history. In this paper, polymer memory effects could be evaluated at the Darcy scale by history matching the pressure drop between individual pressure ports and the producer as a function of injection rate (conventional method). Since the number of successive contraction events increases with radial distance, the polymer has a different pre-history at the various pressure ports. Rheology curves obtained from history matching the radial flow experiment were overlapping, which shows that there is no influence of geometry on in-situ rheology for the particular HPAM polymer investigated. In addition, the onset of shear-thickening was independent of volumetric injection rate in radial flow.
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Yang, Cheng-Hong, and Po-Yin Chang. "Forecasting the Demand for Container Throughput Using a Mixed-Precision Neural Architecture Based on CNN–LSTM." Mathematics 8, no. 10 (October 15, 2020): 1784. http://dx.doi.org/10.3390/math8101784.
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Forecasting the demand for container throughput is a critical indicator to measure the development level of a port in global business management and industrial development. Time-series analysis approaches are crucial techniques for forecasting the demand for container throughput. However, accurate demand forecasting for container throughput remains a challenge in time-series analysis approaches. In this study, we proposed a mixed-precision neural architecture to forecasting the demand for container throughput. This study is the first work to use a mixed-precision neural network to forecast the container throughput—the mixed-precision architecture used the convolutional neural network for learning the strength of the features and used long short-term memory to identify the crucial internal representation of time series depending on the strength of the features. The experiments on the demand for container throughput of the five ports in Taiwan were conducted to compare our deep learning architecture with other forecasting approaches. The results indicated that our mixed-precision neural architecture exhibited higher forecasting performance than classic machine learning approaches, including adaptive boosting, random forest regression, and support vector regression. The proposed architecture can effectively predict the demand for port container throughput and effectively reduce the costs of planning and development of ports in the future.
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Göhringer, Diana, Michael Hübner, Etienne Nguepi Zeutebouo, and Jürgen Becker. "Operating System for Runtime Reconfigurable Multiprocessor Systems." International Journal of Reconfigurable Computing 2011 (2011): 1–16. http://dx.doi.org/10.1155/2011/121353.
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Operating systems traditionally handle the task scheduling of one or more application instances on processor-like hardware architectures. RAMPSoC, a novel runtime adaptive multiprocessor System-on-Chip, exploits the dynamic reconfiguration on FPGAs to generate, start and terminate hardware and software tasks. The hardware tasks have to be transferred to the reconfigurable hardware via a configuration access port. The software tasks can be loaded into the local memory of the respective IP core either via the configuration access port or via the on-chip communication infrastructure (e.g. a Network-on-Chip). Recent-series of Xilinx FPGAs, such as Virtex-5, provide two Internal Configuration Access Ports, which cannot be accessed simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled, e.g. by a special-purpose operating system running on an embedded processor. For that purpose and to handle the relations between temporally and spatially scheduled operations, the novel approach of an operating system is of high importance. This special purpose operating system, called CAP-OS (Configuration Access Port-Operating System), which will be presented in this paper, supports the clients using the configuration port with the services of priority-based access scheduling, hardware task mapping and resource management.
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Gomez-Cornejo, Julen, Itxaso Aranzabal, Iraide López Ropero, Angel Javier Mazón, and Aitzol Zuloaga. "A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices." Electronics 12, no. 1 (December 27, 2022): 102. http://dx.doi.org/10.3390/electronics12010102.
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This paper proposes a methodology to access data and manage the content of distributed memories in FPGA designs through the configuration bitstream. Thanks to the methods proposed, it is possible to read and write the data content of registers without using the in/out ports of registers in a straightforward fashion. Hence, it offers the possibility of performing several operations, such as, to load, copy or compare the information stored in registers without the necessity of physical interconnections. This work includes two flows that simplify the designing process when using the proposed approach: while the first enables the protection or unprotection of writing on different partial regions through the bitstream, the second permits homogeneous instances of a design implemented in different reconfigurable regions to be obtained without losing efficiency. The approach is based and has been physically validated on the ZYNQ from Xilinx, and when using partially reconfigurable designs, it does not affect the hardware overhead nor the maximum operating frequency of the design.
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Heselhaus, T., and T. G. Noll. "A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement." Advances in Radio Science 9 (August 1, 2011): 247–53. http://dx.doi.org/10.5194/ars-9-247-2011.
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Abstract. The conventional sensing scheme of single-ended read-only-ports as integrated in 8T-SRAM cells suffers from low performance compared to double-ended complementary sensing schemes. In the proposed sensing scheme the pre-charge voltage of the single-ended read-bit-line is set to a level above the threshold voltage of the sensing device with an adjustable margin. This margin is minimized to speed up the read access on the one hand and kept large enough to provide a sufficient bit-line noise margin on the other hand. The pre-charge voltage level of the proposed sensing circuit tracks the threshold voltage of the sensing device under process variations in order to maintain a minimum required bit-line noise margin. To avoid unnecessary bit-line discharging, the proposed sensing scheme employs a modified 8T-SRAM cell. Compared to the conventional 8T-SRAM cell, the read port of the proposed cell provides a virtual ground line running in parallel to the bit-lines. An internal driver of the sensing circuit releases the virtual ground line during the evaluation period to prevent the charge dissipation resulting in a raised voltage level. The reduced pre-charge level and the increased virtual ground lead to a reduced bit-line voltage swing and thus a bit-line power reduction. Access time, energy dissipation, and noise margin of the proposed sensing circuit are compared with conventional sensing circuits from the literature for different numbers of memory cells connected to the bit-line. It is shown, that for a specific number of memory cells per bit-line the proposed circuit achieves fastest access time at low power operation.
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Humphrey, Caroline, and Vera Skvirskaja. "Introduction." Focaal 2014, no. 70 (December 1, 2014): 3–11. http://dx.doi.org/10.3167/fcl.2014.700101.
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The introduction first outlines different perspectives on the Black Sea: in history, as a site of imperial conflicts and a buffer zone; in area studies, as a “region”; and in anthropology, as a sea crisscrossed by migration, cultural influences, alternative visions, and often a mutual turning of backs. We then discuss the Black Sea in the context of maritime ethnography and the study of ports, “hero cities”, pipelines, and political crises. The following sections consider Smith's notion of the “territorialization of memory” in relation to histories of exile and the more recent interactions brought about by migration and trade. In the concluding section we discuss how the Black Sea has appeared as a “horizon” and imaginary of the beyond for the peoples living around its shores.
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Lúzio, Jorge. "The “Orient” in the “New World”: The Carreira da Índia and the Flows between Asia and Portuguese America." Asian Diasporic Visual Cultures and the Americas 2, no. 1-2 (March 2, 2016): 32–50. http://dx.doi.org/10.1163/23523085-00202006.
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The history of Brazil in its colonial period is characterized by the movement of Asian people, goods, and merchandise radiating from Brazilian ports that received ships via the Carreira da Índia, the main sea route integrating the Portuguese Empire both commercially and politically. Asian memory and imagination were present in the urban centres of the Portuguese American colonies in the form of cultural material before the actual presence of Asians, which began to occur through cycles of immigration into Brazilian lands during the nineteenth century. This article traces the circulation of ivory carvings from Asia into Portuguese America as a way of illustrating the presence of Asian material cultures in the New World, as well as the relevance of the Carreira da Índia to these cultural connections.
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Lee, Eunju, Dohee Kim, and Hyerim Bae. "Container Volume Prediction Using Time-Series Decomposition with a Long Short-Term Memory Models." Applied Sciences 11, no. 19 (September 27, 2021): 8995. http://dx.doi.org/10.3390/app11198995.
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The purpose of this study is to improve the prediction of container volumes in Busan ports by applying external variables and time-series data decomposition methods to deep learning prediction models. Previous studies on container volume forecasting were based on traditional statistical methodologies, such as ARIMA, SARIMA, and regression. However, these methods do not explain the complexity and variability of data caused by changes in the external environment, such as the global financial crisis and economic fluctuations. Deep learning can explore the inherent patterns of data and analyze the characteristics (time series, external environmental variables, and outliers); hence, the accuracy of deep learning-based volume prediction models is better than that of traditional models. However, this does not include the study of overall trends (upward, steady, or downward). In this study, a novel deep learning prediction model is proposed that combines prediction and trend identification of container volume. The proposed model explores external variables that are related to container volume, combining port volume time-series decomposition with external variables and deep learning-based multivariate long short-term memory (LSTM) prediction. The results indicate that the proposed model performs better than the traditional LSTM model and follows the trend simultaneously.
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Spyrou, Evangelos D., Ioannis Tsoulos, and Chrysostomos Stylios. "Applying and Comparing LSTM and ARIMA to Predict CO Levels for a Time-Series Measurements in a Port Area." Signals 3, no. 2 (April 15, 2022): 235–48. http://dx.doi.org/10.3390/signals3020015.
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Air pollution is a major problem in the everyday life of citizens, especially air pollution in the transport domain. Ships play a significant role in coastal air pollution, in conjunction with transport mobility in the broader area of ports. As such, ports should be monitored in order to assess air pollution levels and act accordingly. In this paper, we obtain CO values from environmental sensors that were installed in the broader area of the port of Igoumenitsa in Greece. Initially, we analysed the CO values and we have identified some extreme values in the dataset that showed a potential event. Thereafter, we separated the dataset into 6-h intervals and showed that we have an extremely high rise in certain hours. We transformed the dataset to a moving average dataset, with the objective being the reduction of the extremely high values. We utilised a machine-learning algorithm, namely the univariate long short-term memory (LSTM) algorithm to provide the predicted outcome of the time series from the port that has been collected. We performed experiments by using 100, 1000, and 7000 batches of data. We provided results on the model loss and the root-mean-square error as well as the mean absolute error. We showed that with the case with batch number equals to 7000, the LSTM we achieved a good prediction outcome. The proposed method was compared with the ARIMA model and the comparison results prove the merit of the approach.
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Seo, Yeongkyo, and Kon-Woo Kwon. "High-Density 1R/1W Dual-Port Spin-Transfer Torque MRAM." Micromachines 13, no. 12 (December 15, 2022): 2224. http://dx.doi.org/10.3390/mi13122224.
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Spin-transfer torque magnetic random-access memory (STT-MRAM) has several desirable features, such as non-volatility, high integration density, and near-zero leakage power. However, it is challenging to adopt STT-MRAM in a wide range of memory applications owing to the long write latency and a tradeoff between read stability and write ability. To mitigate these issues, an STT-MRAM bit cell can be designed with two transistors to support multiple ports, as well as the independent optimization of read stability and write ability. The multi-port STT-MRAM, however, is achieved at the expense of a higher area requirement due to an additional transistor per cell. In this work, we propose an area-efficient design of 1R/1W dual-port STT-MRAM that shares a bitline between two adjacent bit cells. We identify that the bitline sharing may cause simultaneous access conflicts, which can be effectively alleviated by using the bit-interleaving architecture with a long interleaving distance and the sufficient number of word lines per memory bank. We report various metrics of the proposed design based on the bit cell design using a 45 nm process. Compared to a standard single-port STT-MRAM, the proposed design shows a 15% lower read power and a 19% higher read-disturb margin. Compared with prior work on the 1R/1W dual-port STT-MRAM, the proposed design improves the area by 25%.
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Manie, Yibeltal Chanie, Jyun-Wei Li, Peng-Chun Peng, Run-Kai Shiu, Ya-Yu Chen, and Yuan-Ta Hsu. "Using a Machine Learning Algorithm Integrated with Data De-Noising Techniques to Optimize the Multipoint Sensor Network." Sensors 20, no. 4 (February 16, 2020): 1070. http://dx.doi.org/10.3390/s20041070.
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In this paper, for an intensity wavelength division multiplexing (IWDM)-based multipoint fiber Bragg grating (FBG) sensor network, an effective strain sensing signal measurement method, called a long short-term memory (LSTM) machine learning algorithm, integrated with data de-noising techniques is proposed. These are considered extremely accurate for the prediction of very complex problems. Four ports of an optical coupler with distinct output power ratios of 70%, 60%, 40%, and 30% have been used in the proposed distributed IWDM-based FBG sensor network to connect a number of FBG sensors for strain sensing. In an IWDM-based FBG sensor network, distinct power ratios of coupler ports can contain distinct powers or intensities. However, unstable output power in the sensor system due to random noise, harsh environments, aging of the equipment, or other environmental factors can introduce fluctuations and noise to the spectra of the FBGs, which makes it hard to distinguish the sensing signals of FBGs from the noise signals. As a result, noise reduction and signal processing methods play a significant role in enhancing the capability of strain sensing. Thus, to reduce the noise, to improve the signal-to-noise ratio, and to accurately measure the sensing signal of FBGs, we proposed a long short-term memory (LSTM) deep learning algorithm integrated with discrete waveform transform (DWT) data smoother (de-noising) techniques. The DWT data de-noising methods are important techniques for analyzing and de-noising the sensor signals, and it further improves the strain sensing signal measurement accuracy of the LSTM model. Thus, after de-noising the sensor data, these data are fed into the LSTM model to measure the sensing signal of each FBG. The experimental results prove that the integration of LSTM with the DWT data de-noising technique achieved better sensing signal measurement accuracy, even in noisy data or environments. Therefore, the proposed IWDM-based FBG sensor network can accurately sense the signal of strain, even in bad or noisy environments; can increase the number of FBG sensors multiplexed in the sensor system; and can enhance the capacity of the sensor system.
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Rhook, Nadia. "‘Annamese Coolies’ at Australian Ports: Charting Colonial Geographies of Emotion, and Settler Memory, from French Vietnam to New Caledonia via Interwar Australia." Australian Historical Studies 48, no. 3 (July 3, 2017): 399–415. http://dx.doi.org/10.1080/1031461x.2017.1338740.
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Brown, Michael C. "Multiple System Configurations in a 32-bit Extreme Environment." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000301–6. http://dx.doi.org/10.4071/hitec-2012-tha12.
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Full computational systems are needed at extreme environments (to 300°C) to increase functionality and reduce cost in the ever advancing oil/gas, geothermal, aeronautic, and automotive industries. Commercially available electronic components are not available to build a reliable system. A single microcontroller device can be used in systems of varying complexity, from small, mid, large, and multiprocessor scale. The 32-bit microcontroller will use a low power silicon-on-insulator CMOS process to increase long term reliability. Communication ports are provided to allow for simple systems with a single processor to complex multiprocessor systems with multiple controlled devices and external memory. As no adequate non-volatile solution is available for extreme conditions, multiple boot options are available to load instructions from external sources. Fault tolerance should be provided by system error detection. Battery backup must be provided for program and data retention. The resulting microcontroller will allow a wide variety of extreme environment systems, from simple to complex.
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Sovinsky, John. "3D Modeling of Complex Combinations of Dies, Packages, Lead Frames, Sockets and Test Boards for Electrical, Thermal and Manufacturing Verification of Advanced Semiconductor Devices." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 001656–95. http://dx.doi.org/10.4071/2010dpc-wp11.
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The software process described permits putting unlimited layers of dies and substrates in the same CAD database where many advanced optimizations and tunings can be accomplished on the entire electronic system simultaneously. Gates and swappable memory and FPGA pins may be optimally selected to reduce wire length and the number of routing layers. Die placement may also be optimized across multiple subtrates for the same purpose. Interposers between substrates or side routing can be implemented and I/O locations optimized for maximum performance. Native scripts may be used to generate composite electrical models in the major electrical analysis tools that define 3D geometries precisely without 2-1/2 D abbreviations. Exact ACIS and Step models define the complex stackups for Thermal analysis in major Thermal Modeling softwares. All these models are created with high speed which enables the multiple design cycle iterations necessary for the refinement of a quality product. All relevant material properties and ports are exported with the 3D graphical data. Where appropriate changes are initialised back into parametric models. Customizations of the process by the users are routine.
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DOROJEVETS, MIKHAIL. "ARCHITECTURE AND DESIGN OF AN 8-BIT FLUX-1 SUPERCONDUCTOR RSFQ MICROPROCESSOR." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 521–29. http://dx.doi.org/10.1142/s0129156402001435.
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The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.
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Hong, Hyunsu, Hyungjin Jeon, Cheong Youn, and Hyeonsoo Kim. "Incorporation of Shipping Activity Data in Recurrent Neural Networks and Long Short-Term Memory Models to Improve Air Quality Predictions around Busan Port." Atmosphere 12, no. 9 (September 12, 2021): 1172. http://dx.doi.org/10.3390/atmos12091172.
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Air pollution sources and the hazards of high particulate matter 2.5 (PM2.5) concentrations among air pollutants have been well documented. Shipping emissions have been identified as a source of air pollution; therefore, it is necessary to predict air pollutant concentrations to manage seaport air quality. However, air pollution prediction models rarely consider shipping emissions. Here, the PM2.5 concentrations of the Busan North and Busan New Ports were predicted using a recurrent neural network and long short-term memory model by employing the shipping activity data of Busan Port. In contrast to previous studies that employed only air quality and meteorological data as input data, our model considered shipping activity data as an emission source. The model was trained from 1 January 2019 to 31 January 2020 and predictions and verifications were performed from 1–28 February 2020. Verifications revealed an index of agreements (IOA) of 0.975 and 0.970 and root mean square errors of 4.88 and 5.87 µg/m3 for Busan North Port and Busan New Port, respectively. Regarding the results based on the activity data, a previous study reported an IOA of 0.62–0.84, with a higher predictive power of 0.970–0.975. Thus, the extended approach offers a useful strategy to prevent PM2.5 air pollutant-induced damage in seaports.
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Zou, Yu, Kazi Abu Zubair, Mazen Alwadi, Rakin Muhammad Shadab, Sanjay Gandham, Amro Awad, and Mingjie Lin. "ARES: Persistently Secure Non-Volatile Memory with Processor-transparent and Hardware-friendly Integrity Verification and Metadata Recovery." ACM Transactions on Embedded Computing Systems 21, no. 1 (January 31, 2022): 1–32. http://dx.doi.org/10.1145/3492735.
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Emerging byte-addressable Non-Volatile Memory (NVM) technology, although promising superior memory density and ultra-low energy consumption, poses unique challenges to achieving persistent data privacy and computing security, both of which are critically important to the embedded and IoT applications. Specifically, to successfully restore NVMs to their working states after unexpected system crashes or power failure, maintaining and recovering all the necessary security-related metadata can severely increase memory traffic, degrade runtime performance, exacerbate write endurance problem, and demand costly hardware changes to off-the-shelf processors. In this article, we designed and implemented ARES, a new FPGA-assisted processor-transparent security mechanism that aims at efficiently and effectively achieving all three aspects of a security triad—confidentiality, integrity, and recoverability—in modern embedded computing. Given the growing prominence of CPU-FPGA heterogeneous computing architectures, ARES leverages FPGA’s hardware reconfigurability to offload performance-critical and security-related functions to the programmable hardware without microprocessors’ involvement. In particular, recognizing that the traditional Merkle tree caching scheme cannot fully exploit FPGA’s parallelism due to its sequential and recursive function calls, we (1) proposed a Merkle tree cache architecture that partitions a unified cache into multiple levels with parallel accesses and (2) further designed a novel Merkle tree scheme that flattened and reorganized the computation in the traditional Merkle tree verification and update processes to fully exploit the parallel cache ports and to fully pipeline time-consuming hashing operations. Beyond that, to accelerate the metadata recovery process, multiple parallel recovery units are instantiated to recover counter metadata and multiple Merkle sub-trees. Our hardware prototype of the ARES system on a Xilinx U200 platform shows that ARES achieved up to 1.4× lower latency and 2.6× higher throughput against the baseline implementation, while metadata recovery time was shortened by 1.8 times. When integrated with an embedded processor, neither hardware changes nor software changes are required. We also developed a theoretical framework to analytically model and explain experimental results.
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SAMARIN, NIKOLAY N. "SOLUTION FOR A SOURCE CODE-LESS SOFTWARE INFORMATION SECURITY ASSESSMENT." H&ES Research 13, no. 2 (2021): 25–34. http://dx.doi.org/10.36724/2409-5419-2021-13-2-25-34.
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Introduction: Digitalisation affects all sectors of human activity, resulting in the creation of a variety of software that implements business logic and technical processes in complex systems. Under these conditions, the issue of identifying malware becomes even more important. The solution to this problem is complicated by the lack of source code and the need to quickly make a decision on the presence or absence of malicious functionality. Research Aim: The aim of the research is to create an approach to assess the information security of software without source code. It is proposed that the approach is based on the use of a hypervisor that provides control over the operation of software with memory as a key characteristic of the presence/absence of its malicious functionality. It is proposed to calculate a software security score as a security metric. Methods: the solution of the set issue is based on the use of virtualization mechanism providing control over all operations over the memory realized by the software and on the use of probability theory methods to get a complex security estimate which takes into account the reliability of the software functioning and its security. Results: the methodology of getting a complex estimation of software functioning security is developed which takes into account the security of software functioning; network security — vulnerabilities and network ports detected by scanning; potentially insecure changes in file system and register and also potentially dangerous operations connected with the use of memory. The architecture of the software prototype that implements the proposed approach is described and its experimental testing is carried out, as a result of which only regular software samples received high security assessment. Practical significance: the developed system can be used for automated analysis of software operating in various complex systems. An important advantage of the software prototype is its scalability and trustworthiness ensured through the use of virtualization tools that do not allow damaging the work of a computer system in case of detection of malicious software.
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Wei, Chih-Chiang, and Hao-Chun Chang. "Forecasting of Typhoon-Induced Wind-Wave by Using Convolutional Deep Learning on Fused Data of Remote Sensing and Ground Measurements." Sensors 21, no. 15 (August 2, 2021): 5234. http://dx.doi.org/10.3390/s21155234.
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Taiwan is an island, and its economic activities are primarily dependent on maritime transport and international trade. However, Taiwan is also located in the region of typhoon development in the Northwestern Pacific Basin. Thus, it frequently receives strong winds and large waves brought by typhoons, which pose a considerable threat to port operations. To determine the real-time status of winds and waves brought by typhoons near the coasts of major ports in Taiwan, this study developed models for predicting the wind speed and wave height near the coasts of ports during typhoon periods. The forecasting horizons range from 1 to 6 h. In this study, the gated recurrent unit (GRU) neural networks and convolutional neural networks (CNNs) were combined and adopted to formulate the typhoon-induced wind and wave height prediction models. This work designed two wind speed prediction models (WIND-1 and WIND-2) and four wave height prediction models (WAVE-1 to WAVE-4), which are based on the WIND-1 and WIND-2 model outcomes. The Longdong and Liuqiu Buoys were the experiment locations. The observatory data from the ground stations and buoys, as well as radar reflectivity images, were adopted. The results indicated that, first, WIND-2 has a superior wind speed prediction performance to WIND-1, where WIND-2 can be used to identify the temporal and spatial changes in wind speeds using ground station data and reflectivity images. Second, WAVE-4 has the optimal wave height prediction performance, followed by WAVE-3, WAVE-2, and WAVE-1. The results of WAVE-4 revealed using the designed models with in-situ and reflectivity data directly yielded optimal predictions of the wind-based wave heights. Overall, the results indicated that the presented combination models were able to extract the spatial image features using multiple convolutional and pooling layers and provide useful information from time-series data using the GRU memory cell units. Overall, the presented models could exhibit promising results.
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Horst, Nicole K., and Mark Laubach. "Working with memory: evidence for a role for the medial prefrontal cortex in performance monitoring during spatial delayed alternation." Journal of Neurophysiology 108, no. 12 (December 15, 2012): 3276–88. http://dx.doi.org/10.1152/jn.01192.2011.
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Neuronal spike activity was recorded in the medial prefrontal cortex (mPFC) as rats performed an operant spatial delayed alternation task. The sensitivities of neurons to choice, outcome, and temporal information-related aspects of the task were examined. About one-third of neurons were sensitive to the location of delayed responding while animals were at one of two spatially distinct response ports. However, many fewer neurons (<10%) maintained choice information over the delay, each exhibiting persistent differences in firing rates for only a portion of the delay. Another third of cells encoded information about behavioral outcomes, and some of these neurons (>20% of all cells) fired at distinct rates in advance of correct and incorrect responses (i.e., prospective encoding of outcome). Other cells were sensitive to reward-related feedback stimuli (>20%), the outcome of the preceding trial (retrospective encoding, 5–10%), and/or the time since a trial was last performed (10–20%). An anatomical analysis of the recording sites found that cells that were sensitive to choice, temporal, and outcome information were commingled within the middle layers of the mPFC. Together, our results suggest that spatial processing is only part of what drives mPFC neurons to become active during spatial working memory tasks. We propose that the primary role of mPFC in these tasks is to monitor behavioral performance by encoding information about recent trial outcomes to guide expectations and responses on the current trial. By encoding these variables, the mPFC is able to exert control over action and ensure that tasks are performed effectively and efficiently.
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Marcus, Lloyde George, and Innocent-George Nora. "Development of a general purpose First-In-First-Out (FIFO) core." i-manager's Journal on Circuits and Systems 10, no. 1 (2022): 1. http://dx.doi.org/10.26634/jcir.10.1.18663.
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First-In-First-Out cores (FIFOs) are memory storage elements that are used in digital systems for buffering data through a system for later processing. This paper presents the design and implementation of a General Purpose FIFO Core which allows adjustment of the capacity along with the size of each data word. Status indicators were provided to indicate whether or not the FIFO was empty, half-full, or full. The number of data words stored in the FIFO was also indicated by designated output ports of the system. A status flag was also available to indicate when the size reached a predetermined threshold value. A separate interface was provided that allowed the data at any address to be accessed for reading. It was also possible to write a data word to the back of the FIFO while another data word was read from the front simultaneously. The FSM-D architectural model was applied to the design of the FIFO Core and the implementation was done in VHDL using the Xilinx ISE 14.7. The implemented core was simulated using ISim Logic Simulator of the Xilinx ISE platform, and it was found that the system core behaved as specified by the test cases.
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Arapu, Valentin. "Plague – ”The Turkish disease”: a traditional Romanian perception (historical, theological, ethnological and epidemiological aspects)." Journal of Ethnology and Culturology 30 (December 2021): 5–10. http://dx.doi.org/10.52603/rec.2021.30.01.
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The article addresses the issue of the traditional Romanian perception of the plague as ”Turkish disease” and presents relevant historical, theological, ethnological and epidemiological information. This perception is based on the memory of the frequent wars waged by the Ottomans on Romanian territory; wars during which contagious diseases were recurrent, and implicitly the plague. In historiography, the invocation of the plague epidemics in the context of Ottoman history was nuanced in the works of Mihail Critobul from Imbros, Dimitrie Cantemir, Montesquieu, Constantin Bazili. The reluctance of the natives towards the Turks is explained by the cultural, religious and linguistic differences, by the behavior of the Ottomans and by the non-acceptance of the other’s values. The inhabitants of the principalities believed that the plague also entered through the Ottoman ships coming from Constantinople and moored in the ports of Galați and Brăila. The epidemiological phobias of the natives were amplified by the fact that the Turks, especially those from the royal family, neglected any sanitary restrictions during the plague epidemics. The Ottoman plague’s fatalism is explained by their religious beliefs. The divine factor is also invoked in Romanian folklore, the plague being perceived as God’s punishment sent to the Turks for the misfortunes brought to the Romanians.
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CAPPELLO, FRANCK, PIERRE FRAIGNIAUD, BERNARD MANS, and ARNOLD L. ROSENBERG. "AN ALGORITHMIC MODEL FOR HETEROGENEOUS HYPER-CLUSTERS: RATIONALE AND EXPERIENCE." International Journal of Foundations of Computer Science 16, no. 02 (April 2005): 195–215. http://dx.doi.org/10.1142/s0129054105002942.
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A formal model of hyperclusters of processors—that is, clusters of clusters of … of clusters of processors—is formulated. The model characterizes a hypercluster ℋ via a suite of parameters that expose the computational and communicational powers of ℋ's constituent processors and networks. The hyperclusters studied enjoy heterogeneity along three orthogonal axes. (1) The processors that populate a hypercluster may differ in computational powers (speed of computation and memory access). (2) The clusters comprising a hypercluster are organized hierarchically and are interconnected via a hierarchy of networks of possibly differing bandwidths and speeds. (3) The clusters at each level of the hierarchy may differ in sizes. The resulting HiHCoHP model is rather detailed, exposing architectural features such as the bandwidth and transit costs of both networks and their ports. The algorithmic tractability of the model is demonstrated by reviewing two case studies that use the model to study heterogeneous clusters (HNOWs, for short). The first study develops an algorithm for the trigger-broadcast problem in HNOWs, in which a broadcast "triggers" personalized computations at each node of the cluster. The algorithm is predictably efficient in general and is actually optimal in special circumstances. The second study develops an asymptotically optimal algorithm for sharing a large "bag of tasks" within an HNOW.
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Namgung, Ho, and Joo-Sung Kim. "Regional Collision Risk Prediction System at a Collision Area Considering Spatial Pattern." Journal of Marine Science and Engineering 9, no. 12 (December 2, 2021): 1365. http://dx.doi.org/10.3390/jmse9121365.
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To reduce the risk of collision in territorial sea areas, including trade ports and entry waterways, and to enhance the safety and efficiency of ship passage, the International Maritime Organization requires the governing body of every country to establish and operate a vessel traffic service (VTS). However, previous studies on risk prediction models did not consider the locations of near collisions and actual collisions and only employed a combined collision risk index in surveillance sea areas. In this study, we propose a regional collision risk prediction system for a collision area considering spatial patterns using a density-based spatial clustering of applications with noise (DBSCAN). Furthermore, a fuzzy inference system based on a near collision (FIS-NC) and long short-term memory (LSTM) is adopted to help a vessel traffic service operator (VTSO) make timely optimal decisions. In the local spatial pattern stage, the ship trajectory was determined by identifying the actual-collision and near-collision locations simultaneously. Finally, the system was developed by learning a sequence dataset from the extracted trajectory of the ship when a collision occurred. The proposed system can recommend an action faster than the fuzzy inference system based on the near-collision location. Therefore, using the developed system, a VTSO can quickly predict ship collision risk situations and make timely optimal decisions at dangerous surveillance sea areas.
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KISH, LASZLO B., and OLIVIER SAIDI. "UNCONDITIONALLY SECURE COMPUTERS, ALGORITHMS AND HARDWARE, SUCH AS MEMORIES, PROCESSORS, KEYBOARDS, FLASH AND HARD DRIVES." Fluctuation and Noise Letters 08, no. 02 (June 2008): L95—L98. http://dx.doi.org/10.1142/s0219477508004362.
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In the case of the need of extraordinary security, Kirchhoff-loop-Johnson-(like)-noise ciphers can easily be integrated on existing types of digital chips in order to provide secure data communication between hardware processors, memory chips, hard disks and other units within a computer or other data processor system. The secure key exchange can take place at the very first run and the system can renew the key later at random times with an authenticated fashion to prohibit man-in-the-middle attack. The key can be stored in flash memories within the communicating chip units at hidden random addresses among other random bits that are continuously generated by the secure line but are never actually used. Thus, even if the system is disassembled, and the eavesdropper can have direct access to the communication lines between the units, or even if she is trying to use a man-in-the-middle attack, no information can be extracted. The only way to break the code is to learn the chip structure, to understand the machine code program and to read out the information during running by accessing the proper internal ports of the working chips. However such an attack needs extraordinary resources and even that can be prohibited by a password lockout. The unconditional security of commercial algorithms against piracy can be provided in a similar way.
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Shaik, Cheman. "Detection of Forgery and Fabrication in Passports and Visas using Cryptography and QR Codes." Advanced Computing: An International Journal 12, no. 1 (January 31, 2021): 1–11. http://dx.doi.org/10.5121/acij.2021.12101.
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In this paper, we present a novel solution to detect forgery and fabrication in passports and visas using cryptography and QR codes. The solution requires that the passport and visa issuing authorities obtain a cryptographic key pair and publish their public key on their website. Further they are required to encrypt the passport or visa information with their private key, encode the ciphertext in a QR code and print it on the passport or visa they issue to the applicant. The issuing authorities are also required to create a mobile or desktop QR code scanning app and place it for download on their website or Google Play Store and iPhone App Store. Any individual or immigration uthority that needs to check the passport or visa for forgery and fabrication can scan its QR code, which will decrypt the ciphertext encoded in the QR code using the public key stored in the app memory and displays the passport or visa information on the app screen. The details on the app screen can be compared with the actual details printed on the passport or visa. Any mismatch between the two is a clear indication of forgery or fabrication. Discussed the need for a universal desktop and mobile app that can be used by immigration authorities and consulates all over the world to enable fast checking of passports and visas at ports of entry for forgery and fabrication
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Malliri, A., K. Siountri, E. Skondras, D. D. Vergados, and C. N. Anagnostopoulos. "THE ENHANCEMENT OF UNDERWATER CULTURAL HERITAGE ASSETS USING AUGMENTED REALITY (AR)." ISPRS - International Archives of the Photogrammetry, Remote Sensing and Spatial Information Sciences XLII-2/W10 (April 17, 2019): 119–25. http://dx.doi.org/10.5194/isprs-archives-xlii-2-w10-119-2019.
Full textAbstract:
<p><strong>Abstract.</strong> Τhe development in the fields of Underwater Cultural Heritage (UCH) management and Maritime Archaeology, yields an interdisciplinary and creative academic framework, such as the Information and Communication Technologies (ICT) sector that has been proved to build intelligent systems and applications. However, the ways to fully make use of these technologies are still being explored, as their potential have not been exploited yet. Underwater archaeological sites, semi (/or fully) submerged settlements, ancient ports and shipwrecks, unlike land sites, are not accessible to public due to their special (sub) marine environment and depth. In this paper, an innovative research idea of using Augmented Reality (AR) for maintaining the memory and the information of underwater archaeological sites, is presented. Although the “artificial” visual documentation cannot replace the authentic values of the underwater tangible heritage, the AR technology can contribute to the protection of the intangible properties and the conquered knowledge of the past of a place. This research work will focus, among other case studies, on the (semi) submerged fortifications and their contiguous contents of the acropolis of Halai in east Lokris, Greece. Hence, along with the climate change that may lead more antiquities covered by water during the following years, the advances in the communication field and the up-coming 5G and cloud technologies will make the idea fully applicable, contributing to the enhancement of the coastal and the underwater archaeological remains.</p>
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., Shambhavi. "Router1x3 Protocol Design Implementation and Verification with Virtual Cut through Mechanism for Network on Chip (NoC)." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 10, 2021): 16–24. http://dx.doi.org/10.22214/ijraset.2021.36226.
Full textAbstract:
Hundreds of processors and memory cores are implemented on a single substrate called the System on Chip (SoC). The SoC with bus-based architecture has restrictions on the processing speed of the system and as the design becomes complex and the issue of scalability arises. Hence NoC is designed to enhance the scalability, data reliability, and processing speed with low power consumption by decoupling communication from computations [1]. Using NoC the IP cores of SoC are connected through on-chip routers and send data to each other through packet switching. The router is a processing chip that decides the right path for data transmission, hence the efficient design of the router is essential to enhance the performance and throughput of the system [2]. To reduces latency through the switch, the Virtual cut-through mechanism is a packet switching technique, in which the switch starts forwarding a packet as soon as the destination address is processed by header. Hence the present work focuses on a router input-output protocol design with the Virtual Cut-through mechanism for closed-loop communication. Router 1x3 has a single input port and three output ports. The architecture of Router 1x3 with sub-modules such as FIFO, FSM, Synchronizer, and Register is designed analyzed and verified using Verilog, System Verilog language, and Universal Verification Methodology(UVM). And it is also implemented on Xilinx 14.5 IDE with Spartan-6- XC6SLX45 FPGA.