Relevant bibliographies by topics / MEMORY PORTS

Academic literature on the topic 'MEMORY PORTS'

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Published: 11 September 2023

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Journal articles on the topic "MEMORY PORTS"

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Townsend, Kevin R., Osama G. Attia, Phillip H. Jones, and Joseph Zambreno. "A Scalable Unsegmented Multiport Memory for FPGA-Based Systems." International Journal of Reconfigurable Computing 2015 (2015): 1–12. http://dx.doi.org/10.1155/2015/826283.

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On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.
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C, Chandrashekar, and Dr Basavaraj I Neelgar. "Design and implementation of Dual-Port Memory." Journal of University of Shanghai for Science and Technology 23, no. 06 (June 26, 2021): 1716–22. http://dx.doi.org/10.51201/jusst/21/06478.

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Multiport memory cell using a dual-port memory cell provides required access to multi-processor-based applications. Simultaneous access can be provided using two-pass transistors, pair of bit lines, and a word line. Using specific word lines and bit lines of SRAM cell access can be provided by using dual ports memory. The single address of a memory cell can be accessed at a time during each clock pulse using single-port SRAM this drawback can be overcome by using dual-port RAM which supports concurrent read or writes access at different addresses. Efficiency is improved by using dual-port RAM. Each processor can be made to operate at different clock frequencies thereby dual-port RAM will not have any limitations of access between the two ports.
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Chen, Chien-In Henry. "Using PDM on Multiport Memory Allocation in Data Path." VLSI Design 1, no. 3 (January 1, 1994): 217–32. http://dx.doi.org/10.1155/1994/62462.

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A data path consists of memory elements (i.e. registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to memory synthesis have been proposed in the literature. However, only single port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. In this paper, an efficient method, Partitioned Dependence Matrix (PDM), is presented for memory synthesis which deals not only with single port memory synthesis but also multiport memory synthesis according to the design constraints. With suitable modifications, the proposed technique can also be applied to multiport memory synthesis in which the maximum number of read ports is different from the maximum number of write ports. Therefore, the entire design space is explored and has the capability to handle early architectural design exploration so that the quality of designs produced by an automatic synthesis tool is more adequate for production use in comparison to manual design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. A key element in our approach is the successful adoption of techniques originally developed for problems in test generation to the field of memory synthesis.
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CARBALLO, DANIEL J., INMACULADA PARDINES, and MARCOS SANCHEZ-ELEZ. "A RECONFIGURABLE MODULAR ARCHITECTURE TO EXPLOIT WORD-LEVEL PARALLELISM." Journal of Circuits, Systems and Computers 18, no. 07 (November 2009): 1227–41. http://dx.doi.org/10.1142/s0218126609005630.

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Contemporary memory system design aims to achieve high performance and low energy consumption at a reasonable cost. To balance these requirements, we propose a modular reconfigurable architecture to design memories over FPGAs. The proposed memory system can be reconfigured taking into account: the number of words, the word size of the data, the number of physical memory banks and the number of ports of the banks. Different operating modes have been defined, each one implying a certain configuration for the memory system. Simulations of these modes show the performance of our reconfigurable memory in terms of timing and power consumption.
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Rotem, Nadav, and Yosi Ben Asher. "Combining static and dynamic array detection for binary synthesis with multiple memory ports." Design Automation for Embedded Systems 15, no. 1 (November 30, 2010): 1–18. http://dx.doi.org/10.1007/s10617-010-9065-z.

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Ditmar, Johan, Steve McKeever, and Alex Wilson. "Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation." International Journal of Reconfigurable Computing 2008 (2008): 1–14. http://dx.doi.org/10.1155/2008/674340.

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This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs.
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Lin, Zhiting, Honglan Zhan, Xuan Li, Chunyu Peng, Wenjuan Lu, Xiulong Wu, and Junning Chen. "In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, no. 5 (May 2020): 1316–20. http://dx.doi.org/10.1109/tvlsi.2020.2976099.

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Deng, Jiang Ming, Te Fang Chen, and Shu Cheng. "MVB-Based Dynamic Supervision of Docks in Traffic Memory." Advanced Materials Research 403-408 (November 2011): 2728–31. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.2728.

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A high reliability of Traffic Memory(TM) working condition is of vital importance to information transfer in MVB. In order to avoid bus traffic overflows, the minimum possible time intervals or loading ratios of TM for a given number of ports were calculated. The longer supervision period it had, the more number of docks could be supervised. The number of docks supervised, during supervision intervals, was submitted to Normal distribution ( Ν(μ,σ2)). From the possibility distribution function it could σfind maximum possibility of the number of docks in working. From the disturbance rejection test of the fixed factor σ , a reasonable setting of sink-time supervision interval could be made to guarantee a high reliability for TM working condition.
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Mansoursamaei, Meead, Mahmoud Moradi, Rosa G. González-Ramírez, and Eduardo Lalla-Ruiz. "Machine Learning for Promoting Environmental Sustainability in Ports." Journal of Advanced Transportation 2023 (March 3, 2023): 1–17. http://dx.doi.org/10.1155/2023/2144733.

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Maritime transportation is one of the essential drivers of the global economy as it enables both lower transportation costs and intermodal operations across multiple forms of transportation. Maritime ports are essential interfaces that support cargo handling between sea and hinterland transportation. Besides, in this area, environmental protection is becoming extremely important. Global warming, air pollution, and greenhouse gas emissions are all having a detrimental influence on the environment and will most likely continue to do so for future generations. Hence, there is a growing need to promote environmental sustainability in maritime-based transportation. The application of machine learning (ML), as one of the main subdomains of artificial intelligence (AI), can be considered a component within the process of digital transformation to advance green activities in maritime port logistics. Thus, this article presents the results of a systematic literature review of the recent literature on machine learning for promoting environmentally sustainable maritime ports. It collects and analyses the articles whose contributions lie in the interplay between three main dimensions, i.e., machine learning, port-related operations, and environmental sustainability. Throughout a review protocol, this research is constituted on the major focuses of impact, problems, and techniques to discern the current state of the art as well as research directions. The research findings indicate that the articles using polynomial regression models are dominant in the literature, and the recurrent neural network (RNN) and long short-term memory (LSTM) are the most recent approaches. Moreover, in terms of environmental sustainability, emissions and energy consumption are the most studied problems. mAccording to the research gaps observed in the review, two broad directions for future research are identified: (i) altering attention on a greater diversity of machine learning approaches for promoting environmental sustainability in ports and (ii) leveraging new outlooks to perform more green practical works on port-related operations.
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Kumar, Sanjeev, and Alvaro Munoz. "Comparison of Memory Assignment Schemes for Switch Architectures with Shareable Parallel Memory Modules." Journal of Electrical and Computer Engineering 2010 (2010): 1–7. http://dx.doi.org/10.1155/2010/126591.

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Switching Architectures deploying shareable parallel memory modules are quite versatile in their ability to scale to higher capacity while retaining the advantage of sharing its entire memory resource among all input and output ports. The two main classes of such architectures, namely, the Shared Multibuffer-(SMB-) based switch and the Sliding-Window-(SW-) based packet switch, both deploy parallel memory modules that are physically separate but logically connected. Inspite of their similarity in regards to using shareable parallel memory modules, they differ in switching control and scheduling of packets to parallel memory modules. SMB switch uses centralized control whereas the SW switch uses a decentralized control for switching operations. In this paper, we present a new memory assignment scheme for the Sliding-Window (SW) switch for assigning packets to parallel memory modules that maximizes the parallel storage of packets to multiple memory modules. We compare the performance of a sliding-window switch deploying this new memory assignment scheme with that of an SMB switch architecture under conditions of identical traffic type and memory resources deployed. The simulation results show that the new memory assignment scheme for the sliding window switch maximizes parallel storage of packets input in a given switch cycle, and it does not require speed-up of memory modules. Furthermore, it provides a superior performance compared to that of the SMB switch under the constraints of fixed memory-bandwidth and memory resources.
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Dissertations / Theses on the topic "MEMORY PORTS"

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Calchand, Nandish Rajpravin. "Modeling and control of magnetic shape memory alloys using port hamiltonian framework." Thesis, Besançon, 2014. http://www.theses.fr/2014BESA2074/document.

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Les matériaux actifs sont des matériaux qui réagissent quand on leur applique un champ extérieur comme la température, la lumière, un champ magnétique ou un champ électrique. Ces champs changent les propriétés du matériau comme la longueur, la susceptibilité magnétique ou la permittivité électrique. Ces changements peuvent être utilisé pour faire du travail. Quelques exemples sont les matériaux piézoélectriques, qui changent de longueur quand on applique un champ électrique, les alliages à mémoire de forme qui changent leur longueur sous l’action de la température. Un matériau plus récent qu’on appelle les alliages mémoire de forme magnétique se de forme sous l’action d’un champ magnétique. Dans cette thèse, on utilise ce matériau pour Confectionner un actionneur. Pour ce faire, on utilise la thermodynamique des procédés irréversibles pour modéliser le matériau. La thermodynamique s’avère très versatile pour ce type de matériau car il permet de quantifier l’ échange et la transformation d’ énergie dans le matériau. Aussi, étant donné que le matériau se comporte d’une façon non-linéaire et hystérique, le cadre énergétique nous permets justement de prendre en compte ces non- linearités. Cette thèse utilise l’approche énergétique notamment les Hamiltonien à ports pour modéliser un actionneur à base d’alliage à mémoire de forme. Cette méthode nous permets aussi de concevoir des lois de commande pour contrôler le matériau
Active materials are a class of material which react to an external stimulus such as temperature,photons, magnetic field or electric field. These stimuli cause some properties of the material tochange usually their length. Some examples are piezoelectric material which change their lengthunder the action of an electric field, Shape Memory alloys which alter their shape on applicationof heat, and more recently Magnetic Shape Memory Alloys (MSMA) which undergo a deformationon application of a magnetic field. Harnessing this property of MSMAs, we hereby present anactuator using this novel material. We extensively make use of an energy framework, namely thethermodynamics of irreversible processes to model the material. This framework has been provento be very versatile in modelling energy exchange and transformation as it occurs in the materialand also to incorporate hysteresis which arises naturally in such materials. Another advantage of thismethod is its ability to give us constitutive laws based on simple assumptions. Furthermore, usingan energy framework allows us to apply some energy based control. Port Hamiltonian Control is onesuch method and it is not limited only to linear models. This latter characteristic has proven veryuseful since MSMAs are very non-linear in nature
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Silva, Nuno Miguel Correia da. "Porta de mar." Doctoral thesis, Universidade de Lisboa, Faculdade de Arquitetura, 2016. http://hdl.handle.net/10400.5/13637.

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Atwell, James W. "A Multiplexed Memory Port for Run Time Reconfigurable Applications." Thesis, Virginia Tech, 1999. http://hdl.handle.net/10919/36219.

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Configurable computing machines (CCMs) are available as plug in cards for standard workstations. CCMs make it possible to achieve computing feats on workstations that were previously only possible with super computers. However, it is difficult to create applications for CCMs. The development environment is fragmented and complex. Compilers for CCMS are emerging but they are in their infancy and are inefficient.

The difficulties of implementing run time reconfiguration (RTR) on CCMs are addressed in this thesis. Tools and techniques are introduced to simplify the development and synthesis of applications and partitions for RTR applications. A multiplexed memory port (MMP) is presented in JHDL and VHDL that simplifies the memory interface, eases the task of writing applications and creating partitions, and makes applications platform independent. The MMP is incorporated into an existing CCM compiler. It is shown that the MMP can increase the compiler's functionality and efficiency.
Master of Science

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Tomás, Ana Catarina Albuquerque. "Porto de abrigo, porto de pesca." Master's thesis, Universidade de Lisboa, Faculdade de Arquitetura, 2019. http://hdl.handle.net/10400.5/18459.

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Dissertação de Mestrado Integrado em Arquitetura, com a especialização em Arquitetura apresentada na Faculdade de Arquitetura da Universidade de Lisboa para obtenção do grau de Mestre.
O presente trabalho parte do interesse pelo tema lugares de memória e como estes, cada vez mais procurados pelo homem contemporâneo, se apresentam como um meio de tranquilizar as constantes crises identitárias que se têm tornado cada vez mais recorrentes. Pela fragmentação dos espaços vividos, intenta-se, através do ato de projectar, exprimir a natureza, a história, a tradição e a sociedade do lugar escolhido, num objecto de clara e transparente lógica espacial. Da escolha da baía de Sines, como o lugar de intervenção, motivada pelo desaparecimento gradual da identidade secular marítima, atualmente ameaçada, tornara-se fundamental o estudo e interpretação da sua condição de pertença naquele que é, hoje, um dos maiores portos industriais de Portugal. Criando uma nova oportunidade para a reconstrução de um discurso coeso entre Sines e o mar, entretanto quebrada, o Porto de Abrigo, enquadrado numa das propostas dadas à baía – o Percurso de Memória – pretende-se que este seja o resultado de um culminar de intenções da restituição da memória e da identidade. Através das características excecionais que o envolvem, este será um lugar reflexivo, um lugar de memória que, não só se tornará capaz de acentuar a condição excecional da baía, como a identidade piscatória local.
ABSTRACT: The present work is based on the interest on ‘lugares de memória ‘(places of memory) and how these, increasingly searched by the contemporary man, are presented as a means of reassuring the constant crises of identity that has become increasingly recurrent. By fragmenting the spaces, through the act of design, it is intended to express the nature, history, tradition and society of the chosen place, in an object of clear and transparent spatial logic. The choice of Sines Bay, as the place of intervention, motivated by the gradual disappearance of the secular maritime identity, currently threatened, it has become fundamental to study and interpret its condition of belonging, in what is today, one of the largest industrial ports of Portugal. Creating a new opportunity for the reconstruction of a cohesive interaction between Sines and the sea, meanwhile broken, the ‘Porto de Abrigo’ (shelter harbour), framed in one of the proposals given to the bay - the ‘Percurso de Memória’ (Memory Path) - is intended to be the culmination of restitution of memory and identity. By the exceptional characteristics that surround it, this will be a reflective place, a place of memory that will not only be able to accentuate the exceptional condition of the bay, but the local fishing identity.
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Taretto, Erika. "Poets and places : sites of literary memory in the Hellenistic world." Thesis, Durham University, 2017. http://etheses.dur.ac.uk/12223/.

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This dissertation argues for the existence of a widespread yet underexplored Hellenistic habit of linking the memory of archaic and classical Greek poets to specific places. Through a combination of in-depth case studies and a panoramic overview of Hellenistic sites of literary memory, the dissertation establishes the significance of literary geographies and explores the means through which they were established. The first chapter focuses on the house of Pindar and its alleged treatment on the part of Alexander the Great. The second chapter investigates the memorialisation of Homer in Alexandria, showing that the desire to shape literary geographies fundamentally shapes the identity of the new Egyptian city. The third chapter moves from the centre to the periphery of the Hellenistic world and focuses on the best documented case of a site of memory dedicated to an ancient poet: the Archilocheion on Paros. The fourth and last chapter offers an overview of the evidence for Hellenistic sites dedicated to the memory of archaic and classical poets in the Hellenistic age. By demonstrating that sites of literary of memory are an important Hellenistic aspect of the reception of poetry, this dissertation hopes to open the way to further studies about both the Hellenistic and later literary geographies.
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Barros, Mariana Sardinha. "O SAGRADO CORAÇÃO DE PORTO NACIONAL." Pontifícia Universidade Católica de Goiás, 2008. http://localhost:8080/tede/handle/tede/2287.

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In this work, we visualize the city of Porto Nacional (TO) by the lenses of memory of its residents on the Sagrado Coração de Jesus School, founded by French Dominican sisters in 1904. The arrival of religious, representatives of the discourse on the "civilization" can be interpreted as an attempt to domestication of the hinterland. The meanings articulated by the community in memory of former students and teachers of the School, which tell us about the collective memory, references are built and constantly reinforced, featuring a process of formation and assertion of identity. The space occupied by the School, yesterday and today, are places of memory, as they are loaded with symbolic value and evoke memories of those who lived there or those who have heard stories about him. They are places where the memory is crystallized and passed. Important in the history of Porto Nacional and reference to the people, the School is the cultural heritage of the city.
Neste trabalho, visualizamos a cidade de Porto Nacional (TO) pelas lentes da memória de seus moradores sobre o Colégio Sagrado Coração de Jesus, fundado por irmãs dominicanas francesas em 1904. A chegada das religiosas, representantes do discurso sobre a civilização , pode ser interpretada como uma tentativa de domesticação do sertão. Os significados articulados pela comunidade de memória dos ex-alunos e professores do Colégio, que nos informam sobre a memória coletiva, são referências construídas e constantemente reforçadas, caracterizando um processo de constituição e afirmação de identidade. Os espaços ocupados pelo Colégio, ontem e hoje, são lugares de memória, pois são carregados de valor simbólico e evocam lembranças daqueles que lá viveram ou dos que ouviram histórias sobre ele. São lugares onde a lembrança é cristalizada e transmitida. Importante para a história de Porto Nacional e referência para os portuenses, o Colégio é patrimônio cultural da cidade.
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Costa, Ângelo Miguel Faria da. "Prevenção de lesões do membro inferior em futebolistas." Master's thesis, Instituto de Ciências Biomédicas Abel Salazar, 2010. http://hdl.handle.net/10216/63623.

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Costa, Ângelo Miguel Faria da. "Prevenção de lesões do membro inferior em futebolistas." Dissertação, Instituto de Ciências Biomédicas Abel Salazar, 2010. http://hdl.handle.net/10216/63623.

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Simões, Elvis Silveira. "No centro e à margem: a trajetória histórica dos trabalhadores arrumadores de Rio Grande-RS, entre as décadas de 1950/60." Universidade Federal de Pelotas, 2017. http://guaiaca.ufpel.edu.br:8080/handle/prefix/4174.

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES
presente pesquisa tem como objetivo analisar as memórias e as experiências dos trabalhadores arrumadores de Rio Grande-RS, entre as décadas de 1950/60. Neste sentido, as análises buscaram destacar as tomadas de decisões e disputas dos trabalhadores, os quais visaram realizar a transição de Sindicato do Comércio Armazenador, para Sindicato dos Arrumadores de Rio Grande, a luz da Lei 2.196, de 1º de abril de 1954, abrangendo assim seu campo de atuação para o comércio, indústria e o Porto. Conjuntamente, analisaremos como se inseriram nestes distintos ambientes e estabeleceram suas relações de trabalho e estratégias, assim como buscaram lidar com as inseguranças diante a condição de um trabalhado sazonal e avulso. Para tanto, será a partir das memórias reavivadas dos trabalhadores arrumadores, portuários e consertadores, bem como no diálogo com as demais fontes que buscou-se compreender a trajetória histórica desta categoria.
The present research has the objective of analyzing the memories and the experiences of the laborers of Rio Grande-RS, between the decades of 1950/60. In this sense, the analyzes sought to highlight the decision-making and disputes of the workers, which aimed to carry out the transition from Trade Union of Storage Trade, to Union of Arrumadores of Rio Grande, in light of Law 2.196, of April 1, 1954, covering so its field of action for commerce, industry and Porto. Together, we will analyze how they were inserted in these different environments and established their working relationships and strategies, as well as trying to deal with the insecurities faced with the condition of a seasonal and isolated worker. To do so, it will be from the revived memories of the ushers, port workers and repairers, as well as in the dialogue with the other sources that sought to understand the historical trajectory of this category.
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Marques, Marina Sofia Quitério. "Sentimento de perda: vivências da mulher com amputação do membro inferior." Master's thesis, Instituto de Ciências Biomédicas Abel Salazar, 2008. http://hdl.handle.net/10216/7150.

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Books on the topic "MEMORY PORTS"

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(Society), Kathā, ed. Sketches from memory. New Delhi: Katha, 2007.

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Memory and fire: Ten American Jewish poets. New York: P. Lang, 1989.

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Ivănescu, Mircea, Adam J. Sorkin, Radu Andriescu, Cristian Popescu, and Bogdan Ștefănescu. Memory glyphs: 3 prose poets from Romania. Prague: Twisted Spoon, 2009.

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Meaning & memory: Interviews with fourteen Jewish poets. Columbus: Ohio State University Press, 2001.

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Cadenhead, Kenneth. James Cadenhead, RSA: Keeping his memory green. Auburn, Ala. (259 Conrey Dr., Auburn 36830): K. Cadenhead, 2003.

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Cadenhead, Kenneth. James Cadenhead RSA: Keeping his memory green. Auburn: Kenneth Cadenhead, 2003.

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Driving with Dvořák: Essays on memory and identity. Lincoln: University of Nebraska Press, 2010.

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1941-, Coltelli Laura, ed. The spiral of memory: Interviews. Ann Arbor: University of Michigan Press, 1996.

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Memory is the weapon. Grant Park, South Africa: African Perspectives Pub., 2009.

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Mattera, Don. Memory is the weapon. Johannesburg: Ravan Press, 1987.

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Book chapters on the topic "MEMORY PORTS"

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Parodi, Mauro, and Marco Storace. "Basic Concepts: Linear Two-Ports with Memory and Higher-Order Linear Circuits." In Linear and Nonlinear Circuits: Basic and Advanced Concepts, 143–247. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-35044-4_11.

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Conde, Jorge, and Kaspar Loftin. "Recife: Three Poets of Memory." In The Palgrave Encyclopedia of Urban Literary Studies, 1–5. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-62592-8_124-1.

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Conde, Jorge, and Kaspar Loftin. "Recife: Three Poets of Memory." In The Palgrave Encyclopedia of Urban Literary Studies, 1–5. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-319-62592-8_124-2.

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Conde, Jorge, and Kaspar Loftin. "Recife: Three Poets of Memory." In The Palgrave Encyclopedia of Urban Literary Studies, 1583–87. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-319-62419-8_124.

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Piavanini, Joanne. "‘Breaking Bread with the Dead’: Elegies for Poets." In Cultural Memory in Seamus Heaney’s Late Work, 87–124. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-46927-6_4.

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Eckersall, Peter. "Memory and City: Port B and the Tokyo Olympics." In Performativity and Event in 1960s Japan, 132–60. London: Palgrave Macmillan UK, 2013. http://dx.doi.org/10.1057/9781137017383_7.

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Siegfried, Brandie R. "Notorious: Gráinne Ní Mháille, Graven Memory, and the Uses of Irish Legend." In Scholars and Poets Talk about Queens, 233–49. New York: Palgrave Macmillan US, 2015. http://dx.doi.org/10.1057/9781137534903_24.

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Xiong, Wangping, Ji-cheng Shu, Yao-hui Ye, and Caiying Peng. "Research on the Arbiter and Quantum Memory of Multi-Port." In Advances in Intelligent and Soft Computing, 647–52. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-29387-0_101.

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Tomeu, A. J., A. Gámez, and A. G. Salguero. "A Parallel Implementation for Cellular Potts Model with Software Transactional Memory." In Practical Applications of Computational Biology and Bioinformatics, 13th International Conference, 53–60. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-23873-5_7.

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Mazzara, Federica. "Objects, Debris and Memory of the Mediterranean Passage: Porto M in Lampedusa." In Border Lampedusa, 153–73. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59330-2_10.

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Conference papers on the topic "MEMORY PORTS"

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Healey, Peter, and David W. Smith. "Holographic associative memory switching system." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1987. http://dx.doi.org/10.1364/oam.1987.thv3.

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An N × N optical space switch is described which uses holographic associative memory techniques to store switch states. The switch states are stored as follows: Light from one input port is spatially expanded and then phase-front encoded by a spatial light modulator and directed onto a phase volume holographic recording material. Light corresponding to the available output ports is allowed to fall, in turn, to the same region of the holographic medium. By using a unique phase-front code on the input (reference) wave as it is stored in association with each output (object) wave, a multiplexed phase volume hologram with associative recall properties is created. This process is repeated for all N input ports. Crosstalk can be minimized and efficiency maximized by selecting a suitable orthogonal set of reference wave codes and by maximizing the angular separation between the object point sources so that the Bragg extinction angle is exceeded. The main advantage of this type of optical switching system is that all switch states are preprogrammed and may be tailored to particular needs.
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Abdel-Hafeez, Saleh, Sanabel Otoom, and Muhannad Quwaider. "Design of SRAM-based 8T-Cell for Memory Alias Table." In 2nd International Conference on NLP Techniques and Applications (NLPTA 2021). Academy and Industry Research Collaboration Center (AIRCC), 2021. http://dx.doi.org/10.5121/csit.2021.111907.

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Memory Alias Table exploits a major role in Register Renaming Unit (RRU) for maintaining the translation between logical registers to physical registers for the given instruction(s). This work presents the design of the memory Alias Table based on the 8TCell with multiport write, read, and content-addressable operation for 2-WAY three operands machine cycle. Results show that four read ports operate simultaneously within a half-cycle, while two-write ports operate simultaneously within the other half-cycle. The operation of content-addressable with two parallel ports is managed during the half-cycle of the read phase; thus, the three operations occur within a single cycle without latency. HSPICE simulations conduct 32-rows x 6-bit with 21T-Cell memory Alias Table that has 4- read ports, 2-write ports, and 2-content-addressable ports using a standard 65 nm/1V CMOS process. Simulations reveal that the proposed design operates within a one-cycle of 1 GHz consuming an average power of 0.87 mW
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Moreira, José Eduardo. "Multiple Omega Networks for Parallel Processing." In Simpósio Brasileiro de Arquitetura de Computadores e Processamento de Alto Desempenho. Sociedade Brasileira de Computação, 1992. http://dx.doi.org/10.5753/sbac-pad.1992.22711.

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In this paper we propose the use of multiple Omega networks as an interconnection system for shared memory multiprocessors. This allows us to achieve a much higher bandwidth of communication, accommodating the needs of current high-performance processors, including those with multiple memory ports. We also obtain a very scalable system, by defining a processor-switch-memory building block that can be used in systems with processor count in the range of a few units to several thousands. The performance evaluation of multiple Omega networks is clone through a simple analytical model that allows us to compare their performance to a that of a single network, and investigate alternatives for processors with multiple memory ports. The results show that the performance (in terms of bandwidth and latency of communication) of systems with multiple networks is more stable with respect to variations in systems parameters such as number of processors and memory access rate, than that of systems with just a single network.
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"BDI AGENTS WITH FUZZY ASSOCIATIVE MEMORY FOR VESSEL BERTHING IN CONTAINER PORTS." In 6th International Conference on Enterprise Information Systems. SciTePress - Science and and Technology Publications, 2004. http://dx.doi.org/10.5220/0002617403150320.

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Goodrich, Corey. "A Case Study on the Benefits of Functional Memory Access during ATE Test and Electrical Fault Isolation Techniques for Embedded SRAM." In ISTFA 2014. ASM International, 2014. http://dx.doi.org/10.31399/asm.cp.istfa2014p0528.

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Abstract Test coverage of embedded memories is often split between test modes. A BIST solution is typically used to isolate and test the memory array through test specific ports. The functional interconnect between logic and memory is tested with traditional ATPG test modes where a bypass cell on the scan chain is used to clock data through the memory. This approach may miss test coverage if the functional path is different from the test path[1]. Although commercial ATPG tools provide some capability in this area, the most advanced type of fault models which target small delay defects or cross talk faults are not as streamlined as they are for traditional fault models. Additionally, more advanced fault types don’t typically have the same diagnostic capability. In this paper, capabilities are developed for maximizing the effectiveness of test on embedded SRAM interconnects in an ATPG context. Also, a method is outlined to characterize and validate the timing robustness of the memory ports and provide a silicon diagnostic capability for localizing critical paths and isolating physical defects.
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Moon, Soo-Mook, and Kemal Ebcioğlu. "A study on the number of memory ports in multiple instruction issue machines." In Proceedings of 26th Annual International Symposium on Microarchitecture (Cat. No.93TH0602-3). IEEE, 1993. http://dx.doi.org/10.1109/micro.1993.282741.

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Marom, Dan M., Paul Shames, Fang Xu, Ramesh R. Rao, and Yeshayahu Fainman. "Compact Free-Space Multistage Interconnection Network Demonstration." In Optics in Computing. Washington, D.C.: Optica Publishing Group, 1997. http://dx.doi.org/10.1364/oc.1997.othd.3.

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Communication between large numbers of I/O ports will require switching of Terabit aggregate bandwidth to meet the needs of future applications. Advances in fiber amplifiers have increased interest in transparent optical networks which do not rely on data regeneration in the electronic domain. Additionally, since polarization compensation in a single mode fiber [1] allows automatic and stable control of the polarization states of transmitted optical signals, it may enable utilization of polarization dependent all-optical switches. Polarization switching has been proposed for ‘free-space’ multistage interconnection networks (MIN) for switching and multiprocessor interconnections [2-5]. In this paper we present a ‘folded’ optical MIN system that permits switching high-speed signals between multiple input and output nodes. Optical routing is performed by bypass-exchange switches built of birefringent computer generated holograms (BCGH) combined with electrically addressed ferroelectric liquid crystal (FLC) device. This scaleable system can switch high bandwidth communication lines or permit memory access and multiprocessor interconnections. In the following we discuss the system design, network protocol, and performance of our optical MIN.
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Jain, Hardik, Matthew Edwards, Ethan R. Elenberg, Ankit Singh Rawat, and Sriram Vishwanath. "Achieving Multi-port Memory Performance on Single-Port Memory with Coding Techniques." In 2020 3rd International Conference on Information and Computer Technologies (ICICT). IEEE, 2020. http://dx.doi.org/10.1109/icict50521.2020.00065.

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Shaw, Jonathan, Christopher McMahon, Yin Shyang Ng, and Félix Beaudoi. "Dual Port RAM MBIST Failure Analysis Using Time Resolved Dynamic Laser Stimulation." In ISTFA 2008. ASM International, 2008. http://dx.doi.org/10.31399/asm.cp.istfa2008p0188.

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Abstract This paper presents the use of Dynamic Laser Stimulation (DLS) and Time-Resolved DLS (TR-DLS) to provide fail site localization and complementary information on a failed embedded memory IC. In this study, an embedded dual port RAM within a 90nm IC that failed one of the Memory Built-In Self Tests (MBISTs) was investigated. This technique rapidly localized the failing area within the memory read/write circuitry. The TR-DLS provided maps for each operation of the MBIST pattern. With this information, the failure was clearly identified as a read operation failure. The TR-DLS technique also provided much refined site signature (down to just one net) within the sense amp of the Port B of the dual port RAM. This information provided very specific indication on how to improve the operation of that particular sense amp circuitry within the dual port RAM Memory.
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Yijun, Gu, and Wang Zuo. "Mapping N-Port Memory with Dual-Port Array." In 2009 WRI World Congress on Computer Science and Information Engineering. IEEE, 2009. http://dx.doi.org/10.1109/csie.2009.889.

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Reports on the topic "MEMORY PORTS"

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Rivest, Ronald L., and Lance A. Glasser. A Fast Multiport Memory Based on Single-Port Memory Cells. Fort Belvoir, VA: Defense Technical Information Center, July 1991. http://dx.doi.org/10.21236/ada239455.

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Johnson, Eric E. A Prototype Virtual Port Memory Multiprocessor. Fort Belvoir, VA: Defense Technical Information Center, May 1988. http://dx.doi.org/10.21236/ada217115.

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Rozo, Esteban, Ana Guglielmucci, and Magda Páez Torres. El derecho a la memoria. Universidad del Rosario, October 2022. http://dx.doi.org/10.12804/dvcn_10336.36801_num6.

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Ad portas de cumplirse seis años de la firma del Acuerdo de Paz con las Farc, en Colombia sigue en vilo la constitución del Museo de Memoria de Colombia que ha sido blanco de disputas políticas y de una serie de trabas que han causado malestar entre las víctimas. Así lo registra un análisis investigativo de la Universidad del Rosario.
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Tavik, Gregory C. Testing the One-Port Random Access Memory (1PRAM) Module of TRW's CPUAX Signal Processing Superchip. Fort Belvoir, VA: Defense Technical Information Center, April 1991. http://dx.doi.org/10.21236/ada234127.

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