Academic literature on the topic 'Memory Devices - Classification'

Internet of Things (IoT) devices have become increasingly widespread. Despite their potential of improving multiple application domains, these devices have poor security, which can be explored by attackers to build large-scale botnets. In this work, we propose a host-based approach to detect botnets in IoT devices, named IoTDS (Internet of Things Detection System). It relies on one-class classifiers, which model only the legitimate device behaviour for further detection of deviations, avoiding the manual labelling process. The proposed solution is underpinned by a novel agent-manager architecture based on HTTPS, which prevents the IoT device from being overloaded by the training activities. To analyse the device’s behaviour, the approach extracts features from the device’s CPU utilisation and temperature, memory consumption, and number of running tasks, meaning that it does not make use of network traffic data. To test our approach, we used an experimental IoT setup containing a device compromised by bot malware. Multiple scenarios were made, including three different IoT device profiles and seven botnets. Four one-class algorithms (Elliptic Envelope, Isolation Forest, Local Outlier Factor, and One-class Support Vector Machine) were evaluated. The results show the proposed system has a good predictive performance for different botnets, achieving a mean F1-score of 94% for the best performing algorithm, the Local Outlier Factor. The system also presented a low impact on the device’s energy consumption, and CPU and memory utilisation.

Synaptic devices, which are considered as one of the most important components of neuromorphic system, require a memory effect to store weight values, a high integrity for compact system, and a wide window to guarantee an accurate programming between each weight level. In this regard, memristive devices such as resistive random access memory (RRAM) and phase change memory (PCM) have been intensely studied; however, these devices have quite high current-level despite their state, which would be an issue if a deep and massive neural network is implemented with these devices since a large amount of current-sum needs to flow through a single electrode line. Organic transistor is one of the potential candidates as synaptic device owing to flexibility and a low current drivability for low power consumption during inference. In this paper, we investigate the performance and power consumption of neuromorphic system composed of organic synaptic transistors conducting a pattern recognition simulation with MNIST handwritten digit data set. It is analyzed according to threshold voltage (VT) window, device variation, and the number of available states. The classification accuracy is not affected by VT window if the device variation is not considered, but the current sum ratio between answer node and the rest 9 nodes varies. In contrast, the accuracy is significantly degraded as increasing the device variation; however, the classification rate is less affected when the number of device states is fewer.

The memristor-based neural network takes full use of the benefits of memristive devices, such as their low power consumption, high integration density, and great network recognition capacity, and therefore can be efficiently used for binary image classification in AI based applications. Before implementing the memristor-based memory at circuit level, the performance need to be analyzed. In this work, a nine-layer neuromorphic network is designed and is used to classify binary images. Using the MNIST dataset, the performance of architecture is validated and the impact of device yield and resistance fluctuations under various neuron configurations on network performance are studied. The implementation of restive random access memory (memristor based memory) is carried out using the memtorch in python 3.7 scripting language and the simulation was carried out using MemTorch, an open-source framework for customized large-scale memristive DL applications. The findings indicate that the nine-layer network has an accuracy of about 98 percent in digit recognition.

Due to the daily use of mobile technologies, we live in constant connection with the world through the Internet. Technological innovations in smart devices have allowed us to carry out everyday activities such as communicating, working, studying or using them as a means of entertainment, which has led to smartphones displacing computers as the most important device connected to the Internet today, causing users to demand smarter applications or functionalities that allow them to meet their needs. Artificial intelligence has been a major innovation in information technology that is transforming the way users use smart devices. Using applications that make use of artificial intelligence has revolutionised our lives, from making predictions of possible words based on typing in a text box, to being able to unlock devices through pattern recognition. However, these technologies face problems such as overheating and battery drain due to high resource consumption, low computational capacity, memory limitations, etc. This paper reviews the most important artificial intelligence algorithms for mobile devices, emphasising the challenges and problems that can arise when implementing these technologies in low-resource devices.

Power efficiency is becoming a critical aspect of IoT devices. In this paper, we present a compact object-detection coprocessor with multiple cores for multi-scale/type classification. This coprocessor is capable to process scalable block size for multi-shape detection-window and can be compatible with the frame-image sizes up to 2048 × 2048 for multi-scale classification. A memory-reuse strategy that requires only one dual-port SRAM for storing the feature-vector of one-row blocks is developed to save memory usage. Eventually, a prototype platform is implemented on the Intel DE4 development board with the Stratix IV device. The power consumption of each core in FPGA is only 80.98 mW.

Portable electronic systems allow the analysis and monitoring of continuous time signals, such as human activity, integrating deep learning techniques with cloud computing, causing network traffic and high energy consumption. In addition, the use of algorithms based on neural networks are a very widespread solution in these applications, but they have a high computational cost, not suitable for edge devices. In this context, solutions are created that bring data analysis closer to the edge of the network, so in this paper models adapted to an edge device for the recognition of human activity are evaluated, considering characteristics such as inference time, memory, and precision. Two categories of models based on deep and convolutional neural networks are developed by implementing them in C language and comparing with the TensorFlow Lite platform. The results show that the implementations with libraries have a better accuracy result of 76% using principal component analysis inputs, obtaining an execution time of 9ms. Therefore, when evaluating the models, we must not only consider their accuracy but also the execution time and memory on the device.

Abstract Topological-soliton-based devices, like the ferromagnetic domain-wall device, have been proposed as non-volatile memory (NVM) synapses in electronic crossbar arrays for fast and energy-efficient implementation of on-chip learning of neural networks (NN). High linearity and symmetry in the synaptic weight-update characteristic of the device (long-term potentiation (LTP) and long-term depression (LTD)) are important requirements to obtain high classification/regression accuracy in such an on-chip learning scheme. However, obtaining such linear and symmetric LTP and LTD characteristics in the ferromagnetic domain-wall device has remained a challenge. Here, we first carry out micromagnetic simulations of the device to show that the incorporation of defects at the edges of the device, with the defects having higher perpendicular magnetic anisotropy compared to the rest of the ferromagnetic layer, leads to massive improvement in the linearity and symmetry of the LTP and LTD characteristics of the device. This is because these defects act as pinning centres for the domain wall and prevent it from moving during the delay time between two consecutive programming current pulses, which is not the case when the device does not have defects. Next, we carry out system-level simulations of two crossbar arrays with synaptic characteristics of domain-wall synapse devices incorporated in them: one without such defects, and one with such defects. For on-chip learning of both long short-term memory networks (using a regression task) and fully connected NN (using a classification task), we show improved performance when the domain-wall synapse devices have defects at the edges. We also estimate the energy consumption in these synaptic devices and project their scaling, with respect to on-chip learning in corresponding crossbar arrays.

Due to the recent increasing utilization of deep learning models on edge devices, the industry demand for Deep Learning Model Optimization (DLMO) is also increasing. This paper derives a usage strategy of DLMO based on the performance evaluation through light convolution, quantization, pruning techniques and knowledge distillation, known to be excellent in reducing memory size and operation delay with a minimal accuracy drop. Through experiments regarding image classification, we derive possible and optimal strategies to apply deep learning into Internet of Things (IoT) or tiny embedded devices. In particular, strategies for DLMO technology most suitable for each on-device Artificial Intelligence (AI) service are proposed in terms of performance factors. In this paper, we suggest a possible solution of the most rational algorithm under very limited resource environments by utilizing mature deep learning methodologies.

This work proposes positive feedback (PF) device-based synaptic devices for reliable binary neural networks (BNNs). Due to PF operation, the fabricated PF device shows a high on/off current ratio (2.69 [Formula: see text] 107). The PF device has a charge-trap layer by which the turn-on voltage ( Von) of the device can be adjusted by program/erase operations and a long-term memory function is implemented. Also, due to the steep switching characteristics of the PF device, the conductance becomes tolerant to the retention time and the variation in turn-on voltage. Simulations show that high accuracy (88.44% for CIFAR-10 image classification) can be achieved in hardware-based BNNs using PF devices with these properties as synapses.

Exiting simple samples in adaptive multi-exit networks through early modules is an effective way to achieve high computational efficiency. One can observe that deployments of multi-exit architectures on resource-constrained devices are easily limited by high memory footprint of early modules. In this paper, we propose a novel approach named recurrent aggregation operator (ReX), which uses recurrent neural networks (RNNs) to effectively aggregate intra-patch features within a large receptive field to get delicate local representations, while bypassing large early activations. The resulting model, named ReXNet, can be easily extended to dynamic inference by introducing a novel consistency-based early exit criteria, which is based on the consistency of classification decisions over several modules, rather than the entropy of the prediction distribution. Extensive experiments on two benchmark datasets, i.e., Visual Wake Words, ImageNet-1k, demonstrate that our method consistently reduces the peak RAM and average latency of a wide variety of adaptive models on low-power devices.

This contribution describes the properties and limitations of multi-layered mechanical devices with variable flexural stiffness. Such structures are supposed to be components of new smart, self-sensing and self-controlling composite materials for lightweight constructions. To enable a proper stiffness control, reliable actuators with high actuation capabilities based on smart materials are used. Those actuators are either driven by electroactive polymers (EAPs) or shape memory alloy (SMA) wires. They control the area moment of inertia of the multi-layered bending structures. To change the area moment of inertia and, hence, the flexural stiffness of an multi-layered beam within a wide range, it is necessary to stack as many layers as possible over each other. The fundamental function of this approach is demonstrated with a three-layer stack consisting of three independent layers and four form closure actuators driven by SMAs. This experimental set-up was able to change its bending stiffness k by a factor of 14.6, with a minimum and maximum stiffness of kmin = 0.11 N mm¯¹ and kmax = 1.73 N mm¯¹, respectively. The usage of four independently controllable actuators yields nine independent flexural-stiffness states of the beam. Both analytical and numerical calculations have shown good agreement with the measured stiffness values.

The field of advanced solution processed spin-coated electronics has rapidly expanded over the last few decades towards the development of low-cost, large area and low power consumer electronics for the design of system-on-panel, system-on-glass, and system-on-chip circuits. They have diverse applications such as wearable and textile integrated devices, seamless and twistable systems, soft skin systems, as well as roll-to-roll light-weight, transparent, conformable, stretchable, and even biodegradable systems. So far, all demonstration of solution processed electronics use thin lm transistors (TFT) without any memory. However, memory is an essential electronic component of all systems and it is important to realize floating gate ash memory devices using similar spin-coated solution processing compatible technique. The first demonstration of floating memory by Kahng and Size in 1967 on transparent glass substrates utilized floating metal gate charge storage layers deposited by high temperature vacuum technology. Since then, there has been intensive research on floating gate technology. However, the high temperature and high vacuum technology is incompatible with large area, flexible and low cost electronics due to the process integration issue. Hence the alternative challenge was taken up on developing solution processed spin-coated memory devices for sol-gel electronics. In this thesis we first introduce different solution processed dielectrics and oxide semi-conductors, thin lm deposition, and behavior at different processing temperatures. Further, we also demonstrate how the band structure of the dielectric, particularly the electron a finity, changes with annealing temperature. Then we propose and demonstrate a new high speed measurement technique for two terminal capacitive devices. In particular, we show that the entire capacitance-voltage curve can be measured in 2.5 s. The measurement is useful for characterization of two terminal capacitive memory devices in terms speed, endurance and retention. This achievement is followed by its application to newly developed fully solution processed, nanoparticle based, robust two terminal memory devices. The link between device performance and its structural and processing parameters such as annealing temperature, thickness of memory layer, supporting dielectric layer and substrate materials, is highlighted. In addition, a detailed analysis and comparison of performance of solution processed memory with regard to state-of-the art processing techniques as well as the selection of materials is presented. This work was extended to achieve the worlds first three terminal fully solution processed inorganic material-based robust ash memory devices with different kinds of solution processed charge trapping layers. We also discuss the advantage of this technology over previously reported sophisticated ultra high vacuum technology based three terminal ash memory devices. Afterwards, we report the discovery of deep level intrinsic traps in solution processed aluminium oxide phosphate. It is also shown that the traps are tunable with the processing temperature. Using XPS and UPS characterization techniques, the origin of these traps is linked with the molecular structure. Utilizing this trap behavior we have fabricated the worlds first fully solution processed ash memory device without tunneling and blocking layers at below 200 C. This discovery may be a breakthrough for large area, solution processed, and flexible electronics applications. Finally, conclusions are drawn on the performance of the memory stack with respect to other processing techniques, along with an outlook for this field and predictions for the future of this technology.

A novel, non-volatile, organic capacitive memory device called p-i-n-metal-oxide-semiconductor (pinMOS) memory is demonstrated with multiple-bit storage that can be programmed and read out electrically and optically. The diode-based architecture simplifies the fabrication process, and makes further optimizations easy, and might even inspire new derived capacitive memory devices. Furthermore, this innovative pinMOS memory device features local charge up of an integrated capacitance rather than of an extra floating gate. Before the device can perform as desired, the leakage current due to the lateral charge up of the doped layers outside the active area needs to be suppressed. Therefore, in this thesis, lateral charging effects in organic light-emitting diodes (OLEDs) are studied first. By comparing the results from differently structured devices, the presence of centimeter-scale lateral current flows in the n-doped and p-doped layers is shown, which results in undesirable capacitance increases and thus extra leakage currents. Such lateral charging can be controlled via structuring the doped layers, leading to extremely low steady-state leakage currents in the OLED (here 10-7 mA/cm2 at -1 V). It is shown that these lateral currents can be utilized to extract the conductivity as well as the activation energy of each doped layer when modeled with an RC circuit model. Secondly, pinMOS memory devices that are based on the diode with structured doped layers are investigated. The memory behavior, which is demonstrated as capacitance switching for electrical signals, and light emission for optical signals, can be tuned either by the applied voltage or ultraviolet light illumination, respectively. The working mechanism is explained by the existence of quasi steady-states as well as the width variation of space charge zones. The pinMOS memory shows excellent repeatability, an endurance of more than 104 write-read-erase-read cycles, and currently already over 24 h retention time. Furthermore, an early-stage investigation on emulating synaptic plasticity reveals the potential of pinMOS memory for applications in neuromorphic computing. Overall, the results indicate that pinMOS memory in principle is promising for a variety of future applications in both electronic and photonic circuits. A detailed understanding of this new concept of memory device, for which this thesis lays an important foundation, is necessary to proceed with further enhancements.:1 Introduction 1 2 Fundamentals of organic semiconductors 5 2.1 Electronic states of a molecule 5 2.1.1 Atomic orbitals and molecular orbitals 5 2.1.2 Solid states 9 2.1.3 Singlet and triplet states 12 2.2 Charge transport 13 2.2.1 Charge carrier mobility 13 2.2.2 Charge carrier transport 14 2.3 Charge injection 17 2.3.1 Current limitation 17 2.3.2 Charge injection mechanisms 20 2.4 Doping 22 3 Organic junctions and devices 25 3.1 Metal-semiconductor junction 25 3.1.1 Schottky junction 25 3.1.2 Surface states 27 3.2 Metal-oxide-semiconductor capacitor 29 3.3 Junctions and diodes 31 3.3.1 PN junction and diode 31 3.3.2 PIN junction and diode 32 4 Organic non-volatile memory devices 35 4.1 Basic concepts 35 4.2 Organic resistive memory devices 37 4.2.1 Device architecture and switching behavior 38 4.2.2 Working mechanisms 38 4.3 Organic transistor-based memory devices 41 4.3.1 Organic field-effect transistor and memory devices based thereon 41 4.3.2 Floating gate memory 43 4.3.3 Charge trapping memory 45 4.4 Organic ferroelectric memory devices 46 4.4.1 Ferroelectric capacitor memory 47 4.4.2 Ferroelectric transistor memory 48 4.4.3 Ferroelectric diode memory 49 5 Experimental methods 53 5.1 Device fabrication 53 5.2 Device characterization 55 5.3 Materials 57 6 Lateral current flow in semiconductor devices having crossbar electrodes 61 6.1 Introduction 61 6.2 Device architecture 62 6.3 Characteristics comparison between unstructured and structured devices 63 6.3.1 Charging measurement 63 6.3.2 Current-voltage characteristics 64 6.3.3 Capacitance-frequency characteristics 67 6.4 Influence of conductivity of doped layers 69 6.4.1 Dependence on doped layers thickness 69 6.4.2 Dependence on temperature 73 6.5 Lateral charging simulation 74 6.5.1 Analytical description 74 6.5.2 RC circuit simulation 76 6.5.3 Parameters for doped layers gained by simulation 79 6.6 Pseudo trap analysis 81 6.6.1 The pseudo trap density of states determination 81 6.6.2 The pseudo trap analysis under simulated identical conditions 84 6.7 Summary 85 7 The pinMOS memory: novel diode-capacitor memory with multiple-bit storage 87 7.1 Introduction 87 7.2 Device architecture 88 7.2.1 Dependence on layout and pixel 89 7.2.2 Fundamental memory behavior characterization 93 7.3 Working mechanism 96 7.3.1 Working mechanism of quasi-steady states 97 7.3.2 Working mechanism of dynamic states 101 7.4 Tunability of the memory effect 105 7.4.1 Operation parameters 106 7.4.2 Photoinduced tunability 108 7.4.3 Intrinsic layer thickness 110 7.5 Potential in neuromorphic computing application 111 7.5.1 Extracting capacitance at 0 V sequentially 112 7.5.2 Mimicking the long-term plasticity (LTP) behavior 113 7.6 Summary 114 8 Optoelectronic properties of pinMOS memory 117 8.1 Introduction 117 8.2 Measurement setup 117 8.3 pinMOS memory emission intensity 118 8.4 Pulse characteristics and device brightness 119 8.5 Conclusion 124 9 Conclusion 125 Bibliography 129 List of Figures 145 List of Tables 151 List of Abbreviations 153 Publications and Conference 157 Acknowledgment 159
Es wird ein neuartiges, organisches kapazitives Speicherelement demonstriert, das p-i-n-Metalloxid-Halbleiter (pinMOS) Speicher genannt wird und eine Mehrfachbitspeicherung besitzt, die elektrisch und optisch programmiert und ausgelesen werden kann. Die auf einer Diode basierende Architektur vereinfacht den Herstellungsprozess sowie die weitere Optimierung und könnte sogar Inspiration für neue kapazitive Speichermedien sein. Darüber hinaus basiert dieses innovative pinMOS Speicherelement auf der lokalen Aufladung einer integrierten Kapazität und nicht auf einem zusätzlichem “Floating Gate”. Bevor das Speicherelement wie gewünscht funktioniert, muss der Leckstrom, der durch die laterale Aufladung der dotierten Schichten außerhalb des aktiven Bereichs verursacht wird, unterdrückt werden. Deshalb werden in dieser Arbeit zuerst die lateralen Aufladungseffekte in organischen Leuchtdioden (OLEDs) untersucht. Beim Vergleich verschiedener Device-Strukturen wird die Existenz von lateralen Stromflüssen im Zentimeterbereich in den n- und p-dotierten Schichten gezeigt, was zu einer unerwünschten erhöhten Kapazität und folglich einem höheren Leckstrom führt. Diese laterale Aufladung kann durch die Strukturierung der dotierten Schichten kontrolliert werden, was zu extrem geringen Gleichgewichtsleckströmen in den OLEDs (10-7 mA/cm2 bei -1 V) resultiert. Es wird auch gezeigt, dass die lateralen Ströme genutzt werden können um die spezifische Leitfähigkeit sowie die Aktivierungsenergie der einzelnen dotierten Schichten zu extrahieren, wenn diese mit einem RC-Modell modelliert werden. Im zweiten Teil werden pinMOS Speicherelemente, die auf der Diode mit strukturierten dotierten Schichten basieren, untersucht. Das Speicherverhalten, dass durch Kapazitätsschaltung für elektrische Signale und als Lichtemission für optische Signale gezeigt wird, kann entweder durch die angelegte Spannung, beziehungsweise durch die Belichtung mit ultraviolettem Licht eingestellt werden. Die Wirkungsweise wird durch die Existenz quasistatischer Gleichgewichte sowie durch die Größenänderung der Raumladungszonen erklärt. Der pinMOS Speicher zeigt eine hervorragende Wiederholbarkeit, eine Beständigkeit über mehr als 104 Schreiben-Lesen-Löschen-Lesen Zyklen und aktuell schon eine Retentionszeit von über 24 h. Weiterhin offenbaren erste Versuche in der Nachahmung von Neuronaler Plastizität das Potenzial von pinMOS Speichern für Anwendungen im “Neuromorphic Computing”. Insgesamt deuten die Ergebnisse an, dass pinMOS Speicher prinzipiell vielversprechend für eine Vielzahl von zukünftigen Anwendungen in elektronischen und photonischen Schaltkreisen ist. Ein tiefgreifendes Verständnis von diesem Konzept neuartiger Speicherelemente, für das diese Arbeit eine wichtige Grundlage bildet, ist notwendig, um weitere Verbesserungen zu entwickeln.:1 Introduction 1 2 Fundamentals of organic semiconductors 5 2.1 Electronic states of a molecule 5 2.1.1 Atomic orbitals and molecular orbitals 5 2.1.2 Solid states 9 2.1.3 Singlet and triplet states 12 2.2 Charge transport 13 2.2.1 Charge carrier mobility 13 2.2.2 Charge carrier transport 14 2.3 Charge injection 17 2.3.1 Current limitation 17 2.3.2 Charge injection mechanisms 20 2.4 Doping 22 3 Organic junctions and devices 25 3.1 Metal-semiconductor junction 25 3.1.1 Schottky junction 25 3.1.2 Surface states 27 3.2 Metal-oxide-semiconductor capacitor 29 3.3 Junctions and diodes 31 3.3.1 PN junction and diode 31 3.3.2 PIN junction and diode 32 4 Organic non-volatile memory devices 35 4.1 Basic concepts 35 4.2 Organic resistive memory devices 37 4.2.1 Device architecture and switching behavior 38 4.2.2 Working mechanisms 38 4.3 Organic transistor-based memory devices 41 4.3.1 Organic field-effect transistor and memory devices based thereon 41 4.3.2 Floating gate memory 43 4.3.3 Charge trapping memory 45 4.4 Organic ferroelectric memory devices 46 4.4.1 Ferroelectric capacitor memory 47 4.4.2 Ferroelectric transistor memory 48 4.4.3 Ferroelectric diode memory 49 5 Experimental methods 53 5.1 Device fabrication 53 5.2 Device characterization 55 5.3 Materials 57 6 Lateral current flow in semiconductor devices having crossbar electrodes 61 6.1 Introduction 61 6.2 Device architecture 62 6.3 Characteristics comparison between unstructured and structured devices 63 6.3.1 Charging measurement 63 6.3.2 Current-voltage characteristics 64 6.3.3 Capacitance-frequency characteristics 67 6.4 Influence of conductivity of doped layers 69 6.4.1 Dependence on doped layers thickness 69 6.4.2 Dependence on temperature 73 6.5 Lateral charging simulation 74 6.5.1 Analytical description 74 6.5.2 RC circuit simulation 76 6.5.3 Parameters for doped layers gained by simulation 79 6.6 Pseudo trap analysis 81 6.6.1 The pseudo trap density of states determination 81 6.6.2 The pseudo trap analysis under simulated identical conditions 84 6.7 Summary 85 7 The pinMOS memory: novel diode-capacitor memory with multiple-bit storage 87 7.1 Introduction 87 7.2 Device architecture 88 7.2.1 Dependence on layout and pixel 89 7.2.2 Fundamental memory behavior characterization 93 7.3 Working mechanism 96 7.3.1 Working mechanism of quasi-steady states 97 7.3.2 Working mechanism of dynamic states 101 7.4 Tunability of the memory effect 105 7.4.1 Operation parameters 106 7.4.2 Photoinduced tunability 108 7.4.3 Intrinsic layer thickness 110 7.5 Potential in neuromorphic computing application 111 7.5.1 Extracting capacitance at 0 V sequentially 112 7.5.2 Mimicking the long-term plasticity (LTP) behavior 113 7.6 Summary 114 8 Optoelectronic properties of pinMOS memory 117 8.1 Introduction 117 8.2 Measurement setup 117 8.3 pinMOS memory emission intensity 118 8.4 Pulse characteristics and device brightness 119 8.5 Conclusion 124 9 Conclusion 125 Bibliography 129 List of Figures 145 List of Tables 151 List of Abbreviations 153 Publications and Conference 157 Acknowledgment 159

Deep ‘Analog Artificial Neural Networks’ (AANNs) perform complex classification problems with high accuracy. However, they rely on humongous amount of power to perform the calculations, veiling the accuracy benefits. The biological brain on the other hand is significantly more powerful than such networks and consumes orders of magnitude less power, indicating some conceptual mismatch. Given that the biological neurons are locally connected, communicate using energy efficient trains of spikes, and the behavior is non-deterministic, incorporating these effects in Artificial Neural Networks (ANNs) may drive us few steps towards a more realistic neural networks.

Emerging devices can offer a plethora of benefits including power efficiency, faster operation, low area in a vast array of applications. For example, memristors and Magnetic Tunnel Junctions (MTJs) are suitable for high density, non-volatile Random Access Memories when compared with CMOS implementations. In this work, we analyze the possibility of harnessing the characteristics of such emerging devices, to achieve neuro-inspired solutions to intricate problems.

We propose how the inherent stochasticity of nano-scale resistive devices can be utilized to realize the functionality of spiking neurons and synapses that can be incorporated in deep stochastic Spiking Neural Networks (SNN) for image classification problems. While ANNs mainly dwell in the aforementioned classification problem solving domain, they can be adapted for a variety of other applications. One such neuro-inspired solution is the Cellular Neural Network (CNN) based Boolean satisfiability solver. Boolean satisfiability (k-SAT) is an NP-complete (k≥3) problem that constitute one of the hardest classes of constraint satisfaction problems. We provide a proof of concept hardware based analog k-SAT solver that is built using MTJs. The inherent physics of MTJs, enhanced by device level modifications, is harnessed here to emulate the intricate dynamics of an analog, CNN based, satisfiability (SAT) solver.

Furthermore, in the effort of reaching human level performance in terms of accuracy, increasing the complexity and size of ANNs is crucial. Efficient algorithms for evaluating neural network performance is of significant importance to improve the scalability of networks, in addition to designing hardware accelerators. We propose a scalable approach for evaluating Liquid State Machines: a bio-inspired computing model where the inputs are sparsely connected to a randomly interlinked reservoir (or liquid). It has been shown that biological neurons are more likely to be connected to other neurons in the close proximity, and tend to be disconnected as the neurons are spatially far apart. Inspired by this, we propose a group of locally connected neuron reservoirs, or an ensemble of liquids approach, for LSMs. We analyze how the segmentation of a single large liquid to create an ensemble of multiple smaller liquids affects the latency and accuracy of an LSM. In our analysis, we quantify the ability of the proposed ensemble approach to provide an improved representation of the input using the Separation Property (SP) and Approximation Property (AP). Our results illustrate that the ensemble approach enhances class discrimination (quantified as the ratio between the SP and AP), leading to improved accuracy in speech and image recognition tasks, when compared to a single large liquid. Furthermore, we obtain performance benefits in terms of improved inference time and reduced memory requirements, due to lower number of connections and the freedom to parallelize the liquid evaluation process.

AbstractIn the last decades, on the one hand, Deep Learning (DL) has become state of the art in several domains, e.g., image classification, object detection, and natural language processing. On the other hand, pervasive technologies—Internet of Things (IoT) units, embedded systems, and Micro-Controller Units (MCUs)—ask for intelligent processing mechanisms as close as possible to data generation. Nevertheless, memory, computational, and energy requirements characterizing DL models are three or more orders of magnitude larger than the corresponding memory, computation, and energy capabilities of pervasive devices. This work aims at introducing a methodology to address this issue and enable pervasive intelligent processing. In particular, by defining Tiny Machine Learning (TML) solutions, i.e., machine and deep learning models that take into account the constraints on memory, computation, and energy of the target pervasive device. The proposed methodology addresses the problem at three different levels. In the first approach, the methodology devices inference-based Deep TML solutions by approximation techniques, i.e., the TML model runs on the pervasive device but was trained elsewhere. Then, the methodology introduces on-device learning for TML. Finally, the third approach develops Wide Deep TML solutions that split and distribute the DL processing over connected heterogeneous pervasive devices.

AbstractIn recent years, Internet of things (IoT) devices have been widely implemented and industrially improved in manufacturing settings to monitor, collect, analyze, and deliver data. Nevertheless, this evolution has increased the risk of cyberattacks, significantly. Consequently, developing effective intrusion detection systems based on deep learning algorithms has proven to become a dependable intelligence tool to protect Industrial IoT devices against cyber-attacks. In the current study, for the first time, two different classifications and detection long short-term memory (LSTM) architectures were fine-tuned and implemented to investigate cyber-security enhancement on a benchmark Industrial IoT dataset (BoT-IoT) which takes advantage of several deep learning algorithms. Furthermore, the combinations of LSTM with FCN and CNN demonstrated how these two models can be used to accurately detect cyber security threats. A detailed analysis of the performance of the proposed models is provided. Augmenting the LSTM with FCN achieves state-of-the-art performance in detecting cybersecurity threats.

Ferrites are the important material for memory devices. In this we discuss the ferrites in detail with their classification, preparation method to their applications. We also present a brief introduction about hard ferrites and their application in memory devices. Ferrites are the materials that offer distinct electrical and magnetic features that are helpful for various applications. It is noted that spin transmission torques may change magnetization through the current travelling through a magnetic tunnel interface, an effect followed by the spin transfer torque magnet random access memory as the switching mechanism. Also, it is observed that the transistor-type memory devices that employ nanostructured materials as loading sites for the trap are nano-floatting Gate (NFGM). Thus, this chapter presents a way forward for the memory devices.

The chapter portrays a new development in the field of embedded systems. It showcases the combination of Machine Learning algorithms and low-memory microcontrollers (ESP32-CAM). The uniqueness of this idea lies in the fact that Machine Learning is generally perceived as a processor-intensive task that requires high memory and storage. However, as seen in this chapter, one may soon realize how wrong this notion is with emerging technologies that are taking over the globe. This project portrays the successful implementation of a binary colour classification model on the ESP32-CAM with 68% accuracy post-training result with a mere 15 images of each colour. Machine learning has increased over the years. Some applications include image classification, object detection, and question-answering. This work merely puts out awareness in this domain and is hopeful that dedicated efforts towards it can solve many industrial problems.

In the long term, the Internet of Things (IoT) is expected to become an integral part of people’s daily lives. In light of this technological advancement, an ever-growing number of objects with limited hardware may become connected to the Internet. In this chapter, we explore the importance of these constrained devices as well as how we can use them in conjunction with fog computing to change the future of the IoT. First, we present an overview of the concepts of constrained devices, IoT, and fog and mist computing, and then we present a classification of applications according to the amount of resources they require (e.g., processing power and memory). After that, we tie in these topics with a discussion of what can be expected in a future where constrained devices and fog computing are used to push the IoT to new limits. Lastly, we discuss some challenges and opportunities that these technologies may bring.

In recent years mobile devices have become an important part of our daily lives and Deep Convolutional Neural Networks have been performing well in the task of image classification. Some considerations have to be made when running a Neural Network inside a mobile device such as computational complexity and storage size. In this paper, common architectures for image classification were analyzed to retrieve the values of accuracy rate, model complexity, memory usage, and inference time. Those values were compared and it was possible to show which architecture to choose from considering mobile restrictions.

There are a number of schemes to perform optical arithmetic computation. While there are parallel carry-free computation models that require cumbersome preprocessing and postprocessing, most digital approaches use direct binary digital computation. Such an approach is serial and requires bit-by-bit computation. Optical implementation of an inherently serial algorithm is generally undesirable. Associative memory processors are inherently parallel and, using appropriate training patterns, are nonalgorithmic. The major disadvantage of such processors is that the number of training patterns is large, leading to large, possibly unrealizable, associative memory requirements, and because the patterns are nonorthogonal and there are imperfections in the physical devices, some of the thus generated results may be in error. Using different classification and error-correcting schemes, the adverse features of an LAM are controlled.

The Internet of Things (IoT) consists of embedded low-power devices that collect and transmit data to centralized head nodes that process and analyze the data, and drive actions. The proliferation of these connected low-power devices will result in a data explosion that will significantly increase data transmission costs with respect to energy consumed and latency. Edge computing performs computations at the edge nodes prior to data transmission to interpret and/or utilize the data, thus reducing transmission costs. In this work, we seek to understand the interactions between IoT applications’ execution characteristics (e.g., compute/memory intensity, cache miss rates, etc.) and the edge nodes’ microarchitectural characteristics (e.g., clock frequency, memory capacity, etc.) for efficient and effective edge computing. Thus, we present a broad and tractable IoT application classification methodology and using this classification, we analyze the microarchitectural characteristics of a wide range of state-of-the-art embedded system microprocessors and evaluate the microprocessors’ applicability to IoT computation using various evaluation metrics. We also investigate and quantify the impact of leakage power reduction on the overall energy consumption across different architectures. Our work provides insights into the microarchitectural characteristics’ impact on system performance and efficiency for various IoT application requirements. Our work also provides a foundation for the analysis and design of a diverse set of microprocessor architectures for IoT edge computing.

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

The threat posed by botnets of infecting a large number of devices and using them together to perform several malicious actions has become a growing issue to the Internet security. One way to deal with it is to have methods able to correctly identify those botnets and then run necessary countermeasures. Many approaches using machine learning (ML) have been proposed over the years to cope with botnet detection. Nonetheless, the algorithms commonly employed cannot adapt to new data without significant effort. In this sense, a ML research topic referred to as stream mining may be a solution. Stream mining algorithms are specially tailored to learn incrementally with new instances, without consuming significant memory or time. This work proposes an approach using the Very Fast Decision Tree, a classification algorithm used on stream mining that can learn incrementally when needed, to identify botnets by observing network flows. When evaluating the approach on multiple scenarios with different botnets, we were able to achieve high performance metrics on the majority of scenarios, while using a significantly low number of labelled instances.

A smart detector of GaAs-based MSM structure that has the functions of variable sensitivity and analog memory has been developed. The variable sensitivity is based on the phenomenon that the photocurrent is proportional to the electric field applied to the electrodes. The analog memory is based on the optical properties of impurities in the GaAs film. This detector is quite useful as an optical synapse because of the analog operation, memory function, and simple structure for a 2-D integration. Two kinds of novel neurodevices are introduced. The first device is an optical learning chip with analog memory. Its functions are to acquire the knowledge, to store it as the synaptic weights at learning phase, and to perform the vector-matrix multiplication at retrieval phase. The optical learning chip consisting of a 32 × 32 smart detector array and a line-shaped LED array with 32 elements, which are monolithically integrated on a GaAs substrate, was fabricated. The pattern classification experiment was successfully performed. The second device is an artificial retina for direct image processing. The input image is projected on the 2-D smart detector array as the synaptic matrix. The function of the retina can be chosen by an electric control signal as an input vector. Edge detection was successfully made by using the artificial retina with 64 × 64 elements.

The performance of learning process (standard system, e-learning or in a virtual environment) is associated with cognitive load and memory working activity. Working memory (or short-term memory) is the ability to hold multiple pieces of information in mind as you solve a problem. An example of short-term memory is a chess master who can explore several possible solutions mentally before choosing the one that will lead to checkmate. This ability to hold information temporarily to complete a task is specifically human. It causes frontal and pre-frontal lobe regions of the brain to become very active. It was proven that the frontal lobe also deals with higher-level cognitive functions like reasoning and judgment. Sometimes called executive function, it is associated with the pre-frontal cortex. The goal of our work is to study different approaches to assess and classify cognitive load and working memory activity along teaching activity. For this purpose, Electroencephalography (EEG) signals were acquired using Emotive EPOC+ neuroheadset and BrainProducts Amplifier with EasyCap helmet. The BrainProducts device offers high accuracy and possibility to investigate signals in Gamma range, but EPOC+ headset allows wireless acquisition that means user’s mobility. The EEG signals were acquired using OpenVibe software from users involved in N-back dual memory tests and some typical reasoning scenarios (math type in our case). The experimental setting involved the use of 16 electrodes among which 6 collected brain signals from frontal and prefrontal brain regions. The raw data were preprocessed to reject the artifacts and filtered to obtain the Delta, Theta, Alpha, Beta, and Gamma waves for further analysis and classification. Particular attention considers the beta wave that reflects active thinking, attention, solving real problems. A low power spectrum denotes relaxation, and it is most evident frontally. Gamma wave denotes mechanism of consciousness, associated with the formation of ideas, language and memory processing, and various types of learning. Alpha wave is also important in our study because it is related to positive and negative emotions, relaxation or responsiveness. For each wave of interest, the power spectrum and signal envelopes were obtained for relaxation state and playing N-back memory and reasoning tests. To classify cognitive load and working memory activity some well-known techniques for regression and classification were used like support vector machine and random forests.