Dissertations / Theses on the topic 'Memory device'

In recent years the optical domain has been traditionally reserved for node-to-node transmission with the processing and switching achieved entirely in the electrical domain. However, with the constantly increasing demand for bandwidth and the resultant increase in transmission speeds, there is a very real fear that current electronic technology as used for processing will not be able to cope with future demands. Fuelled by this requirement for faster processing speeds, considerable research is currently being carried out into the potential of All-optical processing. One of the fundamental obstacles in realising All-optical processing is the requirement for All-optical buffering. Without all-optical buffers it is extremely difficult to resolve situations such as contention and congestion. Many devices have been proposed to solve this problem however none of them provide the perfect solution. The subject of this research is to experimentally demonstrate a novel all-optical memory device. Unlike many previously demonstrated optical storage devices the device under consideration utilises only a single loop mirror and a single SOA as its switch, whilst providing full regenerative capabilities required for long-term storage. I will explain some of the principles and characteristics of the device, which will then be experimentally demonstrated. The device configuration will then be studied and investigated as to its suitability for Hybrid Integrated Technology.

Quantum key distribution (QKD) is one of the most prominent methods for secure exchange of cryptographic keys between two users. The laws of physics provide it with an immense tool towards secure communications. Although QKD has been proven to reach distances on the order of a few hundreds of kilometers, the transmission rate of the key significantly drops when we go to further distances. One possible solution to this is to build a network of trusted nodes. The trust requirement will however narrow its scope of deployability. In this thesis, we focus on improving the key rate performance of secure communications by introducing imperfect quantum memories (QMs) in a measurement-device-independent (MDI) QKD system. In this thesis, a protocol with the potential of beating the existing distance records for conventional QKD systems is proposed. It borrows ideas from quantum repeaters by using memories in the middle of the link, and that of MDI-QKD, which only requires optical source equipment at the user’s end. For certain fast memories, our scheme allows a higher repetition rate than that of quantum repeaters, thereby requiring lower coherence times. By accounting for various sources of nonideality, such as memory decoherence, dark counts, misalignment errors, and background noise, as well as timing issues with memories, we develop a mathematical framework within which we can compare QKD systems with and without memories. In particular, we show that with the state-of-the-art technology for quantum memories, it is possible to devise memory-assisted QKD systems that, at certain distances of practical interest, outperform current QKD implementations. To extend this work, we consider a suitable candidate that fullfils the requirements we have set for the QMs, i.e., the ensemble-based QMs. This type of memories, nevertheless, suffers from multiple-excitation effects, which can deteriorate the performance of the memory-assisted MDI-QKD system. As a solution we propose an alternative approach to the memory-assisted MDI-QKD by employing entangled-photon sources. We fully analyse this system by including modulation errors during the state-preparation at a single-photon source. We identify under which regimes of operation this system outperforms present QKD implementations. Overall we obtain a realistic account of what can be done with current technologies in order to improve the performance, in terms of rate versus distance, of QKD systems. Our findings can guide us toward implementing larger quantum networks.

Phase change memory (PCM) is an emerging non-volatile memory technology that demonstrates promising performance characteristics. The presented research aims to study the feasibility of using resistive non-volatile PCM in embedded memory applications, and in bridging the performance gap in traditional memory hierarchy between volatile and non-volatile memories. The research studies the operation dynamics of PCM, including its electrical, thermal and physical properties; in order to determine its behaviour. A PCM cell circuit model is designed and simulated with the aid of SPICE tools (LTSPICE IV). The first step in the modelling process was to design a single-level PCM (SLPCM) cell circuit model that stores a single bit of data. To design the PCM circuit model; crystallization theory and heat transfer equation were utilized. The developed electrical circuit model evaluates the physical transformations that a PCM cell undergoes in response to an input pulse. Furthermore, the developed model accurately simulated the temperature profile, the crystalline fraction, and the resistance of the cell as a function of the programming pulse. The circuit model is then upgraded into a multilevel phase change memory (MLPCM) cell circuit model. The upgraded MLPCM circuit model stores two bits of data, and incorporates resistance drift with time. The multiple resistance levels were achieved by controlling the programming pulse width in the range of 10ns to 200ns. Additionally, the drift behaviour was precisely evaluated; by using statistical data of drift exponents, and evaluating the exact drift duration. Moreover, the simulation results for the designed SLPCM and MLPCM cell models were found to be in close agreement with experimental data. The simulated I-V characteristics for both SLPCM and MLPCM mimicked the experimentally produced I-V curves. Furthermore, the simulated drift resistance levels matched the experimental data for drift durations up to 103 seconds; which is the available experimental data duration in technical literature. Furthermore, the simulation results of MLPCM showed that the deviation between the programmed and drifted resistance can reach 6x106Ω in less than 1010 seconds. This resistance deviation leads to reading failures in less than 100 seconds after programming, if standard fixed sensing thresholds method was used. Therefore, to overcome drift reliability issues, and retain the density advantage offered by multilevel operation; a time-aware sensing scheme is developed. The designed sensing scheme compensates for the drift caused resistance deviation; by using statistical data of drift coefficients to forecast adaptive sensing thresholds. The simulation results showed that the use of adaptive time-aware sensing thresholds completely eliminated drift reliability issues and read errors. Furthermore, PCM based nanocrossbar memory structure performance in terms of delay and energy consumption is studied in simulation environment. The nanocrossbar is constructed with a grid of connecting wires; and the designed PCM cell circuit model is used as memory element and placed at junction points of the grid. Then the effect of connecting nanowires resistance in PCM nanocrossbar performance is studied in passive crossbars. The resistance of a connecting wire segment was evaluated with physical formulas that calculate nanoscaled conductors’ resistance. Then a resistor that is equivalent to each wire segment resistance is placed in the tested crossbar structure. Simulation results showed that due to connecting wires resistance; the PCM cells are not truly biased to programming voltage and ground. This leads to 40% deviation in the programed low resistive state from the targeted levels. Thus, affecting PCM reliability and decreasing the high to low resistance ratio by 90%. Therefore, programming and architectural solutions to wire resistance related reliability issue ar presented. Where dissipated power across wire resistance is compensated for; by controlling programming pulse duration. The programming solution retained reliability however; it increased programming energy consumption and delay by an average of 40pJ and 60ns respectively per operation. Additionally, the effects of leakage energy in PCM based nanocrossbars were studied in simulation environment. Then, a structural solution was developed and designed. In the designed structure; leakage sneak paths are eliminated by introducing individual word lines to each memory element. This method led to 30% reduction in reading delay, and consumed only about sixth the leakage energy consumed by the standard structure. Moreover, a sensing scheme that aims to reduce energy consumption in PCM based nanocrossbars during reading process was explored. The sensing method is developed using AC current in contrast to the standard DC current reading circuits. In the designed sensing circuit, a low pass filter is utilized. Accordingly, the filter attenuation of the applied AC reading signal indicates the stored state. The proposed circuit design of the AC sensing scheme was constructed and studied in simulation environment. Simulation results showed that AC sensing has reduced reading energy consumption by over 50%; compared to standard DC sensing scheme. Furthermore, the use of SLPCM and MLPCM in memory applications as crossbar memory elements, and in logic applications i.e. PCM based LUTs was explored and tested in simulation environment. The PCM performance in crossbar memory was then compared to current Static Random Access Memory (SRAM) technology and against one of the main emerging resistive non-volatile memory technologies i.e. Memristors. Simulation results showed that programming and reading energy consumption of PCM based crossbars were five orders of magnitude more than SRAM based crossbars. And reading delay of SRAM based crossbars was only 38% of reading delay of PCM based counterparts. However, PCM cells occupies less than 60% of the area required by SRAM and can store multiple bit in a single cell. Moreover, Memristor based nanocrossbars outperformed PCM based ones; in terms of delay and energy consumption. With PCM consuming 2 orders of magnitude more energy during programming and reading. PCM also required 10 times the programming delay. However, PCM crossbars offered higher switching resistance range i.e. 170kΩ compared to the 20kΩ offered by memristors; which support PCM multibit storage capability and higher density.

n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs) with copper electrodes prepared by a novel plasma etching process have been fabricated and studied. Their characteristics are similar to those of TFTs with molybdenum electrodes. The reliability was examined by extended high-temperature annealing and gate-bias stress. High-performance CMOS-type a-Si:H TFTs can be fabricated with this plasma etching method. Electrical characteristics of a-Si:H TFTs after Co-60 irradiation and at different experimental stages have been measured. The gamma-ray irradiation damaged bulk films and interfaces and caused the shift of the transfer characteristics to the positive voltage direction. The field effect mobility, on/off current ratio, and interface state density of the TFTs were deteriorated by the irradiation process. Thermal annealing almost restored the original state's characteristics. Floating gate n-channel a-Si:H TFT nonvolatile memory device with a thin a- Si:H layer embedded in the SiNx gate dielectric layer has been prepared and studied. The hysteresis of the TFT's transfer characteristics has been used to demonstrate its memory function. A steady threshold voltage change between the "0" and "1" states and a large charge retention time of > 3600 s with the "write" and "erase" gap of 0.5 V have been detected. Charge storage is related to properties of the embedded a-Si:H layer and its interfaces in the gate dielectric structure. Discharge efficiencies with various methods, i.e., thermal annealing, negative gate bias, and light exposure, separately, were investigated. The charge storage and discharge efficiency decrease with the increase of the drain voltage under a dynamic operation condition. Optimum operating temperatures are low temperature for storage and higher temperature for discharge. a-Si:H metal insulator semiconductor (MIS) capacitor with a thin a-Si:H film embedded in the silicon nitride gate dielectric stack has been characterized for memory functions. The hysteresis of the capacitor's current-voltage and capacitance-voltage curves showed strong charge trapping and detrapping phenomena. The 9 nm embedded a-Si:H layer had a charge storage capacity six times that of the capacitor without the embedded layer. The nonvolatile memory device has potential for low temperature circuit applications.

Thesis (M.S.)--Missouri University of Science and Technology, 2010.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed January 6, 2010) Includes bibliographical references.

This thesis is focused on two topics: (i) synthesis and characterization of bilayer graphene and pyrolytic carbon by atmospheric pressure chemical vapor deposition, and (ii) application of graphene in the fabrication of a buckyball memory device. Monolayer and bilayer graphene are semi-metal with zero bandgap. One can induce a bandgap in bilayer graphene by applying a gate voltage in the stacking direction. Thus, bandgap and Fermi level in bilayer graphene can be controlled simultaneously with a double-gate device, making it a useful material for future semiconducting applications. Controlled synthesis of bilayer graphene would be the first step to fabricate bilayer graphene based devices. In this context, we report a uniform and low-defect synthesis of bilayer graphene on evaporated nickel films. Ultra-fast cooling is employed to control the number of layers and sample uniformity. The process is self-limiting, which leads to bilayer graphene synthesis over a wide range of growth-time and precursor flow-rate. Pryolytic carbon is another important carbon nanomaterial, due to its diverse applications in electronic and biomedicalengineering. We employ chemical vapor deposition with ultra-fast cooling technique to synthesize pyrolytic carbon. Furthermore, we elucidate a method to calculate the in-plane crystal size by using Raman spectroscopy. Finally, the use of bilayer graphene in a write-once read-many memory device has been demonstrated. The device showed irreversible switching from low-resistance to high-resistance state, with hysteresis in the transport characteristics. The control sample showed random switching and hysteresis due to electromigration of metal atoms into the active material of the device. We attribute the reliability and performance of the reported device to the ultra-smooth graphene contacts, which additionally inhibits electromigration from the underlying metallic film. Moreover, the memory device showed excellent endurance and retention characteristics.

International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California
Honeywell, under contract from NASA Johnson Space Center and Lockheed Engineering and Sciences Company, has developed a new tool for instrumentation data collection. The Stand-Alone Pressure Measurement Device (SAPMD) is part of a family of microminiature data recorders combined with sensors that can be be used as flight development instrumentation on aerospace vehicles and structures. NASA came to Honeywell with a need to collect absolute pressure data during ascent of the Shuttle on various points over the orbiter’s surface. Instrumentation for this data does not exist on current orbiters, and NASA must use computer modeling to determine structural loading calculations. The conventional approach of placing sensors and cabling inside the Shuttle’s frame combined with drilling holes for the pressure sensors was considered too costly and could weaken the orbiter’s structure. The SAPMD measures pressure at various locations on the space shuttle orbiter skin during ascent. In order to avoid the extensive impacts associated with wiring new measurements into the orbiter data system, the device is self contained, incorporating its own sensor, power supply, self-starting sensor, nonvolatile memory for sensor data, and a real-time clock for time reference. The device is small enough (6.28 in x 1.5 in. x 0.5 in.) to be mounted under the thermal protection system tiles and rugged enough to withstand the environments encountered at the interface between tiles throughout an orbiter mission. Data recorded during ascent is recovered after the mission without removing the device. Other sensors such as strain gauges for structural monitoring, vibration gauges for wing flutter, or differential pressure gauges can be used with this hardware.

This research focuses on device design and process integration of high density nonvolatile memory devices. Research was carried out to improve scaling of floating gate memories by increasing charge density as well as spin-based memories by reducing critical switching current. This work demonstrates fabrication of CMOS-compatible nonvolatile hybrid memory device using fullerene molecules as a floating gate. Molecules have dimensions of several Angstroms resulting in an electron density of ~10¹³ cm⁻² or higher. In hybrid MOSCAPs, fullerenes were encapsulated between inorganic oxides, i.e. SiO₂ as a tunnel oxide and HfO₂ as a control oxide. Introduction of a high-k material as a control oxide improves capacitive coupling between control gate and floating gate as well as the program/erase efficiency. The MOS capacitors demonstrate nonvolatile memory operation at room temperature. The device data infers that program/erase mechanism in fullerene devices is Fowler-Nordheim tunneling; however, retention is determined by trap-assisted tunneling. The next part of the work focused on spin-transfer-torque (STT) based magnetic memory. Spin-based memory has the unique potential to be the universal memory because of its high density, fast switching, and nonvolatility. This work presents STT switching of perpendicular magnetic anisotropy (PMA) spin-valves with tilted magnetization using point contact measurement. The PMA materials have high coercivity resulting in good retention and tilted magnetization induces precessional switching resulting in a lower switching current density. First, micromagnetic simulations were performed for spin-valves with tilted magnetization and precessional switching was observed to reduce the switching current. Then, spin-valve structures were fabricated by e-beam evaporation. The structure consisted of Co/Pt and Co/Ni layers, where the thickness of the layers was optimized to obtain different amount of tilt in magnetization. Point contact measurements of tilted spin-valves show STT switching, where the switching field of the free layer varies with the magnitude and sign of the applied current. The observed STT effect is stronger in a 45° tilted spin-valve compared to a 12° tilted device presumably due to the tilted spin polarization. However, tilting introduces nonuniform effective field and canting of the domains which affect the STT.
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A novel, non-volatile, organic capacitive memory device called p-i-n-metal-oxide-semiconductor (pinMOS) memory is demonstrated with multiple-bit storage that can be programmed and read out electrically and optically. The diode-based architecture simplifies the fabrication process, and makes further optimizations easy, and might even inspire new derived capacitive memory devices. Furthermore, this innovative pinMOS memory device features local charge up of an integrated capacitance rather than of an extra floating gate. Before the device can perform as desired, the leakage current due to the lateral charge up of the doped layers outside the active area needs to be suppressed. Therefore, in this thesis, lateral charging effects in organic light-emitting diodes (OLEDs) are studied first. By comparing the results from differently structured devices, the presence of centimeter-scale lateral current flows in the n-doped and p-doped layers is shown, which results in undesirable capacitance increases and thus extra leakage currents. Such lateral charging can be controlled via structuring the doped layers, leading to extremely low steady-state leakage currents in the OLED (here 10-7 mA/cm2 at -1 V). It is shown that these lateral currents can be utilized to extract the conductivity as well as the activation energy of each doped layer when modeled with an RC circuit model. Secondly, pinMOS memory devices that are based on the diode with structured doped layers are investigated. The memory behavior, which is demonstrated as capacitance switching for electrical signals, and light emission for optical signals, can be tuned either by the applied voltage or ultraviolet light illumination, respectively. The working mechanism is explained by the existence of quasi steady-states as well as the width variation of space charge zones. The pinMOS memory shows excellent repeatability, an endurance of more than 104 write-read-erase-read cycles, and currently already over 24 h retention time. Furthermore, an early-stage investigation on emulating synaptic plasticity reveals the potential of pinMOS memory for applications in neuromorphic computing. Overall, the results indicate that pinMOS memory in principle is promising for a variety of future applications in both electronic and photonic circuits. A detailed understanding of this new concept of memory device, for which this thesis lays an important foundation, is necessary to proceed with further enhancements.:1 Introduction 1 2 Fundamentals of organic semiconductors 5 2.1 Electronic states of a molecule 5 2.1.1 Atomic orbitals and molecular orbitals 5 2.1.2 Solid states 9 2.1.3 Singlet and triplet states 12 2.2 Charge transport 13 2.2.1 Charge carrier mobility 13 2.2.2 Charge carrier transport 14 2.3 Charge injection 17 2.3.1 Current limitation 17 2.3.2 Charge injection mechanisms 20 2.4 Doping 22 3 Organic junctions and devices 25 3.1 Metal-semiconductor junction 25 3.1.1 Schottky junction 25 3.1.2 Surface states 27 3.2 Metal-oxide-semiconductor capacitor 29 3.3 Junctions and diodes 31 3.3.1 PN junction and diode 31 3.3.2 PIN junction and diode 32 4 Organic non-volatile memory devices 35 4.1 Basic concepts 35 4.2 Organic resistive memory devices 37 4.2.1 Device architecture and switching behavior 38 4.2.2 Working mechanisms 38 4.3 Organic transistor-based memory devices 41 4.3.1 Organic field-effect transistor and memory devices based thereon 41 4.3.2 Floating gate memory 43 4.3.3 Charge trapping memory 45 4.4 Organic ferroelectric memory devices 46 4.4.1 Ferroelectric capacitor memory 47 4.4.2 Ferroelectric transistor memory 48 4.4.3 Ferroelectric diode memory 49 5 Experimental methods 53 5.1 Device fabrication 53 5.2 Device characterization 55 5.3 Materials 57 6 Lateral current flow in semiconductor devices having crossbar electrodes 61 6.1 Introduction 61 6.2 Device architecture 62 6.3 Characteristics comparison between unstructured and structured devices 63 6.3.1 Charging measurement 63 6.3.2 Current-voltage characteristics 64 6.3.3 Capacitance-frequency characteristics 67 6.4 Influence of conductivity of doped layers 69 6.4.1 Dependence on doped layers thickness 69 6.4.2 Dependence on temperature 73 6.5 Lateral charging simulation 74 6.5.1 Analytical description 74 6.5.2 RC circuit simulation 76 6.5.3 Parameters for doped layers gained by simulation 79 6.6 Pseudo trap analysis 81 6.6.1 The pseudo trap density of states determination 81 6.6.2 The pseudo trap analysis under simulated identical conditions 84 6.7 Summary 85 7 The pinMOS memory: novel diode-capacitor memory with multiple-bit storage 87 7.1 Introduction 87 7.2 Device architecture 88 7.2.1 Dependence on layout and pixel 89 7.2.2 Fundamental memory behavior characterization 93 7.3 Working mechanism 96 7.3.1 Working mechanism of quasi-steady states 97 7.3.2 Working mechanism of dynamic states 101 7.4 Tunability of the memory effect 105 7.4.1 Operation parameters 106 7.4.2 Photoinduced tunability 108 7.4.3 Intrinsic layer thickness 110 7.5 Potential in neuromorphic computing application 111 7.5.1 Extracting capacitance at 0 V sequentially 112 7.5.2 Mimicking the long-term plasticity (LTP) behavior 113 7.6 Summary 114 8 Optoelectronic properties of pinMOS memory 117 8.1 Introduction 117 8.2 Measurement setup 117 8.3 pinMOS memory emission intensity 118 8.4 Pulse characteristics and device brightness 119 8.5 Conclusion 124 9 Conclusion 125 Bibliography 129 List of Figures 145 List of Tables 151 List of Abbreviations 153 Publications and Conference 157 Acknowledgment 159
Es wird ein neuartiges, organisches kapazitives Speicherelement demonstriert, das p-i-n-Metalloxid-Halbleiter (pinMOS) Speicher genannt wird und eine Mehrfachbitspeicherung besitzt, die elektrisch und optisch programmiert und ausgelesen werden kann. Die auf einer Diode basierende Architektur vereinfacht den Herstellungsprozess sowie die weitere Optimierung und könnte sogar Inspiration für neue kapazitive Speichermedien sein. Darüber hinaus basiert dieses innovative pinMOS Speicherelement auf der lokalen Aufladung einer integrierten Kapazität und nicht auf einem zusätzlichem “Floating Gate”. Bevor das Speicherelement wie gewünscht funktioniert, muss der Leckstrom, der durch die laterale Aufladung der dotierten Schichten außerhalb des aktiven Bereichs verursacht wird, unterdrückt werden. Deshalb werden in dieser Arbeit zuerst die lateralen Aufladungseffekte in organischen Leuchtdioden (OLEDs) untersucht. Beim Vergleich verschiedener Device-Strukturen wird die Existenz von lateralen Stromflüssen im Zentimeterbereich in den n- und p-dotierten Schichten gezeigt, was zu einer unerwünschten erhöhten Kapazität und folglich einem höheren Leckstrom führt. Diese laterale Aufladung kann durch die Strukturierung der dotierten Schichten kontrolliert werden, was zu extrem geringen Gleichgewichtsleckströmen in den OLEDs (10-7 mA/cm2 bei -1 V) resultiert. Es wird auch gezeigt, dass die lateralen Ströme genutzt werden können um die spezifische Leitfähigkeit sowie die Aktivierungsenergie der einzelnen dotierten Schichten zu extrahieren, wenn diese mit einem RC-Modell modelliert werden. Im zweiten Teil werden pinMOS Speicherelemente, die auf der Diode mit strukturierten dotierten Schichten basieren, untersucht. Das Speicherverhalten, dass durch Kapazitätsschaltung für elektrische Signale und als Lichtemission für optische Signale gezeigt wird, kann entweder durch die angelegte Spannung, beziehungsweise durch die Belichtung mit ultraviolettem Licht eingestellt werden. Die Wirkungsweise wird durch die Existenz quasistatischer Gleichgewichte sowie durch die Größenänderung der Raumladungszonen erklärt. Der pinMOS Speicher zeigt eine hervorragende Wiederholbarkeit, eine Beständigkeit über mehr als 104 Schreiben-Lesen-Löschen-Lesen Zyklen und aktuell schon eine Retentionszeit von über 24 h. Weiterhin offenbaren erste Versuche in der Nachahmung von Neuronaler Plastizität das Potenzial von pinMOS Speichern für Anwendungen im “Neuromorphic Computing”. Insgesamt deuten die Ergebnisse an, dass pinMOS Speicher prinzipiell vielversprechend für eine Vielzahl von zukünftigen Anwendungen in elektronischen und photonischen Schaltkreisen ist. Ein tiefgreifendes Verständnis von diesem Konzept neuartiger Speicherelemente, für das diese Arbeit eine wichtige Grundlage bildet, ist notwendig, um weitere Verbesserungen zu entwickeln.:1 Introduction 1 2 Fundamentals of organic semiconductors 5 2.1 Electronic states of a molecule 5 2.1.1 Atomic orbitals and molecular orbitals 5 2.1.2 Solid states 9 2.1.3 Singlet and triplet states 12 2.2 Charge transport 13 2.2.1 Charge carrier mobility 13 2.2.2 Charge carrier transport 14 2.3 Charge injection 17 2.3.1 Current limitation 17 2.3.2 Charge injection mechanisms 20 2.4 Doping 22 3 Organic junctions and devices 25 3.1 Metal-semiconductor junction 25 3.1.1 Schottky junction 25 3.1.2 Surface states 27 3.2 Metal-oxide-semiconductor capacitor 29 3.3 Junctions and diodes 31 3.3.1 PN junction and diode 31 3.3.2 PIN junction and diode 32 4 Organic non-volatile memory devices 35 4.1 Basic concepts 35 4.2 Organic resistive memory devices 37 4.2.1 Device architecture and switching behavior 38 4.2.2 Working mechanisms 38 4.3 Organic transistor-based memory devices 41 4.3.1 Organic field-effect transistor and memory devices based thereon 41 4.3.2 Floating gate memory 43 4.3.3 Charge trapping memory 45 4.4 Organic ferroelectric memory devices 46 4.4.1 Ferroelectric capacitor memory 47 4.4.2 Ferroelectric transistor memory 48 4.4.3 Ferroelectric diode memory 49 5 Experimental methods 53 5.1 Device fabrication 53 5.2 Device characterization 55 5.3 Materials 57 6 Lateral current flow in semiconductor devices having crossbar electrodes 61 6.1 Introduction 61 6.2 Device architecture 62 6.3 Characteristics comparison between unstructured and structured devices 63 6.3.1 Charging measurement 63 6.3.2 Current-voltage characteristics 64 6.3.3 Capacitance-frequency characteristics 67 6.4 Influence of conductivity of doped layers 69 6.4.1 Dependence on doped layers thickness 69 6.4.2 Dependence on temperature 73 6.5 Lateral charging simulation 74 6.5.1 Analytical description 74 6.5.2 RC circuit simulation 76 6.5.3 Parameters for doped layers gained by simulation 79 6.6 Pseudo trap analysis 81 6.6.1 The pseudo trap density of states determination 81 6.6.2 The pseudo trap analysis under simulated identical conditions 84 6.7 Summary 85 7 The pinMOS memory: novel diode-capacitor memory with multiple-bit storage 87 7.1 Introduction 87 7.2 Device architecture 88 7.2.1 Dependence on layout and pixel 89 7.2.2 Fundamental memory behavior characterization 93 7.3 Working mechanism 96 7.3.1 Working mechanism of quasi-steady states 97 7.3.2 Working mechanism of dynamic states 101 7.4 Tunability of the memory effect 105 7.4.1 Operation parameters 106 7.4.2 Photoinduced tunability 108 7.4.3 Intrinsic layer thickness 110 7.5 Potential in neuromorphic computing application 111 7.5.1 Extracting capacitance at 0 V sequentially 112 7.5.2 Mimicking the long-term plasticity (LTP) behavior 113 7.6 Summary 114 8 Optoelectronic properties of pinMOS memory 117 8.1 Introduction 117 8.2 Measurement setup 117 8.3 pinMOS memory emission intensity 118 8.4 Pulse characteristics and device brightness 119 8.5 Conclusion 124 9 Conclusion 125 Bibliography 129 List of Figures 145 List of Tables 151 List of Abbreviations 153 Publications and Conference 157 Acknowledgment 159

碩士
中原大學
電子工程研究所
93
Fuse and antifuse devices are important micro-electric devices. Their applications include as memory redundancy, RF circuit trimming, security code, and low-bit-count electric label. Their device structures of fuse devices are mainly metal fuse-type and poly fuse-type. They can be programmed by applying large current to melt the conductor line, and the power consumption of these programming devices is large. The structure of antifuse devices is two conductor plate sandwiched with thin dielectric material. The high voltage is supplied between two plates at programming. These devices require additional process steps. The commercial antifuse products become feasible since the gate oxide breakdown voltage is decreasing with the device shrinking. The standard MOSFET is used here for study of antifuse devices. The gate oxide breakdown mechanics and avalanche breakdown mechanics can be used for programming In this thesis, punch-through mechanics are used for programming wherein the high field causes permanently channel breakdown between source and drain terminal. The programming time and programming voltage are decreased based on this programming method. TCAD tools, TSUPREM4 and MEDICI, are used to simulate the antifuse structure, basic electrical characteristics and program behavior.

碩士
中原大學
電子工程研究所
95
With continuous developing of 3C products, the nonvolatile memory plays a very important role and receives more and more research and development. In order to achieve the requirement of compactness, portability and multi-functions in electronic products, VLSI processing technologies has been scaled down from micron scale into nanometer scale for their high density integration. EEPROM has advantages of electrically erasing and programming capabilities, but usually requires at least two layers of poly-Si films and masks. The extra deposition layers and masks will increase the cost. Alternatively, the single poly processing can be well compatible with logic circuits processes, and thus avoid the high processing cost. This study was focusing on analyzing electrical properties of single-poly pure CMOS (SIPPOS) non-volatile memory which was consisted of 1P MOS plus 1N MOS, two NMOS, and two PMOS. In the study, silicon chips were measured for electrical analysis. Firstly, writing and erasing speed are tuned for finding optimal conditions. Secondly, related electrical characteristics of standard single poly CMOS memory are simulated by process and device simulation TCAD tools. Thirdly, simulated and measured Id-Vd and Id-Vg results are compared and calibrated improving physical properties and reliability of single poly CMOS memory. Finally, these results can be used for evaluating those nonvolatile memories for their possibility in scaling down.

碩士
中原大學
電子工程研究所
102
The artificial neural network simulates the operation of the human brain. It is applied extensively in audio processing and pattern recognition. With the advancement of technology, hardware portability is becoming indispensable nowadays. This thesis uses the 0.25um CMOS foundry technology to implement the 4x3 NOI array neural network and perceptron algorithms with an IC tester to verify and train the circuit. In this thesis, six input patterns were used for the learning algorithm in these NOI synapses. During the training process, the output signals were supervised and compared to the target by updating NOI synapse weights until the system converges. Initially, we measured the circuit and device data to establish their empirical models and embedded them in the software to simulate the neural network. In the simulation, we discussed the input, judgment and stress time, found the best parameter for the system and discussed the reasons why some results fail to converge. Finally, we verified the simulation result through hardware training, and the results show that the simulation training trend is similar to hardware training.

碩士
國立交通大學
電子研究所
84
A design methodology for high-speed and high-reliable flash EEPROM is presented in this thesis. By modifying a 1-D substrate injection model, agate injection probability model for 2-D numerical analysis is introduced,in which a channel hot-electron enhanced barrier lowering term is used to represent the 2-D injection probability. With this model, the writing speedand the generation of oxide-trapped-charges for various drain structures aresimulated. The simulation results have shown that in order to obtain a high-speed and high-reliable EEPROM cell, the distributin of hot-carriers under writing condition must be widened and a p-pocket-surrounded asymmetric LDDstructure has been shown to satisfy the requirement.

碩士
中原大學
物理研究所
106
With the advancement of modern science and technology, electronic products have become an indispensable existence in people''s lives. Each product consists of electronic circuits, processors, logic components, etc., and the base of these components is the field-effect transistor. The miniaturization of the transistor faces the challenge of physical limits and requires new materials to solve. In recent years, two-dimensional materials are one of the most popular nano-materials. We will use 2D materials as channel materials to make field effect transistors. In this paper, we will analyze and discuss the results after measuring electrical properties. Memory plays a very important role in electronic products, but current memory development is facing the challenge of high density capacity. This research demonstrates the novel memory device based on two-dimensional material field effect transistor, in which self-assembled molecular layer is formed on two-dimensional material channel by molecular modification. The molecular configurations can be altered by different gate voltage pulse, leading to the different channel conductance and charge storage states. Using different gate voltage pulse and pulse duration times to control how many molecules are affected, devices can achieve multi-level storage states. We think this is a good step for the attempt in the development of novel memory device.

碩士
國立交通大學
電子研究所
107
Neuromorphic computing is expected to emulate brain functions in the near future. There are several nonvolatile memory such as PCRAM, CBRAM, RRAM have been proposed as synaptic memory device. All of above, RRAM is the most promising candidate, due to its several advantages, low power consumption, simple structure, excellent endurance, high operation speed. However, the desirable characteristic of synaptic device is different from traditional RRAM. It requires analog switching behavior and multi-level conductance states, which are beneficial to learning accuracy. In this thesis, the bipolar resistive switching behavior and synaptic characteristics are investigated in TiOx-based synaptic memory device. There are three parts in this thesis. First, different thickness TiOx film are deposited in TiN/Ti/TiOx/TiN structure. The relationship between thickness and electrical characteristics is discussed. The thickness of the TiOx switching layer determine the working operation current of the devices. The thicker layer device can work at lower compliance current and make smaller conductive filament. In addition, the influence of different pulse amplitudes applied on potentiation and depression is investigated. When lower pulse amplitude was applied on the device, conductance can gradually change and the nonlinearity is better. However, dynamic range become small and noise increase. The second part is that different Ti thickness effect on TiOx-based synaptic device. We compare their electrical characteristics and synaptic characteristics. We observed that the analog behavior can be improved after inserting a thin Ti layer. Different thickness of Ti layer make different thickness of interfacial layer, which leads the TiOx- based memory device has different capability to form and rupture the filament. As a result, they perform different electrical characteristics and weight update behavior. The other part is that comparing ZrOx/TiOx synaptic device and TiOx synaptic device. The ZrOx/TiOx synaptic device shows more stable analog switching and the nonlinearity of potentiation and depression can be improved to 2.08 and 1.84. Furthermore, it exhibits good endurance and data retention properties.It demonstrates good performance not only for data storage application but also for mimicking biological synapse.

The application of Si nanocrystals as floating gate in the metal oxide semiconductor field-effect transistor (MOSFET) based memory, which brings many advantages due to separated charge storage, attracted much attention in recent years. In this work, Si nanocrystal memory with nanocrystals synthesized by ion implantation was characterized to provide a better understanding of the relationship between structure and performance -- especially charge retention characteristics.

In the structural characterization it was demonstrated that scanning tunneling microscopy (STM) and non-contact atomic force microscopy (nc-AFM) enable much more accurate measurements of the ensemble size distribution and array density for small Si nanocrystals in SiO₂, estimated to be around 2-3 nm and 4 x 10¹² -3 x 10¹³ cm⁻², respectively. The reflection high energy electron diffraction (RHEED) pattern further verified the existence of nanocrystals in SiO₂. Capacitance-voltage (C-V) measurements demonstrated the memory effects. The comparison between charge density and nanocrystal density suggests single charge storage on individual Si nanocrystals.

The electronic property of tunnel oxide layer is a key factor influencing charge retention, and was characterized by conductive atomic force microscopy (C-AFM). An overall high conductance observed between the nanocrystal floating gate and the substrate is believed to be responsible for the relatively short retention time for electrons. A narrowed denuded zone contaminated with nanocrystals is suggested to be the reason for the high conductance, which is further supported by switching events and fluctuations in local current-voltage (I-V) curves. From the results of C-AFM, a better control of nanocrystal distribution close to the channel is shown to be critical for non-volatile nanocrystal memory made via Si ion implantation.

Nanoscale charge retention characteristics of both electrons and holes were probed directly by ultrahigh vacuum (UHV) nc-AFM, in which a highly doped Si tip was applied to inject charges into the nanocrystal layer and monitor subsequent charge dissipation. The results reveal a much longer hole retention time (e.g., >1 day) than that for electrons (e.g., <1 hour), which is consistent with the charge retention characteristics from electrical characterization of nanocrystal floating gate MOS capacitors as well as time-resolved photoluminescence measurements. The large difference in charge retention times for electrons and holes is attributed to the difference in tunneling barrier heights: 3.1 eV and 4.7 eV for electrons and holes, respectively. Based on the charge injection and retention characteristics obtained from UHV nc-AFM and nanocrystal floating gate MOS devices, we suggest that hole programming in Si nanocrystal memory is an interesting choice in improving data retention or in further device scaling.

UHV nc-AFM guarantees high detection sensitivity and stability in charge imaging experiments due to a lack of air damping, so a three-dimensional (3D) electrostatic model can be developed to provide quantitative information regarding the distribution and evolution of the localized charges. For example, a transition from initial complementary error function distribution to Gaussian distribution was suggested in the simulation. In addition, charge detection sensitivity was found to increase with the scanning height, showing much room for further improvement of the sensitivity in UHV nc-AFM. The limitation of the electrostatic model is also discussed, and some knowledge regarding the charge distribution obtained from theoretical analysis and other experimental methods is suggested to be necessary supplements to the quantitative charge analysis by nc-AFM.

Finally, the approach used in the electrostatic simulation of nc-AFM was applied in 3D simulation of Si nanocrystal memory. The dependence of Coulomb charging energy on dielectric environment is analyzed. From the local variation of channel minority carrier density due to separated charge storage, the threshold number density of charged nanocrytals for 1D approximation to break down is shown to be 10¹² cm⁻² in the sample geometry investigated.

博士
國立中央大學
電機工程研究所
97
In recent year, organic materials have attracted much attention due to their potential advantages of flexibility, simple process and low cost. Organic memory is an essential device for any electronic logic system to provide or store information for the logic operation, such as radio-frequency identification (RFID)-tags, electronic-papers, and electronic-signage, which strongly demand for a low cost and simple process. The organic memory devices are basically characterized by two types of structure: two terminal bistable and three terminal transistor-like memory devices. The two terminal bistable memory devices offer the advantages of a low operation voltage and a simple process over three terminal transistor-like devices. In chapter 2, we utilize gold nanoparticles embedded polymer to fabricate bistable organic memory. The I–V characteristics show that the device switches from initial OFF-state to ON-state upon application of external electric field. The current transition exhibits in a very narrow voltage range causing an abrupt increase of the current. The conduction mechanism in nanoparticles contained polymer memory was investigated experimentally and theoretically. A trap-filled space-charge-limited current model is proposed to explain the transport mechanism in this memory device. In chapter 3, we get a stable organic bistable nonvolatile memory (ONBM) by using polymer chain stabilized gold nanoparticles (Au-NPs) in a host polymer as the memory active layer. The TEM images show that the polymer stabilized Au-NPs are well-dispersed in the polymer matrix. We further demonstrate our concept that is feasible for polymer stabilized Au-NPs. This concept enables Au-NPs to be well dispersed in host polymer in order to fabricate the stable devices. This concept enables Au-NPs to be well dispersed in host polymer in order to fabricate the stable devices. The electrical bistability of the device can be precisely controlled by applying a positive voltage pulse or a negative voltage pulse, respectively. This memory can be switched on and off over 1000 times without appreciable performance degradation. In addition, the memory state can retain over 3 days in air environment. In the chapter 4, a 16-byte addressable ONBM array on the plastic substrate has demonstrated. The memory cell can be switched on and off over 1,000 times and the longest retention time can be estimated to be nearly one year in the air. In the analysis of the mechanical flexibility, we demonstrated that electrical properties of our ONBM were fairly stable during the application of compressive stress down to 5 mm in bending radius. After connecting the ONBM array to the current-sensing circuit, the ONBM array can be correctly addressed and operated, while maintaining low-power consumption. To our best knowledge, this is the first actively addressable ONBM array ever demonstrated. In the chapter 5, we demonstrate an UV erasable stacked diode-switch organic nonvolatile bistable memory using a polymer-chain stabilized Au nanoparticles on the plastic substrate in the ambient air. The specified DS-ONBM array can be correctly read and avoided crosstalk in a much simplified peripheral circuits. The absorption spectrum of the gold nanoparticles shows ultra-violet (UV) absorption. Therefore, UV light was used to erase data in the DS-ONBM. The function of UV-erasing and diode-switch could greatly simplify the required peripheral circuits. This DS-ONBM was demonstrated to be able to read, write and retain the data and was reusable by UV light illumination. Hence, the UV-erasable DS-ONBM was fully applicable for key applications in printed electronics such as RFID tags.

碩士
國立中山大學
物理學系研究所
94
In order to obtain memory devices with a lower operating voltages、better endurance and retention ,we use nano-dot to replace floating-gate and narrow the thickness of tunnel-oxide to modify the nonvolatile memory device we are now using. These allow the nonvolatile memory device produced in higher density、operated in lower voltage and program in faster speed. In this study, we have fabricated a nano-dot memory device with NiSi2 .The temperature-dependent leakage current has been measured with the voltage bias swept from -5V to 5V on the outer gate electrode as temperature from 1.2K to 300K.The results from the V-I curve show that the sample with tunnel-oxide layer of 2nm HfO2/1nm SiO2 have a larger leakage current during 50K to 60K when temperature measured from 30K to 100K. And the leakage current is larger in 80K than in 100K to 120K when the tunnel-oxide layer is of 3nm SiO2 . Therefore we have discovered the unique phenomena of leakage current in the temperature from 1.2K to 300K.

碩士
長庚大學
半導體產業研發碩士專班
96
A novel non-volatile memory device is studied in this thesis. At first, the structure of novel non-volatile memory device will be introduced, and then the operation theorem. The novel non-volatile memory device is programmed by GIDL-like mechanism and erased by F-N tunneling. The way to read the novel non-volatile memory device is similar to read NROM. Besides, this structure will be applied in NAND array. Single cell with pass gate structure is a small string to simulate the NAND string. The operation of NAND array will be more understood by the characteristics of single cell with pass gate structure and the SPICE simulation. At last is the experiment of single cell with pass gate structure’s endurance and data retention.

碩士
中原大學
電子工程研究所
98
Non-volatile memories play more and more important roles with the emergence of the portable microelectronic products. The non-volatile semiconductor memories have rapidly progressed as the semiconductor technologies advance. The memory devices having low power consumption, high density, high-speed operation, and full compatibility with the standard CMOS processing will be the future development trend in non-volatile memories. This work explores the erasing charge injection in Non-overlapped Implantation (NOI) MOSFETs. The erasing chracteristics of the NOI nMOSFETs are studied in terms of band-to-band induced hot hole injection and interface trap generation. Two experiments are designed to verify the generation model accuracy, and erase operation influence under difference drain and gate biases of the NOI device. It has been successful to confirm the hot-hole-induced interface trap generation by cross examination between these two experiments, including device simulation and theoretical deduction.

博士
國立臺灣大學
化學工程學研究所
102
Organic-based memory devices have received extensive scientific interest due to their advantages of flexibility, scalability, and material variety. However, the relationships between molecular structures, donor/acceptor compositions and electrical memory characteristics have not been fully explored yet. In this thesis, several donor/acceptor polymeric systems were explored for the understanding of structural or composition effects on the electrical characteristics of resistor-type and transistor-type memory devices. Additionally, the stability of the flexible memory devices was also examined in both memory types for the development of next-generation electronics. In the first three parts of this thesis, materials for resistor-type memory application were investigated. In chapter 2, triphenylamine–pyrene containing donor–acceptor (D-A) polyimides (PIs) on flexible poly(ethylene naphthalate) (PEN)/Al/PIs/Al cross-point devices were developed, which showed the memory characteristics changing from volatile to nonvolatile via the relative copolymer ratio. The PIs were prepared from the diamines AMTPA or pyrene-contained APAP and the dianhydride 6FDA, with relative AMTPA/APAP molar compositions of 100/0, 95/5, 90/10 and 0/100. As the APAP content increased, the memory device characteristics changed from volatile to nonvolatile behavior of flash and write once read many (WORM), since the pyrene moiety could stabilize the radical cation of the APAP moieties. In chapter 3, the PIs blended films were prepared from different compositions of PI(AMTPA-6FDA) and polycyclic aromatic compounds (p-type coronene or n-type PDI-DO). The additives of large π-conjugated polycyclic compounds stabilized the charge transfer complex induced by the applied electric field. Thus, the memory device characteristic changed from the volatile to nonvolatile behavior of flash and WORM as the additive contents increased in both blend systems. Due to the stronger accepting ability and higher electron affinity of PDI-DO than those of coronene, the PI(AMTPA):PDI-DO blend based memory devices showed a smaller threshold voltage and changed the memory behavior in a smaller additive content. Additionally, the endurance and bending cyclic measurements confirmed that the above flexible PI memory devices exhibited excellent reliability and mechanical stability. In chapter 4, bistable resistive switching characteristics collected from the nanocomposites of block copolymers (BCP) and graphene oxide (GO). A well-dispersed composite was obtained through a simple process of blending that utilizing supramolecular interaction between BCP and GO. Nonvolatile WORM memory characteristics were observed from the BCP:GO-based device. The composite could serve as charge storage material and effectively enhance the conductivity under applied bias. In the last two parts of this thesis, polymer electrets for transistor-type memory were developed. In chapter 5, memory characteristics of n-type BPE-PTCDI-based OFET using a series of D-A polyimide electrets of PI(AMTPA-6FDA), PI(APAN-6FDA), PI(APAP-6FDA) were studied. Among the polymer electrets, the OFET memory device based on PI(APAP-6FDA) exhibited the largest memory window and the best charge retention ability due to the introduction of polycyclic arene pyrene into the electron donating moiety. With the excellent carrier delocalization, pyrene successfully enhanced the charge storage ability and sustained the CT complex for high performance nonvolatile OFET memories with electrets of D-A polyimide system. In chapter 6, a series of polyimides (PITE(BMI-BMMD), PI(APS-ODPA), and PI(APS-BPA)) were prepared for better understanding the function of CT complex in polymer electret for OFET memory. The memory characteristic changed from the WORM behavior (PITE(BMI-BMMD)) to flash (PI(APS-ODPA) and PI(APS-BPA)), due to the energetic relationships and charge transfer complex. Besides, BPE-PTCDI transistor memory devices fabricated on flexible PET substrates exhibited multilevel data storage (WMRM) characteristics since the dielectric capacity was enhanced by its high sulfur-content of PITE(BMI-BMMD). Such flexible WMRM devices could have potential applications for the next generation high-density data storage components.

碩士
國立交通大學
電子研究所
98
Many types of consumer electronics products require high-capacity memory with the development of the technology, in which demanding for non-volatile memory is the largest. Flash memories face the issue of scale limit, so the research of next generation non-volatile memories is booming. The resistive switching random access memory (RRAM) have these advantages, such as high operation speed, low power consumption, high cell density, and lower scale limit and non-destructive readout, which have the opportunity to become the mainstream of next generation non-volatile memory. In this thesis, the research is focus on the electric characteristic of 1T1R device, and it divides two parts. First part, we used transistor as current limiter to improve the switching characteristic based on the ZrO2 thin films, and second part is the research of 1T1R based on the SrZrO3 thin films. In the first part, ZrO2-based 1T1R devices could efficiently control compliance current and lower the operation current to 25uA, operation voltage to 1.5V, which reach the advantage of low power consumption. In addition, 1T1R device have multistate operation in a single device due to the thickness and number of filaments which controlled by compliance current; there is no data loss at the nondestructive readout test for over 10000 seconds under 0.3V DC voltage; and retention test is 106s at room temperature. Next, size effect is also studied. As the area of ZrO2 thin films scale down (1um2), the resistance ration becomes larger. At LRS, the current is independent on the area, but at HRS, the current is decreasing following the scale down of the ZrO2 area. In the second part, 1T1R devices which are based on the e SrZrO3 thin films could have large resistance ration over 100 times.

碩士
國立交通大學
電信工程研究所
102
In this thesis, we investigate endurance characteristic for 10K cycles in P-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device by using dynamic programming (PGM) scheme of Channel Hot Hole Induced Hot Electron injection (CHHIHE) and Fowler-Nordheim tunneling (FN) erase. After endurance, the Vt shift, gate-induced drain leakage (GIDL) current increase and subthreshold swing (SS) degradation occurred. So, in this work, 3 possible models of degradation are investigated by examining the measurement data and found that the electron trap and interface state models are the most reasonable to affect these degradations.

碩士
國立成功大學
微電子工程研究所
102
Recent years, NAND flash memory device which has been widely applied to 3C mobile products is suitable for mass storage devices because of high storage density, high access speed, and low unit cost. The main purpose of this thesis is about reliability and performance of peripheral devices in NAND flash memory. Since NAND flash memory cell needs high voltage for program - erase cycle, the peripheral device of cell, word line driver circuit, has to transmit high voltage to memory cell from superior circuit. The device transmitting signals receives a large VDS and VSB for substrate. This thesis investigated about reliability of high voltage peripheral devices affected by hot carrier effect with high voltage signals and body bias during transmitting condition. 　　The peripheral device would pass through some specific bias in the process of switching, such as high drain bias and high substrate bias, or the generating large substrate current condition. We did hot carrier stress experiments in these situations and found out degradation mechanisms, reliability, and lifetime of device. These results were verified by TCAD simulations. Results indicated that a high drain bias led to hot carrier effect resulting in significant degradation of drain current in linear region(IDlin), and a high substrate bias led to second impact ionization under channel resulting in a threshold voltage(VTH) shift owing to increased vertical electric field inside device. 　　The other part of this thesis, we research the different LDD(Lightly Doped Drain) length of for the impact of the reliability of devices. After stressing different LDD length devices, the experimental results conformed to expectation that the degradation mechanisms were the same, and characteristics resembled in short channel devices, the shorter the LDD length, the poor the immunity to stress. We also defined the lifetime of devices to investigate impact on lifetime in different dimension. The last part gave evidence for result that two devices with the same total LDD length but different length in source and drain region have the same characteristics but obtain different degradation after stress.

博士
國立臺灣大學
高分子科學與工程學研究所
101
This study has been separated into five chapters. Chapter 1 is general introduction. In Chapter 2, the new functional triphenylamine-based (TPA-based) aromatic polyether (OXPE) and polyester (6FPET) derived from 4,4’-dihydroxyltriphenyamine with 2,5-bis(4-fluorophenyl)-1,3,4-oxadiazole and 4,4’-(hexafluoroisopropylidene)bis(benzoylchloride), respectively, were prepared and used for memory device application. To understand the relationship between linkage group and memory behavior, polyamide 6FPA, polyimide 6FPI, and the coresponding isomer 6FPI’ were also synthesized and investigated their memory properties. Furthermore, to illustrate the linkage effect systematically, TPA-based sulfonyl-containing polymers DSPE, DSPET, DSPA, and DSPI were also added into discussion. Generally, the TPA-based polymers with flexible linkage, lower LUMO energy level, and higher dipole moment have longer retention time. Chapter 3 describes the memory properties of new functional polyimides 5Ph-ODPI, 5Ph-DSPI, 5Ph-PMPI, and 5Ph-NPPI derived from N,N’-bis(4-aminophenyl)-N,N’-di(4-methoxyl-phenyl)1,4-phenylene-diamine and various dianhydrides. For comparison, the corresponding 5Ph-6FPI was also added into discussion. The differences of HOMO energy levels, LUMOs energy levels, and dipole moment among these five polyimides with different electron-withdrawing acceptor moieties were investigated and demonstrated the effect on the memory behavior. 5Ph-ODPI did not show memory properties, 5Ph-6FPI exhibited dynamic random access memory (DRAM) characteristic, 5Ph-PMPI with stronger electron-withdrawing linkage revealed static random access memory (SRAM) behavior, and 5Ph-NPPI with the strongest electron-withdrawing linkage showed write-once-read-many-times (WORM) type non-volatile memory behavior. On the whole, with the electron-withdrawing moiety intensity of polyimides increasing, the retention time of corresponding memory device increases. However, 5Ph-DSPI has the LUMO energy levels between 5Ph-6FPI and 5Ph-PMPI but revealed non-volatile WORM behavior resulting from the highest dipole moment 5.45D. In chapter 4, the new functional polyimides 9Ph-ODPI, 9Ph-DSPI, and 9Ph-PMPI consisting of electron-donating starburst triarylamine unit and different dianhydrides were synthesized and used for memory device application along with 9Ph-6FPI. To investigate the effects of donor moieties within polyimides on memory behavior, the corresponding 3Ph- series polyimides (3Ph-PIs) and 5Ph- series polyimides (5Ph-PIs) were added into discussion. With the electron-donating intensity increasing from 3Ph-PIs, 5Ph-PIs, to 9Ph-PIs, the retention time of memory device shows the systematical increasing tendency. Besides, the in-situ UV-vis absorption spectra of memory devices during switching-ON were utilized as direct evidence to confirm the relationship between charge transfer (CT) complex stability and memory retention time. Finally, the flexible programmable memory device was fabricated for the practical future flexible electronics applications. Chapter 5 contains conclusions and future works.

碩士
國立清華大學
電子工程研究所
94
In recent years, the portable electronic product have widely applied, such as digit camera, notebook computer, mp3 walkman, intelligent IC card, USB Flash personal disc and so on , these play an important role in the market. These products are all based on nonvolatile memory. Nonvolatile memories include three type: (1)conventional flash memory, (2)SONOS memory, (3)nanocrystal memory. These memories have low power losing and fast program/erase speed. Flash memory has leaking and program/erase problems when scaling down, but SONOS and nanocrystal memory have not these problems. Therefore, in the process of scaling down memory device, SONOS and nanocrystal memory are the better choice. In this thesis, we will bring up a new idea of crystallize nanocrystal. Co-sputter system has been introduced to deposit a SizGeyOz film to replace the Floating Gate in Flash structure. Unlike the conventional process, this is a new process to deposit tri-layer of memory structure, and SixGeyOz is a new material. After two different thermal treatments è RTO and Furance, Ge in the SizGeyOz film will be segregated to crystallize Ge nanodots embedded in the SiO2/GeOx film. There are three situations in RTO and Furnace oxidation because the different duration and temperature of oxidation, Three energy band models and chemical formulas can be considered to support experiment results.

碩士
中原大學
電子工程研究所
92
Abstract Non-Volatile Memories (NVMs) have been developed and progressing in past decades, and recently it has been received much attention in mobile and portable applications, such as mobile phones, smart cards and digital cameras. In the First part of this thesis, the history of the Non-Volatile Memory (NVM) and the concept of the NVM are introduced. And the typical NVMs, such as EPROM, EEPROM, and flash memory are also introduced. The main purpose of this thesis presents the characteristics of a single-polysilicon non-volatile memory (NVM) device by using a novel NOI n-MOSFETs. Hot carriers are generated in NOI devices and to be stored as memories . The characteristics of this potential single-transistor NVM cell, including 2-bit operation, programming and erasing characteristics, are investigated. Their stability and reliability characteristics such as retention and cycling are also evaluated.

碩士
大葉大學
電機工程研究所
86
The influence of bias conditions for program,erase operation and reliability for the flash memory device will be developed in ourstudy. The flash memory cell structure is a simple self-aligned doublepolysilicon with the stacked gate structure without any select transistor and a ONO layer were fabricated between the poly gates. Three kinds of device reliability contraints are examined for hot electrondegradation, hot electron avalanche breakdown, and time-dependent dielectric breakdown. Also, we will draw out an optimum design region of oxide thickness and channel length when the drain bias is 5V. Meanwhile, in our work, we will study the influences of program and erase operation under various bias situations, in which the operations are the channel hot electron injection,the source-side Fowler-Nordhiem erasing, the channel Fowler-Nordheim program and erasing, and the negative gate erasing. Eventually, we will hope that ourstudy in this work may be helpful in the next generation design.

碩士
中原大學
電子工程研究所
98
The non-volatile semiconductor memories have rapidly progressed as the semiconductor technologies advance. The memory devices having low power consumption, high density, high-speed operation, and full compatibility with the standard CMOS processing will be the future development trend in non-volatile memories. This work explores the data retention of trapped electrons in the Non-overlapped Implantation (NOI) MOSFETs. As potential non-volatile memories, the NOI devices can be programmed by channel hot electron injection. By Arrhenius equation, the charge loss with time has been modeled and predicted under elevated temperatures. The charge loss in the nitride was also measured using a modified charge pumping method. Data retention characteristics with different programming conditions were studied. Finally, the trend of charge loss in the NOI devices is affected by different program biases.

碩士
國立交通大學
材料科學與工程學系所
102
Resistive random access memory (RRAM) has been widely recognized as the next-generation nonvolatile memory to replace conventional flash memory. This study investigates the resistive switching properties of RRAM containing aluminum (Al) as the top electrode, platinum (Pt) as the bottom electrode and hafnium oxide (HfO2) as the insulator layer prepared by sputtering deposition. Electrical measurement indicated that the thickness of HfO2 layer affects Forming voltage (VForm) of RRAM and too large VForm would permanently damage the device. As to the devices containing thin HfO2 layers, subsequent annealing treatment caused the rough surface and degraded the electrical performance. The area of electrode negligibly affected the resistance of low resistance state (LRS) whereas the resistance of high resistance state (HRS) increase with the decrement of electrode’s area. For the HfO2 layers annealed at 300C, 500C, and 700C for 30 min in the atmospheric ambient, the effect of heat treatment on the remedy of the oxygen deficiency in HfO2 layer and surface roughness were analyzed by using x-ray photoelectron spectroscopy and atomic force microscopy, and the structure of devices were confirmed by using scanning electron microscopy. Moreover, the annealing treatments at temperatures less than 500°C insignificantly affected the electrical performance of samples. When annealing temperature was raised to 700C, the sample exhibited stable resistance of HRS and VSet as well as improved endurance and retention properties. In such a sample, amorphous HfO2 transformed to polycrystalline monoclinic structure as revealed by x-ray diffraction analysis. The improvement of electrical performance was hence ascribed to the presence of grain boundaries which provide stable formation routes of conduction filament in HfO2. However, annealing treatment seemed to reduce the interface traps at the interface of HfO2 and electrode, leading to high and unstable resistance of HRS at the initial stage of operation.

碩士
修平科技大學
電機工程碩士班
105
In this studied, BiFeO3 (BFO) thin films were fabricated on flexible stainless steel (FSS) by spin coating with a sol–gel method and rapid thermal annealing in the case of no oxygen. The thesis is divided into three parts to explore. First, the properties of pure phase BFO thin films after different annealing were discussed and compared. The second and third parts were investigated the partially doped with a small amount of Ni, Zn on the structure, ferroelectricity, dielectric and electrical properties of BiFe1-xNixO3 (BFNO, x=0, x=0.02, x=0.04, x=0.06, x=0.08) and BiFe1-xZnxO3 (BFZO, x=0, x=0.02, x=0.04, x=0.06, x=0.08) thin films. The results also were compared with the pure phase BFO films. According to the experimental resulted, the pure BFO thin films had the best annealing temperature at 500 oC. The X-ray diffraction analysis showed that thin film had the best crystal phase and without secondary phase. Under the annealing temperature at 500 oC, the microstructure, ferroelectric, dielectric and leakage current characteristics of the BFNO and BFZO were studied. The remanent polarization 2Pr and coercive field 2Ec of BFO, BFNO (4%), BFZO (4%) were 110, 140, 120 μC/cm2 and 16.66, 26.66, 12 kV/cm, respectively. Among them the BFNO (4%) thin film had the best ferroelectric properties and could apply in ferroelectric memory devices. The leakage current density of BFO, BFNO (4%), BFZO (4%) under applied field 50kV/cm were 3.36×10-3, 1.754×10-9, 1.26×10-6 A/cm2, respectively. The BFNO (4%) thin film had the relative low leakage current density. In addition, the BFNO (4%) thin film had better dielectric constant and dielectric loss of 32.87 and 0.051, respectively. From this studied, when Ni and Zn doping in BFO thin film could be effectively reduced the leakage current, which could successfully inhibit the Fe3+ ion conversion of Fe2+ ions and reduced the oxygen vacancy. In addition, when Ni was doped with x = 0.04, it had better ferroelectric, dielectric and relative low leakage current characteristics.

碩士
國立交通大學
電子研究所
105
Nonvolatile memory devices are enormously used in consumer electronics. Ferroelectric materials have been attracted attention for past decades since these are the core of ferroelectric random acces memory(FRAM) which play important role in the market due to fast speed and much lower power consumption. However, as the CMOS devices scale down continuously, it is imperative that we find out new ferroelectric materials to replace traditional one such as PZT and SBT which can’t scale and is not applicable for CMOS process. The HfO2-base ferroelectric field effect transistors (FeFETs) with metal-ferroelectrical-insulator-silicon(MFIS) structure become a promising candidate due to the high density, high speed, nonvolatile and non-destructive read. Moreover, it can scale down and integrate into the CMOS technology. In this thesis, we illustrated the fabrication and electrical characteristics of MFIS capacitors and MFM capacitors and then we successfully fabricated HfO2-based MFIS FETs with a TaN/HAO/SiO2/P-sub, in which HAO is used as the ferroelectric gate and SiO2 is used as the buffer layer. The FeFETs annealed at the 650oC have better ferroelectric properties. The memory window of Id-Vg is about 0.4V and Subthreshold slope is 130mV/dec.

碩士
國立彰化師範大學
美術學系
106
Abstract This article is to discuss the contexts of art and the display of works between 2015 and 2018. By reorganize and research the writing, object , photography, pictures, and people, I’m trying to connect these four End-point with my own works: “the memories of past”, “life experiences”, “the accumulation of habitation memories” and “the observation of life”. The paper is telling the extent and structure of this thesis, the meaning of “create” to the author, study method, and classification, relation between pictures and devices, the process of becoming a photograph, how to present a photograph, the different cause by the interaction of photography and devises. Next chapter is talking about the structure of creating by themselves, form of artworks and content. Many artists use it to define the style of their own and compare the content of photography with life contexts. Bringing elements,Filming, photograph bake to the four End-point and the conclusion of reference, and extend these four End-point which are connected with photography become “physical property image” and “heterogeneous image”. Next chapter finds essential topics of creation, clarify the style of creation form. Sorted out the form, content, spirituality of my own works. Chapter four mention the work publish at Z-space, particles develop series, in my personal exhibition “The split of gleam”. Extending to discover in four End-point, the perspective of people and vision, combined with aesthetics unified the attitude of ductility by thinking of four End-point. Presenting the influence between the photograph and human, made by four End-point with a description. Next chapter integrate thoughts and conclusions with previous chapters, rethinking the attitude of creating, finally clarify the stand of the art of myself, and making new thoughts with the pattern of producing photography, the value of art and creative method in the future. Keywords: Paramnésie, Heterogeneous Image, The Split, Photo Documentary, Urban-rural gap