Relevant bibliographies by topics / Memory device

Academic literature on the topic 'Memory device'

Author: Grafiati
Published: 4 June 2021
Last updated: 5 February 2022

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Journal articles on the topic "Memory device"

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Kim, Dongshin, Ik-Jyae Kim, and Jang-Sik Lee. "Memory Devices for Flexible and Neuromorphic Device Applications." Advanced Intelligent Systems 3, no. 5 (January 25, 2021): 2000206. http://dx.doi.org/10.1002/aisy.202000206.

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Novosad, V., Y. Otani, A. Ohsawa, S. G. Kim, K. Fukamichi, J. Koike, K. Maruyama, O. Kitakami, and Y. Shimada. "Novel magnetostrictive memory device." Journal of Applied Physics 87, no. 9 (May 2000): 6400–6402. http://dx.doi.org/10.1063/1.372719.

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Tatematsu, Take. "4464750 Semiconductor memory device." Microelectronics Reliability 25, no. 2 (January 1985): 401. http://dx.doi.org/10.1016/0026-2714(85)90179-9.

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Kim, Byeongjeong, Chandreswar Mahata, Hojeong Ryu, Muhammad Ismail, Byung-Do Yang, and Sungjun Kim. "Alloyed High-k-Based Resistive Switching Memory in Contact Hole Structures." Coatings 11, no. 4 (April 14, 2021): 451. http://dx.doi.org/10.3390/coatings11040451.

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Resistive random-access memory (RRAM) devices are noticeable next generation memory devices. However, only few studies have been conducted regarding RRAM devices made of alloy. In this paper, we investigate the resistive switching behaviors of an Au/Ti/HfTiOx/p-Si memory device. The bipolar switching is characterized depending on compliance current under DC sweep mode. Good retention in the low-resistance state and high-resistance state is attained for nonvolatile memory and long-term memory in a synapse device. For practical switching operation, the pulse transient characteristics are studied for set and reset processes. Moreover, a synaptic weight change is achieved by a moderate pulse input for the potentiation and depression characteristics of the synaptic device. We reveal that the high-resistance state and low-resistance state are dominated by Schottky emissions.
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Yang, Yang, Liping Ma, and Jianhua Wu. "Organic Thin-Film Memory." MRS Bulletin 29, no. 11 (November 2004): 833–37. http://dx.doi.org/10.1557/mrs2004.237.

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AbstractRecently, organic nonvolatile memory devices have attracted considerable attention due to their low cost and high performance. This article reviews recent developments in organic nonvolatile memory and describes in detail an organic electrical bistable device (OBD) that has potential for applications. The OBD consists of a tri-layer of organics/metal nanoclusters/organics sandwiched between top and bottom electrodes. A sufficiently high applied bias causes the metal nanoparticle layer to become polarized, resulting in charge storage near the two metal/organic interfaces. This stored charge lowers the resistance of the device and leads to an electrical switching behavior. The ON and OFF states of an OBD differ in their conductivity by several orders of magnitude and show remarkable bistability—once either state is reached, the device tends to remain in that state for a prolonged period of time. More important, the conductivity states of an OBD can be precisely controlled by the application of a positive voltage pulse (to write) or a negative voltage pulse (to erase). Device performance tests show that the OBD is a promising candidate for high-density, low-cost electrically addressable data storage applications.
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Wang, Lu, Yukai Zhang, and Dianzhong Wen. "Flexible Nonvolatile Bioresistive Random Access Memory with an Adjustable Memory Mode Capable of Realizing Logic Functions." Nanomaterials 11, no. 8 (July 31, 2021): 1973. http://dx.doi.org/10.3390/nano11081973.

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In this study, a flexible bioresistive memory with an aluminum/tussah hemolymph/indium tin oxide/polyethylene terephthalate structure is fabricated by using a natural biological material, tussah hemolymph (TH), as the active layer. When different compliance currents (Icc) are applied to the device, it exhibits different resistance characteristics. When 1 mA is applied in the positive voltage range and 100 mA is applied in the negative voltage range, the device exhibits bipolar resistive switching behavior. Additionally, when 1 mA is applied in both the positive- and negative-voltage ranges, the device exhibits write-once-read-many-times (WORM) characteristics. The device has good endurance, with a retention time exceeding 104 s. After 104 bending cycles, the electrical characteristics remain constant. This memory device can be applied for “AND” and “OR” logic operations in programmable logic circuits. The prepared flexible and transparent biomemristor made of pure natural TH provides a promising new approach for realizing environmentally friendly and biocompatible flexible memory, nerve synapses, and wearable electronic devices.
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Katanosaka, Naok. "4885721 Semiconductor memory device with redundant memory cells." Microelectronics Reliability 30, no. 6 (January 1990): ii. http://dx.doi.org/10.1016/0026-2714(90)90388-4.

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White, Marvin H., Yu (Richard) Wang, Stephen J. Wrazien, and Yijie (Sandy) Zhao. "ADVANCEMENTS IN NANOELECTRONIC SONOS NONVOLATILE SEMICONDUCTOR MEMORY (NVSM) DEVICES AND TECHNOLOGY." International Journal of High Speed Electronics and Systems 16, no. 02 (June 2006): 479–501. http://dx.doi.org/10.1142/s0129156406003801.

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This paper describes the recent advancements in the development of nanoelectronic SONOS nonvolatile semiconductor memory (NVSM) devices and technology, which are employed in both embedded applications, such as microcontrollers, and 'stand-alone', high-density, memory applications, such as cell phones and memory 'sticks'. Multi-dielectric devices, such as the MNOS devices, were among the first NVSM; however, over the ensuing years the double polysilicon, floating-gate device has become the dominant semiconductor NVSM technology. Today, however, questions arise as to future scaling and cost effectiveness of floating gate technology – questions, which have sparked renewed interest in SONOS technology. The latter offers a single polysilicon device structure with reduced lithography steps together with compact cell layouts - compatible with 'standard' CMOS technology for cost effectiveness. In addition, SONOS technology offers performance features, such as reduced erase and write voltage levels to ease the design of peripheral memory circuits with a decrease in electric fields and localized charge storage for improved reliability and multi-bit storage, and ease of memory testing. A special feature of SONOS technology is radiation hardness, which makes this technology ideal for advanced Space and Military systems. SONOS devices use ultra-thin tunnel oxides (2nm) and operate with 'modified' Fowler-Nordheim and 'direct' tunneling in both erase and write (program) modes. A thicker tunnel oxide SONOS device (5nm), called the NROM™ device, uses 'hot electron injection for programming and 'hot hole band-to-band tunneling' for erase. The NROM™ device provides spatially isolated, two-bit storage with the possibility of multi-level charge (MLC) storage at each bit location. This paper describes the physical electronics for these device structures and their erase/write, retention and endurance characteristics. In addition, several novel SONOS device structures are discussed as potential candidates for future NVSM.
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Tsoukalas, Dimitris, and Emanuele Verrelli. "Inorganic Nanoparticles for either Charge Storage or Memristance Modulation." Advances in Science and Technology 77 (September 2012): 196–204. http://dx.doi.org/10.4028/www.scientific.net/ast.77.196.

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We present prototype memory devices using metallic and metal oxide nanoparticles obtained by a physical deposition technique. The two memory device examples demonstrated concern the use of platinum nanoparticles for flash-type memories and the use of titanium oxide nanoparticles for resistive memories. Both approaches give interesting device memory properties with resistive memories being still in an early exploratory phase.
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Li, Liang, Qi-Dan Ling, Siew-Lay Lim, Yoke-Ping Tan, Chunxiang Zhu, Daniel Siu Hhung Chan, En-Tang Kang, and Koon-Gee Neoh. "A flexible polymer memory device." Organic Electronics 8, no. 4 (August 2007): 401–6. http://dx.doi.org/10.1016/j.orgel.2007.02.002.

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Dissertations / Theses on the topic "Memory device"

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Yao, Atsushi. "Logic and memory devices of nonlinear microelectromechanical resonator." 京都大学 (Kyoto University), 2015. http://hdl.handle.net/2433/199314.

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Feng, Tao Atwater Harry Albert. "Silicon nanocrystal charging dynamics and memory device applications /." Diss., Pasadena, Calif. : Caltech, 2006. http://resolver.caltech.edu/CaltechETD:etd-06052006-141803.

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Johnson, Nigel Christopher. "All-optical regenerative memory using a single device." Thesis, Aston University, 2009. http://publications.aston.ac.uk/15331/.

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In recent years the optical domain has been traditionally reserved for node-to-node transmission with the processing and switching achieved entirely in the electrical domain. However, with the constantly increasing demand for bandwidth and the resultant increase in transmission speeds, there is a very real fear that current electronic technology as used for processing will not be able to cope with future demands. Fuelled by this requirement for faster processing speeds, considerable research is currently being carried out into the potential of All-optical processing. One of the fundamental obstacles in realising All-optical processing is the requirement for All-optical buffering. Without all-optical buffers it is extremely difficult to resolve situations such as contention and congestion. Many devices have been proposed to solve this problem however none of them provide the perfect solution. The subject of this research is to experimentally demonstrate a novel all-optical memory device. Unlike many previously demonstrated optical storage devices the device under consideration utilises only a single loop mirror and a single SOA as its switch, whilst providing full regenerative capabilities required for long-term storage. I will explain some of the principles and characteristics of the device, which will then be experimentally demonstrated. The device configuration will then be studied and investigated as to its suitability for Hybrid Integrated Technology.
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Panayi, Christiana. "Memory-assisted measurement-device-independent quantum key distribution systems." Thesis, University of Leeds, 2016. http://etheses.whiterose.ac.uk/12449/.

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Quantum key distribution (QKD) is one of the most prominent methods for secure exchange of cryptographic keys between two users. The laws of physics provide it with an immense tool towards secure communications. Although QKD has been proven to reach distances on the order of a few hundreds of kilometers, the transmission rate of the key significantly drops when we go to further distances. One possible solution to this is to build a network of trusted nodes. The trust requirement will however narrow its scope of deployability. In this thesis, we focus on improving the key rate performance of secure communications by introducing imperfect quantum memories (QMs) in a measurement-device-independent (MDI) QKD system. In this thesis, a protocol with the potential of beating the existing distance records for conventional QKD systems is proposed. It borrows ideas from quantum repeaters by using memories in the middle of the link, and that of MDI-QKD, which only requires optical source equipment at the user’s end. For certain fast memories, our scheme allows a higher repetition rate than that of quantum repeaters, thereby requiring lower coherence times. By accounting for various sources of nonideality, such as memory decoherence, dark counts, misalignment errors, and background noise, as well as timing issues with memories, we develop a mathematical framework within which we can compare QKD systems with and without memories. In particular, we show that with the state-of-the-art technology for quantum memories, it is possible to devise memory-assisted QKD systems that, at certain distances of practical interest, outperform current QKD implementations. To extend this work, we consider a suitable candidate that fullfils the requirements we have set for the QMs, i.e., the ensemble-based QMs. This type of memories, nevertheless, suffers from multiple-excitation effects, which can deteriorate the performance of the memory-assisted MDI-QKD system. As a solution we propose an alternative approach to the memory-assisted MDI-QKD by employing entangled-photon sources. We fully analyse this system by including modulation errors during the state-preparation at a single-photon source. We identify under which regimes of operation this system outperforms present QKD implementations. Overall we obtain a realistic account of what can be done with current technologies in order to improve the performance, in terms of rate versus distance, of QKD systems. Our findings can guide us toward implementing larger quantum networks.
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El, Hassan Nemat Hassan Ahmed. "Development of phase change memory cell electrical circuit model for non-volatile multistate memory device." Thesis, University of Nottingham, 2017. http://eprints.nottingham.ac.uk/39646/.

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Phase change memory (PCM) is an emerging non-volatile memory technology that demonstrates promising performance characteristics. The presented research aims to study the feasibility of using resistive non-volatile PCM in embedded memory applications, and in bridging the performance gap in traditional memory hierarchy between volatile and non-volatile memories. The research studies the operation dynamics of PCM, including its electrical, thermal and physical properties; in order to determine its behaviour. A PCM cell circuit model is designed and simulated with the aid of SPICE tools (LTSPICE IV). The first step in the modelling process was to design a single-level PCM (SLPCM) cell circuit model that stores a single bit of data. To design the PCM circuit model; crystallization theory and heat transfer equation were utilized. The developed electrical circuit model evaluates the physical transformations that a PCM cell undergoes in response to an input pulse. Furthermore, the developed model accurately simulated the temperature profile, the crystalline fraction, and the resistance of the cell as a function of the programming pulse. The circuit model is then upgraded into a multilevel phase change memory (MLPCM) cell circuit model. The upgraded MLPCM circuit model stores two bits of data, and incorporates resistance drift with time. The multiple resistance levels were achieved by controlling the programming pulse width in the range of 10ns to 200ns. Additionally, the drift behaviour was precisely evaluated; by using statistical data of drift exponents, and evaluating the exact drift duration. Moreover, the simulation results for the designed SLPCM and MLPCM cell models were found to be in close agreement with experimental data. The simulated I-V characteristics for both SLPCM and MLPCM mimicked the experimentally produced I-V curves. Furthermore, the simulated drift resistance levels matched the experimental data for drift durations up to 103 seconds; which is the available experimental data duration in technical literature. Furthermore, the simulation results of MLPCM showed that the deviation between the programmed and drifted resistance can reach 6x106Ω in less than 1010 seconds. This resistance deviation leads to reading failures in less than 100 seconds after programming, if standard fixed sensing thresholds method was used. Therefore, to overcome drift reliability issues, and retain the density advantage offered by multilevel operation; a time-aware sensing scheme is developed. The designed sensing scheme compensates for the drift caused resistance deviation; by using statistical data of drift coefficients to forecast adaptive sensing thresholds. The simulation results showed that the use of adaptive time-aware sensing thresholds completely eliminated drift reliability issues and read errors. Furthermore, PCM based nanocrossbar memory structure performance in terms of delay and energy consumption is studied in simulation environment. The nanocrossbar is constructed with a grid of connecting wires; and the designed PCM cell circuit model is used as memory element and placed at junction points of the grid. Then the effect of connecting nanowires resistance in PCM nanocrossbar performance is studied in passive crossbars. The resistance of a connecting wire segment was evaluated with physical formulas that calculate nanoscaled conductors’ resistance. Then a resistor that is equivalent to each wire segment resistance is placed in the tested crossbar structure. Simulation results showed that due to connecting wires resistance; the PCM cells are not truly biased to programming voltage and ground. This leads to 40% deviation in the programed low resistive state from the targeted levels. Thus, affecting PCM reliability and decreasing the high to low resistance ratio by 90%. Therefore, programming and architectural solutions to wire resistance related reliability issue ar presented. Where dissipated power across wire resistance is compensated for; by controlling programming pulse duration. The programming solution retained reliability however; it increased programming energy consumption and delay by an average of 40pJ and 60ns respectively per operation. Additionally, the effects of leakage energy in PCM based nanocrossbars were studied in simulation environment. Then, a structural solution was developed and designed. In the designed structure; leakage sneak paths are eliminated by introducing individual word lines to each memory element. This method led to 30% reduction in reading delay, and consumed only about sixth the leakage energy consumed by the standard structure. Moreover, a sensing scheme that aims to reduce energy consumption in PCM based nanocrossbars during reading process was explored. The sensing method is developed using AC current in contrast to the standard DC current reading circuits. In the designed sensing circuit, a low pass filter is utilized. Accordingly, the filter attenuation of the applied AC reading signal indicates the stored state. The proposed circuit design of the AC sensing scheme was constructed and studied in simulation environment. Simulation results showed that AC sensing has reduced reading energy consumption by over 50%; compared to standard DC sensing scheme. Furthermore, the use of SLPCM and MLPCM in memory applications as crossbar memory elements, and in logic applications i.e. PCM based LUTs was explored and tested in simulation environment. The PCM performance in crossbar memory was then compared to current Static Random Access Memory (SRAM) technology and against one of the main emerging resistive non-volatile memory technologies i.e. Memristors. Simulation results showed that programming and reading energy consumption of PCM based crossbars were five orders of magnitude more than SRAM based crossbars. And reading delay of SRAM based crossbars was only 38% of reading delay of PCM based counterparts. However, PCM cells occupies less than 60% of the area required by SRAM and can store multiple bit in a single cell. Moreover, Memristor based nanocrossbars outperformed PCM based ones; in terms of delay and energy consumption. With PCM consuming 2 orders of magnitude more energy during programming and reading. PCM also required 10 times the programming delay. However, PCM crossbars offered higher switching resistance range i.e. 170kΩ compared to the 20kΩ offered by memristors; which support PCM multibit storage capability and higher density.
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Nominanda, Helinda. "Amorphous silicon thin film transistor as nonvolatile device." Texas A&M University, 2008. http://hdl.handle.net/1969.1/86004.

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n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs) with copper electrodes prepared by a novel plasma etching process have been fabricated and studied. Their characteristics are similar to those of TFTs with molybdenum electrodes. The reliability was examined by extended high-temperature annealing and gate-bias stress. High-performance CMOS-type a-Si:H TFTs can be fabricated with this plasma etching method. Electrical characteristics of a-Si:H TFTs after Co-60 irradiation and at different experimental stages have been measured. The gamma-ray irradiation damaged bulk films and interfaces and caused the shift of the transfer characteristics to the positive voltage direction. The field effect mobility, on/off current ratio, and interface state density of the TFTs were deteriorated by the irradiation process. Thermal annealing almost restored the original state's characteristics. Floating gate n-channel a-Si:H TFT nonvolatile memory device with a thin a- Si:H layer embedded in the SiNx gate dielectric layer has been prepared and studied. The hysteresis of the TFT's transfer characteristics has been used to demonstrate its memory function. A steady threshold voltage change between the "0" and "1" states and a large charge retention time of > 3600 s with the "write" and "erase" gap of 0.5 V have been detected. Charge storage is related to properties of the embedded a-Si:H layer and its interfaces in the gate dielectric structure. Discharge efficiencies with various methods, i.e., thermal annealing, negative gate bias, and light exposure, separately, were investigated. The charge storage and discharge efficiency decrease with the increase of the drain voltage under a dynamic operation condition. Optimum operating temperatures are low temperature for storage and higher temperature for discharge. a-Si:H metal insulator semiconductor (MIS) capacitor with a thin a-Si:H film embedded in the silicon nitride gate dielectric stack has been characterized for memory functions. The hysteresis of the capacitor's current-voltage and capacitance-voltage curves showed strong charge trapping and detrapping phenomena. The 9 nm embedded a-Si:H layer had a charge storage capacity six times that of the capacitor without the embedded layer. The nonvolatile memory device has potential for low temperature circuit applications.
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八尾, 惇. "非線形微小電気機械共振器を用いたロジック及びメモリデバイス." Kyoto University, 2015. http://hdl.handle.net/2433/199521.

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Najib, Mehran. "Toward Analysis of a Cooling Device using Shape Memory Alloys." University of Toledo / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1481300993095304.

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Lenz, Thomas [Verfasser]. "Device physics and nanostructuring of organic ferroelectric memory diodes / Thomas Lenz." Mainz : Universitätsbibliothek Mainz, 2017. http://d-nb.info/1135748624/34.

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Waghela, Krunal R. "Fabrication of a memory device using polyaniline nanofibers and gold nanoparticles." Diss., Rolla, Mo. : Missouri University of Science and Technology, 2010. http://scholarsmine.mst.edu/thesis/pdf/Waghela_09007dcc8072f881.pdf.

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Thesis (M.S.)--Missouri University of Science and Technology, 2010.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed January 6, 2010) Includes bibliographical references.
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Books on the topic "Memory device"

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Field, Lewis. Nonvolatile memory devices. Norwalk, CT: Business Communications Co., 1999.

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Nonvolatile memories: Materials, device and applications. Stevenson Ranch, California, USA: American Scientific Publishers, 2012.

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Jaglall, Susan. Categorical organization as a device for facilitating memory recall. Sudbury, Ont: Laurentian University, Department of Psychology, 1993.

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Dace, Andrea. The flash memory market. Saratoga, Calif: Electronic Trend Publications, 1993.

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Stansberry, Mark. Computer memory: Important trends and directions. Norwalk, CT: Business Communications Co., 2002.

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Weissman, Steven B. The impact of technology on the optical disk memory market. Boston, Mass: Communications Pub. Group, 1986.

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Commission, United States International Trade. In the matter of certain memory devices with increased capacitance and products containing same. Washington, DC: U.S. International Trade Commission, 1996.

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United States International Trade Commission. In the matter of certain dynamic random access memories, components thereof and products containing same: Investigation no. 337-TA-242. Washington, DC: U.S. International Trade Commission, 1987.

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United States International Trade Commission. 64K dynamic random access memory components from Japan: Determination of the Commission in investigation no. 731-TA-270 (preliminary) under the Tariff Act of 1930, together with the information obtained in the investigation. Washington, D.C: U.S. International Trade Commission, 1985.

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Ilene, Hersher, ed. 64K dynamic random access memory components from Japan: Determination of the Commission in investigation no. 731-TA-270 (final) under the Tariff Act of 1930, together with the information obtained in the investigation. Washington, DC: U.S. International Trade Commission, 1986.

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Book chapters on the topic "Memory device"

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Javadova, Mirfatma, and Ilona Chernytska. "Matrix Memory Device." In Lecture Notes in Civil Engineering, 173–78. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-85043-2_17.

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Foerster, Michael, O. Boulle, S. Esefelder, R. Mattheis, and Mathias Kläui. "Domain Wall Memory Device." In Handbook of Spintronics, 1–46. Dordrecht: Springer Netherlands, 2015. http://dx.doi.org/10.1007/978-94-007-7604-3_48-1.

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Foerster, Michael, O. Boulle, S. Esefelder, R. Mattheis, and Mathias Kläui. "Domain Wall Memory Device." In Handbook of Spintronics, 1387–441. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-007-6892-5_48.

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Pellizzer, Fabio. "Phase-Change Memory Device Architecture." In Phase Change Memory, 263–84. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_9.

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Sousa, Véronique, and Gabriele Navarro. "Material Engineering for PCM Device Optimization." In Phase Change Memory, 181–222. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_7.

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Nakazato, K. "Single Electron Memory Device Simulations." In Simulation of Semiconductor Processes and Devices 1998, 201–2. Vienna: Springer Vienna, 1998. http://dx.doi.org/10.1007/978-3-7091-6827-1_51.

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Ielmini, Daniele. "Phase Change Memory Device Modeling." In Phase Change Materials, 299–329. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-84874-7_14.

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Huang, Peng, Bin Gao, and Jinfeng Kang. "RRAM Device Characterizations and Modelling." In Emerging Non-volatile Memory Technologies, 345–81. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-6912-8_11.

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Baddeley, A. D., S. E. Gathercole, and C. Papagno. "The phonological loop as a language learning device." In Exploring Working Memory, 164–98. Abingdon, Oxon ; New York, NY : Routledge, 2017. | Series: World library of psychologists: Routledge, 2017. http://dx.doi.org/10.4324/9781315111261-14.

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Jin, Hai, Bo Li, Ran Zheng, Qin Zhang, and Wenbing Ao. "memCUDA: Map Device Memory to Host Memory on GPGPU Platform." In Lecture Notes in Computer Science, 299–313. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-15672-4_26.

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Conference papers on the topic "Memory device"

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"Memory devices." In 2009 67th Annual Device Research Conference (DRC). IEEE, 2009. http://dx.doi.org/10.1109/drc.2009.5354863.

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"Memory." In 2010 68th Annual Device Research Conference (DRC). IEEE, 2010. http://dx.doi.org/10.1109/drc.2010.5551974.

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Wu, Yi, Shimeng Yu, H. S. Philip Wong, Yu-Sheng Chen, Heng-Yuan Lee, Sum-Min Wang, Pei-Yi Gu, Frederick Chen, and Ming-Jinn Tsai. "AlOx-Based Resistive Switching Device with Gradual Resistance Modulation for Neuromorphic Device Application." In 2012 4th IEEE International Memory Workshop (IMW). IEEE, 2012. http://dx.doi.org/10.1109/imw.2012.6213663.

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Barrios, C. A., and M. Lipson. "Silicon photonic nonvolatile memory device." In Frontiers in Optics. Washington, D.C.: OSA, 2005. http://dx.doi.org/10.1364/fio.2005.jwa63.

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Buckley, J., T. Pro, R. Barattin, A. Calborean, K. Huang, V. Aiello, G. Nicotra, et al. "From Atomistic to Device Level Investigation of Hybrid Redox Molecular/Silicon Field-Effect Memory Devices." In 2009 IEEE International Memory Workshop (IMW). IEEE, 2009. http://dx.doi.org/10.1109/imw.2009.5090591.

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Wong, H. S. Philip. "Emerging memory devices." In 2011 International Semiconductor Device Research Symposium (ISDRS). IEEE, 2011. http://dx.doi.org/10.1109/isdrs.2011.6135200.

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"Spin/memory." In 2011 69th Annual Device Research Conference (DRC). IEEE, 2011. http://dx.doi.org/10.1109/drc.2011.5994476.

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"Spin/Memory." In 2013 71st Annual Device Research Conference (DRC). IEEE, 2013. http://dx.doi.org/10.1109/drc.2013.6633849.

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"Memory devices [breaker page]." In 2006 64th Device Research Conference. IEEE, 2006. http://dx.doi.org/10.1109/drc.2006.305082.

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Lam, Chung. "Phase-change Memory." In 2007 65th Annual Device Research Conference. IEEE, 2007. http://dx.doi.org/10.1109/drc.2007.4373728.

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Reports on the topic "Memory device"

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Cerjan, C., and B. P. Law. Magnetic Random Access Memory (MRAM) Device Development. Office of Scientific and Technical Information (OSTI), January 2000. http://dx.doi.org/10.2172/15006522.

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Chang, Chia-Ching. Biomaterial-based Memory Device Development by Conducting Metallic DNA. Fort Belvoir, VA: Defense Technical Information Center, May 2013. http://dx.doi.org/10.21236/ada584806.

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Devine, Roderick A. Radiation Sensitivity of Unique Memory Devices. Fort Belvoir, VA: Defense Technical Information Center, January 2002. http://dx.doi.org/10.21236/ada405716.

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Missert, Nancy A., and Robert Garcia. Magnetic Nitride Films for Superconducting Memory Devices. Office of Scientific and Technical Information (OSTI), September 2014. http://dx.doi.org/10.2172/1531333.

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Mayas, Magda. Creating with timbre. Norges Musikkhøgskole, August 2018. http://dx.doi.org/10.22501/nmh-ar.686088.

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Abstract:
Unfolding processes of timbre and memory in improvisational piano performance This exposition is an introduction to my research and practice as a pianist, in which I unfold processes of timbre and memory in improvised music from a performer’s perspective. Timbre is often understood as a purely sonic perceptual phenomenon. However, this is not in accordance with a site-specific improvisational practice with changing spatial circumstances impacting the listening experience, nor does it take into account the agency of the instrument and objects used or the performer’s movements and gestures. In my practice, I have found a concept as part of the creating process in improvised music which has compelling potential: Timbre orchestration. My research takes the many and complex aspects of a performance environment into account and offers an extended understanding of timbre, which embraces spatial, material and bodily aspects of sound in improvised music performance. The investigative projects described in this exposition offer a methodology to explore timbral improvisational processes integrated into my practice, which is further extended through collaborations with sound engineers, an instrument builder and a choreographer: -experiments in amplification and recording, resulting in Memory piece, a series of works for amplified piano and multichannel playback - Piano mapping, a performance approach, with a custom-built device for live spatialization as means to expand and deepen spatio-timbral relationships; - Accretion, a project with choreographer Toby Kassell for three grand pianos and a pianist, where gestural approaches are used to activate and compose timbre in space. Together, the projects explore memory as a structural, reflective and performative tool and the creation of performing and listening modes as integrated parts of timbre orchestration. Orchestration and choreography of timbre turn into an open and hybrid compositional approach, which can be applied to various contexts, engaging with dynamic relationships and re-configuring them.
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Hamblen, David, Joseph Cosgrove, Konstantin K. Likharev, Elena Cimpoiasu, and Sergey Tolpygo. Crested Tunnel Barriers for Fast, High Density, Nonvolatile Memory Devices. Fort Belvoir, VA: Defense Technical Information Center, October 2002. http://dx.doi.org/10.21236/ada408876.

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Kim, Ki Wook. Novel Non-Volatile Memory Devices Based on Magnetic Semiconductor Nanostructures for Terabit Integration. Fort Belvoir, VA: Defense Technical Information Center, January 2010. http://dx.doi.org/10.21236/ada519064.

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Richter, Schachar E. Construction and Operation of Three-Dimensional Memory and Logic Molecular Devices and Circuits. Fort Belvoir, VA: Defense Technical Information Center, July 2013. http://dx.doi.org/10.21236/ada587368.

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Battiato, James M., Thomas W. Stone, Miles J. Murdocca, Rebecca J. Bussjager, and Paul R. Cook. Free Space Optical Memory Based on Vertical Cavity Surface Emitting Lasers and Self-Electro-Optic Effect Devices. Fort Belvoir, VA: Defense Technical Information Center, April 1995. http://dx.doi.org/10.21236/ada297049.

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MYERS, DAVID R., JEFFREY R. JESSING, OLGA B. SPAHN, and MARTY R. SHANEYFELT. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99). Office of Scientific and Technical Information (OSTI), January 2000. http://dx.doi.org/10.2172/750886.

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