Dissertations / Theses on the topic 'Memory and power applications'
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1
Wang, Xin. "Power Efficient Embedded Memory Design for Mobile Video Applications." Thesis, North Dakota State University, 2015. https://hdl.handle.net/10365/27621.
Abstract:
This thesis mainly addresses the issue of low-power technology for streaming media
applications. In order to ensure high output video quality under low-voltage supply, the proposed
8-bit pixel memory is sized by different bit positions. A novel MSEpixel estimation method is then
developed according to bit failure rates to directly evaluate the video quality for every 8-bit sizing
combination. Based on this estimation, one area-priory and one quality-priority mobile video
applications are proposed by SPIDER algorithms.
The results show that both luma and chroma data should be considered. More than 70%
power is saved in memory units by using sizing-priority SPIDER algorithms. And the proposed
SPIDER design methodology for low-voltage application is a feasible and efficient trade-off
between the memory reliability and area overhead. Besides, a sample SRAM chip is designed for
tape-out for further verification of the proposed SPIDER methodology.
2
SELMO, SIMONE. "Functional analysis of In-based nanowires for low power phase change memory applications." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2017. http://hdl.handle.net/10281/153247.
Abstract:
Phase change memories (PCMs), based on chalcogenide alloys (mainly Ge2Sb2Te5), are the most promising candidate for the realization of “Storage Class Memories”, which would fill the gap between ‘‘operation’’ and ‘‘storage’’ memories. PCMs are also one of the few currently available technologies for the implementation of nanoeletronic synapses in high density neuromorphic systems. The main improvements needed in order to exploit the full potential of PCMs in these innovative applications are the reduction of the programming currents and power consumption, and further cell downscaling. Thanks to their nano-sized active volume to be programmed and self-heating behavior, phase change nanowires (NWs) are expected to exhibit improved memory performances with respected to commonly used thin-film/heater-based structures.
The Ph. D. Thesis of the candidate reports the study of the phase change properties of ultra-thin In-based NWs for low power consuming PCMs, exploring the more promising features of this class of materials with respect to the commonly considered Ge-Sb-Te alloys.
In particular, the self-assembly of In-Sb-Te, In-doped Sb and In-Ge-Te NWs was successfully achieved by Metal Organic Chemical Vapour Deposition (MOCVD), coupled to vapour-liquid-solid mechanism, catalysed by catalyst nanoparticles. The parameters influencing the NW self-assembly were studied and the compositional, morphological and structural analysis of the grown structures was performed. In all cases, NWs of several μm in length and with diameters as small as 15 nm were obtained. The experimental contribution of the Ph. D. candidate to the NWs growth study was mainly related to the substrates preparation, catalyst deposition and, morphological and elemental analysis of the grown samples. Moreover, the Ph. D. candidate has performed the functional analysis of In3Sb1Te2 and In-doped Sb NW-based PCM devices. To conduct that analysis, a suitable fabrication procedure of the devices and an appropriate electrical measuring set-up have been identified. Reversible and well reproducible phase change memory switching was demonstrated for In3Sb1Te2 and In-doped Sb NW devices, showing low working parameters, such as “RESET” voltage, current and power.
The obtained results support the conclusion that In-based ultra-thin NWs are potential building blocks for the realization of ultra-scaled, high performance PCM devices.Phase change memories (PCMs), based on chalcogenide alloys (mainly Ge2Sb2Te5), are the most promising candidate for the realization of “Storage Class Memories”, which would fill the gap between ‘‘operation’’ and ‘‘storage’’ memories. PCMs are also one of the few currently available technologies for the implementation of nanoeletronic synapses in high density neuromorphic systems. The main improvements needed in order to exploit the full potential of PCMs in these innovative applications are the reduction of the programming currents and power consumption, and further cell downscaling. Thanks to their nano-sized active volume to be programmed and self-heating behavior, phase change nanowires (NWs) are expected to exhibit improved memory performances with respected to commonly used thin-film/heater-based structures. The Ph. D. Thesis of the candidate reports the study of the phase change properties of ultra-thin In-based NWs for low power consuming PCMs, exploring the more promising features of this class of materials with respect to the commonly considered Ge-Sb-Te alloys. In particular, the self-assembly of In-Sb-Te, In-doped Sb and In-Ge-Te NWs was successfully achieved by Metal Organic Chemical Vapour Deposition (MOCVD), coupled to vapour-liquid-solid mechanism, catalysed by catalyst nanoparticles. The parameters influencing the NW self-assembly were studied and the compositional, morphological and structural analysis of the grown structures was performed. In all cases, NWs of several μm in length and with diameters as small as 15 nm were obtained. The experimental contribution of the Ph. D. candidate to the NWs growth study was mainly related to the substrates preparation, catalyst deposition and, morphological and elemental analysis of the grown samples. Moreover, the Ph. D. candidate has performed the functional analysis of In3Sb1Te2 and In-doped Sb NW-based PCM devices. To conduct that analysis, a suitable fabrication procedure of the devices and an appropriate electrical measuring set-up have been identified. Reversible and well reproducible phase change memory switching was demonstrated for In3Sb1Te2 and In-doped Sb NW devices, showing low working parameters, such as “RESET” voltage, current and power. The obtained results support the conclusion that In-based ultra-thin NWs are potential building blocks for the realization of ultra-scaled, high performance PCM devices.
3
Morrison, Matthew Arthur. "Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications." Scholar Commons, 2013. https://scholarcommons.usf.edu/etd/5082.
Abstract:
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Adiabatic logic is a design methodology for reversible logic in CMOS where the current flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architectures. Production of cost-effective Secure Integrated Chips, such as Smart Cards, requires hardware designers to consider tradeoffs in size, security, and power consumption. In order to design successful security-centric designs, the low-level hardware must contain built-in protection mechanisms to supplement cryptographic algorithms such as AES and Triple DES by preventing side channel attacks, such as Differential Power Analysis (DPA). Dynamic logic obfuscates the output waveforms and the circuit operation, reducing the effectiveness of the DPA attack. Significant research exists in the design and analysis of locally optimal adiabatic elements towards mitigation of side channel attacks. However, none of these works have addressed the use of adiabatic logic in implementation of flexible and programmable hardware security policies. Nor has adiabatic logic been employed in hardware security applications such as trustworthy voting systems and data encryption standards.
In this dissertation, I address theory, synthesis, and application of adiabatic and reversible logic circuits for security applications. First, two major debates in reversible computing are addressed. These debates must be addressed in order to devise computational logic primitives in
any emerging quantum computing technology. First, we address whether charged based computing is limited due to the use of charge as a state variable. We propose the use of body biasing in CMOS adiabatic systems as a design methodology for reducing the need for gradually changing the energy barriers. Simulation results in HSPICE at 22nm are presented which show behavior of a source-memory device operating at sub-Landauer operation. Second, we address whether reversible logic can be used to design sequential computing structures, such as memory devices. we present an analysis of Quantum Turing Machines with sequential reversible logic structures, to show that the entropy gain is substantially less than the Landauer Barrier of kTln(2), which is the limiting factor for irreversible computing. A mathematical proof is presented showing bit erasure does not occur in sequential reversible logic structures, and that these devices are physically reversible as long as appropriate delay elements are inserted in the feedback paths to prevent race conditions. This proof validates implementation of sequential reversible logic towards ultra-low power computing.
Next, a novel algorithm for synthesis of adiabatic circuits in CMOS is proposed. This approach is unique because it correlates the offsets in the permutation matrix to the transistors required for synthesis, instead of determining an equivalent circuit and substituting a previously synthesized circuit from a library. Parallelism is used, and the bijective properties of the device to achieve synthesis of the logic structure in O(n) time. Then, using the ESPRESSO heuristic for minimization of Boolean functions method on each output node in parallel, we optimize the synthesized circuit. It is demonstrated that the algorithm produces a 32.86% improvement over previously synthesized circuit benchmarks.
For stronger mitigation of DPA attacks, we propose the implementation of Adiabatic Dynamic Differential Logic for applications in secure IC design. Such an approach is effective in reducing power consumption, demonstrated using HSPICE simulations with 22nm predictive technology. The benefits of our design are demonstrated by comparing instantaneous power waveforms and observing the magnitude of differential power spikes during switching events. First, simulation results for body-biasing on sub-threshold adiabatic inverters show an improvement in differential power up to 43.28% for similar inverters without body biasing. Then, a High Performance Adiabatic Dynamic Differential Logic (PADDL) is presented for an implementation in high frequency secure ICs. This method improves the differential power over previous dynamic and differential logic methods by up to 89.65%. Finally, we propose a Body-Biased Adiabatic Dynamic Differential Logic (BADDL) for ultra-low power applications. Simulation results show that the differential power was improved upon by a factor of 199.16.
Then, we present an adiabatic S-box which significantly reduces energy imbalance compared to previous benchmarks. The design is capable of forward encryption and reverse decryption with minimal overhead, allowing for efficient hardware reuse.
4
Ramclam, Kenneth M. "Low-Power and Robust Level-Shifter with Contention Mitigation for Memory and Standalone Applications." Scholar Commons, 2015. https://scholarcommons.usf.edu/etd/5555.
Abstract:
The scaling down of transistor sizes has imposed significant challenges in today's technology. Memories such as eDRAM, are experiencing poor retention time because of challenges such as reference voltage variation, high transistor leakage, and low cell capacitance. It can be seen that we must consider not only the first order effects, but also the second order effects to ensure we keep up with current technology trends such as Moore's law. In this thesis we explore various circuit level techniques on level shifters in order to achieve better retention time. With our research, we have addressed important design challenges and propose techniques that can be utilized in current and emerging technologies.
Level shifters (LS) are crucial components in low-power design where the die is segregated in multiple voltage domains. LS are used at the voltage domain interfaces to mitigate sneak path current. A less-known but very important application of LS is in high voltage drivers for designs where voltage boosting is needed for performance and functionality. We first study LS in eDRAM where LS is employed in the wordline path. Our investigation reveals that leakage power of LS can pose a serious threat by lowering the wordline voltage and subsequently affecting the speed and retention time of the eDRAM. It can also be noted that the delay of the LS under worse case process corners can cause significant functional discrepancies. We propose low-power pulsed-LS with supply gating to circumvent these issues. Our analysis indicate that pulsed-LS design can improve the worst case speed from 2.7%-43%. We extended this concept to design generic self-collapsible LSs that can be used for other applications such as voltage interfaces. The self-collapsed design in both applications improved the worst case speed from 6%-24% and 89% in some cases.
5
Lai, Farley. "Stream processing optimizations for mobile sensing applications." Diss., University of Iowa, 2017. https://ir.uiowa.edu/etd/5797.
Abstract:
Mobile sensing applications (MSAs) are an emerging class of applications that process continuous sensor data streams to make time-sensitive inferences. Representative application domains range from environmental monitoring, context-aware services to recognition of physical activities and social interactions. Example applications involve city air quality assessment, indoor localization, pedometer and speaker identification. The common application workflow is to read data streams from the sensors (e.g, accelerometers, microphone, GPS), extract statistical features, and then present the inferred high-level events to the user. MSAs in the healthcare domain especially draw a significant amount of attention in recent years because sensor-based data collection and assessment offer finer-granularity, timeliness, and higher accuracy in greater quantity than traditional, labor-intensive, data gathering mechanisms in use today, e.g., surveys methods. The higher fidelity and accuracy of the collected data expose new research opportunities, improve the reliability and accuracy of medical decisions, and empower users to manage personal health more effectively.
Nonetheless, a critical challenge to practical deployment of MSAs in real-world is to effectively manage limited resources of mobile platforms to meet stringent quality of service (QoS) requirements in terms of processing throughput and delay while ensuring long term robustness. To address the challenge, we model MSAs in dataflows as a graph of processing elements that are connected by communication channels. The processing elements may execute in parallel as long as they have sufficient data to process. A key feature of the dataflow model is that it explicitly capture parallelism and data dependencies between processing elements. Based on the graph composition, we first proposed CSense, a stream-processing toolkit for robust and high-rate MSAs. In this work, CSense provide a simple language for developers to describe their sensing flow without the need to deal with system intricacy, such as memory allocation, concurrency control and power management. The results show up to 19X performance difference may be achieved automatically compared with a baseline using the default runtime concurrency and memory management.
Following this direction, we saw the opportunities that MSAs can be significantly improved from the perspective of memory performance and energy efficiency in view of the iterative execution. Therefore, we next focus on optimizing the runtime memory management through compile time analysis. The contribution is a stream compiler that captures the whole program memory behavior to generate an efficient memory layout for runtime access. Experiments show that our memory optimizations reduce memory footprint by as much as 96% while matching or improving the performance of the StreamIt compiler with cache optimizations enabled.
On the other hand, while there is a significant body of work that has focused on optimizing the throughput or latency of processing sensor streams, little to no attention has been given to energy efficiency. We proposed an accurate offline energy prediction model for MSAs that leverages the pipeline structure and iterative execution nature to search for the most energy saving batching configuration w.r.t. a deadline constraint. The developers are expected to visualize the energy delay trade-off in the parameter space without runtime profiling. The evaluation shows the worst-case prediction errors are about 7% and 15% for energy and latency respectively despite variable application workloads.
6
Mandlekar, Anup Shrikant. "An Application Framework for a Power-Aware Processor Architecture." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/34484.
Abstract:
The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design to bridge the gap between event-driven applications and the target architecture. The architecture, although promising in terms of performance and energy-efficiency,
was explored for limited number of applications. This thesis presents a model-driven approach for the design of an application framework, facilitating rapid development of software
applications to test the architecture performance. The application framework is integrated
with the prior automation framework bringing software applications at the right level of abstraction. The processor architecture design is made flexible and scalable, making it suitable
for a wide range of applications. Additionally, an embedded flash memory based architecture design for reduction in the static power consumption is proposed. This thesis estimates significant reduction in overall power consumption with the incorporation of flash memory.Master of Science
7
Cortes, Christoffer, and Adam Krauser. "Android : Resource Consumption in Native and Web Applications." Thesis, Blekinge Tekniska Högskola, Sektionen för datavetenskap och kommunikation, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4681.
Abstract:
There is an ongoing debate by people in the industry whether to make native or web applications. These discussions mostly surround issues about development costs, user experience and capabilities. Another aspect of this debate is the fact that mobile devices have varying hardware specifications which is another factor to consider when making this decision. What we want to shed some light on is how performance is affected on the device when using these two different approaches of application development. The use of CPU/RAM and Energy is our primary concern and in our experiment we measure these values on two similar applications where one uses Nested Layouts and the other a WebView. The experiment was made on three different devices with varying specifications. What we found was that Web applications have a bigger impact on overall performance and because of this use more battery. While the debate certainly won't come to a close with results they are conclusive when it comes to the topic of performance and will be of value to developers who are concerned about it.
8
Mugisha, Dieudonne Manzi. "Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime." DigitalCommons@USU, 2015. https://digitalcommons.usu.edu/etd/4550.
Abstract:
Near-Threshold Computing embodies an intriguing choice for mobile processors due to the promise of superior energy efficiency, extending the battery life of these devices while reducing the peak power draw. However, process, voltage, and temperature variations cause a significantly high failure rate of Level One cache cells in the near-threshold regime a stark contrast to designs in the super-threshold regime, where fault sites are rare.
This thesis work shows that faulty cells in the near-threshold regime are highly clustered in certain regions of the cache. In addition, popular mobile benchmarks are studied to investigate the impact of run-time workloads on timing faults manifestation. A technique to mitigate the run-time faults is proposed. This scheme maps frequently used data to healthy cache regions by exploiting the application cache behaviors. The results show up to 78% gain in performance over two other state-of-the-art techniques.
9
Mahato, Prabir. "Study and development of resistive memories for flexible electronic applications." Thesis, Lyon, 2020. http://www.theses.fr/2020LYSEI134.
Abstract:
L’avènement de l’électronique flexible a entraîné des recherches rapides sur des capteurs, des dispositifs bio-implantables et portables pour l’évaluation de maladies telles que l’épilepsie, la maladie de Parkinson et les crises cardiaques. Les dispositifs de mémoire sont des composants majeurs dans tous les circuits électroniques, uniquement secondaires aux transistors, par conséquent de nombreux efforts de recherche sont consacrés au développement de dispositifs de mémoire flexibles. Les mémoires à accès aléatoire à pont conducteur (CBRAM) basées sur la création / dissolution d'un filament métallique dans un électrolyte solide sont d'un grand intérêt pour la recherche en raison de leur architecture métallique isolante métallique simple, de leurs capacités basse tension et de leur compatibilité avec les substrats flexibles. Dans ce travail, au lieu d'un oxyde métallique conventionnel ou d'une couche de chalcogénure, un polymère biocompatible - l'oxyde de polyéthylène (PEO) - est utilisé comme couche d'électrolyte solide en utilisant l'eau comme solvant. Des dispositifs de mémoire, constitués d'empilements tri-couches Ag / PEO / Pt, ont été fabriqués à la fois sur du silicium et des substrats flexibles en utilisant un processus hétérogène combinant un dépôt physique en phase vapeur et un revêtement par rotation. Pour cela, une étude systématique de l'effet de la concentration de la solution et de la vitesse de dépôt sur l'épaisseur du PEO est présentée. Des mesures SEM / EDX et AFM ont ensuite été effectuées sur des structures planes dédiées à «nano-gap» et ont révélé la formation de précipités métalliques d'Ag ainsi que des changements morphologiques de la couche de polymère après commutation de résistance. Les performances des dispositifs de mémoire résistive sont ensuite évaluées sur silicium et substrats flexibles. En particulier, la programmation des statistiques de tension, le rapport de résistance OFF / ON, les cycles d'endurance et les tests de rétention sont effectués et l'effet de la conformité du courant est analysé. Le mécanisme de conduction dans le HRS / LRS est étudié sur les appareils de référence Ag / PEO / Pt et Pt / PEO / Pt. Enfin, la caractérisation électrique des dispositifs sur substrat souple est réalisée sous contrainte mécanique, donnant des résultats prometteurs. Les dispositifs CBRAM à base de polymères sont donc proposés comme candidats potentiels pour le développement durable de dispositifs de mémoire flexiblesThe advent of flexible electronics has brought about rapid research towards sensors, bio implantable and wearable devices for assessment of diseases such as epilepsy, Parkinson’s and heart attacks. Memory devices are major component in any electronic circuits, only secondary to transistors, therefore many research efforts are devoted to the development of flexible memory devices. Conductive Bridge Random Access Memories (CBRAMs) based on creation/dissolution of a metallic filament within a solid electrolyte are of great research interest because of their simple Metal Insulator Metal architecture, low-voltage capabilities, and compatibility with flexible substrates. In this work, instead of a conventional metallic oxide or a chalcogenide layer, a biocompatible polymer - Polyethylene Oxide (PEO) – is employed as the solid electrolyte layer using water as solvent. Memory devices, consisting in Ag/PEO/Pt tri-layer stacks, were fabricated on both silicon and flexible substrates using a heterogeneous process combining physical vapour deposition and spin coating. To aim this, a systematic study on the effect of solution concentration and deposition speed on the PEO thickness is presented. SEM/EDX and AFM measurements were then conducted on devoted “nano-gap” planar structures and have revealed the formation of metallic Ag precipitates together with morphological changes of the polymer layer after resistance switching. The performance of the resistive memory devices is then assessed on silicon and flexible substrates. In particular programming voltage statistics, OFF/ON resistance ratio, endurance cycles and retention tests are performed and the effect of current compliance is analysed. The conduction mechanism in the HRS/LRS is studied on the Ag/PEO/Pt and Pt/PEO/Pt reference devices. Finally, the electrical characterization of devices on flexible substrate is performed under mechanical stress, showing promising results. Polymer-based CBRAM devices are therefore suggested as potential candidates for sustainable development of flexible memory devices
10
Ly, Aliou. "Développement d’un oscillateur paramétrique optique continu intense et à faible bruit pour des applications aux communications quantiques." Thesis, Université Paris-Saclay (ComUE), 2017. http://www.theses.fr/2017SACLS528/document.
Abstract:
La portée des communications quantiques est limitée à quelques dizaines de km en raison de l’atténuation dans les fibres. Les répéteurs quantiques (relais quantiques synchronisés par des mémoires quantiques photoniques) furent introduits afin d’accroître ces distances. Or, pour le moment, les mémoires les plus performantes fonctionnent à des longueurs d’onde n’appartenant pas à la bande C télécom. Afin de profiter de ces mémoires, l’utilisation d’interfaces quantiques (milieu non linéaire quadratique) fut proposée comme alternative. En ajoutant ainsi par somme de fréquences un photon de pompe de longueur d’onde appropriée au photon télécom portant l’information, on transfère l’information à une longueur d’onde compatible avec les mémoires, et ceci sans dégradation de l’information portée initialement par le photon télécom. Notre but est ainsi de construire un oscillateur paramétrique optique continu simplement résonant (SRO) qui fournira un faisceau à 1648 nm qui sera sommé en fréquence aux photons télécom à 1536 nm pour transférer l’information vers un photon stockable dans une mémoire à base d’atomes alcalins. Pour transférer efficacement l’information, le SRO doit satisfaire quelques critères : une haute finesse spectrale (largeur de raie ~kHz), une forte puissance (~1W) et une longueur d’onde plus grande que celle du photon télécom à convertir. Pour ce faire, nous utilisons le faisceau non-résonant d’un SRO continu. Le premier travail réalisé dans cette thèse a été de faire la démonstration de la possibilité d’avoir un faisceau à la fois intense et pur spectralement en sortie d’un SRO continu. En réutilisant un SRO déjà développé durant nos travaux antérieurs, nous avons pu stabiliser au niveau du kHz la fréquence du faisceau non résonant à 947 nm (onde signal) de ce SRO, tout en émettant une puissance de plus d’un watt. Ensuite, nous avons conçu le SRO dont le faisceau non résonant à 1648 nm (onde complémentaire) a été stabilisé à court terme en-dessous du kHz avec une puissance de l’ordre du watt. Nous avons ensuite étudié la stabilité à long terme de la longueur d’onde du complémentaire à 1648 nm. Nous avons mesuré des dérives de fréquences de l’ordre de 10 MHz/mn. Ces dérives, venant essentiellement de la cavité de référence sur laquelle le SRO est asservi, peuvent être réduites en contrôlant activement la cavité d’une part, et en utilisant des techniques de stabilisation en fréquence robustes, d’autre partLong distance quantum communications are limited to few tens of km due to the attenuation of light in telecom fibres. Quantum repeaters (quantum relays synchronized by photonic quantum memories) were introduced in order to increase distances. Or, currently, the most efficient memories do not operate at wavelengths in the telecom C band. In order to take advantage of these memories, the use of quantum interfaces (second order nonlinear medium) was proposed as an alternative. Thus, by adding by sum frequency generation a pump photon at an appropriate wavelength to the telecom photon carrying the information, one transfers the information to a wavelength compatible with these memories, and this with a preservation of the information initially carried by the telecom photon. Our aim is thus to build a continuous-wave singly resonant optical parametric oscillator (cw SRO) which will provide a wave at 1648 nm that will be frequency summed to telecom photons at 1536 nm to transfer the information to a photon storable into alkali atoms based memory. To efficiently transfer the information, the cw SRO has to fulfill some requirements: a high spectral purity (linewidth ~kHz), a high output power (~1 W) and a wavelength longer than that of the telecom photon to be converted. To this aim, we use the non-resonant wave of a cw SRO. The first work done during this thesis was to experimentally prove the possibility to have both high output power and high spectral purity from a cw SRO. By reusing a cw SRO already built during our previous works, we were able to stabilize at the kHz level the frequency of the non-resonant wave at 947 nm (signal wave) of this SRO, with an output power of more than one watt. Then, we built the cw SRO of which non-resonant wave at 1648 nm (idler wave) has been frequency stabilized below the kHz level along with an output power of the order of one watt. We next studied the long term stability of the idler wavelength at 1648 nm. We have measured frequency drifts of the order of 10 MHz/mn. These drifts originating mainly from the reference cavity to which the SRO is locked, can be reduced by, firstly, an active control of the cavity and by, secondly, the use of robust frequency stabilization techniques
11
Mbaye, Amadou. "Linéarisation des amplificateurs de puissance large-bande pour des applications de communications tactiques et de diffusion audio ou vidéo numérique." Thesis, Paris Est, 2015. http://www.theses.fr/2015PEST1021/document.
Abstract:
L'amplificateur de puissance est le module le plus critique dans les équipements de communication radio. Il détermine la qualité de la liaison par sa linéarité et a une contribution conséquente dans la consommation de l'émetteur ; environ 60% de l'énergie consommée est consacré à l'amplification. Il est donc crucial de le faire fonctionner avec un rendement énergétique élevé. Cependant, ces deux spécifications principales de l'amplificateur que sont la linéarité et le rendement énergétique sont antagoniques. Par conséquent, la conception d'un module d'amplification de puissance suppose de trouver un compromis entre la linéarité et le rendement. L'optimisation de ce compromis est la raison d'être des techniques de linéarisation d'amplificateurs et d'amélioration du rendement, parmi lesquelles la prédistorsion numérique (DPD) et les techniques de réduction du PAPR du signal (CFR).Le cœur de cette thèse est la linéarisation d'amplificateurs RF haute-puissance et large-bande par prédistorsion numérique (DPD). Dans ces travaux, nous abordons trois problématiques liées à la prédistorsion et qui constituent des verrous technologiques importants. Le premier aspect concerne l'implémentation de la prédistorsion numérique dans un contexte multi-bande où le signal à linéariser comporte plusieurs formes d'ondes, situées à des fréquences différentes. La seconde problématique est l'utilisation conjointe de la prédistorsion avec une technique de CFR. Dans la majorité des applications haute-puissance, les techniques de DPD et de CFR sont présentes de manière complémentaire, cependant elles sont utilisées de façon autonome et disjointe. Celles-ci gagneraient en performances de linéarisation en étant implémentées de manière plus concertée. . Le dernier thème abordé par cette thèse est l'effet des désadaptations d'impédance de l'antenne sur le mode de fonctionnement de l'amplificateur. La variation de l'impédance d'antenne entraine des réflexions de signal vers l'amplificateur qui modifient ses spécifications de linéarité et de rendement. Nous améliorons la linéarité du système DPD + AP, lorsque l'amplificateur est soumis à des variations de l'impédance à sa charge, grâce à une correction adaptative de gainPower amplifier is one of the most critical element within radiocommunications systems. The PA is their main source of nonlinearities and it has a great contribution on the emitter's power consumption. Running the PA with highest power efficiency is thus as crucial as having it linear for a good communication quality. However these two specifications of the PA are antagonistic and PA manifacturers need to find a compromise between linearity and power efficiency. Digital Predistortion (DPD) and Crest factor Reduction techniques are intended to improve power efficiency while preserving linearity or inversely. Linearization of wideband RF power amplifiers using Digital Predistortion is the focus of this thesis. Three DPD issues are investigated in these works. The first issue deals with multiband linearization where signals with various waveforms located at different frequency bands are amplified. The second objective of this thesis is to study a concurrent DPD/CFR systems based on an automatic estimation of the necessary CFR gain. The last part of this dissertation deals with PA linearization under antenna load variations. Indeed, the impedance of antenna may vary because of electromagnetic objects that are present in its vicinity. Those impedance variations may instigate signal reflections toward the PA, that modify some of its main specifications (linearity, delivered power and efficiency). Our goal in this field is to preserve DPD linearization performances under antenna load mismatch
12
Du, Nan. "Beyond "More than Moore": Novel applications of BiFeO3 (BFO)-based nonvolatile resistive switches." Doctoral thesis, Universitätsbibliothek Chemnitz, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-202508.
Abstract:
The size reduction of transistors has been the main reason for a successful development of semiconductor integrated circuits over the last decades. Because of the physically limited downscaling of transistors, alternative technologies namely the information processing and nonvolatile resistive switches (also termed memristors) have come into focus. Memristors reveal a fast switching speed, long retention time, and stable endurance. Nonvolatile analog bipolar resistive switching with a considerable large On/Off ratio is reported in BiFeO3 (BFO)-based resistive switches. So far resistive switches are mainly applied in memory applications or logic operations. Given the excellent properties of BFO based memristors, the further exploration of functionalities for memristive devices is required. A new approach for hardware based cryptographic system was developed within the framework of this dissertation. By studying the power conversion efficiencies on BFO memristor at various harmonics, it has been shown that two sets of clearly distinguishable power ratios are achievable when the BFO memristor is set into high or into low resistance state. Thus, a BFO-based binary encoding system can be established. As an example the unrecoverable seizure information from encoded medical data suggests the proper functioning of the proposed encryption system. Aside from cryptographic functionality, the single pairing spike timing dependent plasticity (STDP) in BFO-based artificial synapses is demonstrated, which can be considered as the cornerstone for energy-efficient and fast hardware-based neuromorphic networks. In comparison to the biological driven realistic way, only single one pairing of pre- and postsynaptic spikes is applied to the BFO-based artificial synapse instead of 60-80 pairings. Thus, the learning time constant of STDP function can be reduced from 25 ms to 125 usIn den letzten Jahrzehnten war die Größenreduktion von Transistoren einer der Hauptgründe für die Leistungssteigerung von integrierten Halbleiterschaltungen. Aufgrund des physikalisch beschränkten Skalierungspotentials, werden alternative Technologien für Halbleiterschaltungen entwickelt. Dazu zählen neuartige Widerstandsschalter, sogenannte Memristoren, welche wegen ihrer schnellen Schaltgeschwindigkeit, langen Speicherzeit und stabilen Haltbarkeit in den Fokus der Forschung gerückt sind. Das nichtflüchtige analoge bipolare Schalten des Widerstandwertes mit einem On/Off Verhältnis größer als 100 wurde in BiFeO 3 (BFO)-basierten Widerstands-schaltern beobachtet. Bisher wurden Widerstandsschalter hauptsächlich als Speicher oder in rekonfigurierbaren Logikschaltungen verwendet. Aufgrund der ausgezeichneten Eigenschaften von BFO-basierten Memristoren, ist die Untersuchung weiterer neuer Funktionalitäten vielversprechend. Als neuer Ansatz für ein Hardware-basiertes Kryptosystem wird in der vorliegenden Arbeit die Ausnutzung des Leistungsübertragungskoeffizienten in BFO Memristoren vorgeschlagen. Mit Hilfe der unterschiedlichen Oberschwingungen, welche von einem BFO Memristor im ON und OFF Zustand generiert werden, wurde ein Kryptosystem zum Kodieren binärer Daten entwickelt. Ein Test des Hardware-basierten Kryptosystems an Biodaten ergab, dass die kodierten Biodaten keine vorhersagbare Korrelation mehr enthielten. In der vorliegenden Arbeit wurden darüberhinaus BFO-basierte künstliche Synapsen mit einer Aktionspotentials-Intervall abhängigen Plastizität (STDP) für Einzelpulse entwickelt. Diese Einzelpuls-STDP legt den Grundstein für energieffiziente und schnelle neuromorphe Netzwerke mit künstlichen Synapsen. Im Vergleich zu biologischen Synapsen mit einer 60-80-Puls-STDP und einem Lernfenster auf der ms-Zeitskale, konnte das Lernfenster von BFO-basierten künstlichen Synapsen von 25 ms auf 125 μs reduziert werden. Solch ein schnelles Lernen ermöglicht auch die extreme Reduzierung des Leistungsverbrauchs in neuromorphen Netzwerken
13
Hitchcock, Yvonne Roslyn. "Elliptic curve cryptography for lightweight applications." Thesis, Queensland University of Technology, 2003. https://eprints.qut.edu.au/15838/1/Yvonne_Hitchcock_Thesis.pdf.
Abstract:
Elliptic curves were first proposed as a basis for public key cryptography in the mid 1980's. They provide public key cryptosystems based on the difficulty of the elliptic curve discrete logarithm problem (ECDLP) , which is so called because of its similarity to the discrete logarithm problem (DLP) over the integers modulo a large prime. One benefit of elliptic curve cryptosystems (ECCs) is that they can use a much shorter key length than other public key cryptosystems to provide an equivalent level of security. For example, 160 bit ECCs are believed to provide about the same level of security as 1024 bit RSA. Also, the level of security provided by an ECC increases faster with key size than for integer based discrete logarithm (dl) or RSA cryptosystems. ECCs can also provide a faster implementation than RSA or dl systems, and use less bandwidth and power. These issues can be crucial in lightweight applications such as smart cards. In the last few years, ECCs have been included or proposed for inclusion in internationally recognized standards. Thus elliptic curve cryptography is set to become an integral part of lightweight applications in the immediate future. This thesis presents an analysis of several important issues for ECCs on lightweight devices. It begins with an introduction to elliptic curves and the algorithms required to implement an ECC. It then gives an analysis of the speed, code size and memory usage of various possible implementation options. Enough details are presented to enable an implementer to choose for implementation those algorithms which give the greatest speed whilst conforming to the code size and ram restrictions of a particular lightweight device. Recommendations are made for new functions to be included on coprocessors for lightweight devices to support ECC implementations Another issue of concern for implementers is the side-channel attacks that have recently been proposed. They obtain information about the cryptosystem by measuring side-channel information such as power consumption and processing time and the information is then used to break implementations that have not incorporated appropriate defences. A new method of defence to protect an implementation from the simple power analysis (spa) method of attack is presented in this thesis. It requires 44% fewer additions and 11% more doublings than the commonly recommended defence of performing a point addition in every loop of the binary scalar multiplication algorithm. The algorithm forms a contribution to the current range of possible spa defences which has a good speed but low memory usage. Another topic of paramount importance to ECCs for lightweight applications is whether the security of fixed curves is equivalent to that of random curves. Because of the inability of lightweight devices to generate secure random curves, fixed curves are used in such devices. These curves provide the additional advantage of requiring less bandwidth, code size and processing time. However, it is intuitively obvious that a large precomputation to aid in the breaking of the elliptic curve discrete logarithm problem (ECDLP) can be made for a fixed curve which would be unavailable for a random curve. Therefore, it would appear that fixed curves are less secure than random curves, but quantifying the loss of security is much more difficult. The thesis performs an examination of fixed curve security taking this observation into account, and includes a definition of equivalent security and an analysis of a variation of Pollard's rho method where computations from solutions of previous ECDLPs can be used to solve subsequent ECDLPs on the same curve. A lower bound on the expected time to solve such ECDLPs using this method is presented, as well as an approximation of the expected time remaining to solve an ECDLP when a given size of precomputation is available. It is concluded that adding a total of 11 bits to the size of a fixed curve provides an equivalent level of security compared to random curves. The final part of the thesis deals with proofs of security of key exchange protocols in the Canetti-Krawczyk proof model. This model has been used since it offers the advantage of a modular proof with reusable components. Firstly a password-based authentication mechanism and its security proof are discussed, followed by an analysis of the use of the authentication mechanism in key exchange protocols. The Canetti-Krawczyk model is then used to examine secure tripartite (three party) key exchange protocols. Tripartite key exchange protocols are particularly suited to ECCs because of the availability of bilinear mappings on elliptic curves, which allow more efficient tripartite key exchange protocols.
14
Hitchcock, Yvonne Roslyn. "Elliptic Curve Cryptography for Lightweight Applications." Queensland University of Technology, 2003. http://eprints.qut.edu.au/15838/.
Abstract:
Elliptic curves were first proposed as a basis for public key cryptography in the mid 1980's. They provide public key cryptosystems based on the difficulty of the elliptic curve discrete logarithm problem (ECDLP) , which is so called because of its similarity to the discrete logarithm problem (DLP) over the integers modulo a large prime. One benefit of elliptic curve cryptosystems (ECCs) is that they can use a much shorter key length than other public key cryptosystems to provide an equivalent level of security. For example, 160 bit ECCs are believed to provide about the same level of security as 1024 bit RSA. Also, the level of security provided by an ECC increases faster with key size than for integer based discrete logarithm (dl) or RSA cryptosystems. ECCs can also provide a faster implementation than RSA or dl systems, and use less bandwidth and power. These issues can be crucial in lightweight applications such as smart cards. In the last few years, ECCs have been included or proposed for inclusion in internationally recognized standards. Thus elliptic curve cryptography is set to become an integral part of lightweight applications in the immediate future. This thesis presents an analysis of several important issues for ECCs on lightweight devices. It begins with an introduction to elliptic curves and the algorithms required to implement an ECC. It then gives an analysis of the speed, code size and memory usage of various possible implementation options. Enough details are presented to enable an implementer to choose for implementation those algorithms which give the greatest speed whilst conforming to the code size and ram restrictions of a particular lightweight device. Recommendations are made for new functions to be included on coprocessors for lightweight devices to support ECC implementations Another issue of concern for implementers is the side-channel attacks that have recently been proposed. They obtain information about the cryptosystem by measuring side-channel information such as power consumption and processing time and the information is then used to break implementations that have not incorporated appropriate defences. A new method of defence to protect an implementation from the simple power analysis (spa) method of attack is presented in this thesis. It requires 44% fewer additions and 11% more doublings than the commonly recommended defence of performing a point addition in every loop of the binary scalar multiplication algorithm. The algorithm forms a contribution to the current range of possible spa defences which has a good speed but low memory usage. Another topic of paramount importance to ECCs for lightweight applications is whether the security of fixed curves is equivalent to that of random curves. Because of the inability of lightweight devices to generate secure random curves, fixed curves are used in such devices. These curves provide the additional advantage of requiring less bandwidth, code size and processing time. However, it is intuitively obvious that a large precomputation to aid in the breaking of the elliptic curve discrete logarithm problem (ECDLP) can be made for a fixed curve which would be unavailable for a random curve. Therefore, it would appear that fixed curves are less secure than random curves, but quantifying the loss of security is much more difficult. The thesis performs an examination of fixed curve security taking this observation into account, and includes a definition of equivalent security and an analysis of a variation of Pollard's rho method where computations from solutions of previous ECDLPs can be used to solve subsequent ECDLPs on the same curve. A lower bound on the expected time to solve such ECDLPs using this method is presented, as well as an approximation of the expected time remaining to solve an ECDLP when a given size of precomputation is available. It is concluded that adding a total of 11 bits to the size of a fixed curve provides an equivalent level of security compared to random curves. The final part of the thesis deals with proofs of security of key exchange protocols in the Canetti-Krawczyk proof model. This model has been used since it offers the advantage of a modular proof with reusable components. Firstly a password-based authentication mechanism and its security proof are discussed, followed by an analysis of the use of the authentication mechanism in key exchange protocols. The Canetti-Krawczyk model is then used to examine secure tripartite (three party) key exchange protocols. Tripartite key exchange protocols are particularly suited to ECCs because of the availability of bilinear mappings on elliptic curves, which allow more efficient tripartite key exchange protocols.
15
Katrue, Srikanth. "Power reduction techniques for memory elements /." Online version of thesis, 2007. http://hdl.handle.net/1850/5720.
16
Feki, Anis. "Conception d’une mémoire SRAM en tension sous le seuil pour des applications biomédicales et les nœuds de capteurs sans fils en technologies CMOS avancées." Thesis, Lyon, INSA, 2015. http://www.theses.fr/2015ISAL0018/document.
Abstract:
L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumisEmergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal
17
Dancy, Abram P. (Abram Paul). "Power supplies for ultra low power applications." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/10069.
Abstract:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.Includes bibliographical references (p. 101-103).
by Abram P. Dancy.
M.Eng.
18
Nizamuddin, Muhammad Ali. "Predistortion for Nonlinear Power Amplifiers with Memory." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/36184.
Abstract:
The fusion of voice and data applications, along with the demand for high data-rate applications such as video-on-demand, is making radio frequency (RF) spectrum an increasingly expensive commodity for current and future communications. Although bandwidth-efficient digital modulation alleviates part of the problem by requiring a minimal use of spectral resources, they put an extra design burden on RF engineers. RF transmitters and power amplifiers account for more than half the total maintenance cost of a base-station, while occupying nearly the same portion of space. Therefore, power amplifiers become a bottleneck for digital systems in terms of space and power consumption. However, power-efficient use of the amplifiers, although desirable, is extremely detrimental to end-to-end performance due to the very high peak-to-average power ratios of modulations that are used today. In order to reduce distortion while maintaining high power conversion efficiency in a power amplifier, linearization schemes are needed. In addition, significant frequency-dependent Memory Effects result in high power amplifiers operating on wideband signals. Therefore, these effects need to be considered during any attempt to minimize amplifier distortion.
In this thesis, we present two schemes to cancel nonlinear distortion of a power amplifier, along with its memory effects and results for one of the schemes. The results highlight the fact that in the presence of significant memory effects, cancellation of these effects is necessary to achieve reasonable improvement in performance through linearization. We focus on predistortive schemes due to their digital- friendly structure and simple implementation. The operating environment consists of a multi-carrier W-CDMA signal. All of the studies are performed using numerical simulation on MATLAB and Agilent's Advanced Design System (ADS).
Master of Science
19
Zhu, Zhichun. "Power considerations for memory-related microarchitecture designs." W&M ScholarWorks, 2003. https://scholarworks.wm.edu/etd/1539623427.
Abstract:
The fast performance improvement of computer systems in the last decade comes with the consistent increase on power consumption. In recent years, power dissipation is becoming a design constraint even for high-performance systems. Higher power dissipation means higher packaging and cooling cost, and lower reliability. This Ph.D. dissertation will investigate several memory-related design and optimization issues of general-purpose computer microarchitectures, aiming at reducing the power consumption without sacrificing the performance. The memory system consumes a large percentage of the system's power. In addition, its behavior affects the processor power consumption significantly. In this dissertation, we propose two schemes to address the power-aware architecture issues related to memory: (1) We develop and evaluate low-power techniques for high-associativity caches. By dynamically applying different access modes for cache hits and misses, our proposed cache structure can achieve nearly lowest power consumption with minimal performance penalty. (2) We propose and evaluate look-ahead architectural adaptation techniques to reduce power consumption in processor pipelines based on the memory access information. The scheme can significantly reduce the power consumption of memory-intensive applications. Combined with other adaptation techniques, our schemes can effectively reduce the power consumption for both computer- and memory-intensive applications. The significance, potential impacts, and contributions of this dissertation are: (1) Academia and industry R & D has solely targeted the objective of high performance in both hardware and software designs since the beginning stage of building computer systems. However, the pursuit of high performance without considering energy consumption will inevitably lead to increased power dissipation and thus will eventually limit the development and progress of increasingly demanded mobile, portable, and high-performance computing systems. (2) Since our proposed method adaptively combines the merits of existing low-power cache designs, it approaches the optimum in terms of both retaining performance and saving energy. This low power solution for highly associative caches can be easily deployed with a low cost. (3) Using "a cache miss", a common program execution event, as a triggering signal to slow down the processor issue rate, our scheme can effectively reduce processor power consumption. This design can be easily and practically deployed in many processor architectures with a low cost.
20
Hanai, Ryo. "Memory management for real-time applications." 京都大学 (Kyoto University), 2007. http://hdl.handle.net/2433/135980.
21
Dulloor, Subramanya R. "Systems and applications for persistent memory." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54396.
Abstract:
Performance-hungry data center applications demand increasingly higher performance from their storage in addition to larger capacity memory at lower cost. While the existing storage technologies (e.g., HDD and flash-based SSD) are limited in their performance, the most prevalent memory technology (DRAM) is unable to address the capacity and cost requirements of these applications. Emerging byte-addressable, non-volatile memory technologies (such as PCM and RRAM) offer performance within an order of magnitude of DRAM, prompting their inclusion in the processor memory subsystem. Such load/store accessible non-volatile or persistent memory (referred to as NVM or PM) introduces an interesting new tier that bridges the performance gap between DRAM and PM, and serves the role of fast storage or slower memory. However, PM has several implications on system design, both hardware and software: (i) the hardware caching mechanisms, while necessary for acceptable performance, complicate the ordering and durability of stores to PM, (ii) the high performance of PM (compared to NAND) and the fact that it is byte-addressable necessitate rethinking of the system software to manage PM and the interfaces to expose PM to the applications, and (iii) the future memory-based applications that will likely employ systems coupling PM with DRAM (for cost and capacity reasons) must be extremely conscious of the performance characteristics of PM and the challenges of using fast vs. slow memory in ways that best meet their performance demands.
The key contribution of our research is a set of technologies that addresses these challenges in a bottom-up fashion. Since the real hardware is not yet available, we first implement a hardware emulator that can faithfully emulate the relative performance characteristics of DRAM and PM in a system with separate DRAM and emulated PM regions. We use this emulator to perform all of our evaluations. Next we explore system software support to enable low-overhead PM access by new and legacy applications. Towards this end, we implement PMFS, an optimized light-weight POSIX file system that exploits PM's byte-addressability to avoid overheads of block-oriented storage and enable direct PM access by applications (with memory-mapped I/O). To provide strong consistency guarantees, PMFS requires only a simple hardware primitive that provides software enforceable guarantees of durability and ordering of stores to PM. We demonstrate that PMFS achieves significant (up to an order of magnitude) gains over traditional file systems (such as ext4) on a RAMDISK-like PM block device.
Finally, we address the problem of designing memory-based applications for systems with both DRAM and PM by extending our system software to manage both the tiers. We demonstrate for several representative large in-memory applications that it is possible to use a small amount of fast DRAM and large amounts of slower PM without a proportional impact to an application's performance, provided the placement of data structures is done in a careful fashion. To simplify the application programming, we implement a set of libraries and automatic tools (called X-Mem) that enables programmers to achieve optimal data placement with minimal effort on their part. Finally, we demonstrate the potentially large benefits of application-driven memory tiering with X-Mem across a range of applications.
22
Choi, David Suho. "Integration of non-volatile memory with volatile memory for embedded memory architectures and signal processing applications." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1692120591&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
23
Neagu, Mădălin. "Self-healing and secure low-power memory systems." Doctoral thesis, Universitat Politècnica de Catalunya, 2017. http://hdl.handle.net/10803/460893.
Abstract:
The main objective of this thesis is to bring new contributions to the self-healing and secure systems domain. In particular, to develop a self-healing technique for memory systems and to increase security of memory systems, techniques which favor low-power consumption. In order to achieve the main objective, three major research objectives were proposed: design of an error detection and correction scheme for errors that occur in memory systems and integrate them in a memory system, design techniques to increase the security and data privacy of memory systems against different types of attacks and to combine the previous two into a single solution, in order to achieve a self-healing and secure low-power memory system. The low-power aspect of the proposed solutions and techniques is evaluated during design stage and afterwards through simulation. Also, the architectures are evaluated from several other points of view, such as error detecting and correcting performance, area and delay overhead, and security efficiency.
The first chapter contains a short introduction of the domain and subject of the thesis, current state of the art in this domain, proposed objectives and thesis organization.
The second chapter contains a unidirectional error detecting, correcting and localization scheme, which is used for the self-healing technique. The chapter begins with an introduction and motivation about error detecting and correcting codes and
their usage in memory systems and continues with a theoretical background. The chapter continues with the design of the proposed codes, which are explained in detail and illustrated through several figures. Then, they are analyzed from the following points of view: coding scheme, error localization, error correction and error escapes. For the latter three, metrics are defined, in order to evaluate the codes. Afterwards, the implementation of the proposed codes is exposed in several figures. Also, the usage of the codes is explained, as well as DRAM repair strategies. In the end of this chapter, the efficiency of the proposed codes is evaluated and exemplified. The evaluation process contains other metrics: speed and delay, area overhead, power consumption and code redundancy.
Chapter 3 contains a proposed scheme to increase security in memory systems against cold-boot attacks. The technique uses data scrambling, hence the chapter begins with a short theoretical background and a review of data scrambling methods. It continues with the proposed solution, which is based on using unique scrambling vectors in an interleaved way, and theoretical
performance and efficiency. The chapter ends with evaluation and experimental results for the proposed methodology.
Evaluations of area overhead, power consumption and access time are performed in the CACTI simulation tool and on a FPGA development board.
Chapter 4 approaches specific types of threats that can prevail in memory systems: simple and differential power or electromagnetic analysis attacks (SPEMA and DPEMA). The chapter begins with short introduction and motivation sections, and
continues with a theoretical background about possible threats. In the following section, SPEMA and DPEMA are explained and discussed in detail. Afterwards, the proposed solutions for mitigating SPEMA and DPEMA are exhibited, and ends with
evaluation and experimental results. An information leakage function is defined and used in evaluating the security efficiency of the solutions. The implementation costs are assessed with the use of the CACTI simulation tool, with respect to area and delay overhead, and power consumption.
The final chapter, 5, contains the conclusions of the work, scientific contributions and future research directions.
24
Ruppert, Eric. "The consensus power of shared-memory distributed systems." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape3/PQDD_0028/NQ49848.pdf.
25
Hettiaratchi, Sambuddhi Sinha Bandara. "Power optimized memory access in high-level synthesis." Thesis, Imperial College London, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.407906.
26
Tolentino, Matthew Edward. "Managing Memory for Power, Performance, and Thermal Efficiency." Diss., Virginia Tech, 2009. http://hdl.handle.net/10919/26301.
Abstract:
Extraordinary improvements in computing performance, density, and capacity have driven rapid increases in system energy consumption, motivating the need for energy-efficient performance. Harnessing the collective computational capacity of thousands of these systems can consume megawatts of electrical power, even though many systems may be underutilized for extended periods of time. At scale, powering and cooling unused or lightly loaded systems can waste millions of dollars annually.
To combat this inefficiency, we propose system software, control systems, and architectural techniques to improve the energy efficiency of high-capacity memory systems while preserving performance. We introduce and discuss several new application-transparent, memory management algorithms as well as a formal analytical model of a power-state control system rooted in classical control theory we developed to proportionally scale memory capacity with application demand. We present a prototype implementation of this control-theoretic runtime system that we evaluate on sequential memory systems. We also present and discuss why the traditional performance-motivated approach of maximizing interleaving within memory systems is problematic and should be revisited in terms of power and thermal efficiency. We then present power-aware control techniques for improving the energy efficiency of symmetrically interleaved memory systems. Given the limitations of traditional interleaved memory configurations, we propose and evaluate unorthodox, asymmetrically interleaved memory configurations. We show that when coupled with our control techniques, significant energy savings can be achieved without sacrificing application performance or memory bandwidth.Ph. D.
27
Harel, Nissim. "Memory Optimizations for Distributed Stream-based Applications." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/13988.
Abstract:
Distributed stream-based applications manage large quantities of data and exhibit unique production and consumption patterns that set them apart from general-purpose applications. This dissertation examines possible ways of creating more efficient memory management schemes. Specifically, it looks at the memory reclamation problem. It takes advantage of special traits of streaming applications to extend the definition of the garbage collection problem for those applications and include not only data items that are not reachable but also items that have no effect on the final outcome of the application. Streaming applications typically fully process only a portion of the data, and resources directed towards the remaining data items (i.e., those that dont affect the final outcome) can be viewed as wasted resources that should be minimized.
Two complementary approaches are suggested:
1. Garbage Identification
2. Adaptive Resource Utilization
Garbage Identification is concerned with an analysis of dynamic data dependencies to infer those items that the application is no longer going to access. Several garbage identification algorithms are examined. Each one of the algorithms uses a set of application properties (possibly distinct from one another) to reduce the memory consumption of the application. The performance of these garbage identification algorithms is compared to the performance of an ideal garbage collector, using a novel logging/post-mortem analyzer. The results indicate that the algorithms that achieve a low memory footprint (close to that of an ideal garbage collector) perform their garbage identification decisions locally; however, they base these decisions on best-effort global information obtained from other components of the distributed application.
The Adaptive Resource Utilization (ARU) algorithm analyzes the dynamic relationships between the production and consumption of data items. It uses this information to infer the capacity of the system to process data items and adjusts data generation accordingly. The ARU algorithm makes local capacity decisions based on best-effort global information. This algorithm is found to be as effective as the most successful garbage identification algorithm in reducing the memory footprint of stream-based applications, thus confirming the observation that using best-effort global information to perform local decisions is fundamental in reducing memory consumption for stream-based applications.
28
Hernandez, Allison 1979. "Analysis of magnetic random access memory applications." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8461.
Abstract:
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2002.Includes bibliographical references (p. 45-47).
Magnetic Random Access Memory (MRAM) is considered to be the most viable option for nonvolatile memory in the computer industry. This need for nonvolatile computer memory has resulted in the dramatic evolution of MRAM technology in the past ten years. Currently in the latter stages of development, emphasis is being put on experiments concerning optimization of density and reduction of the switching fields of the magnetic elements. Applications of MRAM technology are currently being explored by companies who seek to obtain relevant intellectual property in those areas. Once research is completed, companies must create a business plan that recognizes the initial, breakthrough markets and implement technology integration accordingly.
by Allison Hernandez.
M.Eng.
29
Guo, Weimin M. Eng Massachusetts Institute of Technology. "Orthopaedic applications of ferromagnetic shape memory alloys." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45957.
Abstract:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2008.Includes bibliographical references (leaves 36-40).
Ferromagnetic shape memory alloys (FSMAs) are a new class of magnetic field-actuated active materials with no current commercial applications. By applying a magnetic field of around 0.4 T, they can exert a stress of approximately 1.5 MPa, exhibiting a strain of up to 6%. This thesis evaluates their technical and commercial feasibility in orthopaedic applications. Remote actuation is a key advantage FSMAs have over current implant materials. Also, the human body temperature is constant, providing a stable environment for FSMAs to operate. A number of potential orthopaedic applications are proposed and evaluated. Out of these, the most prominent application is the spinal traction device. It is a temporary implantable device, intended to perform internal spinal traction. A design has been proposed, with suggestions of suitable materials for its various components and appropriate device dimensions. Preliminary market and cost analyses have been conducted. This orthopaedic technology is currently in its infant stage. To commercialize this device, more trials are needed.
by Weimin Guo.
M.Eng.
30
Chou, Wu-chun. "Coding applications in volume holographic memory systems." Diss., The University of Arizona, 1999. http://hdl.handle.net/10150/283998.
Abstract:
Volume holographic memory (VHM) systems are page-oriented optical data storage systems with a relatively large storage capacity, a high aggregate data transfer rate, and a fast access time as compared with other conventional mass data storage systems. In addition to the noise sources commonly present in a conventional communication channel, the VHM systems use a two-dimensional (2-D) data format and therefore suffers from 2-D electrical/optical hybrid noises. In this dissertation, we apply digital communication coding techniques to such a page-oriented optical memory system. To establish a coding performance baseline, we take an information theoretical perspective to study the design of 4F optical imaging systems, and the storage capacity of page-wise accessed VHM systems. In addition to the information-based figure of merit, bit-error rate (BER) serves as a more practical data fidelity measure. A BER-based optical design and a constant BER recording schedule in VHM systems are shown to support the coding analyses based on the BER metric. We analyze the VHM storage capacity while applying Reed-Solomon error-correction coding (ECC) and demonstrate that the use of the 2-D interleaving together with ECC results in a significant capacity improvement in the presence of systematic errors. In addition, soft-decision iterative decoding affords us a 2-D parallel decoding scheme that unifies the 2-D page equalization and decoding. A highly parallel decoder is discussed in the context of the 2-D low-pass channel mitigation and error correction. In the last part of this dissertation, we consider hardware implementation issues in 2-D optical systems. We design two coding related components using the MOSIS Orbit 2 mum n-well process to fabricate two CMOS VLSI chips. Power consumption and aerial scaling laws are discussed for each applications.
31
Chitty, R., L. Capote, J. Kaschmitter, and D. Tuckerman. "Compact Memory Module for High Performance Applications." International Foundation for Telemetering, 1989. http://hdl.handle.net/10150/614702.
Abstract:
International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, CaliforniaA common problem in many space applications is the need for a reliable large memory capacity in a light weight, low volume package. The Fairchild Space Company (FSC) is developing a high density static RAM based on VHSIC Hybrid Wafer Scale Integration (HWSI) technology for use in high reliability applications. Advances in interconnect technology and electronic packaging result in a bit density of 2.1 x 10⁷ bits per cu. in. Emphasis will be placed on the general benefits to the aerospace community of the device's high packing density and configurable 16, 32, and 64 bit word width. A specific application of the 64 Megabit SRAM module in the Fairchild Solid State Recorder is discussed to illustrate the performance advantage over conventional single chip and less conventional multi-chip package technologies.
32
Xu, Bin. "Shape memory polymeric nanocomposites for biological applications." Thesis, Heriot-Watt University, 2011. http://hdl.handle.net/10399/2489.
Abstract:
The aim of this work is to develop novel shape memory polymers (SMPs) and nanocomposites for potential biological applications. A kind of commercial SMP, shape memory polyurethane (SMPU), was used to prepare nanocomposites by incorporating nano-clay into the SMPU substrate. The mechanical behaviour, thermal property and shape memory efficiency were studied with various nanofiller loadings. Chemical synthesis methods were also employed to prepare the other designable SMP and its nanocomposites, i.e. the shape memory polystyrene co-polymer (SMPS). Multiple technologies were adopted to enhance the SMPS matrix such as modifying the chemical components, introducing various functional nanoparticles into the polymeric network and improving the dispersion of the nanoparticles. Different methods were used to characterize the overall performance of the obtained materials. Mechanical tests were performed at different dimensional scales with a varied degree of localisation. Nanoindentation was firstly applied to assess the micro-mechanical properties of shape memory polymer nanocomposites at scales down to particle size. The micro-mechanical analysis provided the fundamental information on the SMPs and their nanocomposites for bio-MEMS applications. Potential applications were also explored through manufacturing different type of device models and testing their shape recovery efficiencies. Finally, theoretical contributions were made in two areas. The first one was the theoretical analysis on the nanoparticles enhancement to the soft polymeric matrix. The other was in developing a constitutive model to describe the thermo-viscoelastic property and shape memory behaviour for SMP nanocomposites.
33
Hotton, Matthew. "The clinical applications of working memory training." Thesis, University of Oxford, 2016. https://ora.ox.ac.uk/objects/uuid:62a7a411-9624-4fc6-9330-3a279013db42.
Abstract:
Working memory is involved in a variety of cognitive tasks, with working memory capacity predicting an individual's ability to process information and focus attention on taskrelated information. Subsequently, recent research has investigated whether working memory capacity can be improved through training and whether improvements generalise to other cognitive, behavioural or emotional domains. This training is typically adaptive in nature, changing in difficulty according to participant ability, and can be completed in the participant's home on a computer, giving it the potential to be an easily accessible intervention for a range of clinical populations. The first paper presents a systematic review evaluating the effectiveness of computerised working memory training for individuals with neurodevelopmental disorders, which are often associated with working memory difficulties. The review found that to date, working memory training has been investigated in four neurodevelopmental disorders: attention deficit/hyperactivity disorder; autism spectrum disorder; intellectual disability and specific learning disorder. The findings indicate that although training appears to produce short-term improvements in the working memory capacity, this does not reliably generalise to other cognitive processes or disorder-specific symptoms. The second paper presents a randomised controlled trial investigating the effects of working memory training for reducing worry in high-worriers. Working memory capacity limitations, and subsequent difficulties in attentional control, are believed to be central to the maintenance of worry. Participants were randomly assigned to complete 15 days of nonadaptive working memory training using a 1-back task, or adaptive working memory training using a n-back task. Training led to improvements in working memory capacity and worry symptoms post-training and at four-week follow-up, with improvements on the adaptive training task significantly correlating with improvements in working memory capacity and worry. These findings are discussed in terms of implications for clinical practice and future research, together with the limitations of the study.
34
Josefson, Carl Elof. "Evaluation of ferroelectric materials for memory applications." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA232112.
Abstract:
Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 1990.Thesis Advisor(s): Panholzer, R. Second Reader: Neighbours, J.R. "June 1990." Description based on signature page. DTIC Identifiers(s): Nonvolitile memories, ferroelectric materials. Author(s) subject terms: Ferrorelectric, nonvolatile memory, radiation hard. Includes bibliographical references (p. 80-86). Also available online.
35
Salén, Filip. "Visualization of Dynamic Memory in C++ Applications." Thesis, Luleå tekniska universitet, Institutionen för system- och rymdteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-75286.
Abstract:
Optimized memory management is important for a demanding application to achieve high-performance results. But un-optimized or unwanted memory behaviors can usually be difficult to detect without an overview of how memory is structured during run-time. This thesis explores real-time visualization of dynamic memory allocation for applications using the memory pool allocation technique. In the thesis, technical and graphical challenges are described together with their solutions and the design choices that were made. The final result is a program that can visualize dynamic memory management in real time, with the focus on displaying a detailed and comprehensive memory overview that preserves the level of detail over time.Optimerad minneshantering är viktig för att uppnå hög prestanda i en krävande applikation. Men att upptäcka icke optimerade eller oönskade minnesbeteenden kan vara svårt utan en visuell översikt över hur minnet är strukturerat under programmets exekvering. Denna avhandling undersöker hur dynamisk minnesallokering kan visualiseras i realtid för applikationer som använder allokeringstekniken minnes\-pool. I avhandlingen beskrivs tekniska och grafiska utmaningar tillsammans med deras lösningar och de designval som gjordes. Slutresultatet är ett program som kan visualisera dynamisk minneshantering i realtid och som fokuserar på att visa en detaljerad och omfattande minnesöversikt som bevarar detaljeringsgraden över tiden.
36
Blomster, Katie Ann. "Schemes for reducing power and delay in SRAMs." Online access for everyone, 2006. http://www.dissertations.wsu.edu/Thesis/Summer2006/k%5Fblomster%5F071706.pdf.
37
Qi, Huan. "Memory, Movement, and MoodRetrieving the Power of Architecture as a Physical Container of Memory." University of Cincinnati / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1397734632.
38
Cheng, Yong. "Power electronics controller prototyping tool for power system applications." Master's thesis, Mississippi State : Mississippi State University, 2006. http://sun.library.msstate.edu/ETD-db/ETD-browse/browse.
39
Das, Sauparna 1979. "Magnetic machines and power electronics for power MEMS applications." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/34465.
Abstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 321-323).
This thesis presents the modeling, design, and characterization of microfabricated, surface-wound, permanent-magnet (PM) generators, and their power electronics, for use in Watt-level Power MEMS applications such as a microscale gas turbine engine. The generators are three-phase, axial-flux, synchronous machines, comprising a rotor with an annular PM and ferromagnetic core, and a stator with multi-turn surface windings on a soft magnetic substrate. The fabrication of the PM generators, as well as the development of their high-speed spinning rotor test stand, was carried out by collaborators at the Georgia Institute of Technology. The machines are modeled by analytically solving 2D magneto-quasistatic Maxwell's Equations as a function of radius and then integrating the field solutions over the radial span of the machine to determine the open-circuit voltage, torque and losses in the stator core. The model provides a computationally fast method to determine power and efficiency of an axial-air-gap PM machine as a function of geometry, speed and material properties. Both passive and active power electronics have been built and tested. The passive power electronics consist of a three-phase transformer and diode bridge rectifier.
(cont.) The active power electronics consist of a switch-mode rectifier based on the boost semi-bridge topology which is used to convert the unregulated AC generator voltages to a regulated 12 V DC without the need for rotor position/speed or stator terminal current/voltage sensing. At the rotational speed of 300,000 rpm, one generator converts 16.2 W of mechanical power to electrical power. Coupled to the transformer and diode bridge rectifier, it delivers 8 W DC to a resistive load. This is the highest output power ever delivered by a microscale electric generator to date. The corresponding power and current densities of 57.8 MW/m3 and 6x 108 A/m2, respectively, are much higher than those of a macroscale electric generator. At the rotational speed of 300,000 rpm, the generator and switch-mode rectifier delivered 5.5 W DC to a resistive load at a power density three times that of the passive electronics. This Watt-scale electrical power generation demonstrates the viability of scaled PM machines and power electronics for practical Power MEMS applications.
by Sauparna Das.
Ph.D.
40
Balachandran, Ajith. "Novel power electronic device structures for power conditioning applications." Thesis, University of Sheffield, 2014. http://etheses.whiterose.ac.uk/9574/.
Abstract:
The work presented in this thesis contains an investigation into the methods by which the semiconductor device performance can be improved with an aim to reduce the overall losses in the power conversion system. The types of devices discussed and evaluated in this thesis include Silicon MOSFETs, IGBT, CIGBT and GaN HEMT devices. The performance improvement methods suggested in literature usually involve a trade-off of device characteristics with one another. Therefore an investigation into new device technologies and structures is deemed necessary such that the performance trade-off can be avoided or be improved.
41
Kameswar, Rao Vaddina. "Evaluation of A Low-power Random Access Memory Generator." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7823.
Abstract:
In this work, an existing RAM generator is analysed and evaluated. Some of the aspects that were considered in the evaluation are the optimization of the basic SRAM cell, how the RAM generator can be ported to newer technologys, automating the simulation process and the creation of the workflow for the energy model.
One of the main focus of this thesis work is to optimize the basic SRAM cell. The SRAM cell which is used in the RAM generator is not optimized for area nor power. A compact layout is suggested which saves a lot of area and power. The technology that is used to create the RAM generator is old and a suitable way to port it to newer technology has also been found.
To create an energy model one has to simulate a lot of memories with a lot of data. This cannot be done in the traditional way of simulating circuits using the GUI. Hence an automation procedure has been suggested which can be made to work to create energy models by simulating the memories comprehensively.
Finally, basic ground work has been initiated by creating a workflow for the creation of the energy model.
42
Mohan, Nitin. "Low-Power High-Performance Ternary Content Addressable Memory Circuits." Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/2873.
Abstract:
Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of TCAMs, high power consumption is one of the most critical challenges faced by TCAM designers. This work proposes circuit techniques for reducing TCAM power consumption. The main contribution of this work is divided in two parts: (i) reduction in match line (ML) sensing energy, and (ii) static-power reduction techniques. The ML sensing energy is reduced by employing (i) positive-feedback ML sense amplifiers (MLSAs), (ii) low-capacitance comparison logic, and (iii) low-power ML-segmentation techniques. The positive-feedback MLSAs include both resistive and active feedback to reduce the ML sensing energy. A body-bias technique can further improve the feedback action at the expense of additional area and ML capacitance. The measurement results of the active-feedback MLSA show 50-56% reduction in ML sensing energy. The measurement results of the proposed low-capacitance comparison logic show 25% and 42% reductions in ML sensing energy and time, respectively, which can further be improved by careful layout. The low-power ML-segmentation techniques include dual ML TCAM and charge-shared ML. Simulation results of the dual ML TCAM that connects two sides of the comparison logic to two ML segments for sequential sensing show 43% power savings for a small (4%) trade-off in the search speed. The charge-shared ML scheme achieves power savings by partial recycling of the charge stored in the first ML segment. Chip measurement results show that the charge-shared ML scheme results in 11% and 9% reductions in ML sensing time and energy, respectively, which can be improved to 19-25% by using a digitally controlled charge sharing time-window and a slightly modified MLSA. The static power reduction is achieved by a dual-VDD technique and low-leakage TCAM cells. The dual-VDD technique trades-off the excess noise margin of MLSA for smaller cell leakage by applying a smaller VDD to TCAM cells and a larger VDD to the peripheral circuits. The low-leakage TCAM cells trade off the speed of READ and WRITE operations for smaller cell area and leakage. Finally, design and testing of a complete TCAM chip are presented, and compared with other published designs.
43
ZHOU, YUAN. "POWER VARIATIONS AND TEST SCHEDULING FOR EMBEDDED MEMORY ARRAYS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1140810178.
44
Ramamoorthy, Saravanan. "LOW-POWER ADDRESS POINTER DESIGN FOR FIFO MEMORY CIRCUITS." Available to subscribers only, 2009. http://proquest.umi.com/pqdweb?did=1796420511&sid=1&Fmt=2&clientId=1509&RQT=309&VName=PQD.
45
Alghanim, Abdulrahman A. "High power waveform measurement system enabling characterisation of high power devices including memory effects." Thesis, Cardiff University, 2008. http://orca.cf.ac.uk/54653/.
Abstract:
The increasing demand for higher data rates in wireless communication systems has led to the more effective and efficient use of all allocated frequency bands. In order to use the whole bandwidth at maximum efficiency, one needs to have RF power amplifiers with a higher linear level and memory-less performance. This is considered to be a major challenge to circuit designers. In this thesis the linearity and memory are studied and examined via the behaviour of the inter-modulation distortion (IMD). A major source of the in-band distortion can be shown to be influenced by the out-of-band impedances presented at either the input or the output of the device, especially those impedances terminated the low frequency (IF) components. Thus, in order to regulate the in-band distortion, the out of-band distortion must be controllable. This has necessitated the development of an upgraded measurement system, where, for the first time, the IF measurement system power is scaled up and extended from approximately 2W to approximately 100W. This was made possible by the design of high power IF bias tee and its integration with a high power IF test-set. The investigation of the influence of out of-band distortion, particularly that at the low frequencies, generally referred to as base-band memory effects, on in-band distortion in high power LDMOS devices, has been made possible by the development of this pioneering, high-power modulated waveform measurement system since it allows for the observation and control of all relevant frequency components (RF, IF and DC). This measurement system is capable of handling IF and RF power levels in excess of 100W with bandwidths ranging from approximately 10 kHz to approximately 12GHz, which makes it particularly appropriate for the characterisation of devices used in base-station mobile communications system applications These subsequent measurements demonstrate that the bandwidth, over which the base-band impedances must be controlled, should be extended beyond the generally accepted value of twice to at least four times the modulated bandwidth. Moreover, the measurement system permitted an intensive investigation of the base-band impedance terminations variations on inter-modulation distortion allowing an optimum to be found that minimise overall in-band distortion (circuit linearisation technique). Hence, indicating that it may be possible to meet the 3rd Generation Partnership Project (3GPP) standards for the maximum allowable adjacent channel leakage ratio (ACLR) in mobile terminals without using any extra linearisation techniques such as predistortion. These important observations have significant implications for modern PA linearisation techniques, as well as requiring careful consideration when designing PA bias networks.
46
Mou, Duan. "Complex oxide films for memory and detector applications." Doctoral thesis, KTH, Electronic Systems Design, 1998. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-2715.
47
Ansari, Mohammad M. "Efficient execution of concurrent applications using transactional memory." Thesis, University of Manchester, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.496238.
Abstract:
Challenges in the research and development of uniprocessors have led to the rise of multi-cores. However, multi-cores introduce new challenges to software development: applications will need to be developed using concurrent programming techniques and highly scalable to improve performance on successive generations of multi-cores, i.e. as the number of cores increases. Traditionally concurrent programming has employed locks to safeguard concurrent access to shared data, but these are known to be challenging to use, and only a minority of developers have the expertise to write correct, let alone highly scalable, lock-based code.
48
Zaffaroni, Paolo. "Nonlinear long memory models with applications in finance." Thesis, London School of Economics and Political Science (University of London), 1997. http://etheses.lse.ac.uk/1468/.
Abstract:
The last decade has witnessed a great deal of research in modelling volatility of financial asset returns, expressed by time-varying variances and covariances. The importance of modelling volatility lies in the dependence of any financial investment decision on the expected risk and return as formalized in classical asset pricing theory. Precise evaluation of volatilities is a compulsory step in order to perform correct options pricing according to recent theories of the term structure of interest rates and for the construction of dynamic hedge portfolios. Models of time varying volatility represent an important ground for the development of new estimation and forecasting techniques for situations not reconcilable with the Gaussian or, more generally, a linear time series framework. This is particularly true for the statistical analysis of time series with long range dependence in a nonlinear framework. The aim of this thesis is to introduce parametric nonlinear time series models with long memory, with particular emphasis on volatility models, and to provide a methodology which yields asymptotically exact inference on the parameters of the models. The importance of these results stems from: (i) rigorous asymptotics was lacking from the stochastic volatility literature; (ii) the statistical literature does not cover the analysis of the asymptotic behaviour of quadratic forms in nonlinear non-Gaussian variates that characterizes our problem.
49
Tsung, Chih-qu, and 鄭智聰. "Design and Applications of Low-Power Memory Generators." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/6g3e4k.
Abstract:
碩士國立中山大學
資訊工程學系研究所
96
Memory unit has become a major core component in most SoC designs, and thus reusable memory IP is crucial in speeding up the design process. In this thesis, we develop a low-power SRAM generator to reduce the design efforts by producing all the files required in traditional cell-based design flow. Several methods are used to reduce power consumption in the memory circuits, including hierarchical word-line architecture and block amplifiers. The SRAM generator can be extended to generate cache memory with mixed hard IP and soft IP where cache memory cells are hard IP while the cache controller is soft IP. Based on the SRAM generator, we can also generate some popular memory units such as register files, FIFO, LIFO, and delay elements used in many applications.
50
Panda, Soumya Ranjan. "Junctionless Nanowire : Towards Logic Circuits and Memory Applications." Thesis, 2017. http://ethesis.nitrkl.ac.in/8924/1/2017_MT_SRPanda.pdf.
Abstract:
The increasing prominence of portable systems and the need to limit the power consumption (and hence heat dissipation) in very high density VLSI chips have led to rapid and innovative development of short channel multi-gate devices during the recent decades. The driving forces of these portable devices require low power consumption and must be good resilient to noise as they are being driven by very small voltages. These short channel devices need high electrostatic control over the channel which can be achieved by multiple-gate metal oxide semiconductors field effect transistors (MG-MOSFET). As we will go on scaling the devices the problem not only lies with the electrical characteristics but also with fabrication of the device. To avoid fabrication related issues and to achieve some improved performance junctionless devices are proposed.
In this dissertation, the short channel performance of the proposed Junctionless nanowire transistor (JNT) have been evaluated. As we know in integrated circuits (IC) transistors are the key components to evaluate its performance so, we have studied the performance of CMOS inverter and universal gates using the proposed device. To achieve significant performance proper current flow is required in pull up and down network, fro this sizing of both oppositely device is very important which has been covered in respective sections.
In modern chips most part (area) is mainly memory. As for memory design array of transistors connected in a sophisticated fashion is required so its very much important to analyze the performance. We have analyzed stability of static random access memory (SRAM) cell in terms of different noise margin criteria and its sizing constraints. For the first time in this work we have analyzed N-Curves for the proposed device.