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1
Shao, Zili, and Yuan-Hao Chang. "Non-Volatile memory (NVM) technologies." Journal of Systems Architecture 71 (November 2016): 1. http://dx.doi.org/10.1016/j.sysarc.2016.11.007.
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Chu, Zhaole, Yongping Luo, and Peiquan Jin. "An Efficient Sorting Algorithm for Non-Volatile Memory." International Journal of Software Engineering and Knowledge Engineering 31, no. 11n12 (December 2021): 1603–21. http://dx.doi.org/10.1142/s0218194021400143.
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Non-volatile memory (NVM) has emerged as an alternative of the next-generation memory due to its non-volatility, byte addressability, high storage-density, and low-energy consumption. However, NVM also has some limitations, e.g. asymmetric read and write latency. Therefore, at present, it is not realistic to completely replace DRAM with NVM in computer systems. A more feasible scheme is to adopt the hybrid memory architecture composed of NVM and DRAM. Following the assumption of hybrid memory architecture, in this paper, we propose an NVM-friendly sorting algorithm called NVMSorting. Particularly, we introduce a new concept called Natural Run to improve the existing MONTRES algorithm. Further, we apply the proposed NVMSorting to database join algorithms to improve the performance of the existing sort-merge join. To verify the performance of our proposal, we implement six existing sorting algorithms as baselines, including the MONTRES algorithm, and conduct comparative experiments on real Intel Optane DC persistent memory. The results show that NVMSorting outperforms other sorting algorithms in terms of execution time and NVM writes. In addition, the results of the join experiment show that the NVMSorting algorithm achieves the highest performance among all schemes. Especially, in the partially ordered data, the execution time of NVMSorting is 2.9%, 2.7%, and 4.2% less than MONTRES, external sort, and quick sort, respectively. Also, the amount of NVM writes of the NVMSorting is 26.1%, 43.6%, 96.2% less than MONTRES, external sort, and quick sort, respectively.
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Kawata, Hirotaka, Gaku Nakagawa, and Shuichi Oikawa. "Using DRAM as Cache for Non-Volatile Main Memory Swapping." International Journal of Software Innovation 4, no. 1 (January 2016): 61–71. http://dx.doi.org/10.4018/ijsi.2016010105.
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The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years. However, these improvements have been seriously affecting power consumption. One of the greatest challenges is to achieve efficient power management for battery-equipped mobile devices. To solve this problem, the authors focus on the emerging non-volatile memory (NVM), which has been receiving increasing attention in recent years. Since its performance is comparable with that of DRAM, it is possible to replace the main memory with NVM, thereby reducing power consumption. However, the price and capacity of NVM are problematic. Therefore, the authors provide a large memory space without performance degradation by combining NVM with other memory devices. In this study, they propose a design for non-volatile main memory systems that use DRAM as a swap space. This enables both high performance and energy efficient memory management through dynamic power management in NVM and DRAM.
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Li, Xiaochang, and Zhengjun Zhai. "UHNVM: A Universal Heterogeneous Cache Design with Non-Volatile Memory." Electronics 10, no. 15 (July 22, 2021): 1760. http://dx.doi.org/10.3390/electronics10151760.
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During the recent decades, non-volatile memory (NVM) has been anticipated to scale up the main memory size, improve the performance of applications, and reduce the speed gap between main memory and storage devices, while supporting persistent storage to cope with power outages. However, to fit NVM, all existing DRAM-based applications have to be rewritten by developers. Therefore, the developer must have a good understanding of targeted application codes, so as to manually distinguish and store data fit for NVM. In order to intelligently facilitate NVM deployment for existing legacy applications, we propose a universal heterogeneous cache hierarchy which is able to automatically select and store the appropriate data of applications for non-volatile memory (UHNVM), without compulsory code understanding. In this article, a program context (PC) technique is proposed in the user space to help UHNVM to classify data. Comparing to the conventional hot or cold files categories, the PC technique can categorize application data in a fine-grained manner, enabling us to store them either in NVM or SSDs efficiently for better performance. Our experimental results using a real Optane dual-inline-memory-module (DIMM) card show that our new heterogeneous architecture reduces elapsed times by about 11% compared to the conventional kernel memory configuration without NVM.
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He, Qinlu, Huiguo Dong, Genqing Bian, Fan Zhang, Weiqi Zhang, Kexin Liu, and Zhen Li. "The Research of Spark Memory Optimization Based on Non-Volatile Memory." Journal of Nanoelectronics and Optoelectronics 17, no. 1 (January 1, 2022): 30–39. http://dx.doi.org/10.1166/jno.2022.3166.
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With the advent of the significant data era, more and more data information needs to be processed, bringing tremendous challenges to storage and computing. The spark amount of data is getting larger and larger, and the I/O bottleneck of computing and scheduling from the disk has increasingly become an essential factor restricting performance. The spark came into being and proposed in-memory computing, which significantly improved the computing speed. In addition, the high rate of the memory is easy to lose without power, and the small but expensive feature is also an urgent need to improve. The emergence of new non-volatile memory (NVM) not only brings the characteristics of non-volatile, large capacity, low latency but also brings new opportunities and challenges to the storage system. Therefore, based on the emergence of NVM and the problems to be improved in Spark memory, this paper proposes an NVM-based Spark memory optimization method. Add NVM to the Spark memory system, build a hybrid storage structure of NVM and memory, and make the partition management for NVM storage. What’s more, add some new persistence levels and optimize RDDs and other vital data. In the end, make the related optimization for cache and recovery.
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Haywood Dadzie, Thomas, Jiwon Lee, Jihye Kim, and Hyunok Oh. "NVM-Shelf: Secure Hybrid Encryption with Less Flip for Non-Volatile Memory." Electronics 9, no. 8 (August 13, 2020): 1304. http://dx.doi.org/10.3390/electronics9081304.
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The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. The non-volatility triggers a security issue against physical attacks, which is a vulnerability caused by memory extraction and snapshots. However, simply encrypting the NVM degrades the performance of the memory (high energy consumption, short lifetime), since typical encryption causes an avalanche effect while most NVMs suffer from the memory-write operation. In this paper, we propose NVM-shelf: Secure Hybrid Encryption with Less Flip (shelf) for Non-Volatile Memory (NVM), which is hybrid encryption to reduce the flip penalty. The main idea is that a stream cipher, such as block cipher CTR mode, is flip-tolerant when the keystream is reused. By modifying the CTR mode in AES block cipher, we let the keystream updated in a short period and reuse the keystream to achieve flip reduction while maintaining security against physical attacks. Since the CTR mode requires additional storage for the nonce, we classify write-intensive cache blocks and apply our CTR mode to the write-intensive blocks and apply the ECB mode for the rest of the blocks. To extend the cache-based NVM-shelf implementation toward SPM-based systems, we also propose an efficient compiler for SA-SPM: Security-Aware Scratch Pad Memory, which ensures the security of main memories in SPM-based embedded systems. Our compiler is the first approach to support full encryption of memory regions (i.e., stack, heap, code, and static variables) in an SPM-based system. By integrating the NVM-shelf framework to the SA-SPM compiler, we obtain the NVM-shelf implementation for both cache-based and SPM-based systems. The cache-based experiment shows that the NVM-shelf achieves encryption flip penalty less than 3%, and the SPM-based experiment shows that the NVM-shelf reduces the flip penalty by 31.8% compared to the whole encryption.
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Jung, Myoungsoo, Ellis H. Wilson, Wonil Choi, John Shalf, Hasan Metin Aktulga, Chao Yang, Erik Saule, Umit V. Catalyurek, and Mahmut Kandemir. "Exploring the Future of Out-of-Core Computing with Compute-Local Non-Volatile Memory." Scientific Programming 22, no. 2 (2014): 125–39. http://dx.doi.org/10.1155/2014/303810.
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Drawing parallels to the rise of general purpose graphical processing units (GPGPUs) as accelerators for specific high-performance computing (HPC) workloads, there is a rise in the use of non-volatile memory (NVM) as accelerators for I/O-intensive scientific applications. However, existing works have explored use of NVM within dedicated I/O nodes, which are distant from the compute nodes that actually need such acceleration. As NVM bandwidth begins to out-pace point-to-point network capacity, we argue for the need to break from the archetype of completely separated storage. Therefore, in this work we investigate co-location of NVM and compute by varying I/O interfaces, file systems, types of NVM, and both current and future SSD architectures, uncovering numerous bottlenecks implicit in these various levels in the I/O stack. We present novel hardware and software solutions, including the new Unified File System (UFS), to enable fuller utilization of the new compute-local NVM storage. Our experimental evaluation, which employs a real-world Out-of-Core (OoC) HPC application, demonstrates throughput increases in excess of an order of magnitude over current approaches.
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Bittman, Daniel, Peter Alvaro, Pankaj Mehra, Darrell D. E. Long, and Ethan L. Miller. "Twizzler: A Data-centric OS for Non-volatile Memory." ACM Transactions on Storage 17, no. 2 (June 7, 2021): 1–31. http://dx.doi.org/10.1145/3454129.
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Byte-addressable, non-volatile memory (NVM) presents an opportunity to rethink the entire system stack. We present Twizzler, an operating system redesign for this near-future. Twizzler removes the kernel from the I/O path, provides programs with memory-style access to persistent data using small (64 bit), object-relative cross-object pointers, and enables simple and efficient long-term sharing of data both between applications and between runs of an application. Twizzler provides a clean-slate programming model for persistent data, realizing the vision of Unix in a world of persistent RAM. We show that Twizzler is simpler, more extensible, and more secure than existing I/O models and implementations by building software for Twizzler and evaluating it on NVM DIMMs. Most persistent pointer operations in Twizzler impose less than 0.5 ns added latency. Twizzler operations are up to faster than Unix , and SQLite queries are up to faster than on PMDK. YCSB workloads ran 1.1– faster on Twizzler than on native and NVM-optimized SQLite backends.
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Bez, Roberto, Emilio Camerlenghi, and Agostino Pirovano. "Materials and Processes for Non-Volatile Memories." Materials Science Forum 608 (December 2008): 111–32. http://dx.doi.org/10.4028/www.scientific.net/msf.608.111.
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The development of the semiconductor industry through the CMOS technology has been possible thanks to the unique properties of the silicon and silicon dioxide material. Nevertheless the continuous scaling of the device dimension and the increase of the integration level, i.e. the capability to follow for more than 20 years the so-called Moore’s law, has been enabled not only by the Si-SiO2 system, but also by the use of other materials. The introduction of new materials every generation has allowed the integration of sub-micron and now of nanometer scale devices: different types of dielectrics, like Si3N4 or doped-SiO2, to form spacer, barrier and separation layers; conductive films, like WSi2, TiSi2, CoSi2 and NiSi2, to build low resistive gates; metals, like W, Ti, TiN, to have low resistive contacts, or like Al or Cu, to have low resistive interconnects. Although the technology development has been mainly driven by the CMOS transistor downscaling, other devices and most of all Non-Volatile Memories (NVM) have been able to evolve due to the large exploitation of these materials. NVM today represent a large portion of the overall semiconductor market and one of the most important technologies for the mobile application segment. In particular the main technology line in the NVM field is represented by the Flash Memory. Flash memory cell is based on the concept of a MOS transistor with a Floating-Gate (FG). The writing/reading operations of the cell are possible thanks again to the unique properties of the SiO2 system, being a quasi-ideal dielectric at low electric field, enabling the Flash memory to store electrons for several years, and becoming a fair conductor at higher electric field by tunnel effect, thus allowing reaching fast programming speeds. Flash have now reached the integration of many billions of bits in one monolithic component with cell dimension of 0.008um2 at 45nm technology node, always based on the FG concept. Nevertheless Flash have technological and physical constraint that will make more difficult their further scaling, even if the scaling limits are still under debate. In this contest there is the industrial interest for alternative technologies that exploit new materials and concepts to go beyond the Flash technology, to allow better scaling, and to enlarge the memory performance. Hence other technologies, alternative to floating gate devices, have been proposed and are under investigation. These new proposals exploit different physical mechanisms and different materials to store the information: magnetism and magnetoresistive materials (e.g. Co, Ni, Fe, Mn) in magnetic memories or MRAM; ferroelectricity and perovskite materials (e.g. PbTixZr1-xO3 or SrBi2Ta2O9 or BaxSr1-xTiO3) in ferroelectric memories or FeRAM; phase change and chalcogenide materials (e.g. Ge2Sb2Te5 or AsInSbTe) in phase-change memory or PCM. Among these alternative NVM, PCM are one of the most promising candidates to become a mainstream NVM, having the potentiality to improve the performance compared to Flash - random access time, read throughput, direct write, bit granularity, endurance - as well as to be scalable beyond Flash technology.
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Wang, Ming Qian, Jie Tao Diao, Nan Li, Xi Wang, and Kai Bu. "A Study on Reconfiguring On-Chip Cache with Non-Volatile Memory." Applied Mechanics and Materials 644-650 (September 2014): 3421–25. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3421.
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NVM has become a promising technology to partly replace SRAM as on-chip cache and reduce the gap between the core and cache. To take all advantages of NVM and SRAM, we propose a Hybrid Cache, constructing on-chip cache hierarchies with different technologies. As shown in article, hybrid cache performance and power consumption of Hybrid Cache have a large advantage over caches base on single technologies. In addition, we have shown some other methods that can optimize the performance of hybrid cache.
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Ye, Chencheng, Yuanchao Xu, Xipeng Shen, Hai Jin, Xiaofei Liao, and Yan Solihin. "Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory." ACM Transactions on Architecture and Code Optimization 19, no. 2 (June 30, 2022): 1–26. http://dx.doi.org/10.1145/3511706.
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This article points out an important threat that application-level Garbage Collection (GC) creates to the use of non-volatile memory (NVM). Data movements incurred by GC may invalidate the pointers to objects on NVM and, hence, harm the reusability of persistent data across executions. The article proposes the concept of movement-oblivious addressing (MOA), and develops and compares three novel solutions to materialize the concept for solving the addressability problem. It evaluates the designs on five benchmarks and a real-world application. The results demonstrate the promise of the proposed solutions, especially hardware-supported Multi-Level GPointer, in addressing the problem in a space- and time-efficient manner.
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Ding, Chen, Jiguang Wan, and Rui Yan. "HybridKV: An Efficient Key-Value Store with HybridTree Index Structure Based on Non-Volatile Memory." Journal of Physics: Conference Series 2025, no. 1 (September 1, 2021): 012093. http://dx.doi.org/10.1088/1742-6596/2025/1/012093.
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Abstract Non-Volatile Memory (NVM) is a new type of storage media with non-volatile data, higher storage density, better performance and concurrency. Persistent key-value stores designed for earlier storage devices, using Log-Structured Merge Tree (LSM-Tree), have serious read-write amplification problem and do not take full advantage of these new devices. Existing works on NVM index structure are mostly based on Radix-Tree or B+-Tree, index structure based on Radix-Tree has better performance but takes up more space. In this paper, we present a new index structure named HybridTree on NVM. HybridTree combines the characteristics of Radix-Tree and B+-Tree. The upper layer is composed of prefix index nodes similar to Radix-Tree, which is indexed by the key prefix speed up data locating, and providing multi-thread support. The lower layer consists of variable-length adaptive B+-Tree nodes organizing key-value data to reduce space waste caused by node sparseness. We evaluate HybridTree on a real NVM devices (Inter Optane DC Persistent Memory). Evaluation results show that HybridTree’s random write performance is 1.2x to 1.62x compared to Fast & Fair and 1.11x to 1.52x compared to NV-Tree, with 54% space utilization reduced compared to WORT. We further integrate HybridTree into LevelDB to build a high performance key-value store HybridKV. By storing HybridTree directly on NVM, the problem of read and write amplification of LSM-Tree is avoided. We evaluate HybridKV on a hybrid DRAM/NVM systems, according to the results, HybridKV can improve random write performance by 7.5x compared to LevelDB and 3.23x compared to RocksDB. In addition, the random read performance of HybridKV is 7x compared to NoveLSM.
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Naqi, Muhammad, Nayoung Kwon, Sung Jung, Pavan Pujar, Hae Cho, Yong Cho, Hyung Cho, Byungkwon Lim, and Sunkook Kim. "High-Performance Non-Volatile InGaZnO Based Flash Memory Device Embedded with a Monolayer Au Nanoparticles." Nanomaterials 11, no. 5 (April 24, 2021): 1101. http://dx.doi.org/10.3390/nano11051101.
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Non-volatile memory (NVM) devices based on three-terminal thin-film transistors (TFTs) have gained extensive interest in memory applications due to their high retained characteristics, good scalability, and high charge storage capacity. Herein, we report a low-temperature (<100 °C) processed top-gate TFT-type NVM device using indium gallium zinc oxide (IGZO) semiconductor with monolayer gold nanoparticles (AuNPs) as a floating gate layer to obtain reliable memory operations. The proposed NVM device exhibits a high memory window (ΔVth) of 13.7 V when it sweeps from −20 V to +20 V back and forth. Additionally, the material characteristics of the monolayer AuNPs (floating gate layer) and IGZO film (semiconductor layer) are confirmed using transmission electronic microscopy (TEM), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) techniques. The memory operations in terms of endurance and retention are obtained, revealing highly stable endurance properties of the device up to 100 P/E cycles by applying pulses (±20 V, duration of 100 ms) and reliable retention time up to 104 s. The proposed NVM device, owing to the properties of large memory window, stable endurance, and high retention time, enables an excellent approach in futuristic non-volatile memory technology.
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Khan, Mohammad Nasim Imtiaz, Shivam Bhasin, Bo Liu, Alex Yuan, Anupam Chattopadhyay, and Swaroop Ghosh. "Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories." Journal of Low Power Electronics and Applications 11, no. 4 (September 28, 2021): 38. http://dx.doi.org/10.3390/jlpea11040038.
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Emerging Non-Volatile Memories (NVMs) such as Magnetic RAM (MRAM), Spin-Transfer Torque RAM (STTRAM), Phase Change Memory (PCM) and Resistive RAM (RRAM) are very promising due to their low (static) power operation, high scalability and high performance. However, these memories bring new threats to data security. In this paper, we investigate their vulnerability against Side Channel Attack (SCA). We assume that the adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. First, we show our analysis of simulation results. Then, we use commercial NVM chips to validate the analysis. We also investigate the effectiveness of encoding against SCA on emerging NVMs. Finally, we summarize two new flavors of NVMs that can be resilient against SCA. To the best of our knowledge, this is the first attempt to do a comprehensive study of SCA vulnerability of the majority of emerging NVM-based cache.
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Gong, Cihun-Siyong, Yung-Chang Chang, Li-Ren Huang, Chih-Jen Yang, Kung-Ming Ji, Kuen-Long Lu, and Jian-Chiun Liou. "Two Dimensional Parity Check with Variable Length Error Detection Code for the Non-Volatile Memory of Smart Data." Applied Sciences 8, no. 8 (July 24, 2018): 1211. http://dx.doi.org/10.3390/app8081211.
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This paper proposes a novel technology of memory protection for the Non-Volatile Memory (NVM), applied to smart sensors and smart data. Based on the asymmetry of failure rate between the statuses of bit-0 and bit-1 in the non-volatile memory, as a result of the pollution of the radiation of cosmic ray, a two-dimensional parity with variable length error detection code (2D-VLEDC) for memory protection is proposed. 2D-VLEDC has the feature of variable length of redundant bits varied with content of data word in the NVM. The experimental results show that the same error detection quality could be achieved with a 30% redundancy improvement by applying the proposed 2D-VLEDC. The proposed design is particularly suitable for the use of safety-related fields, such as the automotive electronics and industrial non-volatile memories involved in the industrial automation.
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Liu, Gang, Leying Chen, and Shimin Chen. "Zen." Proceedings of the VLDB Endowment 14, no. 5 (January 2021): 835–48. http://dx.doi.org/10.14778/3446095.3446105.
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Emerging <u>N</u>on-<u>V</u>olatile <u>M</u>emory (NVM) technologies like 3DX-point promise significant performance potential for OLTP databases. However, transactional databases need to be redesigned because the key assumptions that non-volatile storage is orders of magnitude slower than DRAM and only supports blocked-oriented access have changed. NVMs are byte-addressable and almost as fast as DRAM. The capacity of NVM is much (4-16x) larger than DRAM. Such NVM characteristics make it possible to build OLTP database entirely in NVM main memory. This paper studies the structure of OLTP engines with hybrid NVM and DRAM memory. We observe three challenges to design an OLTP engine for NVM: tuple metadata modifications, NVM write redundancy, and NVM space management. We propose Zen, a high-throughput log-free OLTP engine for NVM. Zen addresses the three design challenges with three novel techniques: metadata enhanced tuple cache, log-free persistent transactions, and light-weight NVM space management. Experimental results on a real machine equipped with Intel Optane DC Persistent Memory show that Zen achieves up to 10.1x improvement compared with existing solutions to run an OLTP database as large as the size of NVM while achieving fast failure recovery.
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Chen, An. "A review of emerging non-volatile memory (NVM) technologies and applications." Solid-State Electronics 125 (November 2016): 25–38. http://dx.doi.org/10.1016/j.sse.2016.07.006.
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Ge, Fen, Lei Wang, Ning Wu, and Fang Zhou. "A Cache Fill and Migration Policy for STT-RAM-Based Multi-Level Hybrid Cache in 3D CMPs." Electronics 8, no. 6 (June 6, 2019): 639. http://dx.doi.org/10.3390/electronics8060639.
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Recently, in 3D Chip-Multiprocessors (CMPs), a hybrid cache architecture of SRAM and Non-Volatile Memory (NVM) is generally used to exploit high density and low leakage power of NVM and a low write overhead of SRAM. The conventional access policy does not consider the hybrid cache and cannot make good use of the characteristics of both NVM and SRAM technology. This paper proposes a Cache Fill and Migration policy (CFM) for multi-level hybrid cache. In CFM, data access was optimized in three aspects: Cache fill, cache eviction, and dirty data migration. The CFM reduces unnecessary cache fill, write operations to NVM, and optimizes the victim cache line selection in cache eviction. The results of experiments show that the CFM can improve performance by 24.1% and reduce power consumption by 18% when compared to conventional writeback access policy.
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Cai, Tao, Qingjian He, Dejiao Niu, Fuli Chen, Jie Wang, and Lei Li. "A New Embedded Key–Value Store for NVM Device Simulator." Micromachines 11, no. 12 (December 2, 2020): 1075. http://dx.doi.org/10.3390/mi11121075.
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The non-volatile memory (NVM) device is a useful way to solve the memory wall in computers. However, the current I/O software stack in operating systems becomes a performance bottleneck for applications based on NVM devices, especially for key–value stores. We analyzed the characteristics of key–value stores and NVM devices and designed a new embedded key–value store for an NVM device simulator named PMEKV. The embedded processor in NVM devices was used to manage key–value pairs to reduce the data transfer between NVM devices and key–value applications. Meanwhile, it also cut down the data copy between the user space and the kernel space in the operating system to alleviate the I/O software stacks on the efficiency of key–value stores. The architecture, data layout, management strategy, new interface and log strategy of PMEKV are given. Finally, a prototype of PMEKV was implemented based on PMEM. We used YCSB to test and compare it with Redis, MongDB, and Memcache. Meanwhile, the Redis for PMEM named PMEM-Redis and PMEM-KV were also used to test and compared with PMEKV. The results show that PMEKV had the advantage of throughput and adaptability compared with the current key–value stores.
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Zhu, Guangyu, Jaehyun Han, Sangjin Lee, and Yongseok Son. "An Empirical Evaluation of NVM-Aware File Systems on Intel Optane DC Persistent Memory Modules." Electronics 10, no. 16 (August 17, 2021): 1977. http://dx.doi.org/10.3390/electronics10161977.
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The emergence of non-volatile memories (NVM) brings new opportunities and challenges to data management system design. As an important part of the data management systems, several new file systems are developed to take advantage of the characteristics of NVM. However, these NVM-aware file systems are usually designed and evaluated based on simulations or emulations. In order to explore the performance and characteristics of these file systems on real hardware, in this article, we provide an empirical evaluation of NVM-aware file systems on the first commercially available byte-addressable NVM (i.e., the Intel Optane DC Persistent Memory Module (DCPMM)). First, to compare the performance difference between traditional file systems and NVM-aware file systems, we evaluate the performance of Ext4, XFS, F2FS, Ext4-DAX, XFS-DAX, and NOVA file systems on DCPMMs. To compare DCPMMs with other secondary storage devices, we also conduct the same evaluations on Optane SSDs and NAND-flash SSDs. Second, we observe how remote NUMA node access and device mapper striping affect the performance of DCPMMs. Finally, we evaluate the performance of the database (i.e., MySQL) on DCPMMs with Ext4 and Ext4-DAX file systems. We summarize several observations from the evaluation results and performance analysis. We anticipate that these observations will provide implications for various memory and storage systems.
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Lei, Mengya, Fan Li, Fang Wang, Dan Feng, Xiaomin Zou, and Renzhi Xiao. "SecNVM: An Efficient and Write-Friendly Metadata Crash Consistency Scheme for Secure NVM." ACM Transactions on Architecture and Code Optimization 19, no. 1 (March 31, 2022): 1–26. http://dx.doi.org/10.1145/3488724.
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Data security is an indispensable part of non-volatile memory (NVM) systems. However, implementing data security efficiently on NVM is challenging, since we have to guarantee the consistency of user data and the related security metadata. Existing consistency schemes ignore the recoverability of the SGX style integrity tree (SIT) and the access correlation between metadata blocks, thereby generating unnecessary NVM write traffic. In this article, we propose SecNVM, an efficient and write-friendly metadata crash consistency scheme for secure NVM. SecNVM utilizes the observation that for a lazily updated SIT, the lost tree nodes after a crash can be recovered by the corresponding child nodes in NVM. It reduces the SIT persistency overhead through a restrained write-back metadata cache and exploits the SIT inter-layer dependency for recovery. Next, leveraging the strong access correlation between the counter and DMAC, SecNVM improves the efficiency of security metadata access through a novel collaborative counter-DMAC scheme. In addition, it adopts a lightweight address tracker to reduce the cost of address tracking for fast recovery. Experiments show that compared to the state-of-the-art schemes, SecNVM improves the performance and decreases write traffic a lot, and achieves an acceptable recovery time.
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Wan, Zhe, Tianyi Wang, Yiming Zhou, Subramanian S. Iyer, and Vwani P. Roychowdhury. "Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines." ACM Journal on Emerging Technologies in Computing Systems 18, no. 2 (April 30, 2022): 1–23. http://dx.doi.org/10.1145/3502721.
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Recently, analog compute-in-memory (CIM) architectures based on emerging analog non-volatile memory (NVM) technologies have been explored for deep neural networks (DNNs) to improve scalability, speed, and energy efficiency. Such architectures, however, leverage charge conservation, an operation with infinite resolution, and thus are susceptible to errors. Thus, the inherent stochasticity in any analog NVM used to execute DNNs, will compromise performance. Several reports have demonstrated the use of analog NVM for CIM in a limited scale. It is unclear whether the uncertainties in computations will prohibit large-scale DNNs. To explore this critical issue of scalability, this article first presents a simulation framework to evaluate the feasibility of large-scale DNNs based on CIM architecture and analog NVM. Simulation results show that DNNs trained for high-precision digital computing engines are not resilient against the uncertainty of the analog NVM devices. To avoid such catastrophic failures, this article introduces the analog bi-scale representation for the DNN, and the Hessian-aware Stochastic Gradient Descent training algorithm to enhance the inference accuracy of trained DNNs. As a result of such enhancements, DNNs such as Wide ResNets for CIFAR-100 image recognition problem are demonstrated to have significant performance improvements in accuracy without adding cost to the inference hardware .
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Park, Joong-Hyun, Myung-Hun Shin, and Jun-Sin Yi. "The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiOX as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide." Nanomaterials 9, no. 5 (May 22, 2019): 784. http://dx.doi.org/10.3390/nano9050784.
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We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium–tin–zinc–oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH4:N2O, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal–insulator–silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH4:N2O = 30:5), the MIS capacitor exhibited the widest memory window; the flat band voltage (ΔVFB) shifts of 4.45 V was obtained at the sweep voltage of ±11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiOX charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm2/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 × 107 were obtained at the initial sweep of the devices. As an NVM, ΔVFB was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 μs. The ΔVFB was returned to the pristine condition with a negative voltage pulse of −1 V and 1 μs under a 400–700 nm light illumination of ~10 mWcm−2 in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial ΔVFB (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels.
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Bahn, Hyokyung, and Kyungwoon Cho. "Implications of NVM Based Storage on Memory Subsystem Management." Applied Sciences 10, no. 3 (February 3, 2020): 999. http://dx.doi.org/10.3390/app10030999.
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Recently, non-volatile memory (NVM) has advanced as a fast storage medium, and legacy memory subsystems optimized for DRAM (dynamic random access memory) and HDD (hard disk drive) hierarchies need to be revisited. In this article, we explore the memory subsystems that use NVM as an underlying storage device and discuss the challenges and implications of such systems. As storage performance becomes close to DRAM performance, existing memory configurations and I/O (input/output) mechanisms should be reassessed. This article explores the performance of systems with NVM based storage emulated by the RAMDisk under various configurations. Through our measurement study, we make the following findings. (1) We can decrease the main memory size without performance penalties when NVM storage is adopted instead of HDD. (2) For buffer caching to be effective, judicious management techniques like admission control are necessary. (3) Prefetching is not effective in NVM storage. (4) The effect of synchronous I/O and direct I/O in NVM storage is less significant than that in HDD storage. (5) Performance degradation due to the contention of multi-threads is less severe in NVM based storage than in HDD. Based on these observations, we discuss a new PC configuration consisting of small memory and fast storage in comparison with a traditional PC consisting of large memory and slow storage. We show that this new memory-storage configuration can be an alternative solution for ever-growing memory demands and the limited density of DRAM memory. We anticipate that our results will provide directions in system software development in the presence of ever-faster storage devices.
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Ievtukh, V. A., A. N. Nazarov, V. I. Turchanikov, and V. S. Lysenko. "Nanocluster NVM Cells Metrology: Window Formation, Relaxation and Charge Retention Measurements." Advanced Materials Research 718-720 (July 2013): 1118–23. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.1118.
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In the paper a measurement technique for study main technical and physical parameters of nanocluster non-volatile memory capacitance cell is presented. The charging/discharging process features associated with nanoclusters (nanocrystals) incorporated into gate dielectric are discussed. Original equipment for fast capacitance measurements based on computer interfaces is considers.
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Zhang, Baoquan, and David H. C. Du. "NVLSM: A Persistent Memory Key-Value Store Using Log-Structured Merge Tree with Accumulative Compaction." ACM Transactions on Storage 17, no. 3 (August 31, 2021): 1–26. http://dx.doi.org/10.1145/3453300.
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Computer systems utilizing byte-addressable Non-Volatile Memory ( NVM ) as memory/storage can provide low-latency data persistence. The widely used key-value stores using Log-Structured Merge Tree ( LSM-Tree ) are still beneficial for NVM systems in aspects of the space and write efficiency. However, the significant write amplification introduced by the leveled compaction of LSM-Tree degrades the write performance of the key-value store and shortens the lifetime of the NVM devices. The existing studies propose new compaction methods to reduce write amplification. Unfortunately, they result in a relatively large read amplification. In this article, we propose NVLSM, a key-value store for NVM systems using LSM-Tree with new accumulative compaction. By fully utilizing the byte-addressability of NVM, accumulative compaction uses pointers to accumulate data into multiple floors in a logically sorted run to reduce the number of compactions required. We have also proposed a cascading searching scheme for reads among the multiple floors to reduce read amplification. Therefore, NVLSM reduces write amplification with small increases in read amplification. We compare NVLSM with key-value stores using LSM-Tree with two other compaction methods: leveled compaction and fragmented compaction. Our evaluations show that NVLSM reduces write amplification by up to 67% compared with LSM-Tree using leveled compaction without significantly increasing the read amplification. In write-intensive workloads, NVLSM reduces the average latency by 15.73%–41.2% compared to other key-value stores.
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Chen, Wei-Ming, Tei-Wei Kuo, and Pi-Cheng Hsiu. "Heterogeneity-aware Multicore Synchronization for Intermittent Systems." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–22. http://dx.doi.org/10.1145/3476992.
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Intermittent systems enable batteryless devices to operate through energy harvesting by leveraging the complementary characteristics of volatile (VM) and non-volatile memory (NVM). Unfortunately, alternate and frequent accesses to heterogeneous memories for accumulative execution across power cycles can significantly hinder computation progress. The progress impediment is mainly due to more CPU time being wasted for slow NVM accesses than for fast VM accesses. This paper explores how to leverage heterogeneous cores to mitigate the progress impediment caused by heterogeneous memories. In particular, a delegable and adaptive synchronization protocol is proposed to allow memory accesses to be delegated between cores and to dynamically adapt to diverse memory access latency. Moreover, our design guarantees task serializability across multiple cores and maintains data consistency despite frequent power failures. We integrated our design into FreeRTOS running on a Cypress device featuring heterogeneous dual cores and hybrid memories. Experimental results show that, compared to recent approaches that assume single-core intermittent systems, our design can improve computation progress at least 1.8x and even up to 33.9x by leveraging core heterogeneity.
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Angizi, Shaahin, Navid Khoshavi, Andrew Marshall, Peter Dowben, and Deliang Fan. "MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET." ACM Transactions on Design Automation of Electronic Systems 27, no. 2 (March 31, 2022): 1–18. http://dx.doi.org/10.1145/3484222.
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Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency ( EAT ) product on average by ~98% and ~70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.
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Butterfield, N. R., R. Mays, B. Khan, R. Gudlavalleti, and F. C. Jain. "Quantum Dot Gate (QDG) Quantum Dot Channel (QDC) Multistate Logic Non-Volatile Memory (NVM) with High-K Dielectric HfO2 Barriers." International Journal of High Speed Electronics and Systems 29, no. 01n04 (March 2020): 2040001. http://dx.doi.org/10.1142/s0129156420400017.
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This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.
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Shen, Zongjie, Chun Zhao, Yanfei Qi, Ivona Z. Mitrovic, Li Yang, Jiacheng Wen, Yanbo Huang, Puzhuo Li, and Cezhou Zhao. "Memristive Non-Volatile Memory Based on Graphene Materials." Micromachines 11, no. 4 (March 25, 2020): 341. http://dx.doi.org/10.3390/mi11040341.
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Resistive random access memory (RRAM), which is considered as one of the most promising next-generation non-volatile memory (NVM) devices and a representative of memristor technologies, demonstrated great potential in acting as an artificial synapse in the industry of neuromorphic systems and artificial intelligence (AI), due its advantages such as fast operation speed, low power consumption, and high device density. Graphene and related materials (GRMs), especially graphene oxide (GO), acting as active materials for RRAM devices, are considered as a promising alternative to other materials including metal oxides and perovskite materials. Herein, an overview of GRM-based RRAM devices is provided, with discussion about the properties of GRMs, main operation mechanisms for resistive switching (RS) behavior, figure of merit (FoM) summary, and prospect extension of GRM-based RRAM devices. With excellent physical and chemical advantages like intrinsic Young’s modulus (1.0 TPa), good tensile strength (130 GPa), excellent carrier mobility (2.0 × 105 cm2∙V−1∙s−1), and high thermal (5000 Wm−1∙K−1) and superior electrical conductivity (1.0 × 106 S∙m−1), GRMs can act as electrodes and resistive switching media in RRAM devices. In addition, the GRM-based interface between electrode and dielectric can have an effect on atomic diffusion limitation in dielectric and surface effect suppression. Immense amounts of concrete research indicate that GRMs might play a significant role in promoting the large-scale commercialization possibility of RRAM devices.
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Wu, Chien-Hung, Song-Nian Kuo, Kow-Ming Chang, Yi-Ming Chen, Yu-Xin Zhang, Ni Xu, Wu-Yang Liu, and Albert Chin. "Investigation of Microwave Annealing on Resistive Random Access Memory Device with Atmospheric Pressure Plasma Enhanced Chemical Vapor Deposition Deposited IGZO Layer." Journal of Nanoscience and Nanotechnology 20, no. 7 (July 1, 2020): 4244–47. http://dx.doi.org/10.1166/jnn.2020.17561.
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Non-volatile memory (NVM) is essential in almost every consumer electronic products. The most prevalent NVM used nowadays is flash memory (Meena, J.S., et al., 2014. Overview of emerging nonvolatile memory technologies. Nanoscale Res. Letters, 9(1), p.526). However, some bottlenecks of flash memory have been identified, such as high operation voltage, low operation speed, and poor retention time. Resistive random access memory (RRAM) is considered to be the most promising one to become the next generation NVM device since its simple structure, fast program/erase speed, and low power consumption. In this experiment, the RRAM device is fabricated, and its IGZO (memory) layer is deposited with AP-PECVD technique which can reduce cost of the process. Microwave annealing (MWA) is used to enhance electrical characteristics of the RRAM device (Fuh, C.S., et al., 2011. Role of environmental and annealing conditions on the passivation-free In–Ga– Zn–O TFT. Thin Solid Films, 520, pp.1489–1494). Experiment results show that with appropriate MWA treatment, the IGZO RRAM device exhibits better electrical characteristics under bipolar operation, all forming/set/reset voltage for RRAM device is simultaneously lowered.
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Guo, Pengfei, Andrew Sarangan, and Imad Agha. "A Review of Germanium-Antimony-Telluride Phase Change Materials for Non-Volatile Memories and Optical Modulators." Applied Sciences 9, no. 3 (February 4, 2019): 530. http://dx.doi.org/10.3390/app9030530.
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Chalcogenide phase change materials based on germanium-antimony-tellurides (GST-PCMs) have shown outstanding properties in non-volatile memory (NVM) technologies due to their high write and read speeds, reversible phase transition, high degree of scalability, low power consumption, good data retention, and multi-level storage capability. However, GST-based PCMs have shown recent promise in other domains, such as in spatial light modulation, beam steering, and neuromorphic computing. This paper reviews the progress in GST-based PCMs and methods for improving the performance within the context of new applications that have come to light in recent years.
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Elyasi, Mehrdad, Chengkuo Lee, Cheng-Yu Hsieh, and Dim-Lee Kwong. "Multi-bit memory cell using long-range non-anchored actuation for high temperature applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000152–59. http://dx.doi.org/10.4071/hiten-ta18.
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A novel micro-electro-mechanical (MEM) based non-volatile memory (NVM) is proposed. The storage principle is based on Lorentz's transduction, utilizing long-range motion of a non-anchored element which has current carrying sliding contact with a conductive path. Position of the moving element indicates the stored data in the multi-bit cell. Data is written in the cell with displacing the moving element by Lorentz's force, is read by utilizing differential port resistances, and is held by adhesion forces. Data writing at up to 300°C, and data retention and reading for higher temperatures are reliable.
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Li, Shuo, Nong Xiao, Peng Wang, Guangyu Sun, Xiaoyang Wang, Yiran Chen, Hai Helen Li, Jason Cong, and Tao Zhang. "RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses." IEEE Transactions on Computers 68, no. 2 (February 1, 2019): 239–54. http://dx.doi.org/10.1109/tc.2018.2868368.
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Hu, Danqi, Fang Lv, Chenxi Wang, Hui-Min Cui, Lei Wang, Ying Liu, and Xiao-Bing Feng. "NVM Streaker: a fast and reconfigurable performance simulator for non-volatile memory-based memory architecture." Journal of Supercomputing 74, no. 8 (June 2, 2018): 3875–903. http://dx.doi.org/10.1007/s11227-018-2438-y.
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Bauer, Anton J., Martin Lemberger, Tobias Erlbacher, and Wenke Weinreich. "High-K: Latest Developments and Perspectives." Materials Science Forum 573-574 (March 2008): 165–80. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.165.
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The paper reviews recent progress and current challenges in implementing high-k dielectrics in microelectronics. Logic devices, non-volatile-memories, DRAMs and low power mixedsignal components are found to be the technologies where high-k dielectrics are implemented or will be introduced soon. Two gate architectures have to be considerd: MOS with metal as gate electrode and MIM. In particular, Hf-silicates for logic and NVM devices in conventional MOS architecture and ZrO2 for DRAM cells in MIM architecture are discussed.
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Suresh, Vignesh, Meiyu Stella Huang, Madapusi P. Srinivasan, and Sivashankar Krishnamoorthy. "High Density Metal Oxide (ZnO) Nanopatterned Platforms for Electronic Applications." MRS Proceedings 1498 (2013): 255–61. http://dx.doi.org/10.1557/opl.2013.344.
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ABSTRACTFabrication methodologies with high precision and tenability for nanostructures of metal and metal oxides are widely explored for engineering devices such as solar cells, sensors, non-volatile memories (NVM) etc. In this direction, metal and metal oxide nanopatterned arrays are the state-of-the-art platforms upon which the device structures are built where the tunable orderly arrangement of the nanostructures enhances the device performance. We describe here a coalition of fabrication protocols that employ block copolymer self-assembly and nanoimprint lithography (NIL) to obtain metal oxide nanopatterns with sub-100 nm spatial resolution. The protocols are easily scalable down to sub-50 nm and below.Nanopatterned arrays of ZnO created by using NIL assisted templates through area selective atomic layer deposition (ALD) and radio frequency (RF) sputtering find application in NVM and photovoltaics. We have employed NIL that produced nanoporous polymer templates using Si molds derived from block copolymer lithography (BCL) for pattern transfer into ZnO. The resulting ZnO nanoarrays were highly dense (8.6 x 109 nanofeatures per cm2) exhibiting periodic feature to feature spacing and width that replicated the geometric attributes of the template. Such nanopatterns find application in NVM, where a change in the density and periodicity of the arrays influences the charge storage characteristics. The above assembly and patterning protocols were employed to fabricate metal-oxide-semiconductor (MOS) capacitor devices for investigating application in NVM. Patterned ZnO nanoarrays were used as charge storage centres for the MOS capacitor devices. Preliminary results upon investigating the flash memory performance showed good flat-band voltage hysteresis window at a relatively low operating voltage due to high charge trap density.
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Hosseini, Fateme S., Fanruo Meng, Chengmo Yang, Wujie Wen, and Rosario Cammarota. "Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–21. http://dx.doi.org/10.1145/3477016.
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Hardware accelerators are essential to the accommodation of ever-increasing Deep Neural Network (DNN) workloads on the resource-constrained embedded devices. While accelerators facilitate fast and energy-efficient DNN operations, their accuracy is threatened by faults in their on-chip and off-chip memories, where millions of DNN weights are held. The use of emerging Non-Volatile Memories (NVM) further exposes DNN accelerators to a non-negligible rate of permanent defects due to immature fabrication, limited endurance, and aging. To tolerate defects in NVM-based DNN accelerators, previous work either requires extra redundancy in hardware or performs defect-aware retraining, imposing significant overhead. In comparison, this paper proposes a set of algorithms that exploit the flexibility in setting the fault-free bits in weight memory to effectively approximate weight values, so as to mitigate defect-induced accuracy drop. These algorithms can be applied as a one-step solution when loading the weights to embedded devices. They only require trivial hardware support and impose negligible run-time overhead. Experiments on popular DNN models show that the proposed techniques successfully boost inference accuracy even in the face of elevated defect rates in the weight memory.
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Khan, Mohammad Nasim Imtiaz, and Swaroop Ghosh. "Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories." Journal of Low Power Electronics and Applications 11, no. 4 (September 24, 2021): 36. http://dx.doi.org/10.3390/jlpea11040036.
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Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.
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Wen, Fei, Mian Qin, Paul Gratz, and Narasimha Reddy. "Software Hint-Driven Data Management for Hybrid Memory in Mobile Systems." ACM Transactions on Embedded Computing Systems 21, no. 1 (January 31, 2022): 1–18. http://dx.doi.org/10.1145/3494536.
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Hybrid memory systems, comprised of emerging non-volatile memory (NVM) and DRAM, have been proposed to address the growing memory demand of current mobile applications. Recently emerging NVM technologies, such as phase-change memories (PCM), memristor, and 3D XPoint, have higher capacity density, minimal static power consumption and lower cost per GB. However, NVM has longer access latency and limited write endurance as opposed to DRAM. The different characteristics of distinct memory classes render a new challenge for memory system design. Ideally, pages should be placed or migrated between the two types of memories according to the data objects’ access properties. Prior system software approaches exploit the program information from OS but at the cost of high software latency incurred by related kernel processes. Hardware approaches can avoid these latencies, however, hardware’s vision is constrained to a short time window of recent memory requests, due to the limited on-chip resources. In this work, we propose OpenMem: a hardware-software cooperative approach that combines the execution time advantages of pure hardware approaches with the data object properties in a global scope. First, we built a hardware-based memory manager unit (HMMU) that can learn the short-term access patterns by online profiling, and execute data migration efficiently. Then, we built a heap memory manager for the heterogeneous memory systems that allows the programmer to directly customize each data object’s allocation to a favorable memory device within the presumed object life cycle. With the programmer’s hints guiding the data placement at allocation time, data objects with similar properties will be congregated to reduce unnecessary page migrations. We implemented the whole system on the FPGA board with embedded ARM processors. In testing under a set of benchmark applications from SPEC 2017 and PARSEC, experimental results show that OpenMem reduces 44.6% energy consumption with only a 16% performance degradation compared to the all-DRAM memory system. The amount of writes to the NVM is reduced by 14% versus the HMMU-only, extending the NVM device lifetime.
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Rahman, Md Ferdous, Sheikh Rashel Al Ahmed, Golam Saklayen, and Abu Bakar Md Ismail. "Experimental Study on Silicon Nanocrystals Rich Lanthanum Fluoride Films for Future Electronic Devices." Rajshahi University Journal of Science and Engineering 44 (November 19, 2016): 61–66. http://dx.doi.org/10.3329/rujse.v44i0.30388.
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Feasibility for the future electronic devices a thorough investigation on Silicon nanocrystals (Si-NCs) rich Lanthanum Fluoride (LaF3) film fabricated using a novel onestep chemical method has been reported here. Colloidal solution of Si-NCs in hydrofluoric acid (HF) was prepared from meso-porous silicon by ultrasonic vibration (sonication). On a silicon (Si) substrate LaCl3 solution in HCL is allowed to react with the colloidal solution of prepared Si-NCs. LaCl3 reacts with HF of Si-NCs solution and produces LaF3 crystals that deposits on the silicon substrate as a film embedding Si-NCs. This is a novel single step chemical way of depositing LaF3 insulating layer embedding Si-NCs (LaF3:Si-NCs). The XRD and EDX analysis of the deposited film show a polycrystalline and non-stoichiometric nature of LaF3. The presence of Si-NCs was confirmed by SEM. Application of this material has been tested for low-voltage operating non-volatile memory (NVM) and Schottky junction solar cells. The Al/LaF3:Si-NCs/Al structure as NVM offered a memory window of 525 mV at a programming and erasing bias of 2V. LaF3:Si-NCs films showed strong light absorption. Current-Voltage (I-V) characteristics of the Schottky device in ITO/LaF3:Si-NCs/Al structure showed a dependency on the incident light intensity where current was varied in the range of 5 mA to 40 mA and under various light illumination i.e., 400 lux to 1200 lux. Experimental results show a lot of promise of Si-NCs-rich LaF3 film to be used as an insulating film in non-volatile memory as well as a photoactive material in Schottkey junction solar cell.
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Virwani, Kumar, Geoffrey W. Burr, Pritish Narayanan, and Bülent Kurdi. "Mixed-Ionic-Electronic-Conduction (MIEC)-Based Access Devices for 3D Multilayer Crosspoint Memory." MRS Proceedings 1729 (2015): 3–14. http://dx.doi.org/10.1557/opl.2015.24.
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ABSTRACTA number of applications call for the organization of resistive non-volatile memory (NVM) into large, densely-packed crossbar arrays. While resistive-NVM devices often possess some degree of inherent nonlinearity (typically 3-30× contrast), the operation of large (>1000×1000 device) arrays at low power tends to require large (> 1e7) ON-to-OFF ratios between the currents passed at high and at low voltages. Such large nonlinearities can be implemented by including a distinct access device together with each of the state-bearing resistive-NVM elements. While such an access device need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device.We review our work on high-performance access devices based on Cu-containing Mixed-Ionic-Electronic Conduction (MIEC) materials [1–7]. (This version focuses only on the MIEC-based access device itself; previously-published longer versions of this work [8–10] also include more extensive surveys of competing devices as well.) These devices require only the low processing temperatures of the Back-End-Of-the-Line (BEOL), making them highly suitable for implementing multi-layer crossbar arrays. MIEC-based access devices offer large ON/OFF ratios (>1e7), a significant voltage margin Vm (over which current < 10nA), and ultra-low leakage (<10pA), while also offering the high current densities needed for PCM and the fully bipolar operation needed for high-performance RRAM. Scalability to critical dimensions (CD) <30nm and thicknesses <15nm, tight distributions and 100% yield in large (512kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50ns turn-ON times have all been demonstrated. Numerical modeling of these MIEC-based access devices shows that their operation depends on Cu+ mediated hole conduction. Circuit simulations reveal that while scaled MIEC devices are suitable for large crossbar arrays of resistive-NVM devices with low (<1.2V) switching voltages, a compact vertical stack of two MIEC devices in series could support large crossbar arrays for switching voltages up to 2.5V.
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Kim, Jeong-Geun, Shin-Dug Kim, and Su-Kyung Yoon. "Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System." Electronics 9, no. 12 (December 16, 2020): 2158. http://dx.doi.org/10.3390/electronics9122158.
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This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application’s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement.
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Zhuge, Qingfeng, Hao Zhang, Edwin Hsing-Mean Sha, Rui Xu, Jun Liu, and Shengyu Zhang. "Exploring Efficient Architectures on Remote In-Memory NVM over RDMA." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–20. http://dx.doi.org/10.1145/3477004.
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Efficiently accessing remote file data remains a challenging problem for data processing systems. Development of technologies in non-volatile dual in-line memory modules (NVDIMMs), in-memory file systems, and RDMA networks provide new opportunities towards solving the problem of remote data access. A general understanding about NVDIMMs, such as Intel Optane DC Persistent Memory (DCPM), is that they expand main memory capacity with a cost of multiple times lower performance than DRAM. With an in-depth exploration presented in this paper, however, we show an interesting finding that the potential of NVDIMMs for high-performance, remote in-memory accesses can be revealed through careful design. We explore multiple architectural structures for accessing remote NVDIMMs in a real system using Optane DCPM, and compare the performance of various structures. Experiments are conducted to show significant performance gaps among different ways of using NVDIMMs as memory address space accessible through RDMA interface. Furthermore, we design and implement a prototype of user-level, in-memory file system, RIMFS, in the device DAX mode on Optane DCPM. By comparing against the DAX-supported Linux file system, Ext4-DAX, we show that the performance of remote reads on RIMFS over RDMA is 11.44 higher than that on a remote Ext4-DAX on average. The experimental results also show that the performance of remote accesses on RIMFS is maintained on a heavily loaded data server with CPU utilization as high as 90%, while the performance of remote reads on Ext4-DAX is significantly reduced by 49.3%, and the performance of local reads on Ext4-DAX is even more significantly reduced by 90.1%. The performance comparisons of writes exhibit the same trends.
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Kuznetsov, Sergey Dmitrievich, Pavel Evgenievich Velikhov, and Qiang Fu. "Real-Time Analytics, Hybrid Transactional/Analytical Processing, In-Memory Data Management, and Non-Volatile Memory." Proceedings of the Institute for System Programming of the RAS 33, no. 3 (2021): 171–98. http://dx.doi.org/10.15514/ispras-2021-33(3)-13.
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These days, real-time analytics is one of the most often used notions in the world of databases. Broadly, this term means very fast analytics over very fresh data. Usually the term comes together with other popular terms, hybrid transactional/analytical processing (HTAP) and in-memory data processing. The reason is that the simplest way to provide fresh operational data for analysis is to combine in one system both transactional and analytical processing. The most effective way to provide fast transactional and analytical processing is to store an entire database in memory. So on the one hand, these three terms are related but on the other hand, each of them has its own right to life. In this paper, we provide an overview of several in-memory data management systems that are not HTAP systems. Some of them are purely transactional, some are purely analytical, and some support real-time analytics. Then we overview nine in-memory HTAP DBMSs, some of which don't support real-time analytics. Existing real-time in-memory HTAP DBMSs have very diverse and interesting architectures although they use a number of common approaches: multiversion concurrency control, multicore parallelization, advanced query optimization, just in time compilation, etc. Additionally, we are interested whether these systems use non-volatile memory, and, if yes, in what manner. We conclude that an emergence of new generation of NVM will greatly stimulate its use in in-memory HTAP systems.
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Zou, Yu, Kazi Abu Zubair, Mazen Alwadi, Rakin Muhammad Shadab, Sanjay Gandham, Amro Awad, and Mingjie Lin. "ARES: Persistently Secure Non-Volatile Memory with Processor-transparent and Hardware-friendly Integrity Verification and Metadata Recovery." ACM Transactions on Embedded Computing Systems 21, no. 1 (January 31, 2022): 1–32. http://dx.doi.org/10.1145/3492735.
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Emerging byte-addressable Non-Volatile Memory (NVM) technology, although promising superior memory density and ultra-low energy consumption, poses unique challenges to achieving persistent data privacy and computing security, both of which are critically important to the embedded and IoT applications. Specifically, to successfully restore NVMs to their working states after unexpected system crashes or power failure, maintaining and recovering all the necessary security-related metadata can severely increase memory traffic, degrade runtime performance, exacerbate write endurance problem, and demand costly hardware changes to off-the-shelf processors. In this article, we designed and implemented ARES, a new FPGA-assisted processor-transparent security mechanism that aims at efficiently and effectively achieving all three aspects of a security triad—confidentiality, integrity, and recoverability—in modern embedded computing. Given the growing prominence of CPU-FPGA heterogeneous computing architectures, ARES leverages FPGA’s hardware reconfigurability to offload performance-critical and security-related functions to the programmable hardware without microprocessors’ involvement. In particular, recognizing that the traditional Merkle tree caching scheme cannot fully exploit FPGA’s parallelism due to its sequential and recursive function calls, we (1) proposed a Merkle tree cache architecture that partitions a unified cache into multiple levels with parallel accesses and (2) further designed a novel Merkle tree scheme that flattened and reorganized the computation in the traditional Merkle tree verification and update processes to fully exploit the parallel cache ports and to fully pipeline time-consuming hashing operations. Beyond that, to accelerate the metadata recovery process, multiple parallel recovery units are instantiated to recover counter metadata and multiple Merkle sub-trees. Our hardware prototype of the ARES system on a Xilinx U200 platform shows that ARES achieved up to 1.4× lower latency and 2.6× higher throughput against the baseline implementation, while metadata recovery time was shortened by 1.8 times. When integrated with an embedded processor, neither hardware changes nor software changes are required. We also developed a theoretical framework to analytically model and explain experimental results.
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Rahman, Labonnah Farzana, Mohammad Marufuzzaman, Lubna Alam, and Mazlin Bin Mokhtar. "Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications." Electronics 10, no. 6 (March 13, 2021): 676. http://dx.doi.org/10.3390/electronics10060676.
Full textAbstract:
Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the charge pump topologies based on input/output voltage, pumping efficiency, power dissipation, charge transfer capability, design complexity, pumping capacitor, clock frequencies with a minimum load balance, etc. Finally, this review study summarizes with the discussion on the outline of appropriate schemes and recommendations to future researchers in selecting the most suitable CP design methods for low power applications.
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Günzel, Mario, Christian Hakert, Kuan-Hsun Chen, and Jian-Jia Chen. "HEART: H ybrid Memory and E nergy- A ware R eal- T ime Scheduling for Multi-Processor Systems." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–23. http://dx.doi.org/10.1145/3477019.
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Dynamic power management (DPM) reduces the power consumption of a computing system when it idles, by switching the system into a low power state for hibernation. When all processors in the system share the same component, e.g., a shared memory, powering off this component during hibernation is only possible when all processors idle at the same time. For a real-time system, the schedulability property has to be guaranteed on every processor, especially if idle intervals are considered to be actively introduced. In this work, we consider real-time systems with hybrid shared-memory architectures, which consist of shared volatile memory (VM) and non-volatile memory (NVM). Energy-efficient execution is achieved by applying DPM to turn off all memories during the hibernation mode. Towards this, we first explore the hybrid memory architectures and suggest a task model, which features configurable hibernation overheads. We propose a multi-processor procrastination algorithm (HEART), based on partitioned earliest-deadline-first (pEDF) scheduling. Our algorithm facilitates reducing the energy consumption by actively enlarging the hibernation time. It enforces all processors to idle simultaneously without violating the schedulability condition, such that the system can enter the hibernation state, where shared memories are turned off. Throughout extensive evaluation of HEART, we demonstrate (1) the increase in potential hibernation time, respectively the decrease in energy consumption, and (2) that our algorithm is not only more general but also has better performance than the state of the art with respect to energy efficiency in most cases.
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Mispan, Mohd Syafiq, Aiman Zakwan Jidin, Muhammad Raihaan Kamarudin, and Haslinah Mohd Nasir. "Lightweight hardware fingerprinting solution using inherent memory in off-the-shelf commodity devices." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 1 (January 1, 2022): 105. http://dx.doi.org/10.11591/ijeecs.v25.i1.pp105-112.
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An emerging technology known as Physical unclonable function (PUF) can provide a hardware root-of-trust in building the trusted computing system. PUF exploits the intrinsic process variations during the integrated circuit (IC) fabrication to generate a unique response. This unique response differs from one PUF to the other similar type of PUFs. Static random-access memory PUF (SRAM-PUF) is one of the memory-based PUFs in which the response is generated during the memory power-up process. Non-volatile memory (NVM) architecture like SRAM is available in off-the-shelf microcontroller devices. Exploiting the inherent SRAM as PUF could wide-spread the adoption of PUF. Therefore, in this study, we evaluate the suitability of inherent SRAM available in ATMega2560 microcontroller on Arduino platform as PUF that can provide a unique fingerprint. First, we analyze the start-up values (SUVs) of memory cells and select only the cells that show random values after the power-up process. Subsequently, we statistically analyze the characteristic of fifteen SRAM-PUFs which include uniqueness, reliability, and uniformity. Based on our findings, the SUVs of fifteen on-chip SRAMs achieve 42.64% uniqueness, 97.28% reliability, and 69.16% uniformity. Therefore, we concluded that the available SRAM in off-the-shelf commodity hardware has good quality to be used as PUF.
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Cagliari, Bruna Casagranda, Paulo Francisco Butzen, and Raphael Martins Brum. "Design Considerations of a Nonvolatile Accumulator Based 8-bit Processor." Journal of Integrated Circuits and Systems 16, no. 1 (April 23, 2021): 1–10. http://dx.doi.org/10.29292/jics.v16i1.247.
Full textAbstract:
The rise of the Internet of Things (IoT) and the constant growth of portable electronics have leveraged the concern with energy consumption due to the use of batteries in these devices. The nonvolatile memory (NVM) emerged as a solution to mitigate the problem due to its ability to retain data on sleep mode without a power supply. Nonvolatile processors (NVPs), in turn, may further improve energy saving, by making use of nonvolatile flip-flops (NVFFs) that store system state in parallel, allowing the device to be turned off when idle and resume execution instantly after power-on. This work describes the initial steps to implement a nonvolatile version of Neander, a hypothetical processor created for educational purposes. First, we implemented Neander in Register Transfer Level (RTL), separating the combinational logic from the sequential elements. Then, the latter were replaced by transistor-level descriptions ofvolatile flip-flops. We then validated this implementation by employing a mixed-signal simulation over a set of benchmarks. Results shown the expected behavior for the whole instruction set. Then, we implemented MTJ-based non-volatile flip-flops in circuit-level, using an open-source MTJ model. These elements were exhaustive validated using electrical simulations. With these results, we intend to carry on the implementation and fully equip our processor with nonvolatile features such as instant wake up.