Academic literature on the topic 'Mémoire non volatile, NVM'
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Journal articles on the topic "Mémoire non volatile, NVM"
Shao, Zili, and Yuan-Hao Chang. "Non-Volatile memory (NVM) technologies." Journal of Systems Architecture 71 (November 2016): 1. http://dx.doi.org/10.1016/j.sysarc.2016.11.007.
Full textChu, Zhaole, Yongping Luo, and Peiquan Jin. "An Efficient Sorting Algorithm for Non-Volatile Memory." International Journal of Software Engineering and Knowledge Engineering 31, no. 11n12 (December 2021): 1603–21. http://dx.doi.org/10.1142/s0218194021400143.
Full textKawata, Hirotaka, Gaku Nakagawa, and Shuichi Oikawa. "Using DRAM as Cache for Non-Volatile Main Memory Swapping." International Journal of Software Innovation 4, no. 1 (January 2016): 61–71. http://dx.doi.org/10.4018/ijsi.2016010105.
Full textLi, Xiaochang, and Zhengjun Zhai. "UHNVM: A Universal Heterogeneous Cache Design with Non-Volatile Memory." Electronics 10, no. 15 (July 22, 2021): 1760. http://dx.doi.org/10.3390/electronics10151760.
Full textHe, Qinlu, Huiguo Dong, Genqing Bian, Fan Zhang, Weiqi Zhang, Kexin Liu, and Zhen Li. "The Research of Spark Memory Optimization Based on Non-Volatile Memory." Journal of Nanoelectronics and Optoelectronics 17, no. 1 (January 1, 2022): 30–39. http://dx.doi.org/10.1166/jno.2022.3166.
Full textHaywood Dadzie, Thomas, Jiwon Lee, Jihye Kim, and Hyunok Oh. "NVM-Shelf: Secure Hybrid Encryption with Less Flip for Non-Volatile Memory." Electronics 9, no. 8 (August 13, 2020): 1304. http://dx.doi.org/10.3390/electronics9081304.
Full textJung, Myoungsoo, Ellis H. Wilson, Wonil Choi, John Shalf, Hasan Metin Aktulga, Chao Yang, Erik Saule, Umit V. Catalyurek, and Mahmut Kandemir. "Exploring the Future of Out-of-Core Computing with Compute-Local Non-Volatile Memory." Scientific Programming 22, no. 2 (2014): 125–39. http://dx.doi.org/10.1155/2014/303810.
Full textBittman, Daniel, Peter Alvaro, Pankaj Mehra, Darrell D. E. Long, and Ethan L. Miller. "Twizzler: A Data-centric OS for Non-volatile Memory." ACM Transactions on Storage 17, no. 2 (June 7, 2021): 1–31. http://dx.doi.org/10.1145/3454129.
Full textBez, Roberto, Emilio Camerlenghi, and Agostino Pirovano. "Materials and Processes for Non-Volatile Memories." Materials Science Forum 608 (December 2008): 111–32. http://dx.doi.org/10.4028/www.scientific.net/msf.608.111.
Full textWang, Ming Qian, Jie Tao Diao, Nan Li, Xi Wang, and Kai Bu. "A Study on Reconfiguring On-Chip Cache with Non-Volatile Memory." Applied Mechanics and Materials 644-650 (September 2014): 3421–25. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3421.
Full textDissertations / Theses on the topic "Mémoire non volatile, NVM"
Jovanovic, Natalija. "Bascules et registres non-volatiles à base de ReRAM en technologies CMOS avancées." Electronic Thesis or Diss., Paris, ENST, 2016. http://www.theses.fr/2016ENST0023.
Full textNon-volatile memories and flip-flops can improve the energy efficiency in battery-operated devices by eliminating the sleep-mode consumption, while maintaining the system state. Among emerging embedded NVM technologies, ReRAMs differentiate itself with a fast programming time, a simple CMOS-compatible structure and a good scalability. Previously proposed ReRAM-based non-volatile flip-flops (NVFF) have been implemented in 90nm or older CMOS nodes and suffer from CMOS reliability issues in scaled nodes due to high programming and forming voltages. This thesis makes the analysis of robust and reliable non-volatile design in 28nm CMOS node and below. It presents two novel thin-gate oxide CMOS design solutions for the programming of ReRAM devices. The programming circuits are applied in dual-voltage NVFF architecture which employs two ReRAM devices (2R). Alternative 1R NVFF architecture is also proposed in order to achieve higher density and lower consumption. With regard to the existing ReRAM technologies, given NVFF solutions are optimized for ReRAM programming conditions which improve endurance and minimize programming power. Statistical analysis of the FF core and its optimization was performed, to evaluate the best restore operation architectures which meet digital CMOS circuit design yield requirements. The NVFFs are implemented in 28nm CMOS FDSOI and benchmarked against a master slave flip-flop from a standard library and a data-retention flip-flop. Finally, to minimize the NVFF area overhead without impacting the robustness of \nv{} operations, multi-port non-volatile register file (NVRF) based on the 1R NVFF solution is proposed
Innocenti, Jordan. "Conception et procédés de fabrication avancés pour l’électronique ultra-basse consommation en technologie CMOS 80 nm avec mémoire non volatile embarquée." Thesis, Nice, 2015. http://www.theses.fr/2015NICE4142/document.
Full textThe increase of the scope of application and the performance of microcontrollers is accompanied by an increase in power consumption reducing the life-time of mobile systems (smartphones, tablets, laptops, biomedical implants, …). Here, the work consists of reducing the dynamic consumption of circuits manufactured in embedded non-volatile memories (e-NVM) CMOS 80 nm technology by improving the performance of MOS transistors. In order to increase the carriers’ mobility, manufacturing techniques used in the most advanced technological nodes (40 nm, 32 nm) are firstly studied according to different criteria (process integration, cost, current/performance gain). Then, selected techniques are optimized and adapted to be used on an e-NVM technological platform. The next step is to study how to transform the current gain into dynamic power gain without impacting the static consumption. To do so, the supply voltage and the transistor widths are reduced. Up to 20 % in dynamic current gain is demonstrated using ring oscillators and a digital circuit designed with 20,000 standard cells. The methodology applied on the circuit allows automatic reduction to all transistor widths without additional design modifications. Finally, a last study is performed in order to optimize the consumption, the performance and the area of digital standard cells through design improvements and by reducing the mechanical stress of STI oxide
Barlas, Marios Dimitrios. "Development and characterization of innovative nonvolatile OxRAM memory cells compatible with advanced nodes." Electronic Thesis or Diss., Aix-Marseille, 2019. http://www.theses.fr/2019AIXM0229.
Full textTransition Metal Oxide ReRAM is a class of non-volatile memory technologies where the switching between memory states is enabled by the reversible breakdown of the oxide by means of the creation and dissolution of a percolation path (filament). The main advantages of the technology lie in the scalability of the memory cell –mainly owed to the sub 10nm dimension of the filament, its low power consumption (< 300 pJ/ switch) and material compatibility to advanced CMOS. Nevertheless, there are two major roadblocks that have prevented so far the implementation of ReRAM in large arrays: first, the requirement for an initial breakdown happening voltages significantly higher than the operating voltage range and second, the intrinsic and extrinsic variability components arising from material interaction to its environment as well as the fundamental stochastic nature of percolative conduction. This work, is focused on HfO2 based ReRAM technology. In the first part, we investigate different dopants to engineer the conductive properties of HfO2 by combining a first-principles approach and in-depth material characterization techniques. In the second part, the proposed HfSiOx alloy is integrated in the BEOL of a 130nm process and the impact of the integration of the switching zone in forming, switching, error rate evolution and data retention is investigated. In the last part, a HfO2 based integration in the early MOL of an advanced FDSOI 300mm CMOS process is demonstrated investigating standard HfO2 ReRAM performances and limitations
Chatzistergiou, Andreas. "Library support for historical and persistent data structures in non-volatile memories." Thesis, University of Edinburgh, 2016. http://hdl.handle.net/1842/25797.
Full textGuilmain, Marc. "Fabrication de mémoire monoélectronique non volatile par une approche de nanogrille flottante." Thèse, Université de Sherbrooke, 2013. http://hdl.handle.net/11143/6127.
Full textBossu, Germain. "Architectures innovantes de mémoire non-volatile embarquée sur film mince de silicium." Aix-Marseille 1, 2009. http://www.theses.fr/2009AIX11044.
Full textCMOS platforms are heading silicon thin film to face parasitic effects blocking bulk transistor scaling. This technological option is opening the way of new non-volatile memory device architectures. This PhD study deals with thin film technology tuning to turn into dense embedded non-volatile memory working with standard circuit power supply for an easy co-integration on bulk and thin film CMOS platforms. The first proposed SQeRAM cell is based on Silicon-On-Nothing technology process flow added to bulk CMOS core process. The resulting memory point presents charges stored at the opposite interface of inversion layer. This memory device is quasi-non-volatile due to a thin ONO stack allowing 3V only power supply. A semi-analytical model is developed to describe Independent Double Gate transistor considering electrons, holes and doping level. By the association of this approach with a charge-sheet Bulk transistor model, SQeRAM physical phenomena are detailed. In addition technological optimization is discussed to allow double-bit applications. SQeRAM scaling limitations, particularly technological process control, leads me to imagine another new non-volatile memory point built on a pure thin film IDG transistor. Concept, realization and specificities are described. The associated model developed drives physical mechanisms analysis of the main electrical characteristics versus trapped charge density. At last my PhD thesis brings up the guidelines of a new hybrid memory based on silicon thin film device combining non-volatile storage and floating body properties of the 1T-DRAM
Nail, Cécile. "Etude de mémoire non-volatile hybride CBRAM OXRAM pour faible consommation et forte fiabilité." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT010/document.
Full textAs Information Technologies (IT) are still growing, memory devices need to evolve to answer IT market demands. Nowadays, new technologies are emerging and are entering the market. Resistive Random Access Memory (RRAM) are part of these emerging devices and offer great advantages in terms of power consumption, performances, density and the possibility to be integrated in the back end of line. However, to be competitive, some roadblocks still have to be overcome especially regarding technology variability, reliability and thermal stability. Their place on memory market is then still undefined. Moreover, as RRAM working principle depends on stack materials and has to be observed at nanometer resolution, switching mechanism understanding is still challenging. This thesis proposes an analysis of oxide-based CBRAM microscopic working principle based on electrical characterization results and atomistic simulation. Then, an interdependence between RRAM electrical performances as well as material parameters is studied to point out new parameters that can be taken into account to target specific memory applications
Puglia, Gianlucca Oliveira. "Exploring atomicity on memory mapped files based on non-volatile memory file systems." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2017. http://tede2.pucrs.br/tede2/handle/tede/7768.
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As tecnologias de mem?rias n?o-vol?teis s?o uma grande promessa na ?rea de arquitetura de computadores e ? esperado que sejam poderosas ferramentas para solucionar os problemas referentes a manipula??o eficiente de dados dos dias de hoje. Estas tecnologias prov?m alta performance e acesso em granularidade de bytes com a distinta vantagem de serem persistentes. Por?m, afim de explorar estas tecnologias em todo seu potencial, os sistemas e arquiteturas de hoje precisam buscar meios de se adaptar a esta nova forma de acessar dados e de superar os desafios que v?m com ela.Trabalhos existentes na ?rea j? prop?em m?todos para adaptar as arquiteturas existentes para o uso de NVM bem como formas inovadoras de empregar estas mem?rias em futuras aplica??es. No entanto, o suporte dos sistemas operacionais a estas solu??es, ainda que existente, ainda ? muito limitado. Neste trabalho, n?s apresentamos duas varia??es da chamada de sistema msync, modeladas para explorar as caracter?sticas das tecnologias de NVM e garantir consist?ncia para os dados dos usu?rios. Ambas s?o solu??es simples que permitem aos usu?rios definirem checkpoints de seus arquivos usando a sintaxe comum de sistemas de arquivos. N?s implementamos e testamos estes m?todos sobre o sistema operacional Linux utilizando como base um sistema de arquivo nativamente voltado a NVM. Nossos resultados mostram que estes mecanismos s?o capazes de garantir a integridade dos arquivos mesmo na presen?a de falhas no sistema enquanto mant?m uma performance razo?vel.
Upcoming non-volatile memory technologies are a big promise in computer architecture and are expected to be powerful tools to address today?s issues regarding efficient data manipulation. They provide high performance and byte granularity while also having the distinct advantage of being persistent. However in order to explore these technologies to their full potential, existing systems and architecture must adapt to this new way of working with data and workaround the challenges that come with it. Existing work in the area already proposes methods to adapt existing architecture to NVM as well as innovative ways to employ these memories in future applications. However operating system support to such NVM-enabled solutions, although existent, still very limited. In this work, we present two variations of the existing mmap system call, designed to both explore NVM characteristics and provide user data consistency. Both are very simple solutions that allow users to control the persistence and define checkpoints to their files while using the common mapped file syntax. We have implemented and tested these methods over Linux using a NVM file system as our base. Our results show that these mechanisms can ensure file integrity in the presence of system failures while also providing a reasonable performance.
Yao, Thierry. "Modélisation et conception d'une mémoire non-volatile dédiée aux applications bas coût télé-alimentées." Paris, ENST, 2002. http://www.theses.fr/2002ENST0018.
Full textDelizy, Tristan. "Gestion de la mémoire dynamique pour les systèmes embarqués avec mémoire hétérogène." Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI134.
Full textReducing energy consumption is a key challenge to the realisation of the Internet of Things. While emerging memory technologies may offer power reduction and high integration density, they come with major drawbacks such as high latency or limited endurance. As a result, system designers tend to juxtapose several memory technologies on the same chip. We aim to provide the embedded application programmer with a transparent software mechanism to leverage this memory heterogeneity. This work studies the interaction between dynamic memory allocation and memory heterogeneity. We provide cycle accurate simulation of embedded platforms with various memory technologies and we show that different dynamic allocation strategies have a major impact on performance. We demonstrates that interesting performance gains can be achieved even for a low fraction of memory using low latency technology, but only with a clever placement strategy between memory banks. We propose an efficient strategy based on application profiling in our simulator
Book chapters on the topic "Mémoire non volatile, NVM"
Dimitrakis, Panagiotis. "Introduction to NVM Devices." In Charge-Trapping Non-Volatile Memories, 1–36. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-15290-5_1.
Full textYu, Hao, and Yuhao Wang. "Fundamentals of NVM Physics and Computing." In Design Exploration of Emerging Nano-scale Non-volatile Memory, 29–44. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4939-0551-5_2.
Full textYu, Hao, and Yuhao Wang. "Nonvolatile State Identification and NVM SPICE." In Design Exploration of Emerging Nano-scale Non-volatile Memory, 45–83. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4939-0551-5_3.
Full textKhyzha, Artem, and Ori Lahav. "Abstraction for Crash-Resilient Objects." In Programming Languages and Systems, 262–89. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-99336-8_10.
Full textButterfield, N. R., R. Mays, B. Khan, R. Gudlavalleti, and F. C. Jain. "Quantum Dot Gate (QDG) Quantum Dot Channel (QDC) Multistate Logic Non-Volatile Memory (NVM) with High-K Dielectric HfO2 Barriers." In Selected Topics in Electronics and Systems, 1–12. WORLD SCIENTIFIC, 2021. http://dx.doi.org/10.1142/9789811242823_0001.
Full textWu, Xiaohan, Ruijing Ge, Deji Akinwande, and Jack C. Lee. "Memristors Based on 2D Monolayer Materials." In Memristor - An Emerging Device for Post-Moore’s Computing and Applications. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.98331.
Full textConference papers on the topic "Mémoire non volatile, NVM"
Brewer, J. E. "NVM in the far term." In 2005 Non-Volatile Memory Technology Symposium. IEEE, 2005. http://dx.doi.org/10.1109/nvmt.2005.1541374.
Full textLindstrom, Jan, Dhananjoy Das, Torben Mathiasen, Dulcardo Arteaga, and Nisha Talagala. "NVM aware MariaDB database system." In 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA). IEEE, 2015. http://dx.doi.org/10.1109/nvmsa.2015.7304362.
Full textBu, Jiankang, William Belcher, Courtney Parker, and Hank Prosack. "Unique Challenges and Solutions in CMOS Compatible NVM." In 2006 7th Annual Non-Volatile Memory Technology Symposium. IEEE, 2006. http://dx.doi.org/10.1109/nvmt.2006.378876.
Full textLi, Shuangchen, Ping Chi, Jishen Zhao, Kwang-Ting Cheng, and Yuan Xie. "Leveraging nonvolatility for architecture design with emerging NVM." In 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA). IEEE, 2015. http://dx.doi.org/10.1109/nvmsa.2015.7304356.
Full textPark, Sung-Kun, Nam-Yoon Kim, Kwang-il Choi, Jae-Gwan Kim, In-Wook Cho, Kyung-Dong Yoo, Eun-Mee Kwon, and Sang-Yong Kim. "Characteristics comparison of standard logic and HVCMOS processed SGLC embedded NVM." In 2014 14th Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2014. http://dx.doi.org/10.1109/nvmts.2014.7060858.
Full textBayram, Ismail, and Yiran Chen. "NV-TCAM: Alternative interests and practices in NVM designs." In 2014 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2014. http://dx.doi.org/10.1109/nvmsa.2014.6927206.
Full textChoi, Gunhee, Seungboo Kim, and Jongmoo Choi. "Quantitative Analysis of File System Performance on NVM." In 2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2018. http://dx.doi.org/10.1109/nvmsa.2018.00027.
Full textDuan, Hongwei, Liang Shi, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Changlong Li, and Yujiong Liang. "An Empirical Study of NVM-based File System." In 2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2021. http://dx.doi.org/10.1109/nvmsa53655.2021.9628430.
Full textHo, Yu Ting, Chun-Feng Wu, Ming-Chang Yang, Tseng-Yi Chen, and Yuan-Hao Chang. "Replanting Your Forest: NVM-friendly Bagging Strategy for Random Forest." In 2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2019. http://dx.doi.org/10.1109/nvmsa.2019.8863525.
Full textHakert, Christian, Kuan-Hsun Chen, Simon Kuenzer, Sharan Santhanam, Shuo-Han Chen, Yuan-Hao Chang, Felipe Huici, and Jian-Jia Chen. "Split'n Trace NVM: Leveraging Library OSes for Semantic Memory Tracing." In 2020 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2020. http://dx.doi.org/10.1109/nvmsa51238.2020.9188136.
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