Academic literature on the topic 'Mechatronics hardware design and architecture'
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Journal articles on the topic "Mechatronics hardware design and architecture"
Sima, Liviu Mihai. "Design and Testing Ways for Mechatronic Systems." International Journal on Cybernetics & Informatics 11, no. 2 (April 30, 2022): 61–69. http://dx.doi.org/10.5121/ijci.2022.110206.
Full textTan, Yan Zhi, Chee Khiang Pang, Fan Hong, and Tong Heng Lee. "Integrated servo-mechanical design of high-performance mechatronics using generalized KYP Lemma." Microsystem Technologies 19, no. 9-10 (June 26, 2013): 1549–57. http://dx.doi.org/10.1007/s00542-013-1853-5.
Full textChen, Ruirui, Yusheng Liu, Jianjun Zhao, and Xiaoping Ye. "Model verification for system design of complex mechatronic products." Systems Engineering 22, no. 2 (August 24, 2018): 156–71. http://dx.doi.org/10.1002/sys.21470.
Full textNAUNIN, DIETRICH. "LOOKING FORWARD TO THE INTELLIGENT ELECTRICAL MACHINE: ELECTRONICS AND MACHINES COMBINE THEIR ABILITIES." Journal of Circuits, Systems and Computers 05, no. 01 (March 1995): 45–63. http://dx.doi.org/10.1142/s0218126695000059.
Full textUlbrich, Heinz, T. Buschmann, and S. Lohmeier. "Development of the Humanoid Robot LOLA." Applied Mechanics and Materials 5-6 (October 2006): 529–40. http://dx.doi.org/10.4028/www.scientific.net/amm.5-6.529.
Full textZaitceva, Iuliia, and Boris Andrievsky. "Methods of Intelligent Control in Mechatronics and Robotic Engineering: A Survey." Electronics 11, no. 15 (August 5, 2022): 2443. http://dx.doi.org/10.3390/electronics11152443.
Full textMarín Garcés, Josep, Carlos Veiga Almagro, Giacomo Lunghi, Mario Di Castro, Luca Rosario Buonocore, Raúl Marín Prades, and Alessandro Masi. "MiniCERNBot Educational Platform: Antimatter Factory Mock-up Missions for Problem-Solving STEM Learning." Sensors 21, no. 4 (February 17, 2021): 1398. http://dx.doi.org/10.3390/s21041398.
Full textPérez Bayas, Miguel Ángel, Juan Cely, Avishai Sintov, Cecilia E. García Cena, and Roque Saltaren. "Method to Develop Legs for Underwater Robots: From Multibody Dynamics with Experimental Data to Mechatronic Implementation." Sensors 22, no. 21 (November 3, 2022): 8462. http://dx.doi.org/10.3390/s22218462.
Full textFIJALKOWSKI, BOGDAN T. "THE CONCEPT OF A HIGH PERFORMANCE ALL-ROUND ENERGY EFFICIENT MECHATRONICALLY-CONTROLLED TRI-MODE SUPERCAR." Journal of Circuits, Systems and Computers 05, no. 01 (March 1995): 93–107. http://dx.doi.org/10.1142/s0218126695000084.
Full textWalters, R. M., D. A. Bradley, and A. P. Dorey. "A conceptual study for a computer-based tool to support electronics design in a mechatronic environment." Microprocessors and Microsystems 24, no. 2 (April 2000): 51–61. http://dx.doi.org/10.1016/s0141-9331(99)00067-8.
Full textDissertations / Theses on the topic "Mechatronics hardware design and architecture"
Basic, Goran. "Hardware-in-the-loop simulation of mechanical loads for mechatronics system design." Thesis, University of Ottawa (Canada), 2003. http://hdl.handle.net/10393/26323.
Full textYazdanpanah, Fahimeh. "Hardware design of task superscalar architecture." Doctoral thesis, Universitat Politècnica de Catalunya, 2014. http://hdl.handle.net/10803/277376.
Full textExplotar la concurrencia para conseguir un mejor rendimiento es un reto importante y difícil para los sistemas de alto rendimiento. Aunque la teoría es sencilla, en muchos casos la complejidad de los modelos de programación paralela tradicionales impide al programador obtener un buen rendimiento. Se han propuesto diferentes granularidades de particionamiento de tareas para explotar mejor la concurrencia implícita en las aplicaciones. En este sentido, diferentes sistemas software de manejo dinámico de tareas utilizan los principios de ejecución "dataflow" para mejorar el paralelismo a nivel de tarea y superar el rendimiento de los sistemas de planificación estáticos. Estos modelos planfican la ejecución dinámicamente y utilizan tareas, en lugar de instrucciones, como unidad básica de trabajo. De esta forma descargan al programador de tener que realizar la sincronización de las tareas explícitamente en su programa. Aunque estos modelos de programación comparten muchas similitudes con los bien conocidos procesadores fuera de orden (como el análisis dinámico de dependencias y la ejecución en "dataflow"), dependen de un análisis dinámico software de las dependencias. Dicho análisis es inherentemente lento y limita la escalabilidad cuando hay un gran número de tareas pequeñas. Los problemas antes mencionados se incrementan exponencialmente con el número de núcleos disponibles. Para conseguir mantener todos los núcleos ocupados y conseguir acelerar el rendimiento global de la aplicación se hace necesario particionarla en muchas tareas pequeñas. La gestión de dichas tareas (es decir, su creación y distribución entre los núcleos) en software introduce sobrecostes, y por tanto resulta ineficiente conforme aumenta el número de núcleos. En contraposición, un sistema hardware de planificación de tareas puede conseguir mejores rendimientos ya que requiere una menor latencia en la gestión de las tareas. El Task Superscalar (TSS) es una arquitectura híbrida dataflow/von-Neumann que explota el paralelismo a nivel de tareas de los programas. El TSS combina la efectividad de los procesadores fuera de orden con la abstracción de tarea, y por tanto provee una capa unificada de gestión para los CMPs que gestiona los núcleos como unidades funcionales. Previo al trabajo de esta tesis el Task Superscalar se había implementado en software con un paralelismo limitado y mucho consumo de memoria debido a las limitaciones inherentes de una implementación software. En esta tesis se diseñado una implementación hardware de la arquitectura Task Superscalar con capacidad para manejar muchas tareas de pequeño tamaño que es integrable en un futuro computador de altas prestaciones. Así pues, las contribuciones principales de esta tesis son: (1) el diseño de un flujo operacional de la arquitectura Task Superscalar adaptado y mejorado para su implementación hardware; (2) un prototipo HDL de dicho flujo para la exploración de las latencias asociadas a la implementación hardware; (3) un simulador ciclo a ciclo del diseño hardware basado en los resultados obtenidos en la implementación hardware; (4) una exploración completa del espacio de diseño de los componentes hardware (número y cantidad de módulos, tamaños de las memorias, etc.) para diferentes tamaños de computadores (es decir, para diferentes cantidades de nucleos); (5) una comparación con la implementación software actual del mismo modelo de programación utilizando aplicaciones reales y; (6) una exploración de la utilización de recursos hardware de las diferentes configuraciones seleccionadas.
Persson, Robert. "PPS5000 Thruster Emulator Architecture Development & Hardware Design." Thesis, Luleå tekniska universitet, Rymdteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-72827.
Full textMahmud, Akib. "Hardware in the Loop (HIL) Rig Design and Electrical Architecture." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-324661.
Full textDavis, Jesse H. Z. (Jesse Harper Zehring) 1980. "Hardware & software architecture for multi-level unmanned autonomous vehicle design." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/16968.
Full textIncludes bibliographical references (p. 95-96).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
The theory, simulation, design, and construction of a radically new type of unmanned aerial vehicle (UAV) are discussed. The vehicle architecture is based on a commercially available non-autonomous flyer called the Vectron Blackhawk Flying Saucer. Due to its full body rotation, the craft is more inherently gyroscopically stable than other more common types of UAVs. This morphology was chosen because it has never before been made autonomous, so the theory, simulation, design, and construction were all done from fundamental principles as an example of original multi-level autonomous development.
by Jesse H.Z. Davis.
M.Eng.
Pajayakrit, A. "VLSI architecture and design for the Fermat Number Transform implementation." Thesis, University of Newcastle Upon Tyne, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379767.
Full textPatel, Krutartha Computer Science & Engineering Faculty of Engineering UNSW. "Hardware-software design methods for security and reliability of MPSoCs." Awarded by:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/44854.
Full textLiang, Cao. "Hardware/Software Co-Design Architecture and Implementations of MIMO Decoders on FPGA." ScholarWorks@UNO, 2006. http://scholarworks.uno.edu/td/416.
Full textMoreira, Francis Birck. "Profiling and reducing micro-architecture bottlenecks at the hardware level." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/103977.
Full textMost mechanisms in current superscalar processors use instruction granularity information for speculation, such as branch predictors or prefetchers. However, many of these characteristics can be obtained at the basic block level, increasing the amount of code that can be covered while requiring less space to store the data. Moreover, the code can be profiled more accurately and provide a higher variety of information by analyzing different instruction types inside a block. Because of these advantages, block-level analysis can offer more opportunities for mechanisms that use this information. For example, it is possible to integrate information about branch prediction and memory accesses to provide precise information for speculative mechanisms, increasing accuracy and performance. We propose a BLAP, an online mechanism that profiles bottlenecks at the microarchitectural level, such as delinquent memory loads, hard-to-predict branches and contention for functional units. BLAP works at the basic block level, providing information that can be used to reduce the impact of these bottlenecks. A prefetch dropping mechanism and a memory controller policy were developed to use the profiled information provided by BLAP. Together, these mechanisms are able to improve performance by up to 17.39% (3.90% on average). Our technique showed average gains of 13.14% when evaluated under high memory pressure due to highly aggressive prefetch.
Woods, Walt. "The Design of a Simple, Spiking Sparse Coding Algorithm for Memristive Hardware." PDXScholar, 2016. http://pdxscholar.library.pdx.edu/open_access_etds/2721.
Full textBooks on the topic "Mechatronics hardware design and architecture"
Mano, M. Morris. Computer engineering: Hardware design. London: Prentice Hall International, 1988.
Find full textGeorge, Willse, ed. PCI hardware and software: Architecture and design. 3rd ed. San Diego: Annabooks, 1996.
Find full textGeorge, Willse, ed. PCI hardware and software: Architecture and design. San Diego, CA: Annabooks, 1994.
Find full textBelean, Bogdan. Application-Specific Hardware Architecture Design with VHDL. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-65025-8.
Full textKain, Richard Y. Computer architecture: Software and hardware. Hemel Hempstead: Prentice-Hall, 1989.
Find full textKain, Richard Y. Computer architecture: Software and hardware. Englewood Cliffs, N.J: Prentice Hall, 1989.
Find full textHill, Fredrick J. Digital systems: Hardware organization and design. 3rd ed. New York: Wiley, 1987.
Find full textPatterson, David A. Computer organization and design: The hardware/software interface. 4th ed. Boston: Elsevier Morgan Kaufmann, 2008.
Find full textPatterson, David A. Computer organization and design: The hardware/software interface. 3rd ed. Amsterdam: Elsevier/Morgan Kaufmann, 2004.
Find full textHennessy, John L. Computer Organization and Design: The Hardware/Software Interface. San Mateo, Calif: Morgan Kaufmann, 1994.
Find full textBook chapters on the topic "Mechatronics hardware design and architecture"
Marković, Dejan, Robert W. Brodersen, Rashmi Nanda, and Henry Chen. "Simulink-Hardware Flow." In DSP Architecture Design Essentials, 225–51. Boston, MA: Springer US, 2012. http://dx.doi.org/10.1007/978-1-4419-9660-2_12.
Full textGeorge, Varghese, and Jan M. Rabaey. "Hardware Implementation." In Low-Energy FPGAs — Architecture and Design, 127–49. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4615-1421-3_7.
Full textSchagaev, Igor, and Thomas Kaegi-Trachsel. "Hardware: The ERRIC Architecture." In Software Design for Resilient Computer Systems, 189–97. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29465-0_14.
Full textSchagaev, Igor, Eugene Zouev, and Kaegi Thomas. "Hardware: The ERRIC Architecture." In Software Design for Resilient Computer Systems, 197–205. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-21244-5_14.
Full textArora, Mohit. "Low Power Design." In The Art of Hardware Architecture, 95–128. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0397-5_5.
Full textSzefer, Jakub. "Hardware Root of Trust." In Principles of Secure Processor Architecture Design, 53–64. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-031-01760-5_5.
Full textArora, Mohit. "Design Guidelines for EMC Performance." In The Art of Hardware Architecture, 183–214. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0397-5_9.
Full textSarma, Santanu, and Nikil Dutt. "Architecture and Cross-Layer Design Space Exploration." In Handbook of Hardware/Software Codesign, 247–70. Dordrecht: Springer Netherlands, 2017. http://dx.doi.org/10.1007/978-94-017-7267-9_9.
Full textSarma, Santanu, and Nikil Dutt. "Architecture and Cross-Layer Design Space Exploration." In Handbook of Hardware/Software Codesign, 1–24. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-7358-4_9-1.
Full textAbdallah, Abderazek Ben. "Low Power Embedded Core Architecture." In Multicore Systems On-Chip: Practical Software/Hardware Design, 107–26. Paris: Atlantis Press, 2010. http://dx.doi.org/10.2991/978-94-91216-33-6_6.
Full textConference papers on the topic "Mechatronics hardware design and architecture"
Kulic, Dana, and Elizabeth Croft. "Mechatronic System Integration for Senior Students." In ASME 2006 International Mechanical Engineering Congress and Exposition. ASMEDC, 2006. http://dx.doi.org/10.1115/imece2006-13761.
Full textKasthurirathna, Dharshana, Andy Dong, Mahendrarajah Piraveenan, and Irem Y. Tumer. "The Failure Tolerance of Mechatronic Software Systems to Random and Targeted Attacks." In ASME 2013 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/detc2013-12188.
Full textAnanthakrishnan, S., and Viswanath Ananth. "RCS Based Hardware-in-the-Loop Embedded Control of Industrial Stamping Processes." In ASME 2003 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2003. http://dx.doi.org/10.1115/detc2003/cie-48260.
Full textAlvarez Cabrera, Andre´s A., Hitoshi Komoto, and Tetsuo Tomiyama. "Supporting Co-Design of Physical and Control Architectures of Mechatronic Systems." In ASME 2011 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2011. http://dx.doi.org/10.1115/detc2011-48200.
Full textLuo, Ren C., and Hsin-Hung Liu. "Design and implementation of efficient hardware solution based sub-window architecture of Haar classifiers for real-time detection of face biometrics." In 2010 IEEE International Conference on Mechatronics and Automation (ICMA). IEEE, 2010. http://dx.doi.org/10.1109/icma.2010.5589229.
Full textJunglas, Marco, Amir Kazeminia, Ru¨diger Eick, and Dirk So¨ffker. "Reliability-Based Design of Future Highly Reliable Systems." In ASME 2009 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2009. http://dx.doi.org/10.1115/detc2009-86981.
Full textSingh, Surya P. N., and Kenneth J. Waldron. "GL-Link: A Novel Telerobotics-Based Platform Supporting Distributed Mechatronic Research Via the Internet." In ASME 2003 International Mechanical Engineering Congress and Exposition. ASMEDC, 2003. http://dx.doi.org/10.1115/imece2003-42093.
Full textHannius, Olof, Dan Ring, and Johan Karlsson. "Derivation of Diagnostic Requirements for a Distributed UAV Turbofan Engine Control System." In ASME Turbo Expo 2006: Power for Land, Sea, and Air. ASMEDC, 2006. http://dx.doi.org/10.1115/gt2006-90094.
Full textMartin, Adrian, and M. Emami. "An Architecture for Robotic Hardware-in-the-Loop Simulation." In 2006 International Conference on Mechatronics and Automation. IEEE, 2006. http://dx.doi.org/10.1109/icma.2006.257628.
Full textWan Roh, Dong, and Jae Wook Jeon. "Hardware Architecture Design for Template Matching." In 2019 International SoC Design Conference (ISOCC). IEEE, 2019. http://dx.doi.org/10.1109/isocc47750.2019.9078515.
Full textReports on the topic "Mechatronics hardware design and architecture"
Modlo, Yevhenii O., Serhiy O. Semerikov, Stanislav L. Bondarevskyi, Stanislav T. Tolmachev, Oksana M. Markova, and Pavlo P. Nechypurenko. Methods of using mobile Internet devices in the formation of the general scientific component of bachelor in electromechanics competency in modeling of technical objects. [б. в.], February 2020. http://dx.doi.org/10.31812/123456789/3677.
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