Academic literature on the topic 'Mechatronics hardware design and architecture'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Mechatronics hardware design and architecture.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Journal articles on the topic "Mechatronics hardware design and architecture"
1
Sima, Liviu Mihai. "Design and Testing Ways for Mechatronic Systems." International Journal on Cybernetics & Informatics 11, no. 2 (April 30, 2022): 61–69. http://dx.doi.org/10.5121/ijci.2022.110206.
Full textAbstract:
The elements of a mechatronic system, which are mechanical, electrical and electronic, are interconnected and the connection between the different parts must act as a unit. The exchange of information between two components of the system is possible if there is a communication in common parameters. The interface refers to all the ways to handle the processes in a system. The number and design of interfaces within an architecture and system boundary significantly influence the simplicity, adaptability, and testability of a system. Interfaces, which are hardware and software, define the functionality of the system by inserting functions from one component to another. The article describes the method of selecting the components and the way of testing the system during production. Finally, the system must meet the requirements of the customer. The mechatronic system discussed is an industrial product, created in a digital factory.
2
Tan, Yan Zhi, Chee Khiang Pang, Fan Hong, and Tong Heng Lee. "Integrated servo-mechanical design of high-performance mechatronics using generalized KYP Lemma." Microsystem Technologies 19, no. 9-10 (June 26, 2013): 1549–57. http://dx.doi.org/10.1007/s00542-013-1853-5.
Full text
3
Chen, Ruirui, Yusheng Liu, Jianjun Zhao, and Xiaoping Ye. "Model verification for system design of complex mechatronic products." Systems Engineering 22, no. 2 (August 24, 2018): 156–71. http://dx.doi.org/10.1002/sys.21470.
Full text
4
NAUNIN, DIETRICH. "LOOKING FORWARD TO THE INTELLIGENT ELECTRICAL MACHINE: ELECTRONICS AND MACHINES COMBINE THEIR ABILITIES." Journal of Circuits, Systems and Computers 05, no. 01 (March 1995): 45–63. http://dx.doi.org/10.1142/s0218126695000059.
Full textAbstract:
Electrical machines, more than 150 years old, have long been distinguished according to their mechanical structure and frequencies of their supply voltage (or current). This is not true any more after the electronic revolution. Since the fast development in power electronics as well as in control electronics these electronics can give any motor any desired speed-torque characteristic and any motor can become a servodrive having a very precise position control. By implementing digital control algorithms, mainly the cascaded, the state feedback or the cascaded state feedback control, and — if necessary, in addition — adaptive control procedures which compensate the variation of system parameters in the controller, the "intelligent electrical machine" — either with the synchronous or with the induction machine — is created. It is part of mechatronics. It can be installed in modern automated systems, in robots and tool machines, in all kinds of industrial drive systems as well as in locomotives and electric cars. Also modern methods like fuzzy logic and neural networks can be used. It seems that they will not create a second revolution in the control itself, but in the application areas of drives. They add some interesting features to the intelligent electrical machine and make it even more intelligent. They could also speed up the controller design in future.
5
Ulbrich, Heinz, T. Buschmann, and S. Lohmeier. "Development of the Humanoid Robot LOLA." Applied Mechanics and Materials 5-6 (October 2006): 529–40. http://dx.doi.org/10.4028/www.scientific.net/amm.5-6.529.
Full textAbstract:
This paper presents the performance enhanced humanoid robot LOLA which is currently being manufactured. Hardware design, controllers and simulation are based on ex- perience gained during the development of the robot JOHNNIE. The objective of the current research project is to realize a fast, human-like and autonomous walking motion. To enable an optimal design of the robot with respect to lightweight construction, motor and drive sizing, an appropriate simulation model is required. Dynamics simulation is a key tool to develop the hardware and control design properly. For hardware design and detailed dynamic analysis a comprehensive model including motor and gear dynamics is required, while for controller de- sign and stability analysis a simplified model for global system dynamics is sufficient. Both robots are characterized by a lightweight construction. In comparison to JOHNNIE, the new robot LOLA has a modular, multi-sensory joint design with brushless motors. Moreover, the previously purely central electronics architecture is replaced by a network of decentral joint controllers, sensor data acquisition and filtering units and a central PC. The fusion of motor, gear and sensors into a highly integrated mechatronic joint module has several advantages for the whole system, including high power density, good dynamic performance and reliability. Ad- ditional degrees of freedom are introduced in elbow, waist and toes. Linear actuators are used for the knee joints to achieve a better mass distribution in the legs.
6
Zaitceva, Iuliia, and Boris Andrievsky. "Methods of Intelligent Control in Mechatronics and Robotic Engineering: A Survey." Electronics 11, no. 15 (August 5, 2022): 2443. http://dx.doi.org/10.3390/electronics11152443.
Full textAbstract:
Artificial intelligence is becoming an increasingly popular tool in more and more areas of technology. New challenges in control systems design and application are related to increased productivity, control flexibility, and processing of big data. Some kinds of systems require autonomy in real-time decision-making, while the other ones may serve as an essential factor in human-robot interaction and human influences on system performance. Naturally, the complex tasks of controlling technical systems require new modern solutions, but there remains an inextricable link between control theory and artificial intelligence. The first part of the present survey is devoted to the main intelligent control methods in technical systems. Among them, modern methods of adaptive and optimal control, fuzzy logic, and machine learning are considered. In its second part, the crucial achievements in intelligent control applications in robotic and mechatronic systems over the past decade are considered. The references are structured according to the type of such common control problems as stabilization, controller tuning, identification, parametric optimization, iterative learning, and prediction. In the conclusion, the main problems and tendencies toward intelligent control methods improvement are outlined.
7
Marín Garcés, Josep, Carlos Veiga Almagro, Giacomo Lunghi, Mario Di Castro, Luca Rosario Buonocore, Raúl Marín Prades, and Alessandro Masi. "MiniCERNBot Educational Platform: Antimatter Factory Mock-up Missions for Problem-Solving STEM Learning." Sensors 21, no. 4 (February 17, 2021): 1398. http://dx.doi.org/10.3390/s21041398.
Full textAbstract:
Mechatronics and robotics appeared particularly effective in students’ education, allowing them to create non-traditional solutions in STEM disciplines, which have a direct impact and interaction with the world surrounding them. This paper presents the current state of the MiniCERNBot Educational Robotic platform for high-school and university students. The robot provides a comprehensive educative system with tutorials and tasks tuned for different ages on 3D design, mechanical assembly, control, programming, planning, and operation. The system is inspired to existing robotic systems and typical robotic interventions performed at CERN, and includes an education mock-up that follows the example of a previous real operation performed in CERN’s Antimatter Factory. The paper describes the learning paths where the MiniCERNBot platform can be used by students, at different ages and disciplines. In addition, it describes the software and hardware architecture, presenting results on modularity and network performance during education exercises. In summary, the objective of the study is improving the way STEM educational and dissemination activities at CERN Robotics Lab are performed, as well as their possible synergies with other education institutions, such as High-Schools and Universities, improving the learning collaborative process and inspiring students interested in technical studies. To this end, a new educational robotic platform has been designed, inspired on real scientific operations, which allows the students practice multidisciplinary STEM skills in a collaborative problem-solving way, while increasing their motivation and comprehension of the research activities.
8
Pérez Bayas, Miguel Ángel, Juan Cely, Avishai Sintov, Cecilia E. García Cena, and Roque Saltaren. "Method to Develop Legs for Underwater Robots: From Multibody Dynamics with Experimental Data to Mechatronic Implementation." Sensors 22, no. 21 (November 3, 2022): 8462. http://dx.doi.org/10.3390/s22218462.
Full textAbstract:
Exploration of the seabed may be complex, and different parameters must be considered for a robotic system to achieve tasks in this environment, such as soil characteristics, seabed gait, and hydrodynamic force in this extreme environment. This paper presents a gait simulation of a quadrupedal robot used on a typical terrigenous sediment seabed, considering the mechanical properties of the type of soil, stiffness, and damping and friction coefficients, referenced with the specialized literature and applied in a computational multibody model with many experimental data in a specific underwater environment to avoi hydrodynamic effects. The requirements of the positions and torque in the robot’s active joints are presented in accordance with a 5R mechanism for the leg and the natural pattern shown in the gait of a dog on the ground. These simulation results are helpful for the design of a testbed, with a leg prototype and its respective hardware and software architecture and a subsequent comparison with the real results.
9
FIJALKOWSKI, BOGDAN T. "THE CONCEPT OF A HIGH PERFORMANCE ALL-ROUND ENERGY EFFICIENT MECHATRONICALLY-CONTROLLED TRI-MODE SUPERCAR." Journal of Circuits, Systems and Computers 05, no. 01 (March 1995): 93–107. http://dx.doi.org/10.1142/s0218126695000084.
Full textAbstract:
Automotive designers' long-term ambition of combining high performance and excellent liquid and gas fuel economy in the same automotive vehicle, seems to be on the verge of fruition by Cracow University of Technology's Automotive Mechatronics Research-and-Development (R&D) Team with their revolutionary concept of new all-round energy efficient tri-mode supercars (advanced ultralight hybrids). This all-round, energy efficient, tri-mode supercar concept had been conceived shortly before October 1993 when the US President Bill Clinton's Clean Car Initiative launched a commitment by America's Big Three automotive manufacturers in Detroit that are to be assisted by America's national weapons laboratories in a 10-year program to develop environmentally-friendly supercars. Reporting this, the New York Times named President Clinton's teenage dream car as a 1952 Buick "Kaiser Henry J" gas guzzler. The development of the tri-mode supercars at Cracow University of Technology began in the early 1990s on a very much restricted budget, compared with similar projects in other countries, with emphasis on lengthening the operating distance and enhancing the image of them. Longer running distance will be achieved by designing an energy-saving full-time Four-Wheel Driveable (4WD) propulsion, Four-Wheel Brakeable (4WB) dispulsion, Four-Wheel Absorbable (4WA) suspension, Four-Wheel Steerable (4WS) conversion and ultralight chassis and body with an aerodynamic drag of around 0.2, as well as the use of high-performance unconventional combustion engines, modern electronically-controlled electromechanical/ mechanoelectrical Steer-, Autodrive- and Autoabsorbable Wheels ( SA 2 W ) with the AC-AC, AC-DC-AC and/or DC-AC/AC-DC macroelectronic converter commutator (macrocommutator) wheel-hub motors/generators and high-density mechanical energy-storing high-speed Autodrive- and Autoabsorbable Flywheel ( A 2 F ) with the brushless AC-AC, AC-DC-AC and/or DC-AC/AC-DC macrocommutator twin composite-flywheel-hub motors/generators and chemical energy-storing advanced chemoelectrical storage battery. Called the Poly-Supercar (or Polytechnic all-round energy efficient tri-mode supercar), i.e. the advanced ultralight hybrid, it will be the product of four year's R&D to design an experimental four-seat supercar of advanced specification, performance and economy, and with functions which include lane keeping, adaptive cruise control, traffic sign recognition, obstacle detection, collision avoidance, blind spot detection, and day/night vision enhancement.
10
Walters, R. M., D. A. Bradley, and A. P. Dorey. "A conceptual study for a computer-based tool to support electronics design in a mechatronic environment." Microprocessors and Microsystems 24, no. 2 (April 2000): 51–61. http://dx.doi.org/10.1016/s0141-9331(99)00067-8.
Full textDissertations / Theses on the topic "Mechatronics hardware design and architecture"
1
Basic, Goran. "Hardware-in-the-loop simulation of mechanical loads for mechatronics system design." Thesis, University of Ottawa (Canada), 2003. http://hdl.handle.net/10393/26323.
Full textAbstract:
Current research efforts in Hardware-In-The-Loop (HIL) simulations are directed toward testing Electronic Control Units, simulated digitally, in a physical experimental setup. This thesis presents different approach of using HIL simulations. Active and passive mechanical loads can be simulated physically on direct drive motors, under computer control. The work in thesis is based on effort-flow concept, which allows components of the experimental setup to be replaced as needed by physical or digital model. The only requirement that has to be satisfied is that elements of the setup retain their inputs and outputs, in the form of effort and flow pairs.
Based on this theory, the new experimental setup was built, a generic HIL setup containing two DC motors, which are connected by shaft. One of the motors is used to actuate the system, while another motor represents the physical simulator. Based on the sets of derived formulas, physical simulator is able to simulate active and passive loads.
Three different experimental levels are presented in the thesis. The open loop, current control and torque control experiments.
The experimental results prove the concept in whole and show that theory can be applied in real world applications. The focus in this research is on simulation of nonlinear loads, whose models are presented by sets of nonlinear differential equations. Digital simulations require solutions of those equations and it is demanding job. The method of physical simulations presented in this thesis shows simpler way of simulating complex loads.
2
Yazdanpanah, Fahimeh. "Hardware design of task superscalar architecture." Doctoral thesis, Universitat Politècnica de Catalunya, 2014. http://hdl.handle.net/10803/277376.
Full textAbstract:
Exploiting concurrency to achieve greater performance is a difficult and important challenge for current high performance systems. Although the theory is plain, the complexity of traditional parallel programming models in most cases impedes the programmer to harvest performance.
Several partitioning granularities have been proposed to better exploit concurrency at task granularity. In this sense, different dynamic software task management systems, such as task-based dataflow programming models, benefit dataflow principles to improve task-level parallelism and overcome the limitations of static task management systems. These models implicitly schedule computation and data and use tasks instead of instructions as a basic work unit, thereby relieving the programmer of explicitly managing parallelism. While these programming models share conceptual similarities with the well-known Out-of-Order superscalar pipelines (e.g., dynamic data dependency analysis and dataflow scheduling), they rely on software-based dependency analysis, which is inherently slow, and limits their scalability when there is fine-grained task granularity and a large amount of tasks.
The aforementioned problem increases with the number of available cores. In order to keep all the cores busy and accelerate the overall application performance, it becomes necessary to partition it into more and smaller tasks. The task scheduling (i.e., creation and management of the execution of tasks) in software introduces overheads, and so becomes increasingly inefficient with the number of cores. In contrast, a hardware scheduling solution can achieve greater speed-ups as a hardware task scheduler requires fewer cycles than the software version to dispatch a task.
The Task Superscalar is a hybrid dataflow/von-Neumann architecture that exploits the task level parallelism of the program. The Task Superscalar combines the effectiveness of Out-of-Order processors together with the task abstraction, and thereby provides an unified management layer for CMPs which effectively employs processors as functional units. The Task Superscalar has been implemented in software with limited parallelism and high memory consumption due to the nature of the software implementation.
In this thesis, a Hardware Task Superscalar architecture is designed to be integrated in a future High Performance Computer with the ability to exploit fine-grained task parallelism. The main contributions of this thesis are: (1) a design of the operational flow of Task Superscalar architecture adapted and improved for hardware implementation, (2) a HDL prototype for latency exploration, (3) a full cycle-accurate simulator of the Hardware Task Superscalar (based on the previously obtained latencies), (4) full design space exploration of the Task Superscalar component configuration (number and size) for systems with different number of processing elements (cores), (5) comparison with a software implementation of a real task-based programming model runtime using real benchmarks, and (6) hardware resource usage exploration of the selected configurations.Explotar la concurrencia para conseguir un mejor rendimiento es un reto importante y difícil para los sistemas de alto rendimiento. Aunque la teoría es sencilla, en muchos casos la complejidad de los modelos de programación paralela tradicionales impide al programador obtener un buen rendimiento. Se han propuesto diferentes granularidades de particionamiento de tareas para explotar mejor la concurrencia implícita en las aplicaciones. En este sentido, diferentes sistemas software de manejo dinámico de tareas utilizan los principios de ejecución "dataflow" para mejorar el paralelismo a nivel de tarea y superar el rendimiento de los sistemas de planificación estáticos. Estos modelos planfican la ejecución dinámicamente y utilizan tareas, en lugar de instrucciones, como unidad básica de trabajo. De esta forma descargan al programador de tener que realizar la sincronización de las tareas explícitamente en su programa. Aunque estos modelos de programación comparten muchas similitudes con los bien conocidos procesadores fuera de orden (como el análisis dinámico de dependencias y la ejecución en "dataflow"), dependen de un análisis dinámico software de las dependencias. Dicho análisis es inherentemente lento y limita la escalabilidad cuando hay un gran número de tareas pequeñas. Los problemas antes mencionados se incrementan exponencialmente con el número de núcleos disponibles. Para conseguir mantener todos los núcleos ocupados y conseguir acelerar el rendimiento global de la aplicación se hace necesario particionarla en muchas tareas pequeñas. La gestión de dichas tareas (es decir, su creación y distribución entre los núcleos) en software introduce sobrecostes, y por tanto resulta ineficiente conforme aumenta el número de núcleos. En contraposición, un sistema hardware de planificación de tareas puede conseguir mejores rendimientos ya que requiere una menor latencia en la gestión de las tareas. El Task Superscalar (TSS) es una arquitectura híbrida dataflow/von-Neumann que explota el paralelismo a nivel de tareas de los programas. El TSS combina la efectividad de los procesadores fuera de orden con la abstracción de tarea, y por tanto provee una capa unificada de gestión para los CMPs que gestiona los núcleos como unidades funcionales. Previo al trabajo de esta tesis el Task Superscalar se había implementado en software con un paralelismo limitado y mucho consumo de memoria debido a las limitaciones inherentes de una implementación software. En esta tesis se diseñado una implementación hardware de la arquitectura Task Superscalar con capacidad para manejar muchas tareas de pequeño tamaño que es integrable en un futuro computador de altas prestaciones. Así pues, las contribuciones principales de esta tesis son: (1) el diseño de un flujo operacional de la arquitectura Task Superscalar adaptado y mejorado para su implementación hardware; (2) un prototipo HDL de dicho flujo para la exploración de las latencias asociadas a la implementación hardware; (3) un simulador ciclo a ciclo del diseño hardware basado en los resultados obtenidos en la implementación hardware; (4) una exploración completa del espacio de diseño de los componentes hardware (número y cantidad de módulos, tamaños de las memorias, etc.) para diferentes tamaños de computadores (es decir, para diferentes cantidades de nucleos); (5) una comparación con la implementación software actual del mismo modelo de programación utilizando aplicaciones reales y; (6) una exploración de la utilización de recursos hardware de las diferentes configuraciones seleccionadas.
3
Persson, Robert. "PPS5000 Thruster Emulator Architecture Development & Hardware Design." Thesis, Luleå tekniska universitet, Rymdteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-72827.
Full textAbstract:
This Master's Thesis handles prestudy work and early hardware development that resulted in architectural definitions and prototype hardware of electronic ground support equipment. This equipment is destined to emulate the electric power consumption of the PPS5000 Hall Effect Thruster (HET), for use in satellite end-to-end tests of the all-electric Geostationary Satellite Electra, developed at OHB Sweden AB. The Thruster Emulator (TEM) was defined through a resulting compilation of intricate interdependent components that interface the satellite power system and the thruster, which yielded an architecture development to support some basic predefined emulator requirements. This architecture was then analyzed to form a base-line conceptual function of the emulator system, which incorporates the entire HET functionality. Six primary HET impedances were defined, of which the three most complex impedances were investigated fully. For the primary thruster discharge, research is shown of the complexity of implementing advanced electronic load hardware directly to the satellite's 5kW power system with respect to the transient primary plasma discharge during thruster start up, and with limitations on the electronic load reducing emulator-thruster similarities. Additionally, a fully functional plasma ignition emulator prototype circuit board was built to be used in the final hardware of the TEM to emulate the external HET cathode start-up functionality. Finally, a feasibility study for designing a possible solution for the large PPS5000 electromagnet impedance was performed, resulting in the manufacture of two prototype inductors with unsatisfying performance results according to the design requirements.
4
Mahmud, Akib. "Hardware in the Loop (HIL) Rig Design and Electrical Architecture." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-324661.
Full textAbstract:
Different types of machines are tested utilizing so called Hardware In the Loop simulation. To perform HIL-simulation a rig is used consisting of different types of hardware and software. Some of the hardware that are used during a simulation is located inside an EMS box. The box has not been properly updated since 2004, no documentation of changes has been made and often many errors occurs during simulations due to the lack of traceability. During this project a new structure of the EMS box has been designed with modifications to eliminate existing problems, prevent similar problems to occur in the future and improve the usability of the system. A simulation was performed on the camshaft to test if there were any improvements. Most issues were solved but there were one problem that remained. Some noises existed and were rooted in the old box which undeniably remained in the new one.
5
Davis, Jesse H. Z. (Jesse Harper Zehring) 1980. "Hardware & software architecture for multi-level unmanned autonomous vehicle design." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/16968.
Full textAbstract:
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 95-96).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
The theory, simulation, design, and construction of a radically new type of unmanned aerial vehicle (UAV) are discussed. The vehicle architecture is based on a commercially available non-autonomous flyer called the Vectron Blackhawk Flying Saucer. Due to its full body rotation, the craft is more inherently gyroscopically stable than other more common types of UAVs. This morphology was chosen because it has never before been made autonomous, so the theory, simulation, design, and construction were all done from fundamental principles as an example of original multi-level autonomous development.
by Jesse H.Z. Davis.
M.Eng.
6
Pajayakrit, A. "VLSI architecture and design for the Fermat Number Transform implementation." Thesis, University of Newcastle Upon Tyne, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379767.
Full text
7
Patel, Krutartha Computer Science & Engineering Faculty of Engineering UNSW. "Hardware-software design methods for security and reliability of MPSoCs." Awarded by:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/44854.
Full textAbstract:
Security of a Multi-Processor System on Chip (MPSoC) is an emerging area of concern in embedded systems. MPSoC security is jeopardized by Code Injection attacks. Code Injection attacks, which are the most common types of software attacks, have plagued single processor systems. Design of MPSoCs must therefore incorporate security as one of the primary objectives. Code Injection attacks exploit vulnerabilities in \trusted" and legacy code. An architecture with a dedicated monitoring processor (MONITOR) is employed to simultaneously supervise the application processors on an MPSoC. The program code in the application processors is divided into basic blocks. The basic blocks in the application processors are statically instrumented with special instructions that allow communication with the MONITOR at runtime. The MONITOR verifies the execution of all the processors at runtime using control flow checks and either a timing or instruction count check. This thesis proposes a monitoring system called SOFTMON, a design methodology called SHIELD, a design flow called LOCS and an architectural framework called CUFFS for detecting Code Injection attacks. SOFTMON, a software monitoring system, uses a software algorithm in the MONITOR. SOFTMON incurs limited area overheads. However, the runtime performance overhead is quite high. SHIELD, an extension to the work in SOFTMON overcomes the limitation of high runtime overhead using a MONITOR that is predominantly hardware based. LOCS uses only one special instruction per basic block compared to two, as was the case in SOFTMON and SHIELD. Additionally, profile information is generated for all the basic blocks in all the application processors for the MPSoC designer to tune the design by increasing or decreasing the frequency of loop basic blocks. CUFFS detects attacks even without application processors communicating to the MONITOR. The SOFTMON, SHIELD and LOCS approaches can only detect attacks if the application processors communicate to the MONITOR. CUFFS relies on the exact number of instructions in basic blocks to determine an attack, rather than time-frame based measures used in SOFTMON, SHIELD and LOCS. The lowest runtime performance overhead was achieved by LOCS (worst case of 37.5%), while the SOFTMON monitoring system had the least amount of area overheads of about 25%. The CUFFS approach employed an active MONITOR and hence detected a greater range of attacks. The CUFFS framework also detects bit flip errors (reliability errors) in the control flow instructions of the application processors on an MPSoC. CUFFS can detect nearly 70% of all bit flip errors in the control flow instructions. Additionally, a modified CUFFS approach is proposed to ensure reliable inter-processor communication on an MPSoC. The modified CUFFS approach uses a hardware based checksum approach for reliable inter-processor communication and incurred a runtime performance overhead of up to 25% and negligible area overheads compared to CUFFS. Thus, the approaches proposed in this thesis equip an MPSoC designer with tools to embed security features during an MPSoC's design phase. Incorporating security measures at the processor design level provides security against software attacks in MPSoCs and incurs manageable runtime, area and code-size overheads.
8
Liang, Cao. "Hardware/Software Co-Design Architecture and Implementations of MIMO Decoders on FPGA." ScholarWorks@UNO, 2006. http://scholarworks.uno.edu/td/416.
Full textAbstract:
During the last years, multiple-input multiple-output (MIMO) technology has attracted great attentions in the area of wireless communications. The hardware implementation of MIMO decoders becomes a challenging task as the complexity of the MIMO system increases. This thesis presents hardware/software co-design architecture and implementations of two typical lattice decoding algorithms, including Agrell and Vardy (AV) algorithm and Viterbo and Boutros (VB) algorithm. Three levels of parallelisms are analyzed for an efficient implementation with the preprocessing part on embedded MicroBlaze soft processor and the decoding part on customized hardware. The decoders for a 4 by 4 MIMO system with 16-QAM modulation scheme are prototyped on a Xilinx XC2VP30 FPGA device. The hardware implementations of the AV and VB decoders show that they support up to 81 Mbps and 37 Mbps data rate respectively. The performances in terms of resource utilizations and BER are also compared between these two decoders.
9
Moreira, Francis Birck. "Profiling and reducing micro-architecture bottlenecks at the hardware level." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/103977.
Full textAbstract:
A maior parte dos mecanismos em processadores superescalares atuais usam granularidade de instrução para criar ou caracterizar especulações, tais como predição de desvios ou prefetchers. No entanto, muitas das características das instruções podem ser obtidas ao analisar uma granularidade mais grossa, o bloco básico de código, aumentando a quantidade de código coberta em um espaço similar de armazenamento. Adicionalmente, códigos podem ser analisados mais precisamente e prover uma variedade maior de informação ao observar diferentes tipos de instruções e suas relações. Devido a estas vantagens, a análise no nível de blocos pode fornecer mais oportunidades para mecanismos que necessitam desta informação. Por exemplo, é possível integrar informações de desvios mal previstos e acessos a memória para gerar informações mais precisas de quais acessos a memória oferecem melhor desempenho ao serem priorizados. Nesta tese propomos o Block-Level Architecture Profiler (BLAP) (Block Level Architecture Profiler), um mecanismo em hardware que caracteriza gargalos no nível microarquitetural, tal como loads delinquentes, desvios de difícil previsão e contenção nas unidades funcionais. O BLAP trabalha no nível de bloco básico, apenas detectando e fornecendo informações que podem ser usada para otimizar tais gargalos. Um mecanismo para a remoção de prefetches e uma política de controlador de memória DRAM foram criados para usar a informação criada pelo BLAP e demonstrar seu potencial. Juntos, estes mecanismos são capazes de melhorar o desempenho do sistema em até 17.39% (3.9% em média). Nosso método mostrou também ganhos médios de 13.14% quando avaliado com uma pressão na memória mais alta devido a prefetchers mais agressivos.Most mechanisms in current superscalar processors use instruction granularity information for speculation, such as branch predictors or prefetchers. However, many of these characteristics can be obtained at the basic block level, increasing the amount of code that can be covered while requiring less space to store the data. Moreover, the code can be profiled more accurately and provide a higher variety of information by analyzing different instruction types inside a block. Because of these advantages, block-level analysis can offer more opportunities for mechanisms that use this information. For example, it is possible to integrate information about branch prediction and memory accesses to provide precise information for speculative mechanisms, increasing accuracy and performance. We propose a BLAP, an online mechanism that profiles bottlenecks at the microarchitectural level, such as delinquent memory loads, hard-to-predict branches and contention for functional units. BLAP works at the basic block level, providing information that can be used to reduce the impact of these bottlenecks. A prefetch dropping mechanism and a memory controller policy were developed to use the profiled information provided by BLAP. Together, these mechanisms are able to improve performance by up to 17.39% (3.90% on average). Our technique showed average gains of 13.14% when evaluated under high memory pressure due to highly aggressive prefetch.
10
Woods, Walt. "The Design of a Simple, Spiking Sparse Coding Algorithm for Memristive Hardware." PDXScholar, 2016. http://pdxscholar.library.pdx.edu/open_access_etds/2721.
Full textAbstract:
Calculating a sparse code for signals with high dimensionality, such as high-resolution images, takes substantial time to compute on a traditional computer architecture. Memristors present the opportunity to combine storage and computing elements into a single, compact device, drastically reducing the area required to perform these calculations. This work focused on the analysis of two existing sparse coding architectures, one of which utilizes memristors, as well as the design of a new, third architecture that employs a memristive crossbar. These architectures implement either a non-spiking or spiking variety of sparse coding based on the Locally Competitive Algorithm (LCA) introduced by Rozell et al. in 2008. Each architecture receives an arbitrary number of input lines and drives an arbitrary number of output lines. Training of the dictionary used for the sparse code was implemented through external control signals that approximate Oja's rule. The resulting designs were capable of representing input in real-time: no resets would be needed between frames of a video, for instance, though some settle time would be needed. The spiking architecture proposed is novel, emphasizing simplicity to achieve lower power than existing designs.
The architectures presented were tested for their ability to encode and reconstruct 8 x 8 patches of natural images. The proposed network reconstructed patches with a normalized, root-mean-square error of 0.13, while a more complicated CMOS-only approach yielded 0.095, and a non-spiking approach yielded 0.074. Several outputs competing for representation of the input was shown to improve reconstruction quality and preserve more subtle components in the final encoding; the proposed algorithm lacks this feature. Steps to address this were proposed for future work by scaling input spikes according to the current expected residual, without adding much complexity. The architectures were also tested with the MNIST digit database, passing a sparse code onto a basic classifier. The proposed architecture scored 81% on this test, a CMOS-only spiking variant scored 76%, and the non-spiking algorithm scored 85%. Power calculations were made for each design and compared against other publications. The overall findings showed great promise for spiking memristor-based ASICs, consuming only 28% of the power used by non-spiking architectures and 6.6% as much power as a CMOS-only spiking architecture on this task. The spike-based nature of the novel design was also parameterized into several intuitive parameters that could be adjusted to prefer either performance or power efficiency.
The design and analysis of architectures for sparse coding should greatly reduce the amount of future work needed to implement an end-to-end classification pipeline for images or other signal data. When lower power is a primary concern, the proposed architecture should be considered as it surpassed other published algorithms. These pipelines could be used to provide low-power visual assistance, highlighting objects within high-definition video frames in real-time. The technology could also be used to help self-driving cars identify hazards more quickly and efficiently.
Books on the topic "Mechatronics hardware design and architecture"
1
Mano, M. Morris. Computer engineering: Hardware design. London: Prentice Hall International, 1988.
Find full text
2
George, Willse, ed. PCI hardware and software: Architecture and design. 3rd ed. San Diego: Annabooks, 1996.
Find full text
3
George, Willse, ed. PCI hardware and software: Architecture and design. San Diego, CA: Annabooks, 1994.
Find full text
4
Belean, Bogdan. Application-Specific Hardware Architecture Design with VHDL. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-65025-8.
Full text
5
Kain, Richard Y. Computer architecture: Software and hardware. Hemel Hempstead: Prentice-Hall, 1989.
Find full text
6
Kain, Richard Y. Computer architecture: Software and hardware. Englewood Cliffs, N.J: Prentice Hall, 1989.
Find full text
7
Hill, Fredrick J. Digital systems: Hardware organization and design. 3rd ed. New York: Wiley, 1987.
Find full text
8
Patterson, David A. Computer organization and design: The hardware/software interface. 4th ed. Boston: Elsevier Morgan Kaufmann, 2008.
Find full text
9
Patterson, David A. Computer organization and design: The hardware/software interface. 3rd ed. Amsterdam: Elsevier/Morgan Kaufmann, 2004.
Find full text
10
Hennessy, John L. Computer Organization and Design: The Hardware/Software Interface. San Mateo, Calif: Morgan Kaufmann, 1994.
Find full textBook chapters on the topic "Mechatronics hardware design and architecture"
1
Marković, Dejan, Robert W. Brodersen, Rashmi Nanda, and Henry Chen. "Simulink-Hardware Flow." In DSP Architecture Design Essentials, 225–51. Boston, MA: Springer US, 2012. http://dx.doi.org/10.1007/978-1-4419-9660-2_12.
Full text
2
George, Varghese, and Jan M. Rabaey. "Hardware Implementation." In Low-Energy FPGAs — Architecture and Design, 127–49. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4615-1421-3_7.
Full text
3
Schagaev, Igor, and Thomas Kaegi-Trachsel. "Hardware: The ERRIC Architecture." In Software Design for Resilient Computer Systems, 189–97. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29465-0_14.
Full text
4
Schagaev, Igor, Eugene Zouev, and Kaegi Thomas. "Hardware: The ERRIC Architecture." In Software Design for Resilient Computer Systems, 197–205. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-21244-5_14.
Full text
5
Arora, Mohit. "Low Power Design." In The Art of Hardware Architecture, 95–128. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0397-5_5.
Full text
6
Szefer, Jakub. "Hardware Root of Trust." In Principles of Secure Processor Architecture Design, 53–64. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-031-01760-5_5.
Full text
7
Arora, Mohit. "Design Guidelines for EMC Performance." In The Art of Hardware Architecture, 183–214. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0397-5_9.
Full text
8
Sarma, Santanu, and Nikil Dutt. "Architecture and Cross-Layer Design Space Exploration." In Handbook of Hardware/Software Codesign, 247–70. Dordrecht: Springer Netherlands, 2017. http://dx.doi.org/10.1007/978-94-017-7267-9_9.
Full text
9
Sarma, Santanu, and Nikil Dutt. "Architecture and Cross-Layer Design Space Exploration." In Handbook of Hardware/Software Codesign, 1–24. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-7358-4_9-1.
Full text
10
Abdallah, Abderazek Ben. "Low Power Embedded Core Architecture." In Multicore Systems On-Chip: Practical Software/Hardware Design, 107–26. Paris: Atlantis Press, 2010. http://dx.doi.org/10.2991/978-94-91216-33-6_6.
Full textConference papers on the topic "Mechatronics hardware design and architecture"
1
Kulic, Dana, and Elizabeth Croft. "Mechatronic System Integration for Senior Students." In ASME 2006 International Mechanical Engineering Congress and Exposition. ASMEDC, 2006. http://dx.doi.org/10.1115/imece2006-13761.
Full textAbstract:
This paper describes the design and implementation of a senior level course in mechatronic system integration for students completing a mechatronics engineering option in mechanical engineering. The course is designed to give students theoretical and practical experience with a large-scale mechatronic system, and a variety of control, sensing and actuating architectures. The lecture component of the course introduces students to large-scale project integration and interface design, as well as system architecture design. Students learn about alternative control hardware platforms commonly used in industry, such as motion control hardware, field programmable gate arrays and programmable logic controllers. The selection and system integration of various industrial sensors, including vision, are presented. Students also learn about networked control and discrete event control approaches for large-scale industrial systems. The course contains a significant practical laboratory component. In a series of laboratory sessions, students develop and implement subsystems of a part sorting machine, culminating in the integration and demonstration of an automated, autonomous, sensor driven electro-mechanical system for sorting randomly delivered parts. The course offers students a theoretical background as well as significant practical experience with large scale mechatronics systems, as would be encountered in industry. This paper describes the lecture and laboratory content, and the experiences from the first offering of the course.
2
Kasthurirathna, Dharshana, Andy Dong, Mahendrarajah Piraveenan, and Irem Y. Tumer. "The Failure Tolerance of Mechatronic Software Systems to Random and Targeted Attacks." In ASME 2013 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/detc2013-12188.
Full textAbstract:
This paper describes a complex networks approach to study the failure tolerance of mechatronic software systems under various types of hardware and/or software failures. We produce synthetic system architectures based on evidence of modular and hierarchical modular product architectures and known motifs for the interconnection of physical components to software. The system architectures are then subject to various forms of attack. The attacks simulate failure of critical hardware or software. Four types of attack are investigated: degree centrality, betweenness centrality, closeness centrality and random attack. Failure tolerance of the system is measured by a ‘robustness coefficient’, a topological ‘size’ metric of the connectedness of the attacked network. We find that the betweenness centrality attack results in the most significant reduction in the robustness coefficient, confirming betweenness centrality, rather than the number of connections (i.e. degree), as the most conservative metric of component importance. A counter-intuitive finding is that “designed” system architectures, including a bus, ring, and star architecture, are not significantly more failure-tolerant than interconnections with no prescribed architecture, that is, a random architecture. Our research provides a data-driven approach to engineer the architecture of mechatronic software systems for failure tolerance.
3
Ananthakrishnan, S., and Viswanath Ananth. "RCS Based Hardware-in-the-Loop Embedded Control of Industrial Stamping Processes." In ASME 2003 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2003. http://dx.doi.org/10.1115/detc2003/cie-48260.
Full textAbstract:
There is a growing need for providing a flexible mechatronic environment to enhance productivity in industrial processes. Specifically, in the area of sheet metal forming, where stamping quality and part consistency are still achieved by traditional iterative process of trial and error, there is a clear urgency to enhance productivity and quality through automation. The traditional feedback control schemes used in many industrial processes cannot be applied to sheet metal forming, mainly due to the complexity of the stamping process and associated difficulty of using COTS (off-the-shelf) controllers for such applications. In this paper we demonstrate a hardware-in-the-loop flexible mechatronic design environment that will allow batch production of stamped parts with varying geometry and material properties, with minimal defects and greater consistency, using Simulink/RTW/xpcTarget framework which affords the feature of open architecture controller and the NIST Real-time Control System (RCS) architecture that allows structured, hierarchical implementation of industrial controllers. In conjunction with the Neutral Message Language (NML) RCS also allows for distributed hardware-in-the-loop control design with multiple processors. The merits of this approach over conventional approaches are also highlighted.
4
Alvarez Cabrera, Andre´s A., Hitoshi Komoto, and Tetsuo Tomiyama. "Supporting Co-Design of Physical and Control Architectures of Mechatronic Systems." In ASME 2011 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2011. http://dx.doi.org/10.1115/detc2011-48200.
Full textAbstract:
There is a rather recent tendency to define the physical structure and the control structure of a system concurrently when designing the architecture of a product, i.e., to perform codesign. We argue that co-design can only be enabled when the mutual influence between physical system and control is made evident to the designer at an early stage. Though the idea of design integration is not new, to the best of our knowledge, there is no computer tooling that explicitly supports this activity by enabling co-design as stated before. In this paper the authors propose a method for co-design of physical and control architectures as a better approach to design mechatronic systems, allowing to exploit the synergy between software and hardware and detecting certain design problems at an early stage of design. The proposed approach is supported by a set of tools and demonstrated through an example case.
5
Luo, Ren C., and Hsin-Hung Liu. "Design and implementation of efficient hardware solution based sub-window architecture of Haar classifiers for real-time detection of face biometrics." In 2010 IEEE International Conference on Mechatronics and Automation (ICMA). IEEE, 2010. http://dx.doi.org/10.1109/icma.2010.5589229.
Full text
6
Junglas, Marco, Amir Kazeminia, Ru¨diger Eick, and Dirk So¨ffker. "Reliability-Based Design of Future Highly Reliable Systems." In ASME 2009 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2009. http://dx.doi.org/10.1115/detc2009-86981.
Full textAbstract:
This paper focuses on mechatronic systems reliability assessment during the development process phases. Modern technical systems safety requirements are regulated by law, especially the level of safety relevant systems or components. This means it is necessary to decide at early design phase which topology or hardware suites the safety requirements of the system. Therefore the first step is to detect the system impact factors, model the system architecture, and generate a topology tree. One possibility to describe the system architecture is given by the use of the Unified Modeling Language (UML). From the system architecture descriptions MATLAB/Simulink models can be generated. Subsequently the next step is the realization of a reliability-oriented topology, which can be used to consider reliability-oriented aspects.
7
Singh, Surya P. N., and Kenneth J. Waldron. "GL-Link: A Novel Telerobotics-Based Platform Supporting Distributed Mechatronic Research Via the Internet." In ASME 2003 International Mechanical Engineering Congress and Exposition. ASMEDC, 2003. http://dx.doi.org/10.1115/imece2003-42093.
Full textAbstract:
Mechatronics and robotics research efforts of large complexity are increasingly interdisciplinary involving collaboration between software, hardware, controls, and scientific teams. Traditionally, the level of integration has either required repeated site-visits or location of the teams at a common site. As the teams become increasingly diverse and disperse, there is a need for distributed operations platform that not only facilitates smooth communications, but also allows for remote experimentation and control of a common robot or device. By separating the principal design functions, a modular communications platform was developed to support the distance learning and experimental requirements of ambitious mechatronic development projects. This separation results in a modular system that is scalable and customizable to the particular conditions governing an experiment. The platform leverages off-the-shelf hardware and software and the presence of Internet connectivity. Where possible, open-source options were used to make the platform extensible to a variety of platforms and applications. The system is modular and consists of: a video observation/conferencing module, a file-transfer module, and a robot teleoperation module. This allowed multiple teams to test the operation of a robot independently and asynchronously without corrupting the work being conducted by another team member. It also allowed for new forms of interaction and reduced the need for travel between the multiple geographically-distributed research teams. Novel features of this work include a modular multiplatform architecture and an integration of basic telerobotics principles to extend PC-based collaboration/conferencing technologies from a basic communications platform to a means for supporting multi-site (robotics) research experiments. This paper describes the design considerations and evaluations associated with the development of the Great Little Inter link (GL-Link) architecture. This platform was motivated by robotics research ongoing between Stanford and Ohio State Universities. The platform was tested over several months as part of the design of a high-speed quadruped robot. Results from this trial highlight the impact of highly sensitive audio and video inputs and show the need for robustness to bandwidth fluctuations.
8
Hannius, Olof, Dan Ring, and Johan Karlsson. "Derivation of Diagnostic Requirements for a Distributed UAV Turbofan Engine Control System." In ASME Turbo Expo 2006: Power for Land, Sea, and Air. ASMEDC, 2006. http://dx.doi.org/10.1115/gt2006-90094.
Full textAbstract:
This paper presents a method to derive the efficiency of diagnostic functions so that consistency with safety requirements is met. The method is applied to a distributed UAV engine control system, but could as well be applicable to any other mechatronic system. A control system architecture is proposed with a minimum of hardware redundancy for lowest cost and simple design. Efficient diagnostic functions (executable assertions in software) are used to detect and isolate errors. The goal is to completely recover from any transient error and reconfigure the system after a permanent error so that engine thrust remains unaffected. Given the requirement that an engine failure due to the control system is not allowed to occur more than 10 times per million hours, any permanent or transient error must be correctly handled with 99% certainty on node level and 90–95% on system level. The high error coverage figures are much driven by the assumption that a transient error occurs 1 time per 1000 hours in any control system node. The high number used for transient errors are due to the concern about Single Event Upsets (SEUs) that have become a dominating cause of errors in electronic equipment in flight applications.
9
Martin, Adrian, and M. Emami. "An Architecture for Robotic Hardware-in-the-Loop Simulation." In 2006 International Conference on Mechatronics and Automation. IEEE, 2006. http://dx.doi.org/10.1109/icma.2006.257628.
Full text
10
Wan Roh, Dong, and Jae Wook Jeon. "Hardware Architecture Design for Template Matching." In 2019 International SoC Design Conference (ISOCC). IEEE, 2019. http://dx.doi.org/10.1109/isocc47750.2019.9078515.
Full textReports on the topic "Mechatronics hardware design and architecture"
1
Modlo, Yevhenii O., Serhiy O. Semerikov, Stanislav L. Bondarevskyi, Stanislav T. Tolmachev, Oksana M. Markova, and Pavlo P. Nechypurenko. Methods of using mobile Internet devices in the formation of the general scientific component of bachelor in electromechanics competency in modeling of technical objects. [б. в.], February 2020. http://dx.doi.org/10.31812/123456789/3677.
Full textAbstract:
An analysis of the experience of professional training bachelors of electromechanics in Ukraine and abroad made it possible to determine that one of the leading trends in its modernization is the synergistic integration of various engineering branches (mechanical, electrical, electronic engineering and automation) in mechatronics for the purpose of design, manufacture, operation and maintenance electromechanical equipment. Teaching mechatronics provides for the meaningful integration of various disciplines of professional and practical training bachelors of electromechanics based on the concept of modeling and technological integration of various organizational forms and teaching methods based on the concept of mobility. Within this approach, the leading learning tools of bachelors of electromechanics are mobile Internet devices (MID) – a multimedia mobile devices that provide wireless access to information and communication Internet services for collecting, organizing, storing, processing, transmitting, presenting all kinds of messages and data. The authors reveals the main possibilities of using MID in learning to ensure equal access to education, personalized learning, instant feedback and evaluating learning outcomes, mobile learning, productive use of time spent in classrooms, creating mobile learning communities, support situated learning, development of continuous seamless learning, ensuring the gap between formal and informal learning, minimize educational disruption in conflict and disaster areas, assist learners with disabilities, improve the quality of the communication and the management of institution, and maximize the cost-efficiency. Bachelor of electromechanics competency in modeling of technical objects is a personal and vocational ability, which includes a system of knowledge, skills, experience in learning and research activities on modeling mechatronic systems and a positive value attitude towards it; bachelor of electromechanics should be ready and able to use methods and software/hardware modeling tools for processes analyzes, systems synthesis, evaluating their reliability and effectiveness for solving practical problems in professional field. The competency structure of the bachelor of electromechanics in the modeling of technical objects is reflected in three groups of competencies: general scientific, general professional and specialized professional. The implementation of the technique of using MID in learning bachelors of electromechanics in modeling of technical objects is the appropriate methodic of using, the component of which is partial methods for using MID in the formation of the general scientific component of the bachelor of electromechanics competency in modeling of technical objects, are disclosed by example academic disciplines “Higher mathematics”, “Computers and programming”, “Engineering mechanics”, “Electrical machines”. The leading tools of formation of the general scientific component of bachelor in electromechanics competency in modeling of technical objects are augmented reality mobile tools (to visualize the objects’ structure and modeling results), mobile computer mathematical systems (universal tools used at all stages of modeling learning), cloud based spreadsheets (as modeling tools) and text editors (to make the program description of model), mobile computer-aided design systems (to create and view the physical properties of models of technical objects) and mobile communication tools (to organize a joint activity in modeling).