Journal articles: 'Managed memory'

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Schneider, Scott, Jae-Seung Yeom, and Dimitrios S. Nikolopoulos. "Programming Multiprocessors with Explicitly Managed Memory Hierarchies." Computer 42, no. 12 (December 2009): 28–34. http://dx.doi.org/10.1109/mc.2009.407.

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Akram, Shoaib. "Performance Evaluation of Intel Optane Memory for Managed Workloads." ACM Transactions on Architecture and Code Optimization 18, no. 3 (June 2021): 1–26. http://dx.doi.org/10.1145/3451342.

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Intel Optane memory offers non-volatility, byte addressability, and high capacity. It suits managed workloads that prefer large main memory heaps. We investigate Optane as the main memory for managed (Java) workloads, focusing on performance scalability. As the workload (core count) increases, we note Optane’s performance relative to DRAM. A few workloads incur a slight slowdown on Optane memory, which helps conserve limited DRAM capacity. Unfortunately, other workloads scale poorly beyond a few core counts. This article investigates scaling bottlenecks for Java workloads on Optane memory, analyzing the application, runtime, and microarchitectural interactions. Poorly scaling workloads allocate objects rapidly and access objects in Optane memory frequently. These characteristics slow down the mutator and substantially slow down garbage collection (GC). At the microarchitecture level, load, store, and instruction miss penalties rise. To regain performance, we partition heaps across DRAM and Optane memory, a hybrid that scales considerably better than Optane alone. We exploit state-of-the-art GC approaches to partition heaps. Unfortunately, existing GC approaches needlessly waste DRAM capacity because they ignore runtime behavior. This article also introduces performance impact-guided memory allocation (PIMA) for hybrid memories. PIMA maximizes Optane utilization, allocating in DRAM only if it improves performance. It estimates the performance impact of allocating heaps in either memory type by sampling. We target PIMA at graph analytics workloads, offering a novel performance estimation method and detailed evaluation. PIMA identifies workload phases that benefit from DRAM with high (94.33%) accuracy, incurring only a 2% sampling overhead. PIMA operates stand-alone or combines with prior approaches to offer new performance versus DRAM capacity trade-offs. This work opens up Optane memory to a real-life role as the main memory for Java workloads.

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Meyer, Meghan L., and Eleanor Collier. "Theory of minds: managing mental state inferences in working memory is associated with the dorsomedial subsystem of the default network and social integration." Social Cognitive and Affective Neuroscience 15, no. 1 (January 2020): 63–73. http://dx.doi.org/10.1093/scan/nsaa022.

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Abstract We often interact with multiple people at a time and consider their various points of view to facilitate smooth social interaction. Yet, how our brains track multiple mental states at once, and whether skill in this domain links to social integration, remains underspecified. To fill this gap, we developed a novel social working memory paradigm in which participants manage two- or four-people’s mental states in working memory, as well as control trials in which they alphabetize two- or four-people’s names in working memory. In Study 1, we found that the dorsomedial subsystem of the default network shows relative increases in activity with more mental states managed in working memory. In contrast, this subsystem shows relative decreases in activity with more non-mental state information (the number of names alphabetized) managed in working memory. In Study 2, only individual differences in managing mental states in working memory, specifically on trials that posed the greatest mental state load to working memory, correlated with social integration. Collectively, these findings add further support to the hypothesis that social working memory relies on partially distinct brain systems and may be a key ingredient to success in a social world.

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Jantz, Michael R., Forrest J. Robinson, Prasad A. Kulkarni, and Kshitij A. Doshi. "Cross-layer memory management for managed language applications." ACM SIGPLAN Notices 50, no. 10 (December 18, 2015): 488–504. http://dx.doi.org/10.1145/2858965.2814322.

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O’Neill, Eoghan, John McGlone, Peter Kilpatrick, and Dimitrios Nikolopoulos. "Managed acceleration for In-Memory database analytic workloads." International Journal of Parallel, Emergent and Distributed Systems 32, no. 4 (May 6, 2016): 406–27. http://dx.doi.org/10.1080/17445760.2016.1170832.

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Bok, Kyoungsoo, Seunghun Yoo, Dojin Choi, Jongtae Lim, and Jaesoo Yoo. "In-Memory Caching for Enhancing Subgraph Accessibility." Applied Sciences 10, no. 16 (August 9, 2020): 5507. http://dx.doi.org/10.3390/app10165507.

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Graphs have been utilized in various fields because of the development of social media and mobile devices. Various studies have also been conducted on caching techniques to reduce input and output costs when processing a large amount of graph data. In this paper, we propose a two-level caching scheme that considers the past usage pattern of subgraphs and graph connectivity, which are features of graph topology. The proposed caching is divided into a used cache and a prefetched cache to manage previously used subgraphs and subgraphs that will be used in the future. When the memory is full, a strategy that replaces a subgraph inside the memory with a new subgraph is needed. Subgraphs in the used cache are managed by a time-to-live (TTL) value, and subgraphs with a low TTL value are targeted for replacement. Subgraphs in the prefetched cache are managed by the queue structure. Thus, first-in subgraphs are targeted for replacement as a priority. When a cache hit occurs in the prefetched cache, the subgraphs are migrated and managed in the used cache. As a result of the performance evaluation, the proposed scheme takes into account subgraph usage patterns and graph connectivity, thus improving cache hit rates and data access speeds compared to conventional techniques. The proposed scheme can quickly process and analyze large graph queries in a computing environment with small memory. The proposed scheme can be used to speed up in-memory-based processing in applications where relationships between objects are complex, such as the Internet of Things and social networks.

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Wang, Li, JingLing Xue, and XueJun Yang. "Acyclic orientation graph coloring for software-managed memory allocation." Science China Information Sciences 57, no. 9 (June 11, 2014): 1–18. http://dx.doi.org/10.1007/s11432-014-5131-7.

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Krauter, Nicolas, Patrick Raaf, Peter Braam, Reza Salkhordeh, Sebastian Erdweg, and André Brinkmann. "Persistent software transactional memory in Haskell." Proceedings of the ACM on Programming Languages 5, ICFP (August 22, 2021): 1–29. http://dx.doi.org/10.1145/3473568.

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Emerging persistent memory in commodity hardware allows byte-granular accesses to persistent state at memory speeds. However, to prevent inconsistent state in persistent memory due to unexpected system failures, different write-semantics are required compared to volatile memory. Transaction-based library solutions for persistent memory facilitate the atomic modification of persistent data in languages where memory is explicitly managed by the programmer, such as C/C++. For languages that provide extended capabilities like automatic memory management, a more native integration into the language is needed to maintain the high level of memory abstraction. It is shown in this paper how persistent software transactional memory (PSTM) can be tightly integrated into the runtime system of Haskell to atomically manage values of persistent transactional data types. PSTM has a clear interface and semantics extending that of software transactional memory (STM). Its integration with the language’s memory management retains features like garbage collection and allocation strategies, and is fully compatible with Haskell's lazy execution model. Our PSTM implementation demonstrates competitive performance with low level libraries and trivial portability of existing STM libraries to PSTM. The implementation allows further interesting use cases, such as persistent memoization and persistent Haskell expressions.

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Jost, Tiago Trevisan, Gabriel Luca Nazar, and Luigi Carro. "SoMMA: A software-managed memory architecture for multi-issue processors." Microprocessors and Microsystems 77 (September 2020): 103139. http://dx.doi.org/10.1016/j.micpro.2020.103139.

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Nguyen, Khanh, Kai Wang, Yingyi Bu, Lu Fang, and Guoqing Xu. "Understanding and Combating Memory Bloat in Managed Data-Intensive Systems." ACM Transactions on Software Engineering and Methodology 26, no. 4 (February 23, 2018): 1–41. http://dx.doi.org/10.1145/3162626.

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Wynn, Thomas, and Frederick Coolidge. "The role of working memory in the evolution of managed foraging." Before Farming 2003, no. 2 (January 2003): 1–16. http://dx.doi.org/10.3828/bfarm.2003.2.1.

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Lu, Jing, Ke Bai, and Aviral Shrivastava. "Efficient Code Assignment Techniques for Local Memory on Software Managed Multicores." ACM Transactions on Embedded Computing Systems 14, no. 4 (December 8, 2015): 1–24. http://dx.doi.org/10.1145/2738039.

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Smith, Rebecca, and Scott Rixner. "Leveraging Managed Runtime Systems to Build, Analyze, and Optimize Memory Graphs." ACM SIGPLAN Notices 51, no. 7 (October 11, 2016): 131–43. http://dx.doi.org/10.1145/3007611.2892253.

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Voelker, Geoffrey M., Eric J. Anderson, Tracy Kimbrel, Michael J. Feeley, Jeffrey S. Chase, Anna R. Karlin, and Henry M. Levy. "Implementing cooperative prefetching and caching in a globally-managed memory system." ACM SIGMETRICS Performance Evaluation Review 26, no. 1 (June 1998): 33–43. http://dx.doi.org/10.1145/277858.277869.

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Kim, Seonggun, Hwansoo Han, and Kwang-Moo Choe. "Region-based parallelization of irregular reductions on explicitly managed memory hierarchies." Journal of Supercomputing 56, no. 1 (October 10, 2009): 25–55. http://dx.doi.org/10.1007/s11227-009-0340-3.

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Kudela-Świątek, Wiktoria. "Wspólnoty pamięci Hołodomoru w USA i Kanadzie w latach 50.-80. XX wieku." Politeja 18, no. 1(70) (February 1, 2021): 57–72. http://dx.doi.org/10.12797/politeja.18.2021.70.05.

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Communities of Memory of the Holodomor in the USA and Canada in the 1950s-80s The main goal of this article is to show how the Ukrainian community in North America, thanks to cultivating the memory of a marginal event from the point of view of American history, managed to appear in the social life of the USA and Canada. Here I use the concept of ‘community of memory’ to emphasize those Ukrainian communities in the USA and Canada that are of utmost importance in the commemoration of Holodomor. They also managed to retain this event’s memory in many other competing memories, dabbling in the memory of their identity as American Ukrainian. Therefore, in the following sections of the article, I will attempt to answer why it was the diaspora that undertook a tremendous effort to commemorate Holodomor’s victims and the course of that process for years. Finally, I employ critical analysis of media discourses. Moreover, I will consider the Holodomor generation’s role in cultivating that memory and emergence of the ‘communities of memory’.

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SIVARAMAKRISHNAN, K. C., LUKASZ ZIAREK, and SURESH JAGANNATHAN. "MultiMLton: A multicore-aware runtime for standard ML." Journal of Functional Programming 24, no. 6 (June 18, 2014): 613–74. http://dx.doi.org/10.1017/s0956796814000161.

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AbstractMultiMLton is an extension of the MLton compiler and runtime system that targets scalable, multicore architectures. It provides specific support for ACML, a derivative of Concurrent ML that allows for the construction of composable asynchronous events. To effectively manage asynchrony, we require the runtime to efficiently handle potentially large numbers of lightweight, short-lived threads, many of which are created specifically to deal with the implicit concurrency introduced by asynchronous events. Scalability demands also dictate that the runtime minimize global coordination. MultiMLton therefore implements a split-heap memory manager that allows mutators and collectors running on different cores to operate mostly independently. More significantly, MultiMLton exploits the premise that there is a surfeit of available concurrency in ACML programs to realize a new collector design that completely eliminates the need for read barriers, a source of significant overhead in other managed runtimes. These two symbiotic features - a thread design specifically tailored to support asynchronous communication, and a memory manager that exploits lightweight concurrency to greatly reduce barrier overheads - are MultiMLton's key novelties. In this article, we describe the rationale, design, and implementation of these features, and provide experimental results over a range of parallel benchmarks and different multicore architectures including an 864 core Azul Vega 3, and a 48 core non-coherent Intel SCC (Single-Cloud Computer), that justify our design decisions.

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Tabbassum, Kavita, Shah Nawaz Talpur, Sanam Narejo, and Noor-u.-Zaman Leghari. "Management of Scratchpad Memory Using Programming Techniques." Mehran University Research Journal of Engineering and Technology 38, no. 2 (April 1, 2019): 305–12. http://dx.doi.org/10.22581/muet1982.1902.05.

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Consuming the conventional approaches, processors are incapable to achieve effective energy reduction. In upcoming processors on-chip memory system will be the major restriction. On-chip memories are managed by the software SMCs (Software Managed Chips), and are work with caches (on-chip), where inside a block of caches software can explicitly read as well as write specific or complete memory references, or work separately just like scratchpad memory. In embedded systems Scratch memory is generally used as an addition to caches or as a substitute of cache, but due to their comprehensive ease of programmability cache containing architectures are still to be chosen in numerous applications. In contrast to conventional caches in embedded schemes because of their better energy and silicon range effectiveness SPM (Scratch-Pad Memories) are being progressively used. Power consumption of ported applications can significantly be lower as well as portability of scratchpad architectures will be advanced with the language agnostic software management method which is suggested in this manuscript. To enhance the memory configuration and optimization on relevant architectures based on SPM, the variety of current methods are reviewed for finding the chances of optimizations and usage of new methods as well as their applicability to numerous schemes of memory management are also discussed in this paper.

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Prasad, Vivek Kumar, and Madhuri D. Bhavsar. "SLAMMP Framework for Cloud Resource Management and Its Impact on Healthcare Computational Techniques." International Journal of E-Health and Medical Communications 12, no. 2 (July 2021): 1–31. http://dx.doi.org/10.4018/ijehmc.2021030101.

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Technology such as cloud computing(CC) is constantly evolving and being adopted by the industries to manage their data and tasks. CC provides the resources for managing the tasks of the cloud users. The acceptance of the CC in healthcare industries is proven to be more cost-effective and convenient. CC manager has to manage the resources to provide services to the end-users of the healthcare sector. The SLAMMP framework discussed here shows how the resources are managed by using the concept of reinforcement learning (RL) and LSTM (long short-term memory) for monitoring and prediction of the cloud resources for healthcare organizations. The task(s) pattern and anti-pattern scenarios have been observed using HMM (hidden Markov model). These patterns will tune the SLA parameters (service level agreement) using blockchain-based smart contracts (SC). The result discussed here indicates that the variations in the cloud resource demand will be handled carefully using the SLAMMP framework. From the result obtained, it is identified that SLAMMP performs well with the parameter used here.

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Schneider, Scott, Jae-Seung Yeom, Benjamin Rose, John C. Linford, Adrian Sandu, and Dimitrios S. Nikolopoulos. "A comparison of programming models for multiprocessors with explicitly managed memory hierarchies." ACM SIGPLAN Notices 44, no. 4 (February 14, 2009): 131–40. http://dx.doi.org/10.1145/1594835.1504197.

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Yan, Pei Xiang, Jiang Jiang, Xian Ju Yang, and Min Xuan Zhang. "A Probabilistic Cache Sharing Mechanism for Chip Multiprocessors." Applied Mechanics and Materials 135-136 (October 2011): 119–25. http://dx.doi.org/10.4028/www.scientific.net/amm.135-136.119.

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Capacity sharing is efficient for private L2 caches to utilize cache resources in chip multiprocessors. We propose a probabilistic sharing mechanism using reuse replacement strategy. This mechanism adopts decoupled tag and data arrays, and partitions the data arrays into private and shared regions. Probability is introduced to control the capability of each core to compete shared data resources. We assign high probabilities to cores with stress memory demands and dynamically adjust these probabilities corresponding to the monitored run-time memory demands. Simulation results of PARSEC benchmarks show that our mechanism exceeds conventional LRU managed private cache. Compared with reuse replacement managed private cache without sharing among cores, our mechanism achieves an average L2 miss rate reduction of 8.70%.

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Zulfa, Mulki Indana, Ari Fadli, and Arief Wisnu Wardhana. "Application caching strategy based on in-memory using Redis server to accelerate relational data access." Jurnal Teknologi dan Sistem Komputer 8, no. 2 (March 20, 2020): 157–63. http://dx.doi.org/10.14710/jtsiskom.8.2.2020.157-163.

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Utilization of an in-memory database as a cache can overcome relational database latency problems in a web application, especially when using a lot of join queries. This study aims to model the academic relational data into Redis compatible data and analyze the performance of join queries usage to accelerate access to relational data managed by RDBMS. This study used academic data to calculate student GPA that is modeled in the RDBMS and Redis in-memory database (IMDB). The use of Redis as an in-memory database can significantly increase Mysql database system performance up to 3.3 times faster to display student data using join query and to shorten the time needed to display GPA data to 52 microseconds from 61 milliseconds.

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Li, Yi Bing, Shuang Wang, and Fang Ye. "Crash Recovery for Embedded Main Memory Database." Applied Mechanics and Materials 195-196 (August 2012): 1122–24. http://dx.doi.org/10.4028/www.scientific.net/amm.195-196.1122.

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In the last years, the deployment of embedded real-time communication systems has increased dramatically. At the same time, the amount of data that needs to be managed by embedded real-time main memory databases is increasing, thus requiring an efficient data management. However, system crash will cause data loss in main memory, which will seriously affect the normal operation of the entire communication system. This paper introduces an algorithm of system crash recovery applied in main memory database of embedded real-time communication system. This paper expatiates the software architecture of SDR base station, the cause of crash occurring, and proposes the flash recovery algorithm using for system recovery. A main memory database using this algorithm has been applied in a real communication systemmultimode SDR base station communication system.

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Aharony, Michal. "Fredy Hirsch: Changing Perspectives on his Memory." Holocaust and Genocide Studies 35, no. 1 (March 24, 2021): 1–24. http://dx.doi.org/10.1093/hgs/dcab015.

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Abstract At the Theresienstadt family camp in Auschwitz thousands of Jews were kept alive in “favorable” living conditions, only to be gassed after six months. Few scholars have examined one of the most influential figures there, Fredy Hirsch, a gay German-Jewish refugee to Czechoslovakia who initiated and managed the “children’s block.” Hundreds under his care received better food and were spared the brutality prevailing elsewhere in Auschwitz, brightening their final months. How he sacrificed his life for the children offers a particular window into the annihilation of Czech Jewry. The following analyzes changing images of Hirsch in literature and commemoration, the uncertainty surrounding his death, and the meaning survivors ascribed to Hirsch’s homosexuality.

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Robinson, Forrest J., Michael R. Jantz, and Prasad A. Kulkarni. "Code cache management in managed language VMs to reduce memory consumption for embedded systems." ACM SIGPLAN Notices 51, no. 5 (August 2016): 11–20. http://dx.doi.org/10.1145/2980930.2907958.

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Hemdani, Chabane, Rachida Aoudjit, Mustapha Lalam, and Khaled Slimani. "Software and Hardware for managing Scratch Pad Memory." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 2 (May 28, 2018): 69. http://dx.doi.org/10.11591/ijres.v6.i2.pp69-81.

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<p>This paper proposes a low-cost architecture to improve the management SPM (Scratch Pad Memory) in dynamic and multitasking modes. In this context, our management strategy SPM based on Programmable Automaton implemented in Xilinx Vertex-5 FPGA is entirely different from prior research works. SPM is generally managed by software (by a strong programming logic or by compilation). But our Programmable Automaton facilitates access to SPM in order to move code or data and liberates space in SPM. After this step, software takes over content management of SPM (what part of code or data should be placed in SPM, locates spaces of Heap and Stack). So the performance of the programs is actually improved thanks to minimization of the access latency at the DRAM (Dynamic Random Access Memory or Main Memory).</p>

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Knight, Matthew James, and Michael Tlauka. "Map learning and working memory: Multimodal learning strategies." Quarterly Journal of Experimental Psychology 71, no. 6 (January 1, 2018): 1405–18. http://dx.doi.org/10.1080/17470218.2017.1326954.

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The current research investigated whether learning spatial information from a map involves different modalities, which are managed by discrete components in working memory. In four experiments, participants studied a map either while performing a simultaneous interference task (high cognitive load) or without interference (low cognitive load). The modality of interference varied between experiments. Experiment 1 used a tapping task (visuospatial), Experiment 2 a backward counting task (verbal), Experiment 3 an articulatory suppression task (verbal) and Experiment 4 an n-back task (central executive). Spatial recall was assessed in two tests: directional judgements and map drawing. Cognitive load was found to affect spatial recall detrimentally regardless of interference modality. The findings suggest that when learning maps, people use a multimodal learning strategy, utilising resources from all components of working memory.

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Prasetyo, Inung Bagus, Mahar Faiqurahman, and Zamah Sari. "Rancang Bangun Control dan Monitoring Sensor Node WSN Menggunakan Protokol Message Queue Telemetry Transport (MQTT)." Jurnal Repositor 2, no. 1 (January 4, 2020): 15. http://dx.doi.org/10.22219/repositor.v2i1.476.

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The WSN network is increasingly gaining attention because of the potential for new and attractive solutions in the field of industrial automation, asset processing, environmental preparation and others. But there are some problems in building the WSN network. Sensor nodes must manage small, cost-effective, low-resource, node sensors must be managed properly with WSN networks Managing WSN networks, can be done by controlling sensor nodes such as giving commands to data transmission activities and monitoring to determine the condition of sensor nodes. The MQTT protocol with the type of publishing / subscription communication is designed with characteristics similar to the characteristics of the WSN network, which are simple, lightweight, energy efficient and easy to implement.In this study, a server will be implemented that can control and monitor the sensors of the WSN network node using the MQTT protocol. Then RTT parameters are used, Qo parameters include Delay, Jitter, Throughput, Packet Loss and sensor node memory condition parameters when using the MQTT protocol. The RTT and QoS scenarios use variations in data size of 16,32,48,64,80 and 96 bytes. Monitoring memory nodes, performing for 1 minute with a total of 30 data transmissions. The RTT parameter testing results are quite stable. QoS testing is very good with stable delay, jitter, increasing throughput, and 0% of data lost when packet loss testing. The Test Memory node sensor, shows erratic results.

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Motl, Robert W., Eduard Gappmaier, Kathryn Nelson, and Ralph H. B. Benedict. "Physical Activity and Cognitive Function in Multiple Sclerosis." Journal of Sport and Exercise Psychology 33, no. 5 (October 2011): 734–41. http://dx.doi.org/10.1123/jsep.33.5.734.

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Cognitive impairment is prevalent, disabling, and poorly managed in persons with multiple sclerosis (MS). This cross-sectional study examined the associations among physical activity, cognitive processing speed, and learning and memory in 33 persons with MS who underwent neuropsychological assessments and wore a physical activity monitor for 7 days. Cognitive impairment was greatest in cognitive processing speed. Physical activity was significantly correlated with cognitive processing speed (pr = .35), but not learning and memory (pr = .20), after controlling for sex, age, and education. Researchers should examine exercise training and physical activity effects on cognitive performance, particularly processing speed, in MS.

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BOURGOIN, MATHIAS, EMMANUEL CHAILLOUX, and JEAN-LUC LAMOTTE. "SPOC: GPGPU PROGRAMMING THROUGH STREAM PROCESSING WITH OCAML." Parallel Processing Letters 22, no. 02 (May 16, 2012): 1240007. http://dx.doi.org/10.1142/s0129626412400075.

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General purpose computing on graphics processing units (GPGPU) consists of using GPUs to handle computations commonly handled by CPUs. GPGPU programming implies developing specific programs to run on GPUs managed by a host program running on the CPU. To achieve high performance implies to explicitly organize memory transfers between devices. Besides, different incompatible frameworks exist making productivity and portability difficult to achieve. In this paper, we describe SPOC, an OCaml library, defining specific data sets in order to automatically manage transfers between GPU and CPU. SPOC also offers a runtime library looking for multiple frameworks and making them usable transparently. We also describe the link between SPOC and the OCaml garbage collector to optimize transfers dynamically. SPOC benchmarks show that SPOC can offer great performance while simplifying GPGPU programming

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Burakov, Dmitry. "Retesting the institutional memory hypothesis: An experimental study." Panoeconomicus 65, no. 4 (2018): 441–58. http://dx.doi.org/10.2298/pan160105003b.

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In this article, we set ourselves a task to test institutional memory hypothesis as a core of endogenous credit cycles. According to this hypothesis, risks taken by creditors depend largely on availability heuristic and experience of loan officers. To assess validity of this hypothesis we construct and estimate a simple VAR model. The data for this model is acquired from results of an experimental study (lasted for 70 rounds), the purpose of which is to identify behavioral patterns of participants while meeting demand for credit, specifics of subjectively weighted assessment of credit risk, based on shock approach. The results of the study allow confirming institutional memory hypothesis. After initial shock of bad debts, number of periods to recover willingness to accept risk has increased by 39%, which supports the hypothesis of availability heuristic?s influence. However, with improvement of loan portfolio?s quality, willingness to take risk is restoring. In addition, we managed to confirm existence of risk?s underestimation and overestimation periods in an experimental manner.

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Kovaleva, Mariya A., Bonnie M. Jennings, Carolyn Clevenger, Mi-Kyung Song, Patricia C. Griffiths, and Ken Hepburn. "DEMENTIA FAMILY CAREGIVERS’ EXPERIENCES WITH A NURSE-LED MEMORY CARE CLINIC." Innovation in Aging 3, Supplement_1 (November 2019): S109—S110. http://dx.doi.org/10.1093/geroni/igz038.408.

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Abstract The Integrated Memory Care Clinic (IMCC) at Emory Healthcare is a patient-centered medical home led by advanced practice registered nurses (APRNs) who provide both dementia care and primary care. We explored the experiences of informal caregivers of persons living with dementia at the IMCC during their first year post-enrollment. Twelve caregivers completed semi-structured telephone interviews that lasted 29 minutes on average. The data were analyzed via directed content analysis guided by attention only to caregivers’ accounts of their experience at the IMCC. Caregivers’ experiences clustered around two major considerations: the strengths of the IMCC, and ways to enhance the IMCC. Overall, caregivers’ viewed the IMCC as their wished-for care model. Caregivers felt a sense of belonging to the IMCC team, as they understood that the IMCC personnel incorporate caregivers’ input to deliver care. Participants valued APRNs’ competence in dementia care and having direct telephone access to an on-duty APRN around the clock. Caregivers appreciated the care organization at the IMCC with adequate time dedicated for in-person visits. Areas for the IMCC improvement included clarifying the IMCC scope of practice, explaining dementia progression, involving physicians, and providing more medical and non-medical resources at the IMCC. Caregivers’ willingness to have more resources provided by the IMCC emphasizes how many unmet needs caregivers and their persons have. Clarification of the clinics’ scope of practice – what can be done to manage dementia, its symptoms, and comorbidities – highlighted the need to educate caregivers about ways in which dementia, albeit incurable, can be managed.

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Price, Richard. "Rainforest villages, eighteenth-century history." Memory Studies 13, no. 5 (September 17, 2020): 792–804. http://dx.doi.org/10.1177/1750698020943010.

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Based on long term ethnographic work with the Saamaka, and with the benefit of hindsight, this paper unpacks the specific ways in which the descendants of these Suriname Maroons have constructed and transmitted the historical knowledge of their 18th-century ancestors, who escaped slave plantations and confronted the colonial powers from their new settlements in the depth of the forest. In the process, they created an original memory of these historical events— First-Time or Fesiten knowledge—and managed to keep it alive. The article explores the specific ontology, frames and idioms of this historical knowledge, as well as its ideological role, the (dis)connections to hegemonic colonial memory devices, its evolution in time, the ways of transmission, and the memory specialists that have kept and circulated it.

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O'Callaghan, Patrick. "Collective memory in law and policy: the problem of the sovereign debt crisis." Legal Studies 32, no. 4 (December 2012): 642–60. http://dx.doi.org/10.1111/j.1748-121x.2012.00251.x.

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The idea of ‘collective memory’ features prominently in several disciplines but rarely in legal scholarship. Drawing on the work of Henri Bergson, Maurice Halbwachs and GWF Hegel, this paper seeks to present an account of collective memory that is relevant to discourse on law and policy. The paper uses the example of the policy response to the European sovereign debt crisis as a means of illustrating how collective memory of events in the distant past can shape individual behaviour and thinking. It argues that the current policy response can be explained, at least in part, by the influence on policy makers of the standard historical narrative of the Great Inflation of Weimar Germany. When, however, collective memory takes the form of Bergsonian ‘habit memory’, it can inhibit our efforts to resolve hard cases and the German government's opposition to the European Central Bank acting as a lender of last resort in the government bond markets neatly illustrates this point. If the debt crisis is to be managed effectively, policy makers must draw on Bergsonian ‘pure memory’ to explore the bounds of political and economic possibility.

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Wilson, Michael David, Luke Strickland, Simon Farrell, Troy A. W. Visser, and Shayne Loft. "Prospective Memory Performance in Simulated Air Traffic Control." Human Factors: The Journal of the Human Factors and Ergonomics Society 62, no. 8 (September 20, 2019): 1249–64. http://dx.doi.org/10.1177/0018720819875888.

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Objective To examine the effects of interruptions and retention interval on prospective memory for deferred tasks in simulated air traffic control. Background In many safety-critical environments, operators need to remember to perform a deferred task, which requires prospective memory. Laboratory experiments suggest that extended prospective memory retention intervals, and interruptions in those retention intervals, could impair prospective memory performance. Method Participants managed a simulated air traffic control sector. Participants were sometimes instructed to perform a deferred handoff task, requiring them to deviate from a routine procedure. We manipulated whether an interruption occurred during the prospective memory retention interval or not, the length of the retention interval (37–117 s), and the temporal proximity of the interruption to deferred task encoding and execution. We also measured performance on ongoing tasks. Results Increasing retention intervals (37–117 s) decreased the probability of remembering to perform the deferred task. Costs to ongoing conflict detection accuracy and routine handoff speed were observed when a prospective memory intention had to be maintained. Interruptions did not affect individuals’ speed or accuracy on the deferred task. Conclusion Longer retention intervals increase risk of prospective memory error and of ongoing task performance being impaired by cognitive load; however, prospective memory can be robust to effects of interruptions when the task environment provides cuing and offloading. Application To support operators in performing complex and dynamic tasks, prospective memory demands should be reduced, and the retention interval of deferred tasks should be kept as short as possible.

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HAN, Miseon, Yeoul NA, Dongha JUNG, Hokyoon LEE, Seon WOOK KIM, and Youngsun HAN. "Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB." IEICE Transactions on Electronics E101.C, no. 3 (2018): 170–82. http://dx.doi.org/10.1587/transele.e101.c.170.

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Kim, Hyung Tae, and Kyung Chan Jin. "Multi-Application and Large Shared Memory in a Mechatronic System for Massive Computation." Applied Mechanics and Materials 307 (February 2013): 18–22. http://dx.doi.org/10.4028/www.scientific.net/amm.307.18.

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Recent mechatronic systems, such as inspection machines or 3D imaging apparatuses, acquire and compute massive data for final results. A host in the mechatronic system is commonly composed of multiple hardware devices which interface with high-speed external signals. The host and the devices usually have large memory, so efficient data management is important due to data storage and transfer. In our software structure, each device is managed by respective application and large shared memory (LSM) is allocated in the host for the massive data. The shared memory is accessible from the device applications. Actions of the mechatronic system are driven by combining and broadcasting events through and inter-process communication (IPC). The model with LSM and IPC was applied to a 3D RF imaging system. We expect the proposed model can also be applied to machine vision with big image and engineering simulation with hardware accelerators.

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Mareeva, Elena, and Anna Vorobyova. "Cultural memory and paradigms in the study of the past: philosophy, history, cultural studies." SHS Web of Conferences 72 (2019): 03016. http://dx.doi.org/10.1051/shsconf/20197203016.

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The study deals with the fundamental differences in understanding the past in the philosophy of history, in classical historical science, as well as in memory studies. The authors represent the features of the formation of a non-classical methodological paradigm in the interpretation of history by A. Warburg, in the German “historical school”, in the neo-Kantians of the Baden school and in the Annals school. The non-classical methodology in the study of the past is presented in the reversion from conscious personal choice to the mechanisms of the unconscious rallying of the collective in the concepts of cultural memory by M. Halbwachs and J. Assmann. The peculiarity of “mentality”, “identity” and “cultural memory” as concepts of modern non-classical discourse is revealed. It is concluded that the construction of mythological images of the past is a novation of the era of “managed democracy”, which carries elements of authoritarianism. The past, as demonstrated by memory studies, has once again become a myth that the media make good use of.

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Gebhardt, Rodolfo. "SynchroMed II Intrathecal Pump Memory Errors Due to Repeated Magnetic Resonance Imaging." Pain Physician 6;15, no. 6;12 (December 14, 2012): 475–77. http://dx.doi.org/10.36076/ppj.2012/15/475.

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Cancer patients with severe refractory pain are often managed with implantable drug delivery systems (IDDS). The only drugs with US Food and Drug Administration approval for intrathecal use are morphine, ziconotide, and baclofen. Other drugs used and mixed include, hydromorphone, bupivacaine, sufentanil, and fentanyl. These patients often undergo magnetic resonance imaging (MRI) for disease-related monitoring and diagnoses. Although uncommon, IDDS can fail to resume normal functioning after MRI, potentially causing complications. The magnetic field of an MRI will temporarily stop the rotor of the pump motor and suspend drug delivery for the duration of the MRI exposure. The pump should resume normal operation when removed from the MRI magnetic field, but there is a potential for a delay in the return of proper drug infusion and a delay in the logging of motor stall events after an MRI in the SynchroMed II pumps. A 57-yearold man who underwent multiple MRIs with an implanted IDDS experienced 2 separate memory failures leading to multiple complications. After the first pump malfunction, the patient developed withdrawal symptoms and was treated in the emergency department. The first time, a memory reset resolved the problem. The second time, 29 months later, the patient was admitted to the hospital to manage withdrawal symptoms and the pump had to be exchanged with a new device. Post-MRI pump interrogation should be performed on all patients with IDDS to ensure proper functioning of the pump. Special attention should be paid to patients receiving baclofen, as acute withdrawal can be very serious, even deadly. Key words: Cancer pain, MRI, IDDS, SynchroMed II, baclofen, withdrawal, stall.

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Seiler, Larry, Daqi Lin, and Cem Yuksel. "Compacted CPU/GPU Data Compression via Modified Virtual Address Translation." Proceedings of the ACM on Computer Graphics and Interactive Techniques 3, no. 2 (August 26, 2020): 1–18. http://dx.doi.org/10.1145/3406177.

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We propose a method to reduce the footprint of compressed data by using modified virtual address translation to permit random access to the data. This extends our prior work on using page translation to perform automatic decompression and deswizzling upon accesses to fixed rate lossy or lossless compressed data. Our compaction method allows a virtual address space the size of the uncompressed data to be used to efficiently access variable-size blocks of compressed data. Compression and decompression take place between the first and second level caches, which allows fast access to uncompressed data in the first level cache and provides data compaction at all other levels of the memory hierarchy. This improves performance and reduces power relative to compressed but uncompacted data. An important property of our method is that compression, decompression, and reallocation are automatically managed by the new hardware without operating system intervention and without storing compression data in the page tables. As a result, although some changes are required in the page manager, it does not need to know the specific compression algorithm and can use a single memory allocation unit size. We tested our method with two sample CPU algorithms. When performing depth buffer occlusion tests, our method reduces the memory footprint by 3.1x. When rendering into textures, our method reduces the footprint by 1.69x before rendering and 1.63x after. In both cases, the power and cycle time are better than for uncompacted compressed data, and significantly better than for accessing uncompressed data.

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Inggawati, V. Ratna, and Bruno Hami. "Knowledge Management Sebagai Anteceden Kinerja UMKM." BIP's JURNAL BISNIS PERSPEKTIF 9, no. 2 (July 31, 2017): 148–56. http://dx.doi.org/10.37477/bip.v9i2.47.

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MSMEs is a form of business classified as small to medium, from the size of the worker, the total value of net assets, the level of sales and investment is not large. Most MSMEs are owned and managed by individuals, so the most common problem is not being able to maintain performance continuity. One reason is that the owners and managers of MSMEs do not understand the importance of Knowledge Management. Knowledge and expertise are only stored as the thought of its predecessors in the form of tacit knowledge. It should be realized in the form of explicit knowledge. If that does not happen, the performance of MSMEs will be decreased, because the business depends on the memory or habit that occurred. If one day the predecessor retires or dies, then the business falls and eventually goes bankrupt.

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Shukurova Nigina Oripovna and Avezova Nigora Safarovna. "INTERPRETATION OF MYTH AND MYTHOLOGICAL IMAGES IN ENGLISH AND UZBEK LITERATURE." Middle European Scientific Bulletin 6 (November 12, 2020): 54–56. http://dx.doi.org/10.47494/mesb.2020.6.114.

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It is well known from the past that during their centuries-long history, the Turkic peoples have managed to create a multi-layered cultural heritage. One of them is the mythology of the Uzbek and English peoples, which is the product of primitive thinking. Mythology is one of the first examples of artistic thinking of our ancestors. It is the immortal memory of nations, the encyclopedia of knowledge, and the inexhaustible spiritual wealth.

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Rajevic, Manuela Badilla. "THE CHILEAN STUDENT MOVEMENT: CHALLENGING PUBLIC MEMORIES OF PINOCHET'S DICTATORSHIP*." Mobilization: An International Quarterly 24, no. 4 (December 1, 2019): 493–510. http://dx.doi.org/10.17813/1086-671x-24-4-493.

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This article illustrates the connection between the rise of social movements and the profound transformations in the ways post-conflict societies symbolize their difficult past. It examines how the 2011 Chilean student movement developed an alternative memory about Chile's Pinochet regime. I show how the movement claimed fundamental changes within the educational and political systems, framing its demands as a critical response to the socioeconomic neoliberal transformations set in motion by the Pinochet military regime. Through an empirical analysis of the 2011 student movement that combines 60 in-depth interviews with young activists with archival research, this article demonstrates how an alternative version of the dictatorial past was closely linked to the movement's goals and affected internal dynamics of belonging. The results indicate that participants managed to go beyond traumatic narratives concerning human rights crimes that had been dominant in the Chilean public memory about the dictatorship. Therefore, they presented a change that constituted a major challenge to the future of the politics of memory in Chile.

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Peng, Philip W. H. "Intracranial Hypotension with Severe Neurological Symptoms Resolved by Epidural Blood Patch." Canadian Journal of Neurological Sciences / Journal Canadien des Sciences Neurologiques 31, no. 4 (November 2004): 569–71. http://dx.doi.org/10.1017/s0317167100003838.

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Background:A patient with a constellation of severe neurological symptoms caused by spontaneous intracranial hypotension, which was successfully managed by epidural blood patch, was described.Case history:A 50-year-old woman presented to the neurological service with a two-month history of orthostatic headache. Associated clinical features included sensorineural deafness, ataxia and short-term memory loss. Magnetic resonance imaging showed downward displacement of brain structures, bilateral subdural collections and the postgadolinium images demonstrated diffuse dural enhancement suggestive of the diagnosis of spontaneous intracranial hypotension.Results:Following a lumbar epidural blood patch, all symptoms improved significantly and her headache resolved.Conclusion:The principal presentation of spontaneous intracranial hypotension is orthostatic headache. The patient described presented a combination of various neurological symptoms, ataxia, memory loss and deafness, which all responded well to epidural blood patch.

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KaYan, KaYan, Henndy Ginting, and Cakrangadinata Cakrangadinata. "It is Fear, Not Disgust, That Enhances Memory: Experimental Study on Students in Bandung." ANIMA Indonesian Psychological Journal 31, no. 2 (January 25, 2016): 77–83. http://dx.doi.org/10.24123/aipj.v31i2.566.

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A number of research findings have found the impact of emotion on memory. Some researchers stated that disgust has more impact on memory, however according to the current study the effect of fear cannot be ignored. Both disgust and fear are examples of negative emotion that may have a significant influence on behavior, such as in the attempt of creating a healthy lifestyle. The current study involved an experiment where participants were asked to memorize and recall four randomly displayed picture categories that elicit emotions of disgust, fear, joy, and neutral emotion. They also filled out a DS-R (Disgust Scale-Revised) questionnaire and a supporting questionnaire about healthy lifestyle. Analysis of the results showed that disgust did not show an effect on memory, but fear instead did. This is related to the fact that most participants showed a low degree of disgust, and so it was not considered a significant emotion that affected memory compared to fear. In addition, physiologically fear and disgust are managed by different parts of the brain and thus it was assumed that they will have a different impact on memory. The findings implied that, in campaigning for a healthier lifestyle, fear emotion need to be instilled in people.

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Noguchi, Ayako, Koji Hosokawa, Fumimasa Amaya, and Isao Yokota. "Factors related to memory absence and delusional memories in patients in intensive care units managed with light sedation." Intensive and Critical Care Nursing 59 (August 2020): 102830. http://dx.doi.org/10.1016/j.iccn.2020.102830.

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Mariano, Stefania, Andrea Casey, and Fernando Olivera. "Managers and organizational forgetting: a synthesis." Learning Organization 25, no. 3 (April 9, 2018): 169–79. http://dx.doi.org/10.1108/tlo-06-2017-0061.

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Purpose This paper aims to evaluate how managers influence accidental and intentional organizational forgetting, i.e. knowledge depreciation, knowledge loss and unlearning. Design/methodology/approach The literature was reviewed based on predetermined search terms to identify peer-reviewed articles published in English and available in full-text format from the EBSCOhost and Google Scholar databases. Empirical and theoretical contributions were included. Additional articles, books and book chapters were manually selected and included based on recent reviews and syntheses of organizational forgetting work. Findings Findings revealed that managers contributed to preventing accidental knowledge depreciation and loss and preserving organizational memory. With respect to intentional forgetting, findings revealed contradictory positions: on the one hand, managers contributed to the disbandment of existing beliefs and frames of reference, but on the other hand, they preserved existing knowledge and power structures. Research limitations/implications The study was limited by the accessibility of subscribed journals and databases, research scope and time span. Practical implications This paper provides useful guidelines to managers who need to reduce the disruptive effects of accidental forgetting or plan intentional forgetting, i.e. managed unlearning. Originality/value This paper represents a first attempt to review and define the influence of managers on organizational forgetting.

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Lazutina, A. A., and A. V. Sokolov. "ABOUT OPTIMAL MANAGEMENT OF WORK-STEALING DEQUES IN TWO-LEVEL MEMORY." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 190 (April 2020): 51–60. http://dx.doi.org/10.14489/vkit.2020.04.pp.051-060.

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In the parallel work-stealing load balancers, each core owns a personal buffer of tasks called deque. One end of the deque is used by its owner to add and retrieve tasks, while the second end is used by other cores to steal tasks. Our experience in software implementations has shown that it is important to optimize work with cache memory in parallel work-stealing load balancers. For example, by modifying deques so that they can hold task objects instead of pointers, we managed to increase the performance more than 2.5 times on the CPU-bound applications and decrease last-level cache misses up to 30 % compared to Intel TBB (Threading Building Blocks) and Intel / MIT (Massachusetts Institute of Technology) Cilk work-stealing schedulers. Therefore, it is important to investigate special methods of working with deques in two-level memory, and not just try to optimize the use of universal cache implementations. The paper analyzes the problem of optimal control of a work-stealing deque in two-level memory (for example, registers – random access memory), where probabilities of parallel operations with the deque are known. The classic sequential cyclic method for representing a deque in memory is considered. If a deque overflows or empty, we transfer elements from its middle part from the fast memory to the slow memory, since data from the end parts of the deque may be needed earlier. The problem is to find the optimal number of elements from both sides of the deque to leave in the fast memory if the deque is full or empty. The average time to get into the states when it is necessary to reallocate the memory is maximized.The simulation model and the mathematical model in the form of an absorbing Markov chain were constructed. The results of numerical experiments are presented.

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Lazutina, A. A., and A. V. Sokolov. "ABOUT OPTIMAL MANAGEMENT OF WORK-STEALING DEQUES IN TWO-LEVEL MEMORY." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 190 (April 2020): 51–60. http://dx.doi.org/10.14489/vkit.2020.04.pp.051-060.

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In the parallel work-stealing load balancers, each core owns a personal buffer of tasks called deque. One end of the deque is used by its owner to add and retrieve tasks, while the second end is used by other cores to steal tasks. Our experience in software implementations has shown that it is important to optimize work with cache memory in parallel work-stealing load balancers. For example, by modifying deques so that they can hold task objects instead of pointers, we managed to increase the performance more than 2.5 times on the CPU-bound applications and decrease last-level cache misses up to 30 % compared to Intel TBB (Threading Building Blocks) and Intel / MIT (Massachusetts Institute of Technology) Cilk work-stealing schedulers. Therefore, it is important to investigate special methods of working with deques in two-level memory, and not just try to optimize the use of universal cache implementations. The paper analyzes the problem of optimal control of a work-stealing deque in two-level memory (for example, registers – random access memory), where probabilities of parallel operations with the deque are known. The classic sequential cyclic method for representing a deque in memory is considered. If a deque overflows or empty, we transfer elements from its middle part from the fast memory to the slow memory, since data from the end parts of the deque may be needed earlier. The problem is to find the optimal number of elements from both sides of the deque to leave in the fast memory if the deque is full or empty. The average time to get into the states when it is necessary to reallocate the memory is maximized.The simulation model and the mathematical model in the form of an absorbing Markov chain were constructed. The results of numerical experiments are presented.

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Hariharan, I., and M. Kannan. "Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate the Reconfiguration Overheads in Reconfigurable Systems." Journal of Circuits, Systems and Computers 28, no. 14 (March 15, 2019): 1950246. http://dx.doi.org/10.1142/s0218126619502463.

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Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology.

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Journal articles on the topic 'Managed memory'

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