Relevant bibliographies by topics / Machine multiprocesseur

Academic literature on the topic 'Machine multiprocesseur'

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Published: 25 May 2024

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Journal articles on the topic "Machine multiprocesseur"

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Walter, Rico, and Alexander Lawrinenko. "A characterization of optimal multiprocessor schedules and new dominance rules." Journal of Combinatorial Optimization 40, no. 4 (August 12, 2020): 876–900. http://dx.doi.org/10.1007/s10878-020-00634-9.

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Abstract The paper on hand approaches the classical makespan minimization problem on identical parallel machines from a rather theoretical point of view. Using an approach similar to the idea behind inverse optimization, we identify a general structural pattern of optimal multiprocessor schedules. We also show how to derive new dominance rules from the characteristics of optimal solutions. Results of our computational study attest to the efficacy of the new rules. They are particularly useful in limiting the search space when each machine processes only a few jobs on average.
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Wang, Wencheng, and Xiaofei Liu. "A Combinatorial 2-Approximation Algorithm for the Parallel-Machine Scheduling with Release Times and Submodular Penalties." Mathematics 10, no. 1 (December 25, 2021): 61. http://dx.doi.org/10.3390/math10010061.

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In this paper, we consider parallel-machine scheduling with release times and submodular penalties (P|rj,reject|Cmax+π(R)), in which each job can be accepted and processed on one of m identical parallel machines or rejected, but a penalty must paid if a job is rejected. Each job has a release time and a processing time, and the job can not be processed before its release time. The objective of P|rj,reject|Cmax+π(R) is to minimize the makespan of the accepted jobs plus the penalty of the rejected jobs, where the penalty is determined by a submodular function. This problem generalizes a multiprocessor scheduling problem with rejection, the parallel-machine scheduling with submodular penalties, and the single machine scheduling problem with release dates and submodular rejection penalties. In this paper, inspired by the primal-dual method, we present a combinatorial 2-approximation algorithm to P|rj,reject|Cmax+π(R). This ratio coincides with the best known ratio for the parallel-machine scheduling with submodular penalties and the single machine scheduling problem with release dates and submodular rejection penalties.
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Staunstrup, Jørgen, Jens Ove Jespersen, and Ole V. Johansen. "Physical datarepresentation in a multiprocessor database machine." Parallel Computing 2, no. 4 (December 1985): 335–43. http://dx.doi.org/10.1016/0167-8191(85)90032-8.

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Agrawal, Rakesh, and David J. DeWitt. "Recovery architectures for multiprocessor database machines." ACM SIGMOD Record 14, no. 4 (May 1985): 131–45. http://dx.doi.org/10.1145/971699.318912.

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Kuruvilla, Abey, and Giuseppe Paletta. "Minimizing Makespan on Identical Parallel Machines." International Journal of Operations Research and Information Systems 6, no. 1 (January 2015): 19–29. http://dx.doi.org/10.4018/ijoris.2015010102.

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A heuristic algorithm that uses iteratively LPT and MF approaches on different job and machine sets constructed by using the current solution is developed to solve a classical multiprocessor scheduling problem with the objective of minimizing the makespan. Computational results indicate that the proposed algorithm is very competitive with respect to well-known constructive algorithms for a large number of benchmark instances.
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Pan, Feng Shan, Chun Ming Ye, and Xiao Hua Sheng. "Hybrid Particle Swarm Algorithm for Solving Multiprocessor Problem." Applied Mechanics and Materials 66-68 (July 2011): 966–72. http://dx.doi.org/10.4028/www.scientific.net/amm.66-68.966.

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Multiprocessor problem signifies that there are at least one process produced at more than two machines, which increases the difficulty and complexity of the problem. Hybrid particle swarm algorithm is adopted to solve the problem of multiprocessor in this paper.Through the redesigning parameters and programming, the final result is compared with that of genetic algorithm in conferences. The simulation results indicate that Hybrid particle swarm algorithm for solving multiple processors problem is better that of using genetic algorithms.
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Veselovska, Nataliia. "DEVELOPMENT OF ALGORITHMIC SUPPORT FOR PRACTICAL IMPLEMENTATION OF TESTING AND DIAGNOSTIC COMPLEX OF CNC MACHINES." Vibrations in engineering and technology, no. 1(104) (April 29, 2022): 71–80. http://dx.doi.org/10.37128/2306-8744-2022-1-9.

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CNC machines, including multi-purpose machines (product processing centers), have been widely used in connection with the creation of flexible production systems and significant progress in developing and improving the reliability of multi-purpose freely programmable, multiprocessor and small numerical program control devices (CNC) , so the development of algorithmic software for the practical implementation of the test and diagnostic complex and the use of diagnostic systems as a means of automation of information technology is one of the general directions of improving the efficiency of machine-building enterprises. However, in order to make decisions about the scope, stages and feasibility of using a particular diagnostic system for the selected object of study at a particular enterprise, it is necessary to assess its expected benefits. The use of diagnostics during operation of the machine imposes its influence on the means and methods of diagnosis, which should be convenient for use in the factory, to ensure the diagnosis process in the shortest time, to have reliable readings, especially with high requirements for product reliability. and in some cases without disrupting the mechanism, to be economically feasible. The design of the machine is adapted to the needs of diagnostics and must: have built-in devices that evaluate its parameters (pressure in the hydraulic system, temperature of energy-intensive units, accuracy of machining, speed); periodically connect to special equipment that will diagnose the basic parameters of the machine and provide data on its condition. The parameters of the technical condition (diagnostic features), which can be judged on the OD and which are diagnosed during operation of the machine, are: machine parameters that directly characterize its efficiency; damage and defects that occur during operation and lead or may lead to failure; side effects that are functionally or stochastically related to the initial parameters.
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Rappleye, Jason, Martins Innus, Charles M. Weeks, and Russ Miller. "SnBversion 2.2: an example of crystallographic multiprocessing." Journal of Applied Crystallography 35, no. 3 (May 16, 2002): 374–76. http://dx.doi.org/10.1107/s0021889802005782.

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The computer programSnBimplements a direct-methods algorithm, known asShake-and-Bake, which optimizes trial structures consisting of randomly positioned atoms. Although largeShake-and-Bakeapplications require significant amounts of computing time, the algorithm can be easily implemented in parallel in order to decrease the real time required to achieve a solution. By using a master–worker model,SnBversion 2.2 is amenable to all of the prevalent modern parallel-computing platforms, including (i) shared-memory multiprocessor machines, such as the SGI Origin2000, (ii) distributed-memory multiprocessor machines, such as the IBM SP, and (iii) collections of workstations, including Beowulf clusters. A linear speedup in the processing of a fixed number of trial structures can be obtained on each of these platforms.
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Miya, E. N. "Multiprocessor/distributed processing bibliography (in machine-readable form)." ACM SIGARCH Computer Architecture News 13, no. 1 (March 1985): 27–29. http://dx.doi.org/10.1145/1296930.1296933.

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Sarkar, Susmit, Peter Sewell, Francesco Zappa Nardelli, Scott Owens, Tom Ridge, Thomas Braibant, Magnus O. Myreen, and Jade Alglave. "The semantics of x86-CC multiprocessor machine code." ACM SIGPLAN Notices 44, no. 1 (January 21, 2009): 379–91. http://dx.doi.org/10.1145/1594834.1480929.

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Dissertations / Theses on the topic "Machine multiprocesseur"

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Muller, Gilles. "Conception et realisation d'une machine multiprocesseur sure de fonctionnement." Rennes 1, 1988. http://www.theses.fr/1988REN10044.

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Etude de la conception d'une nouvelle architecture de machines sures de fonctionnement. La caracteristique principale de cette architecture est la possibilite de concevoir une machine sure de fonctionnement a partir d'une ou plusieurs machines standards et d'un composant sur de fonctionnement appele memoire stable
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Ng, Paulino. "Conception d'architectures testables et détermination des vecteurs de test pour les circuits spécifiques fortement intégrés de la machine MaRS (machine à réduction symbolique)." Toulouse, ENSAE, 1990. http://www.theses.fr/1990ESAE0003.

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L'évolution des outils de conception assistée par ordinateur de circuits numériques fortement intégrés permet d'envisager la réalisation rapide de circuits intégrés de haute complexité logique. Toutefois, plus ces circuits deviennent complexes, plus leur test devient difficile; il est donc fondamental de prendre en compte les techniques de testabilité au plus tôt lors de la définition du circuit. Dans le projet MaRS (machine à reduction symbolique), trois circuits spécifiques fortement intégrés ont été développés; l'auteur propose des modifications de chacune des architectures, des techniques de conception adaptées rendant le test possible et des vecteurs de tests pour chacun de ces circuits. Ces circuits sont montés sur une carte en circuit imprime multi-couche: il propose alors une technique permettant de réaliser le test des différentes interconnexions de la carte. Ces circuits ont été réalisés, les vecteurs de tests définis sont passés sur un testeur de l'intégration complète de la machine a permis de valider le bon fonctionnement de chacun d'eux.
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LAHJOMRI, MOHAMMED ZAKARIA. "Conception et evaluation d'un mecanisme de memoire virtuelle partagee sur une machine multiprocesseur a memoire distribuee." Rennes 1, 1994. http://www.theses.fr/1994REN10010.

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Les besoins en puissance de calcul ont motive de nombreuses recherches dans le domaine des architectures. Depuis quelques annees, ces recherches ont donne naissance aux machines paralleles a memoire distribuee qui semblent etre la voie actuelle pour realiser des architectures massivement paralleles. Cependant, la difficulte de programmation de ces machines rend difficile l'exploitation de leur performance intrinseque. Actuellement, des recherches sont menees dans le domaine de la conception d'environnements de programmation afin de faciliter l'utilisation de ces machines. A ce titre, la memoire virtuelle partagee parait etre un concept interessant: elle offre un espace d'adressage global permettant une abstraction de la localisation des donnees sur les differentes memoires locales. Nous nous sommes interesses a la conception, la realisation et la validation d'un dispositif de memoire virtuelle partagee appele koan sur une architecture parallele a memoire distribuee, en l'occurance un hypercube ipsc/2. Nous avons par la suite evalue l'efficacite d'un tel dispositif sur des applications paralleles. Cette phase d'experimentation nous a permis de mettre en relief les problemes lies a l'utilisation d'une memoire virtuelle partagee et de proposer des solutions adequates
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Gaildrat, Véronique. "Contribution a l'etude et a la conception d'une machine parallele pour la production rapide d'images de synthese : la machine voxar, conception de l'application synthese d'images realistes." Toulouse 3, 1988. http://www.theses.fr/1988TOU30199.

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L'objectif est de reduire les temps d'obtention d'images de synthese realistes par la technique du lancer de rayon. Un logiciel de synthese d'images, applique a des objets modelises par composition de primitives geometriques, est propose. Afin d'exploiter le parallelisme d'ecran et la coherence spatiale d'une scene, une architecture parallele a ete introduite
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Liang, Yan. "Mise en œuvre d'un simulateur en OCCAM pour la conception d'architectures parallèles à base d'une structure multiprocesseur hiérarchique." Compiègne, 1989. http://www.theses.fr/1989COMPD176.

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La simulation est devenue une étape indispensable dans la phase de conception de machines parallèles et permet d'éviter la construction de prototypes couteux. Dans cette thèse, un simulateur orienté vers des processus parallèles en langage OCCAM a été développé. Notre objectif a été de concevoir un simulateur adapté à un réseau de transputers pour la réalisation d'un prototype de machine parallèle utilisant des liaisons directes entre les transputers par les canaux séries. A titre d'exemple de simulation, une architecture parallèle (coprocesseur) à base d'une structure multiprocessor hiérarchique : maître-esclave a été réalisée au niveau processeur-mémoire-commutateur. La performance théorique est évaluée à l'aide des deux modèles analytiques dont l'un est une combinaison de systèmes ouverts M/M/1, et l'autre est un système ouvert M/M/s. La performance expérimentale a été mesurée respectivement sur les tâches indépendantes et les tâches séquentielles. La configuration expérimentale de sa performance théorique permet d'avoir un aperçu général sur les avantages et les limites d'une structure coprocesseur et d'envisager une implémentation ultérieure
The simulation has become an indispensable phase for conception of parallel processing systems, and enables to avoid construction of expensive prototypes. In this paper, a parallel process-oriented simulator written in OCCAM language has been developed. Our objective is to conceive a simulator adapted to a network of transputers for prototyping parallel processing systems by connecting directly the serial transputer channels. As a simulation example, a parallel processor system (coprocessor) based on hierarchical structure : master-slave has been realized at the processor-memory-switch level. The performance analysis is obtained via two queuing models : the former as independent M/M/1 systems and the latter as a M/M/s system. The experimental performance is measured respectively based on the independent tasks and the sequential tasks. The comparison of analytic and experimental results enables us to constate the advantage and limit of the coprocessor and to encourage us to its implementation
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Toch, Lamiel. "Contributions aux techniques d’ordonnancement sur plates-formes parallèles ou distribuées." Electronic Thesis or Diss., Besançon, 2012. http://www.theses.fr/2012BESA2045.

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Les travaux présentés dans ce document portent sur l'ordonnancement d'applications parallèles sur des plates-formes parallèles (cluster) ou distribuées (grilles de calcul). Dans nos travaux de recherche nous nous sommes concentrés sur l'ordonnancement d'applications modélisées par un DAG, graphe orienté sans cycle, pour les grilles de calcul et sur l'ordonnancement pour les (cluster, machines multiprocesseurs) de programmes parallèles (jobs parallèles) représentés sous la forme de surface rectangulaire dont les deux dimensions sont le nombre de processeurs requis et la durée d'exécution. Les recherches s'articulent autour de trois grands axes. Le premier axe concerne l'ordonnancement d'un ensemble d'instances d'une application pour les grilles de calcul. Le deuxième axe est l'ordonnancement de jobs parallèles dans les clusters. Le troisième est l'ordonnancement d'un lot de jobs parallèles pour les machines parallèles. Cette thèse apporte des contributions sur les trois axes. La première contribution associée au premier axeest l'étude expérimentale avancée de trois algorithmes pour l'ordonnancement d'un ensemble d'instances d'une application sur une plate-forme hétérogène où les coûts de communication sont négligeables : un algorithme de liste, un algorithme de régime permanent et un algorithme génétique. D'autre part nous apportons l'intégration des communications dans cet algorithme génétique. La deuxième contribution associée au deuxième axe est la conception d'une nouvelle technique d'ordonnancement de jobs parallèles pour les clusters : le pliage de jobs qui utilise la virtualisation des processeurs. La dernière contribution porte sur la conception d'une nouvelletechnique inspirée du domaine des statistiques et du traitement du signal appliquée à l'ordonnancement de jobs parallèles dans une machine multiprocesseur. Enfin nous donnons quelques travaux de recherches qui on été réalisés mais qui n'ont pas abouti à des résultats significatifs pour l'ordonnancement
Works presented in this document tackle scheduling of parallel applications in either parallel (cluster) or distributed (computing grid) platforms. In our researches we were concentrated on either scheduling of applications modeled by a DAG, directed acyclic graph, for computing grid or scheduling of parallel programs (parallel jobs) represented by a rectangular shape whose the two dimensions are the number of requested processors and the execution time. The researches follow three main topics. The first topic concerns the scheduling of a set of instances of an application for computing grid. The second topic deals with the scheduling of parallel jobs inclusters. The third one tackles the scheduling of parallel jobs in multiprocessor machines. We brought contributions on these three topics. The first contribution under the first topic consists of the advanced experimental study of three algorithms for scheduling a set of instances of an application on a heterogeneous platform without communication costs : a list-based algorithm, a steady-state algorithm and genetic algorithm. Moreover we integrate communications in this genetic algorithm. The second contribution under the second topic is the design of a new technique for scheduling parallel jobs in clusters : job folding which uses virtualization of processors. The third contribution deals with a new technique which comes from statistics and signal cessing applied to scheduling of parallel jobs in a multiprocessor machine. Eventually we givesome works that we carried out but which did not give significant results for scheduling
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Guillot, Bernard. "Réalisation d'un outil autonome pour l'écriture et l'interrogation de systèmes de gestion de bases de données et de connaissances sur une machine multiprocesseur : évolution du concept de bases de données vers la manipulation d'objets image et graphique." Compiègne, 1986. http://www.theses.fr/1986COMPI219.

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La mise en œuvre d’un système MUMPS autonome sur la machine multimicroprocesseur SM90 nous a permis de dégager certaines fonctionnalités, associées aux niveaux conceptuel et interne des SGBD, qui s’avèrent particulièrement utiles comme outils pour l’écriture de SGBD. Le noyau principal de ces outils réside dans l’intégration d’une organisation hiérarchique et dynamique de données dans le langage MUMPS accessible à partir de la notion de variable globale. La modélisation des informations permet l’usage du système MUMPS dans un contexte de base de données relationnelles et en logique : l’espace de stockage directement accessible à travers le langage est celui des disques du système. Une extension du langage est proposée sous la forme d’une fonction pour l’interrogation et le parcours de l’espace global. Nous montrons une utilisation de l’espace global en déduction dans le cadre d’une interrogation basée sur la logique. La représentation de faits élémentaires, de règles dans une base de connaissances s’expriment à travers la notion de variable globale. L’adjonction de potentialités graphiques au systèmes MUMPS par l’apport d’un coprocesseur spécialisé permet d’envisager la réalisation d’interfaces graphiques de haut niveau. Enfin nous montrons que l’évolution du concept de base de données est lié à sa capacité à manipuler de nouveaux types d’objets, principalement les types graphique et image.
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Guillot, Bernard. "Réalisation d'un outil autonome pour l'écriture et l'interrogation de systèmes de gestion de bases de données et de connaissance sur une machine multiprocesseur évolution du concept de base de données vers la manipulation d'objets image et graphique." Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb375993889.

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Monti, Jean-Marc. "Interprocessor communication supports for a multiprocessor dataflow machine." Thesis, McGill University, 1991. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=60009.

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The dataflow model of computation offers a powerful alternative to the von Neumann based model for exploiting the fine-grain parallelism inherent in scientific computations. Under this model, a program is expressed in the form of a graph, where the data values are carried by tokens, moving on the arcs of the graph. A distinctive feature of dataflow computers is the absence of the conventional program counter. Instead, instruction execution is solely determined by the availability of data which provides ample instruction level fine-grain parallelism. A highly pipelined static dataflow architecture has recently been proposed, based on the argument fetching principle, yielding the McGill Dataflow Architecture (MDFA).
In this thesis, an inter-processor communication mechanism is proposed. With this mechanism, a multiprocessor MDFA system can be constructed, based on a distributed memory organization. An efficient inter-processor synchronization and communication support is presented, for sending and receiving data through an interconnection network. An Interprocessor Communication Unit (ICU) has been designed to implement the above mechanism in the MDFA. A simulation testbed has been implemented to study the performance of the multiprocessor. It includes an assembler, with multiprocessor extensions, and a multiprocessor simulator. An analysis based on the simulations results is presented, focusing on the impact of long latency operations on program performance.
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Ben, Ismail Tarek. "Synthèse au niveau système et conception de systèmes mixtes logiciels-matériels." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0003.

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L'objet de ces travaux de these est d'etudier la specification et la synthese de systemes de controle, qui peuvent etre composes a la fois de logiciel et de materiel, sur des architectures multiprocesseurs (asic, fpga, et logiciel). Ce sujet de recherche fait partie a la fois de la synthese de systemes vlsi et de la conception mixte logicielle/materielle. Afin d'atteindre ces objectifs, une methodologie qui permet de concevoir conjointement le logiciel et le materiel a ete developpee. L'originalite de ce travail vient du fait que les specifications a traiter sont decrites a un tres haut niveau d'abstraction, appele niveau systeme, avec le langage sdl. Ceci permet de concevoir des applications de plus en plus complexes. Ces travaux traitent principalement le probleme du decoupage de systemes de controle en sous-systemes de granularite plus fine et donc plus facilement synthetisables. L'approche de decoupage qui a ete developpee se base sur une boite a outils qui offre au concepteur le moyen de transformer, raffiner, decouper un systeme puis d'affecter chaque sous-systeme a une technologie particuliere en logiciel (c) ou en materiel (vhdl). La methode de decoupage suivie est interactive et utilise une forme intermediaire basee sur un modele de machines a etats finis etendues communicantes via des canaux abstraits. Une autre tache tout aussi importante dans cette methodologie de raffinement est de synthetiser la communication entre les differentes partitions resultat d'un decoupage. Cela se traduit par une etape d'allocation de protocoles de communication et une etape de synthese d'interfaces entre les sous-systemes communicants. La premiere etape consiste a selectionner dans une bibliotheque les modeles de communication necessaires entre les sous-systemes. La deuxieme etape consiste a adapter ou generer les interfaces des differents sous-systemes
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Books on the topic "Machine multiprocesseur"

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Manuel Alejandro Saldana De Fuentes. A parallel programming model for a multi-FPGA multiprocessor machine. 2006.

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Handbook of Multi and ManyCore Processing Chapman HallCRC Computer Information Science. CRC Press, 2012.

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Solihin, Yan. Fundamentals of Parallel Multicore Architecture. Taylor & Francis Group, 2015.

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Fundamentals of Parallel Multicore Architecture. Taylor & Francis Group, 2020.

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Solihin, Yan. Fundamentals of Parallel Multicore Architecture. Taylor & Francis Group, 2015.

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Solihin, Yan. Fundamentals of Parallel Multicore Architecture. Taylor & Francis Group, 2015.

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Fundamentals of Parallel Multicore Architecture. Chapman and Hall/CRC, 2015.

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Book chapters on the topic "Machine multiprocesseur"

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Clocksin, W. F. "The DelPhi Multiprocessor Inference Machine." In Workshops in Computing, 189–98. London: Springer London, 1993. http://dx.doi.org/10.1007/978-1-4471-3421-3_11.

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Austin, John D., and Stephen M. Pizer. "A Multiprocessor Adaptive Histogram Equalization Machine." In Information Processing in Medical Imaging, 375–92. Boston, MA: Springer US, 1988. http://dx.doi.org/10.1007/978-1-4615-7263-3_25.

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Menon, Jai. "Sorting and Join Algorithms for Multiprocessor Database Machines." In Database Machines, 289–322. Berlin, Heidelberg: Springer Berlin Heidelberg, 1986. http://dx.doi.org/10.1007/978-3-642-82937-6_13.

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Agrawal, Rakesh. "A Parallel Logging Algorithm for Multiprocessor Database Machines." In Database Machines, 256–76. New York, NY: Springer New York, 1985. http://dx.doi.org/10.1007/978-1-4612-5144-6_13.

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Boukerche, Azzedine. "Conservative Circuit Simulation on Multiprocessor Machines." In High Performance Computing — HiPC 2000, 415–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44467-x_38.

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Jain, Anamika, Madhu Jain, and Dheeraj Bhardwaj. "Controllable multiprocessor queueing system." In Applications of Mathematical Modeling, Machine Learning, and Intelligent Computing for Industrial Development, 61–76. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003386599-5.

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Zeidler, H. Ch. "RDBM — A Relational Database Machine Based on a Dedicated Multiprocessor System." In Database Machines, 15–44. Berlin, Heidelberg: Springer Berlin Heidelberg, 1986. http://dx.doi.org/10.1007/978-3-642-82937-6_2.

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Cesarini, F., F. Pippolini, and G. Soda. "A Technique for Analyzing Query Execution in a Multiprocessor Database Machine." In Database Machines, 68–90. New York, NY: Springer New York, 1985. http://dx.doi.org/10.1007/978-1-4612-5144-6_4.

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Groesbrink, Stefan. "On the Homogeneous Multiprocessor Virtual Machine Partitioning Problem." In IFIP Advances in Information and Communication Technology, 228–37. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-38853-8_21.

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Gupta, Gopal. "A Distributed Stack Implementation and an Abstract Machine for And-Or Parallel Execution of Logic Programs on Shared Memory Multiprocessors." In Multiprocessor Execution of Logic Programs, 87–140. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2778-7_5.

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Conference papers on the topic "Machine multiprocesseur"

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Zaafrani, Abderrazek, and Xinmin Tian. "Performance Portability of XL HPF Compiler on IBM SP2 and SMP Multiprocessors." In International Symposium on Computer Architecture and High Performance Computing. Sociedade Brasileira de Computação, 1999. http://dx.doi.org/10.5753/sbac-pad.1999.19767.

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High Performance Fortran (HPF) is a data-parallel programming language that allows the programmer to specify the data decomposition onto the processors while the compiler takes care of the tedious tasks of communication generation and computation partitioning. Shifting some of the complex tasks from the user to the compiler should encourage programmers to write and port code to parallel machines especially if the compiler implements these tasks efficiently. In this paper, performance results and analysis of a subset of the SPEC92 is presented for the XL HPF compiler on IBM SP2 machines. In addition to obtaining good performance from the compiler, one of the the main concerns of HPF users is portability. Experimental results and analysis are presented in this paper to investigate performance portability (consistency) first across multiprocessor architectures and then across compilers. For performance portability across multiprocessor machines, the same XL HPF compiler used for the IBM SP2 distributed memory machine experiment is also used to compile and execute the same applications but on IBM SMP machines. The comparable speedup and behaviour obtained for both machines indicates that HPF compilers can be portable across different architectures. For performance portability across compilers, various HPF programming techniques and recommendations are introduced to increase the chances of obtaining performance consistency with different HPF compilers.
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Monro, D. M., J. A. Dallas, J. A. Nicholls, M. D. Cripps, and W. A. Crossland. "An Optically Connected Parallel Machine." In Optical Computing. Washington, D.C.: Optica Publishing Group, 1993. http://dx.doi.org/10.1364/optcomp.1993.othd.5.

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Hamilton, M. L. C. "The application of multiprocessor DSP to machine vision." In IEE Colloquium on `Multiprocessor DSP (Digital Signal Processing) - Applications, Algorithms and Architectures'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950781.

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Chow, K. W., and Bruce G. Batchelor. "Multiprocessor architecture for machine vision." In Applications in Optical Science and Engineering, edited by Bruce G. Batchelor, Susan Snell Solomon, and Frederick M. Waltz. SPIE, 1992. http://dx.doi.org/10.1117/12.132063.

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Shoemaker, Richard L. "Multimicroprocessor computer systems in optics." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1986. http://dx.doi.org/10.1364/oam.1986.fm3.

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The commercial availability of powerful 32-bit microprocessors provides an unprecedented opportunity for researchers to construct inexpensive but very powerful multiprocessor computer systems that are optimally designed for specific computational tasks. However, to obtain good performance from such systems it is essential that both the processor interconnection architecture and the system software be appropriate for the problem. Two multiprocessor system designs being developed at the Optical Sciences Center illustrate the potential of such systems. The first is an image- data-driven dynamically reconfigurable multiprocessor using thirty Motorola 68000 microprocessors interconnected by multiple global data buses. This system is fully operational and is being used to develop machine vision systems capable of very high speed biomedical image acquisition and image understanding. The second system is still in the design phase and will be used for image reconstruction using simulated annealing. It consists of an array of sixty-four Inmos Transputers with fourway or six-way nearest-neighbor interconnections.
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He, Yong, and Zhiyi Tan. "Multiprocessor scheduling problem with machine constraints." In Multispectral Image Processing and Pattern Recognition, edited by Xubang Shen and Jianguo Liu. SPIE, 2001. http://dx.doi.org/10.1117/12.441674.

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Rygol, M., S. B. Pollard, and C. Brown. "A multiprocessor 3D vision system for pick and place." In British Machine Vision Conference 1990. British Machine Vision Association, 1990. http://dx.doi.org/10.5244/c.4.31.

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Correa, Jorge, Nicholas Toombs, and Placid M. Ferreira. "Implementation of an Open-Architecture Control for CNC Systems Based on Open-Source Electronics." In ASME 2016 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2016. http://dx.doi.org/10.1115/imece2016-65964.

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Open control architectures have many advantages including increased computational resources and flexibility of reconfiguration of new manufacturing units. This paper proposes an open architecture for the control of CNC systems based on open source electronics. The software architecture in this paper is a component-based approach where each component has an independent finite state machine (FSM) model. The hardware architecture is a multiprocessor distributed controller, with different levels of processing, and adaptable for different hardware specifications. A discussion of the basic control algorithms, with examples of implementation to the open source platform Arduino, is presented as part of the methodology. Other results in this paper include the preliminary test of the control to a two-axis CNC stage and a mathematical model of the control-loop in Simulink. The architecture in this paper has the potential of transforming CNC in open source electronics from device-oriented systems to systems where users can design their controls for special purpose machines.
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Dunlap, George W., Dominic G. Lucchetti, Michael A. Fetterman, and Peter M. Chen. "Execution replay of multiprocessor virtual machines." In the fourth ACM SIGPLAN/SIGOPS international conference. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1346256.1346273.

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Agrawal, Rakesh, and David J. DeWitt. "Recovery architectures for multiprocessor database machines." In the 1985 ACM SIGMOD international conference. New York, New York, USA: ACM Press, 1985. http://dx.doi.org/10.1145/318898.318912.

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