Relevant bibliographies by topics / Low-Power Read-Out Circuit

Academic literature on the topic 'Low-Power Read-Out Circuit'

Author: Grafiati
Published: 14 March 2023

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Journal articles on the topic "Low-Power Read-Out Circuit"

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Huang, Gongxing, Rongshan Wei, Wanjin Wang, and Qunchao Chen. "A low power read-out integrated circuit for multiple sensors." IEICE Electronics Express 17, no. 17 (September 10, 2020): 20200199. http://dx.doi.org/10.1587/elex.17.20200199.

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Bertuccio, G., L. Fasoli, and M. Sampietro. "Low-power bipolar front-end circuit for VLSI detectors read-out." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 409, no. 1-3 (May 1998): 360–62. http://dx.doi.org/10.1016/s0168-9002(97)01299-0.

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Ferri, Giuseppe, Andrea De Marcellis, Claudia Di Carlo, Vincenzo Stornelli, Alessandra Flammini, Alessandro Depari, Daniele Marioli, and Emiliano Sisinni. "A CCII-Based Low-Voltage Low-Power Read-Out Circuit for DC-Excited Resistive Gas Sensors." IEEE Sensors Journal 9, no. 12 (December 2009): 2035–41. http://dx.doi.org/10.1109/jsen.2009.2033197.

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Teymouri, Masood. "A multipurpose circuit to read out and digitize pixel signal for low‐power CMOS imagers." International Journal of Circuit Theory and Applications 48, no. 11 (August 4, 2020): 1887–99. http://dx.doi.org/10.1002/cta.2854.

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Jo, Sung-Hun. "Low-Power Current Integrating Flat-Passband Infinite Impulse Response Filter for Sensor Read-Out Integrated Circuit in 65-nm CMOS Technology." Electronics 12, no. 5 (March 1, 2023): 1191. http://dx.doi.org/10.3390/electronics12051191.

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Low-power current integrating infinite impulse response filter having flat-passband for sensor read-out integrated circuit is proposed. In a current integrating filter, passband flatness degradation is inevitable due to sinc-like filtering characteristics. In this paper, by proposing a high order infinite impulse response filter architecture, flat-passband characteristic can be achieved. By implementing a filter architecture with a flat passband, the required sampling frequency can be lowered, which in turn can reduce power consumption. Moreover, the proposed high order infinite impulse response filter architecture has a high degree of freedom on adjusting input sample weights. The proposed integrated circuit is implemented in TSMC 65-nm CMOS process and operated on 1.2 V supply voltage.
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Boykin, Tommy O., Nagendra Dhakal, Javaneh Boroumand, F. Javier Gonzalez, Isaiah O. Oladeji, Pedro Figueiredo, Stephen Neushul, and Robert E. Peale. "Spray-deposited metal-chalcogenide photodiodes for low cost infrared imagers." MRS Advances 5, no. 39 (2020): 2013–22. http://dx.doi.org/10.1557/adv.2020.324.

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AbstractLow-cost, light-weight, low-power, large-format, room-temperature, mid-wave infrared (MWIR) detectors are needed for reduced-scale aircraft. An opportunity, suggested by direct-read X-radiography systems, is the use of thin film transistor (TFT) array as read-out integrated circuit (ROIC) for low-cost sensors deposited directly and unpatterned onto this ROIC. TFTs have already been thoroughly optimized for power, weight, large-format, and cost by the flat-panel-display industry. We present experimental investigation of aqueous-spray-deposited, mid-wave-IR, metal-chalcogenide heterojunction CdS/PbS photodiodes for this application. Measured responsivity, detectivity D*, and photoresponse spectra are reported.
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Damilano, Alessia, Hafiz Muhammad Afzal Hayat, Alberto Bonanno, Danilo Demarchi, and Marco Crepaldi. "A Flexible Low-Power 130 nm CMOS Read-Out Circuit With Tunable Sensitivity for Commercial Robotic Resistive Pressure Sensors." IEEE Sensors Journal 15, no. 11 (November 2015): 6650–58. http://dx.doi.org/10.1109/jsen.2015.2462722.

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Renukarani, S., Bhavana Godavarthi, SK Bia Roshini, and Mohammad Khadir. "A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array." International Journal of Engineering & Technology 7, no. 2.20 (April 18, 2018): 109. http://dx.doi.org/10.14419/ijet.v7i2.20.12185.

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A novel idea of 8-Transistor (8T) static random access memory cell with enhanced information stability, sub threshold operation may be outlined. Those prescribed novel built single-ended for dynamic control 8 transistors static RAM (SRAM) cell enhances the static noise margin (SNM) to grater low energy supply. The suggested 8T takes less read and write power supply compared to 6T. Those suggested 8T need higher static noise margin than that from 6T. The portable microprocessor chips need ultralow energy consuming circuits on use battery to more drawn out span. The power utilization might be minimized utilizing non-conventional gadget structures, new circuit topologies, and upgrading the architecture. Although, voltage scaling require of the operation completed over sub threshold for low power consumption, and there will be an inconvenience from exponential decrease in execution. However, to sub threshold regime, that data stability of SRAM cell might a chance to be a amazing issue and worsens for those scaling from claming MOSFET ought to sub-nanometer engineering technology.
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Tasneem, Nishat Tarannum, and Ifana Mahbub. "A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants." Electronics 10, no. 5 (March 3, 2021): 590. http://dx.doi.org/10.3390/electronics10050590.

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This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.
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Al-Shidaifat, AlaaDdin, Sandeep Kumar, Shubhro Chakrabartty, and Hanjung Song. "A Conceptual Investigation at the Interface between Wireless Power Devices and CMOS Neuron IC for Retinal Image Acquisition." Applied Sciences 10, no. 18 (September 4, 2020): 6154. http://dx.doi.org/10.3390/app10186154.

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In this paper, a conceptual investigation of the interface between wireless power devices and a retina complementary metal oxide semiconductor (CMOS) neuron integrated circuit (IC) have been presented. The proposed investigation consists of three designs: design-I, design-II, and design-III. Design-I involves a slotted loop monopole antenna as per American National Standards Institute (ANSI) guidelines, which achieve an ultra-wide band ranging from 3.1 GHz to 10.6 GHz. The biocompatible antenna is made on silicon-nitride substrate using on-wafer packaging technology and it is used as a receiver device. The performance of antenna provides a wideband, sufficient power to receive, and low losses due to the avoidance of printed circuit board (PCB) fabrication. A CMOS based multi-stack power harvesting circuit achieves the output power ranging from 4 mW to 2.7 W and corresponds from the selected Radio Frequency (RF) bands of loop antenna is exhibited in design-II. The power efficiency of 40% to 82%, with respect to output powers of 4 mW to 2.7 W, is achieved. Design-III includes a CMOS based retina neuron circuit that employs a dynamic feedback technique and support to achieve the number of read-out spikes. At the end of the interface between wireless power devices and a CMOS retina neuron IC, 50 mV read-out spikes are achieved, with varying light intensity, from 0 mW/cm2 to 2 mW/cm2. The proposed design-II and design-III are implemented and fabricated using commercial CMOS 0.065 µm, Samsung process. The antenna and RF power harvesting IC could be placed on a contact lens platform while retina neuron IC can be implanted after ganglions cells inside the eye. The antenna and harvesting IC are physically connected to the retina circuit in the form of light. This conceptual investigation could support medical professionals in achieving an interfacing approach to restore the image visualization.
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Dissertations / Theses on the topic "Low-Power Read-Out Circuit"

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Chen, Jian. "ULTRA LOW POWER READ-OUT INTEGRATED CIRCUIT DESIGN." Wright State University / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=wright1345480982.

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Conference papers on the topic "Low-Power Read-Out Circuit"

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Chen, Jian, George Lee, and Saiyu Ren. "Ultra-low power read-out integrated circuit design." In NAECON 2012 - IEEE National Aerospace and Electronics Conference. IEEE, 2012. http://dx.doi.org/10.1109/naecon.2012.6531045.

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Tiwari, Bhawna, Prabal Bhatnagar, Pydi Ganga Bahubalindruni, and Pedro Barquinha. "Low-Power Ethanol Sensor Read-Out Circuit using a-InGaZnO TFTs." In 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2020. http://dx.doi.org/10.1109/iscas45731.2020.9181093.

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"A low power sensor-signal read-out circuit powered by inductive line." In 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings. IEEE, 2006. http://dx.doi.org/10.1109/icsict.2006.306359.

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Bhatnagar, Prabal, Pydi Ganga Bahubalindruni, and Pedro Barquinha. "Low-Power High Sensitive Capacitance Read-Out Circuit Using a-InGaZnO TFTs." In 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2021. http://dx.doi.org/10.1109/iscas51556.2021.9401699.

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Huque, M. A., M. R. Haider, Mo Zhang, Taeho Oh, and Syed K. Islam. "A Low Power, Low Voltage Current Read-Out Circuit for Implantable Electro-Chemical Sensors." In 2007 IEEE Sensors. IEEE, 2007. http://dx.doi.org/10.1109/icsens.2007.4388336.

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Jia, Sumei, Zhi'an Wang, Peng Gao, and Suying Yao. "A Low Power Sensor-Signal Read-Out Circuit for Very Low-Level Chemical Detection." In 2010 Symposium on Photonics and Optoelectronics (SOPO 2010). IEEE, 2010. http://dx.doi.org/10.1109/sopo.2010.5504365.

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Boni, Andrea, Luca Giuffredi, and Alessandro Magnanini. "Low-power humidity read-out circuit in CMOS 180-nm for RFID sensors." In 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2014. http://dx.doi.org/10.1109/icecs.2014.7049979.

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Yelkenci, Asli, Okan Zafer Batur, and Baykal Sarioglu. "Ultra low power all-digital CMOS sensor read out circuit for optically powered biomedical systems." In 2016 9th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI). IEEE, 2016. http://dx.doi.org/10.1109/cisp-bmei.2016.7853003.

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Haider, M. R., S. Mostafa, and S. K. Islam. "A low-power sensor read-out circuit with FSK telemetry for inductively-powered implant system." In 2008 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2008. http://dx.doi.org/10.1109/mwscas.2008.4616833.

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Peng, Qi, Kun Wang, Xuelian Liu, Weifeng Liu, Xiaoming Li, and Yiqi Zhuang. "A low power read-out circuit with frequency accuracy of 0.2% for capacitive and resistive sensors." In 2017 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2017. http://dx.doi.org/10.1109/iscas.2017.8050473.

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