Journal articles: 'LOW-POWER PULSE-TRIGGERED'

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Karimi, Ahmad, Abdalhossein Rezai, and Mohammad Mahdi Hajhashemkhani. "Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop." IEEE Transactions on Nanotechnology 18 (2019): 756–61. http://dx.doi.org/10.1109/tnano.2019.2929233.

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HU, YINGBO, and RUNDE ZHOU. "LOW CLOCK-SWING TSPC FLIP-FLOPS FOR LOW-POWER APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 01 (February 2009): 121–31. http://dx.doi.org/10.1142/s0218126609004971.

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In this paper, two types of Low Clock-Swing True Single Phase Clock (TSPC) Flip-Flops suitable for low-power applications are proposed. One is Low Clock-Swing Edge-Triggered TSPC Flip-Flop (LCSETTFF), constructed with a negative TSPC split out latch and a positive TSPC split out latch. The other is Low Clock-Swing Pulse-Triggered TSPC Flip-Flop (LCSPTTFF), developed in several styles. A double-edge triggered pulse generator is also developed for LCSPTTFF. With low threshold voltage clock transistors adopted, great power efficiency can be obtained in the clock network. Both types of Flip-Flops have advantages of simple structure, low power and much lower clock network power dissipation. All proposed circuits are simulated in HSPICE with 0.18 μm CMOS technology. Simulation results show that the power of LCSETTFF can be reduced by 42%, while the power dissipation, Power-Delay Product (PDP) and Area-Power-Delay Product (APDP) of LCSPTTFF can be reduced by 45–60%, 11–27% and 58–65%, respectively. In addition, the power consumptions of clock network of LCSPTTFF and LCSETTFF are estimated to be reduced by 78% and 56%, respectively, compared with conventional Flip-Flops.

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Hwang, Yin-Tsung, Jin-Fa Lin, and Ming-Hwa Sheu. "Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 2 (February 2012): 361–66. http://dx.doi.org/10.1109/tvlsi.2010.2096483.

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S, Vinothini Jane, Senthilkumar J. P, and Ravi G. "Improved low power implicit pulse triggered flip-flop with reduced power dissipation." International Journal of Computational Complexity and Intelligent Algorithms 1, no. 1 (2018): 1. http://dx.doi.org/10.1504/ijccia.2018.10021267.

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Ravi, G., J. P. SenthilKumar, and S. Vinothini Jane. "Improved low power implicit pulse triggered flip-flop with reduced power dissipation." International Journal of Computational Complexity and Intelligent Algorithms 1, no. 2 (2019): 145. http://dx.doi.org/10.1504/ijccia.2019.103746.

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Verma, Shreya, Tunikipati Usharani, S. Iswariya, and Bhavana Godavarthi. "Implementation of MHLFF based low power pulse triggered flip flop." International Journal of Engineering & Technology 7, no. 1.1 (December 21, 2017): 483. http://dx.doi.org/10.14419/ijet.v7i1.1.10150.

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The present research paper proposes to implement a low power pulse-triggered flip-flop. The proposed design is MHLFF (modified hybrid latch flip-flop). In MHLFF method, the pulse generator will be altered concerning illustration inverters what’s more a pasquinade transistor. This technique will be comparative should understood kind about flip flop what’s more it utilizes a static lock structure. Should succeed Most exceedingly bad situation delay issue brought on Eventually Tom's perusing discharging way comprise from claiming three stacked transistor MHLFF may be presented. We can minimize the power and delay when compared to the existing models i.e, CDFF and SCDFF. The circuit was implementing using Cadence Virtuoso tool in 90-nm and 45-nm technology.

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Lokhande, Vinay R., and Sagar P. Soitkar. "Low Power Positive Edge Triggered Pulse Generater Using Ring Oscillator." Journal of Computational Intelligence and Electronic Systems 5, no. 1 (March 1, 2016): 54–57. http://dx.doi.org/10.1166/jcies.2016.1130.

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Mr. Kankan Sarkar. "Design and analysis of Low Power High Speed Pulse Triggered Flip Flop." International Journal of New Practices in Management and Engineering 5, no. 03 (September 30, 2016): 01–06. http://dx.doi.org/10.17762/ijnpme.v5i03.45.

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The main important aspect is to outline a high speed and utilization of low power pulse triggered flip-flop and simulate the same. Also, we have to minimize leakage in the consumption of power in a flip-flop by employing pulse triggering technique that is adopted for clocks. Here, to solve the problem in the discharging path of the similar flip flop implementations, we employ signal feed through technique. The discharge time is reduced by the proposed method. This design out performs all the other similar pulse triggered flip flop implementation both in speed and power consumption. Now, it is implemented by employing Cadence Virtuoso Schematic Composer in 90nm GPDK. Simulation is done by a simulator known as Spectre.

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Jyothula, Sudhakar. "Low power aware pulse triggered flip flops using modified clock gating approaches." World Journal of Engineering 15, no. 6 (December 3, 2018): 792–803. http://dx.doi.org/10.1108/wje-09-2017-0309.

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PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

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kaala, D. S. R. Krishna. "Design of Low Power Negative Pulse-Triggered Flip-Flop with Enhanced Latch." IOSR Journal of VLSI and Signal Processing 3, no. 3 (2013): 06–12. http://dx.doi.org/10.9790/4200-0330612.

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Razmdideh, Ramin, and Mohsen Saneei. "Two novel low power and very high speed pulse triggered flip-flops." International Journal of Circuit Theory and Applications 43, no. 12 (November 25, 2014): 1925–34. http://dx.doi.org/10.1002/cta.2048.

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Yang, Hanwu, Zicheng Zhang, Jingming Gao, Tao Xun, and Song Li. "A Repetitive Low Impedance High Power Microwave Driver." Electronics 11, no. 5 (March 3, 2022): 784. http://dx.doi.org/10.3390/electronics11050784.

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A low impedance high power microwave (HPM) driver is designed, which can be used in studying multi-gigawatt HPM devices such as the magnetically insulated transmission line oscillator (MILO), based on a helical pulse forming line (PFL) and the Tesla pulse transformer technology. The co-axial PFL is insulated by ethanol–water mixture, whose dielectric constant can be adjusted; and the helical line increases the output pulse width as well as the impedance to make a better match with the load. By the optimal combination of PFL charging voltage and output switch working voltage, the reliability of the PFL can be improved. The Tesla transformer has partial magnetic cores to increase the coupling coefficient and is connected like an autotransformer to increase the voltage step-up ratio. The primary capacitor of the transformer is charged by a high voltage constant current power supply and discharged by a triggered switch. A transmission line is installed between the PFL and the HPM load, to further increase the load voltage. A ceramic disk vacuum interface is used for improving the vacuum of the HPM tube. The experiments show that the driver can operate at 30 GW peak power, 75 ns pulse width and 5 Hz repetition rate.

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sravya, B. Lakshmi, and V. Radha krishna. "Design of low power 4-bit shift registers using conditionally pulse enhanced pulse triggered flip-flop." IOSR journal of VLSI and Signal Processing 4, no. 5 (2014): 54–64. http://dx.doi.org/10.9790/4200-04525464.

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John, Kuruvilla, Vinod Kumar R S, and Kumar S S. "Design of low power and high speed implicit pulse flip-flop and its application." International Journal of Engineering & Technology 7, no. 3 (August 23, 2018): 1893. http://dx.doi.org/10.14419/ijet.v7i3.12845.

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In this paper, a new power efficient and high speed pulsed-triggered flip-flop in implicit style with conditional pulse enhancement and signal feed-through (CPESFTFF) is proposed. This novel architecture is presented for the pulse-triggered D-FF in the CMOS 90-nm technology. Two important features are embedded in this flip-flop architecture. Firstly, a conditional enhancement in width and height of the triggering pulses by using an additional pMOS transistor in the structure is done. Secondly, a modified signal feed-through mechanism which directly samples the input to output by using an nMOS pass transistor is introduced. The proposed design achieves better speed and power performance by successfully solving the longest discharging path problem. The simulation results show that the proposed architecture has improvement in terms of power consumption, D-to-Q delay, and Power Delay Product Performance (PDP) in comparison with other conventional P-FF architectures. A 3-bit up counter is also implemented using proposed P-FF.

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Ms. Ritika Dhabliya. "Power and Delay Analysis of Flip Flop Using Pulse Control Method." International Journal of New Practices in Management and Engineering 2, no. 03 (September 30, 2013): 12–17. http://dx.doi.org/10.17762/ijnpme.v2i03.19.

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The past few years, increasing difficulty in integration can be solved by low power, which is very important and also choosing flip-flop solves the challenges like low power. In this paper, we design and compare the power problem of various indirect pulse triggered flip flop are examined. It can be attained by reconstructing the lower part of Single-ended Conditional Capture Energy Recovery (SCCER) design and by employing the control pulse scheme. The results after the simulation derives transistor count and power required are significantly reduced in the proposed design over existing design.

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Vibhandik, Amruta S., Prof P. V. Baviskar, and Prof K. N. Pawar. "Low Power Explicit Pulse Triggered Flip-Flop Design Based On A Pass Transistor." International Journal of Advanced Engineering Research and Science 3, no. 11 (2016): 208–13. http://dx.doi.org/10.22161/ijaers/3.11.32.

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Shen, Jizhong, Liang Geng, and Xuexiang Wu. "Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique." Journal of Circuits, Systems and Computers 24, no. 07 (June 17, 2015): 1550094. http://dx.doi.org/10.1142/s0218126615500942.

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Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

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Lin, Jin-Fa. "Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 1 (January 2014): 181–85. http://dx.doi.org/10.1109/tvlsi.2012.2232684.

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Lin, J. F. "Low-power pulse-triggered flip–flop design using gated pull-up control scheme." Electronics Letters 47, no. 24 (2011): 1313. http://dx.doi.org/10.1049/el.2011.2542.

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Karimi, Ahmad, Abdalhossein Rezai, and Mohammad Mahdi Hajhashemkhani. "A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power." Integration 60 (January 2018): 160–66. http://dx.doi.org/10.1016/j.vlsi.2017.09.002.

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Wu, Hao, Gang Jin, Yiqi Zhuang, Wenrui Cao, and Lei Bai. "A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design." IEICE Electronics Express 18, no. 17 (September 10, 2021): 20210312. http://dx.doi.org/10.1587/elex.18.20210312.

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A. P. Khandait, Kshama N. Nikhade, Prof. "Low Power Enhanced Speed Dual Edge Pulse Triggered Flip-Flop Based On Signal Feedthrough Scheme." International Journal of Innovative Research in Computer and Communication Engineering 03, no. 06 (June 30, 2015): 5434–39. http://dx.doi.org/10.15680/ijircce.2015.0306042.

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Suresh, G., N. V. Lalitha, and R. Aamani. "Design and Implementation of 4 Bit Static RAM through Low-Power Pulse-Triggered Flip-Flop." International Journal of u- and e- Service, Science and Technology 8, no. 9 (September 30, 2015): 117–26. http://dx.doi.org/10.14257/ijunesst.2015.8.9.13.

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Razmdideh, Ramin, and Mohsen Saneei. "A novel low power and high speed double edge explicit pulse triggered level converter flip-flop." International Journal of Circuit Theory and Applications 43, no. 4 (October 24, 2013): 516–23. http://dx.doi.org/10.1002/cta.1959.

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Razmdideh, Ramin, Ali Mahani, and Mohsen Saneei. "New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption." Journal of Circuits, Systems and Computers 24, no. 10 (October 25, 2015): 1550159. http://dx.doi.org/10.1142/s0218126615501595.

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In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

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Gomathi, R., S. Gopalakrishnan, S. Ravi Chand, S. Selvakumaran, J. Jeffin Gracewell, and Kalivaraprasad B. "Design and Speed Analysis of Low Power Single and Double Edge Triggered Flip Flop with Pulse Signal Feed-Through Scheme." International Journal of Electrical and Electronics Research 10, no. 4 (December 30, 2022): 1107–14. http://dx.doi.org/10.37391/ijeer.100456.

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Flip flop is a fundamental electrical design component. Most electrical designs incorporate memory and their corresponding designs. The consumer electronics or end users need mobility and extended battery backup to enhance design performance. The focus on any parameter in the system is to maximize the performance of the design. Here the task is to reduce the energy use of flip flop. Due to the increased frequency clock delivered to the networks within the design, the edge or level triggered by a flip flop will contribute to power consumption. Due to the short circuit power consumption between ground and Vdd, the static design of the flip flop will increase power consumption. The flip flop is dynamically designed and implemented, leading to higher leakage power. Dynamic clock implementation helps for short-circuit power avoidance. It also provides greater download channel to the ground from output. The clocking system also demands more power. With the TSPC technology and output feedback, the suggested mechanic will increase the performance of the flip flop and establish the Pull-up network. The PMOS that contains the output node X value. The use of an additional NMOS transistor to draw the output value down to the ground, regardless of the input, so that the input runs on the discharge path that improves power, however the pulsed clock which has a smaller width than normal clock as well about 15% high.

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Gusev, A., I. Prudaev, I. Lavrinovich, A. de Ferron, B. M. Novac, and L. Pecastaing. "Subnanosecond switching of standard thyristors triggered in impact-ionization wave mode by a high-voltage PCSS driver." Journal of Physics: Conference Series 2064, no. 1 (November 1, 2021): 012120. http://dx.doi.org/10.1088/1742-6596/2064/1/012120.

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Abstract Power thyristors triggered in impact-ionization wave mode are capable to replace spark gap switches, bringing major advantages into repetitive pulsed power industrial applications. Low power thyristors remained for the moment out of the research focus, most likely because of the challenging driver, which must provide a sufficiently fast and powerful triggering pulse. This paper describes subnanosecond switching of standard off-the-shelf low-power thyristors in impact-ionization wave mode, running by the PCSS trigger generator based on the laser diode and GaAs switches. Several types of thyristors with a rated voltage from 0.6 kV to 2.2 kV have been tested running by both a commercial FID and by the tailored PCSS generators. The triggering and current flow stages were examined. For the 1.6 kV thyristor (TO-247 package), the following parameters have been obtained: switching time 250 ps, dI/dt up to 12 kA/μs, amplitude 85 A and FWHM about 60 ns. In this mode, the first 103 pulses have not revealed any thyristor degradation.

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KRESE, BLAŽ, MATJAŽ PERC, and EDVARD GOVEKAR. "EXPERIMENTAL OBSERVATION OF A CHAOS-TO-CHAOS TRANSITION IN LASER DROPLET GENERATION." International Journal of Bifurcation and Chaos 21, no. 06 (June 2011): 1689–99. http://dx.doi.org/10.1142/s0218127411029367.

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We examine the dynamics of laser droplet generation that is dependent on the detachment pulse power. In the absence of the detachment pulse, undulating pendant droplets are formed at the end of a properly fed metal wire due to the impact of the primary laser pulse that induces melting. Eventually, these droplets detach, i.e. overcome the surface tension, because of their increasing mass. We show that this spontaneous dripping is deterministically chaotic by using a positive largest Lyapunov exponent and a negative divergence. In the presence of the detachment pulse, however, the generation of droplets is fastened depending on the pulse power. At high powers, the spontaneity of dripping is completely overshadowed by the impact of the detachment pulse. Still, amplitude chaos can be detected, which similarly as the spontaneous dripping, is characterized by a positive largest Lyapunov exponent and a negative divergence, thus indicating that the observed dynamics is deterministically chaotic with an attractor as solution in the phase space. In the intermediate regime, i.e. for low and medium detachment pulse powers, the two chaotic states compete for supremacy, yielding an intermittent period-doubling to amplitude chaos transition, which we characterize by means of recurrence plots and their properties. Altogether, the transition from spontaneous to triggered laser droplet generation is characterized by a chaos-to-chaos transition with an intermediate dynamically nonstationary phase in-between. Since metal droplets can be used in various industrial applications, we hope that the accurate determination of the dynamical properties underlying their formation will facilitate their use and guide future attempts at mathematical modeling.

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Gottfried, Jacob A., Charles E. Rose, Sean Simpson, and Azer P. Yalin. "Collective Thomson scattering measurement of plasma evolution during the current pulse in a laser-triggered switch." Applied Physics Letters 121, no. 24 (December 12, 2022): 244101. http://dx.doi.org/10.1063/5.0131471.

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High-voltage laser-triggered switches (HV-LTSs) are used in pulsed-power applications where low jitter and precise timing are required. The switches allow operation in the megaampere, megavolt regime while maintaining low insertion losses. Currently, there is a lack of detailed plasma measurements in these switches, yet such measurements are needed to elucidate the detailed physics, which include a range of processes such as laser breakdown, streamer formation and growth, current flow, plasma evolution, and cooling. Detailed spatially- and temporally resolved measurements of plasma properties within the switches could contribute to validating and advancing numeric models of these systems. This contribution presents laser Thomson scattering measurements of the electron number density and temperature evolution in a HV-LTS. The switch was operated at 6 kV with current flow for a duration of 145 ns and a peak current density of 0.2 MA/cm2 into a matched load. The Thomson scattering diagnostic system uses a 532 nm probe from an Nd:YAG laser allowing a temporal resolution of ∼10 ns. We find that during the switch current pulse, the plasma electron temperature rose from a starting value of 8.1 ± 1.6 eV (due to cooling of the earlier trigger laser plasma) to a peak value of 26 ± 5 eV with an associated increase in the electron density from 8.6 ± 1.7 × 1017 to 3.1 ± 0.6 × 1018 cm−3.

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Sujita, B., and K. Padma Vasavi. "Low Power Area Efficient VLSI Architectures for Shift Register Using Explicit Pulse Triggered Flip Flop Based on Signal Feed-Through Scheme." IOSR Journal of VLSI and Signal Processing 06, no. 05 (May 2016): 33–41. http://dx.doi.org/10.9790/4200-0605013341.

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Badal, Mohammad, Mamun Reaz, Zinah Jalil, and Mohammad Bhuiyan. "Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag." Electronics 5, no. 4 (December 16, 2016): 92. http://dx.doi.org/10.3390/electronics5040092.

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Baginski, Thomas A., Robert N. Dean, and Steven P. Surgnier. "A New Robust One-Shot Switch for High-Power Pulse Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 001650–73. http://dx.doi.org/10.4071/2011dpc-wp21.

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High Voltage (HV) switches capable of operating at high speeds and over a wide range of voltages and energies are used in a variety of pulse power applications in material science and plasma physics. Of particular interest is the use of small-scale capacitor discharges to measure the electrical properties of materials as they are heated from solid through liquid to a gas phase. In a capacitive discharge unit (CDU), energy stored in a capacitor is coupled through a switch into a low-impedance transmission line, which typically terminates with a thin sample of material. The energy coupled to the sample is sufficient to cause vaporization. Voltages in such systems range from a few volts to thousands of volts. These vaporized materials are used either as plasma sources for physics experiments, or to propel a thin layer of electrically insulating polymer for high-pressure-impact studies. Several types of switches have been used to drive these systems, including triggered spark gap, dielectric breakdown, and mercury vapor switches. A wide variety of solid-state devices, such as the insulated gate bipolar transistors, are also being utilized for these applications. Inducing a high-pressure shock wave in a dielectric to produce a transition from dielectric to conductor has also been used as an efficient single-shot switch for capacitor discharges. The high-voltage micro-machined switch presented in this document has been designed as a single-use alternative to the more expensive triggered spark gaps and solid-stage devices. The plasma-bridge switch is intended for large-volume, relatively inexpensive systems, and a cost-effective switch for use in destructive testing.

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Yadav, Deepshikha, and Puneet Azad. "Design and Performance Comparison of Effect of Different Switching Sources on Thermoelectric Energy Harvesting Using Single-Inductor Boost Converters." ECS Transactions 107, no. 1 (April 24, 2022): 3855–62. http://dx.doi.org/10.1149/10701.3855ecst.

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This paper presents a comparison for the amount of power generated using different switching sources in a DC-DC boost converter designed to generate 3-5 V output voltage. The desired output voltage is sufficient to charge a rechargeable battery. The input voltage is supplied by a commercially available thermoelectric generator module (TEG) when subjected to appropriate temperature gradient. Three boost converter circuit configurations with gate pulse, square wave, and PWM switching sources are designed to step-up the low DC voltage of 0.2 V from thermoelectric energy harvester. The output voltage and current levels are measured for estimating the amount of increase in output power. Gate pulsed switching in boost converter generated a highest output voltage of 5.26 V, while square wave triggered circuit could generate maximum 3.5 V. PWM based switching generated an output voltage of 1.98 V for input supply of 0.2 V.

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Jinn-Shyan Wang, Po-Hui Yang, and Duo Sheng. "Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flops." IEEE Journal of Solid-State Circuits 35, no. 4 (April 2000): 583–92. http://dx.doi.org/10.1109/4.839918.

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Trinh, Hoai-An, Hoai-Vu-Anh Truong, and Kyoung Kwan Ahn. "Development of Fuzzy-Adaptive Control Based Energy Management Strategy for PEM Fuel Cell Hybrid Tramway System." Applied Sciences 12, no. 8 (April 12, 2022): 3880. http://dx.doi.org/10.3390/app12083880.

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Currently, the implementation of hybrid proton-exchange membrane fuel cell (PEMFC)-battery-supercapacitor systems for hybrid tramways to replace conventional internal combustion engines and reduce greenhouse gas emissions has triggered an upward trend in developing energy management strategies (EMSs) to effectively deploy this integration. For this purpose, this paper introduces a comprehensive EMS consisting of high-level and low-level controls to achieve appropriate power distribution and stabilize the operating voltage of the powertrain. In the high-level control, a fuzzy logic technique and adaptive control loop are proposed to determine the reference power for energy sources under different working conditions. Meanwhile, the low-level control aims to generate a pulse-width-modulation (PWM) signal for DC/DC converter, associated with each electric source, to regulate the device’s output performance and guarantee the DC bus voltage. Comparisons between the proposed strategy with available approaches are conducted to verify the effectiveness of the proposed EMS through MATLAB/Simulink environment. The simulation results confirm that the proposed EMS not only sufficiently ensures powers distribution even when the abrupt changes of load or high peak power, but also enhance the efficiency of the PEMFC, in which the PEMFC stack efficiency can be exhibited up to 53% with hydrogen consumption less than 21.4%. Moreover, the DC bus voltage can be regulated with a small ripple of around 1%.

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Chen, Xuemiao, Binqiang Luo, Xuping Zhang, Guiji Wang, Fuli Tan, Rongjie Shui, Chao Xu, et al. "A compact pulsed power driver with precisely shaped current waveforms for magnetically driven loading experiments." Review of Scientific Instruments 93, no. 8 (August 1, 2022): 083910. http://dx.doi.org/10.1063/5.0089939.

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Magnetically driven loading techniques based on high current pulsed power drivers are very important tools for researching material dynamic behaviors and high-pressure physics. Based on the technologies of a Marx generator energy storage and low impedance coaxial cable energy transmission, a compact high current pulsed power driver CQ-7 was developed and established at the Institute of Fluid Physics, China Academy of Engineering Physics, which can generate precisely shaped current waveforms for magnetically driven loading experiments. CQ-7 is composed of 256 two-stage Marx generators in parallel with low impedance, high voltage coaxial cables for current output. The 256 Marx generators are divided into 16 groups, and each separate group can be individually triggered to discharge and shape currents in sequence by a low jitter, high voltage pulse trigger with 16 output signals. The electrical parameters of CQ-7 are a capacitance of 20.48 µF, an inductance of 4.12 nH, and a resistance of 3.35 mΩ in a short circuit. When working at the charging voltage of ±40–±60 kV, CQ-7 can deliver a peak current from 5 to 7 MA to the short-circuit loads with a rising time of 400–700 ns at different discharging time sequences. Two different experiments were conducted to test the performance of CQ-7: magnetically driven high velocity flyer plates and solid liner implosion. The results show that CQ-7 can accelerate the aluminum flyer plate with a size of 12 × 8 × 1 mm3 to more than 7.5 km/s and uniformly drive the aluminum liner with an inner diameter of 6.2 mm and a thickness of 0.4 mm to more than 9.5 km/s. Furthermore, these experiments indicate that CQ-7 is a robust platform for material dynamics and high-pressure physics.

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Jones, F. H. M., B. B. Narod, and G. K. C. Clarke. "A Back-Portable Microprocessor-Based Impulse Radar System." Annals of Glaciology 9 (1987): 238. http://dx.doi.org/10.1017/s0260305500000732.

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We have developed and tested a portable impulse radar for ground-based sounding of glaciers. Noteworthy characteristics of the instrument are its portability, low power consumption, digital data storage, and the ability to be operated either manually or automatically under program control. Current system specifications include a band width of 46 MHz; a sampling interval of 10.76 ns; depth precision of 0.9 m; 1024 samples per record; amplitude resolution of 8 bits; minimum recordable signal at the receive antenna equal to 0.26 mV; an operating center frequency of 8.5 MHz and an antenna-damping coefficient of 300 ohms. The transmitter uses paired SCRs and a 12 V to 800 V converter to impress a 1200 V step on to a resistively damped dipole antenna. This pulse is triggered from the receiving system via a fibre optics cable so that each record can include the complete surface-path wavelet. The receiver unit combines a wide-band amplifier (with variable front-end attenuation) with a microprocessor-controlled data-acquisition system of our own design. The result of each sounding can be replayed as an “A-scope” display on a small, low-cost oscilloscope and stored on or retrieved from digital cassettes. In the unattended mode, records are collected at programmable intervals. The system weighs about 7.5 kg and uses dry cells or rechargeable batteries for power. Examples were presented in a poster session of sounding profiles taken in July 1986 on Trapridge Glacier, Yukon Territory in Canada, along lines coinciding with an extensive drilling program. Although not yet fully analysed, we feel that some of the results may represent the effects of crevasses, internal features such as morainal material, varying bed features, and changes in subglacial and englacial hydrology.

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Jones, F. H. M., B. B. Narod, and G. K. C. Clarke. "A Back-Portable Microprocessor-Based Impulse Radar System." Annals of Glaciology 9 (1987): 238. http://dx.doi.org/10.3189/s0260305500000732.

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We have developed and tested a portable impulse radar for ground-based sounding of glaciers. Noteworthy characteristics of the instrument are its portability, low power consumption, digital data storage, and the ability to be operated either manually or automatically under program control. Current system specifications include a band width of 46 MHz; a sampling interval of 10.76 ns; depth precision of 0.9 m; 1024 samples per record; amplitude resolution of 8 bits; minimum recordable signal at the receive antenna equal to 0.26 mV; an operating center frequency of 8.5 MHz and an antenna-damping coefficient of 300 ohms.The transmitter uses paired SCRs and a 12 V to 800 V converter to impress a 1200 V step on to a resistively damped dipole antenna. This pulse is triggered from the receiving system via a fibre optics cable so that each record can include the complete surface-path wavelet. The receiver unit combines a wide-band amplifier (with variable front-end attenuation) with a microprocessor-controlled data-acquisition system of our own design. The result of each sounding can be replayed as an “A-scope” display on a small, low-cost oscilloscope and stored on or retrieved from digital cassettes. In the unattended mode, records are collected at programmable intervals. The system weighs about 7.5 kg and uses dry cells or rechargeable batteries for power.Examples were presented in a poster session of sounding profiles taken in July 1986 on Trapridge Glacier, Yukon Territory in Canada, along lines coinciding with an extensive drilling program. Although not yet fully analysed, we feel that some of the results may represent the effects of crevasses, internal features such as morainal material, varying bed features, and changes in subglacial and englacial hydrology.

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Baginski, Thomas A., Robert N. Dean, and Ed J. Wild. "A Micromachined Robust Planar Triggered Sparkgap Switch for High Power Pulse Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 001869–86. http://dx.doi.org/10.4071/2010dpc-wp24.

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High voltage (HV) switches capable of operating at high speeds with high current levels are used in a variety of applications in commercial and government systems. Examples of HV switches include triggered sparkgap, dielectric breakdown, and mercury vapor switches. The triggered sparkgap switch is a three-element, gas-filled, ceramic-to-metal, hermetically sealed, pressurized switch that operates in an arc discharge mode. Triggered sparkgaps have been in use for many years, providing precision timing and activation of in-flight functions such as missile stage separation. These applications involve the activation of electro-explosive devices such as an exploding bridge-wire [EBW] or an exploding foil initiator [EFI]. This paper discusses the fabrication and characterization of a novel high voltage planar discharge switch using micromachining techniques. The switch provides a low cost alternative to conventional triggered sparkgaps. The switch is designed for direct integration into the strip-line geometries used in a conventional capacitive discharge unit (CDU). The geometry of the device was selected to minimize parasitic impedances associated with conventional firing circuits. The switch design is microfabricated on an alumina substrate utilizing a patterned electron-beam deposited metallic stack. A polyimide layer selectively deposited over the metal stack provides dielectric isolation and passivation for the switch electrodes. A similar methodology was utilized to fabricate sample EFIs for switch validation tests with insensitive secondary high explosive (HE) pellets. The discharging of the HV capacitor through the patterened bridgefoil of an EFI results in rapid vaporization of the metal stack. The high pressure gas formed by the vaporized metal accelerates the adjacent polyimide layer to high velocity. The polyimde layer then impacts the HE pellet, inducing a shock wave, which results in prompt detonation of the material. Thus, this device is a type of MEMS actuator with a very specialized use. Design, fabrication and test data are presented and discussed.

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Song, Young-Woong, Min-Kyu Song, Yoon Jeong Hyun, Daehwan Choi, and J. Y. Kwon. "Fluoropolymer Passivation Enhanced Switching Endurance of MoS₂ Memristors." ECS Meeting Abstracts MA2022-01, no. 18 (July 7, 2022): 1029. http://dx.doi.org/10.1149/ma2022-01181029mtgabs.

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The advances in computing and mobile devices have realized massive generation, collection, and processing of data. The concept "Internet of things" and "Big data" have necessiated large-scale parallel processing, as computing of collected data is highly dependent on matrix multiplication process, which in inherently parallel. In this context, conventional machines are exhibiting their limits as they are unsuited for parallel processing, resulting in low performance and high power consumption [1]. The need for advances in parallel processing hardware is emerging. In this regard, memristors have gathered attention for their high potentials as parallel processing units. There have been reports of memristors with high on/off ratio, fine retention, high switching enderance, and fast switching spped, etc [2-4]. Memristor is a non-volatile memory which stores data as internal resistance, modulated by applied voltage. Even though memristors contain high capabilities for parallel processing, scaling of devices still remain as a challenge. Conventional materials have their limit for both lateral and vertical scaling. To achieve a major breakthrough, we have fabricated memristors based on 2D materials with atomic-scale thickness of ~ 7 nm [5]. As surface-to-volume ratio is high in 2D materials, they are chemically active, leading to susceptible properties to external environment and instability in fabricated devices with 2D materials. To compensate the drawback, we applied fluoropolymer passivation layer and obtained stable switching endurance for 100 potentiation & depression cycles with 25 states. For device fabrication, we used direct current sputtering & wet etching to pattern bottom Au/Cr (50/5 nm) electrodes. Molybdenum disulfide flakes were mechanically exfoliated from bulk mineral and dry-transferred onto bottom electrodes by PDMS (Polydimethylsiloxane) stamps. Top electrodes were patterned by photolithography & evaporation of Ni/Au (5/100 nm). With the introduction of 2D materials to next-generation electronics, memristors can be even more revolutionized towards extreme scaling of devices. By compensating susceptibility in the material itself and studying degradation mechanism, parallel computing would be realized away from power-plugged environment, and accelerate artificial intelligence in our everyday lives. Figure Caption Fig 1. Electrical characterization of the resistive switching MoS2 memristor with non-volatile memory behavior. (a) Semi-log plots of IV curve, resistive switching triggered by voltage sweeping. Inset: False-color SEM image of a fabricated device; scale bar: 4μm. (b) Scheme for pulse voltages (top), potentiation and depression of conductance states (bottom). (c) Encapsulation-enhanced switching stability of MoS2 memristors. Detailed illustration of 20 PD cycles in CYTOP-encapsulated (top) and bare devices (bottom). References [1] J. Backus, Can programming be liberated from the von neumann style? A functional style and its algebra of programs, Commun. ACM 21 (1978) 613–641. [2] J.J. Yang, D.B. Strukov, D.R. Stewart, Memristive devices for computing, Nat. Nanotechnol., 8 (2013) 13–24. [3] C.H. Kim, S. Lim, S.Y. Woo, W.M. Kang, Y.T. Seo, S.T. Lee, S. Lee, D. Kwon, S. Oh, Y. Noh, H. Kim, J. Kim, J.H. Bae, J.H. Lee, Emerging memory technologies for neuromorphic computing, Nanotechnology 30 (2019) 032001. [4] M.-K. Song, S.D. Namgung, D. Choi, H. Kim, H. Seo, M. Ju, Y.H. Lee, T. Sung, Y.- S. Lee, K.T. Nam, J.-Y. Kwon, Proton-enabled activation of peptide materials for biological bimodal memory, Nat. Commun. 11 (2020) 5896. [5] Y.-W. Song, M.-K. Song, D. Choi, J.-Y. Kwon, Encapsulation-enhanced switching stability of MoS2 memristors, J. Alloys Compd. 885 (2021) 161016. Figure 1

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Zulkifli, Shamsul Aizam, Epha Yusriyanna Riyandra, Suriana Salimin, Ahmed Naji Zaidan, and Ronald Jackson. "Investigation of Multilevel Inverter for the Next Distributed Generation Using Low-Cost Microcontroller." International journal of electrical and computer engineering systems 10, no. 1 (December 20, 2019): 11–18. http://dx.doi.org/10.32985/ijeces.10.1.2.

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Nowadays, more research projects have described a converter that is widely used at the distributed generation (DG) level in order to increase the amount of electrical power generation. The converter is known as an inverter when only one DG source is used or as a multi-inverter when several DGs are used. Here, the application of a multilevel inverter with a C2000 microcontroller (Texas Instruments (TI) TMS320F28335 microcontroller), which can be implemented with a current feedback loop, is investigated. This microcontroller acts as a communication interface between MATLAB SIMULINK and the multilevel inverter. Meanwhile, the current control model is modeled in MATLAB for designing the control strategy. It is where the multilevel inverter switches are triggered by using pulse-width modulation (PWM) signals generated by the microcontroller output. At the same time, the proportional integral derivative (PID) current control is used in order to allow the load current to follow the reference current. Based on the results, it can be summarized that the multilevel inverter is a very useful device for the next DG sources when it is combined with current control for load current distribution. From this investigation, it can be seen that in the future DGs could be connected to a multilevel inverter structure, where it will reduce the dependency on filter design and have a more sinusoidal output to the load for different DG power ratings.

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M, MANJULA. "LOW-POWER HIGH PERFORMANCE PULSE-TRIGGERED FLIP-FLOP." International Journal of Computer and Communication Technology, October 2015, 228–32. http://dx.doi.org/10.47893/ijcct.2015.1309.

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In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple twotransistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various post layout simulation results based on UMC CMOS 90- nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate-based FF design, the average leakage power consumption is also reduced by a factor of 3.52.

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INDIRA, T., and CH JAYAPRAKASH. "DESIGN OF LOW POWER AND HIGH PERFORMANCE PULSE TRIGGERED FLIP FLOP USING CONDITIONAL PULSE ENHANCEMENT METHOD." International Journal of Electronics and Electical Engineering, April 2015, 226–32. http://dx.doi.org/10.47893/ijeee.2015.1160.

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In this paper, a novel low-power high performance pulse-triggered flip-flop using conditional pulse enhancement design method is presented. Our proposed design is Enhanced Pulse Triggered Low-power Flip Flop (EPTLFF). It design is done by the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. The EPTLFF avoids unnecessary internal node transitions to reduce power consumption. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various layout simulation results comparison between previously reported design and modified design is based on 90nm and 50nm technology. The proposed design features the best power-delay-product performance in five FF designs under comparison. Its maximum power saving compared to the conventional P-FF designs is up to 18.6%.

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INDIRA, T., and CH JAYAPRAKASH. "DESIGN OF LOW POWER AND HIGH PERFORMANCE PULSE TRIGGERED FLIP FLOP USING CONDITIONAL PULSE ENHANCEMENT METHOD." International Journal of Electronics and Electical Engineering, April 2015, 226–32. http://dx.doi.org/10.47893/ijeee.2015.1160.

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In this paper, a novel low-power high performance pulse-triggered flip-flop using conditional pulse enhancement design method is presented. Our proposed design is Enhanced Pulse Triggered Low-power Flip Flop (EPTLFF). It design is done by the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. The EPTLFF avoids unnecessary internal node transitions to reduce power consumption. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various layout simulation results comparison between previously reported design and modified design is based on 90nm and 50nm technology. The proposed design features the best power-delay-product performance in five FF designs under comparison. Its maximum power saving compared to the conventional P-FF designs is up to 18.6%.

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"Low Power and High Performance MTCMOS Conditional Discharge Flip Flop." International Journal of Engineering and Advanced Technology 8, no. 6S2 (October 10, 2019): 341–45. http://dx.doi.org/10.35940/ijeat.f1093.0886s219.

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Utilization in high-performance integrated circuits has been one of the most severe limitations in models in recent years.. Conditional discharge flip flop (CDFF) related to one of the earliest pulses caused flipflop reduces internal switching activities as that of existing explicit pulse triggered Data close to output flipflop (Ep-DCO). Registers are the main parts for processing information eg: in counters, accumulators etc.,. Implementation of these registers using CDFF can achieve low power consumption and high performance. MTCMOS (multi threshold CMOS) technique saves the leakage power during standby mode operations and hence, enhances the circuit performance for long battery life applications. We find that, using both MTCMOS and conditional discharge technique in flip flop, improves the performance and also consumes low power. In this paper, we simulate CDFF and the proposed MTCMOS CDFF to prove that MTCMOS CDFF is the best among the fastest pulse triggered flipflops. We also implement an application 4 bit shift register using proposed MTCMOS conditional discharge flip flop

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Raja, G. Abhinaya, and P. Srinivas. "Asynchronous Model of Flip-Flop’s and Latches for Low Power Clocking." International Journal of Computer and Communication Technology, April 2016, 106–10. http://dx.doi.org/10.47893/ijcct.2016.1348.

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There is a wide selection of flip-flops in the literature. Many contemporary microprocessors selectively use master-slave and pulsed-triggered flip-flops. Transmission gated flip-flop, are made up of two stages, one master and one slave Alternatively, pulse-triggered flip-flops reduce the two stages into one stage and are characterized by the soft edge property. The concepts discussed in the related work are related to synchronous design’s novel method for low power dissipation asynchronous methods have been improving so as to reduce the power consumption an asynchronous methods for flip-flops are being implemented.

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"DESIGN OF LOW POWER PULSE TRIGGERED DUAL DYNAMIC FLIP FLOP BASED ON A SIGNAL FEED-THROUGH SCHEME." International Journal of Advance Engineering and Research Development 3, no. 04 (April 30, 2016). http://dx.doi.org/10.21090/ijaerd.030448.

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Witanachchi, S., P. Mahawela, and P. Mukherjee. "A Hollow-Cathode Transient Plasma Process for Thin Film Growth." MRS Proceedings 616 (2000). http://dx.doi.org/10.1557/proc-616-235.

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AbstractWe have developed a vapor deposition method that produces a highly ionized transient plasma plume of metallic species in the presence of a low-pressure inert or reactive gas glow discharge. In this process, a transient electrical discharge is formed in a hollow-cathode by a pulse-forming network (PFN) which is triggered by a pulsed CO2 laser. Current pulses with peak currents of 100 kA and pulse widths of about 20 ms have been produced by the PFN. The effect of the PFN power input and the ambient gas pressure on the evaporated material yield is presented. These experiments also showed a higher evaporation rate of carbon in a nitrogen ambient than in an Ar ambient. Carbon films, with rates of deposition exceeding 18A per pulse that are uniform over a large area, have been deposited. The ionic content of the plasma, spatial distribution of ions, and plume expansion dynamics have been investigated by time-of-flight ion probe measurements and optical emission spectroscopy and are presented.

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Schmidt, Ehud J., Hassan Elahi, Ryan Baumgaertner, and Henry R. Halperin. "Abstract 14089: Reduced Pain External Defibrillation (RPD) and MRI-conditional RPD: Reduced Pain ind Equivalent Efficiency Validation in Swine." Circulation 142, Suppl_3 (November 17, 2020). http://dx.doi.org/10.1161/circ.142.suppl_3.14089.

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Introduction: External defibrillators are used for cardioversion and resuscitation after sudden cardiac arrest (SCA). External defibrillators are also required for emergency MRI (acute stroke, spinal trauma). Low-power (9 Joule) ICD RPDs [1], and MRI-conditional external defibrillator prototypes exist [2]. An RPD external defibrillator was constructed, consisting of a Zoll defibrillator integrated with a tetanizing unit. The tetanizing waveform slowly compressed chest musculature prior to the strong biphasic defibrillating pulse, reducing chest contraction during the biphasic pulse, the major pain source. This RPD system (Fig. 1A-D) was evaluated for pain reduction and defibrillation effectiveness in swine. Method: The tetanizing unit consisted of a programmable generator that delivered a triangular 1-KHz pulse of 250-2000msec duration and 10-100 Volt peak amplitude, and subsequently triggered the conventional defibrillator to send out standard short (8msec) powerful (20-400 J) biphasic pulses. Forward limb motion (Fig. 1E), an established pain measure [3], was evaluated by measuring limb acceleration, acceleration rate and work (energy). 5 swine were arrested electrically and then defibrillated. RPD was repeated 15-20 times/swine, varying tetanizing parameters and biphasic energy. Results: Fig. 1F-H compare an RPD defibrillation and equivalent biphasic defibrillation, showing smaller accelerations and acceleration rates. Fig. 1J shows work results, at 30-200J biphasic energy, demonstrating an 83 + 15% limb work reduction with the RPD waveforms. Optimal tetanizing parameters were 15-25V amplitude and 500-750msec duration. Rhythm recovery for RPD and conventional defibrillation was identical. Conclusions: Reduced pain defibrillation may allow cardioversion without anesthesia and faster defibrillation after SCA. References: [1] Hunter DW 2016. [2] Schmidt EJ 2016. [3] Boriani G, 2005.

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Vijayarangan, Vinodini, Sébastien Dozias, Catherine Heusèle, Olivier Jeanneton, Carine Nizard, Chantal Pichon, Jean Michel Pouvesle, Augusto Stancampiano, and Eric Robert. "Boost of cosmetic active ingredient penetration triggered and controlled by the delivery of kHz plasma jet on human skin explants." Frontiers in Physics 11 (April 11, 2023). http://dx.doi.org/10.3389/fphy.2023.1173349.

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This work reports on the demonstration of the penetration of cosmetic active ingredients (caffeine and hyaluronic acid) in human skin explants following safe and controlled plasma jet exposure. First, temperature increase and immunohistochemistry in the stratum corneum and epidermis were characterized to check the safe delivery of plasma jets and to select two operation regimes at 1 and 20 kHz. Plasma exposure for tens of seconds is shown to induce transient modulations of skin pH, transepidermal water loss, and skin wettability, revealing a reversible skin barrier function modulation. Then, it is demonstrated that plasma exposure significantly accelerates the penetration of active ingredients. The tuning of the plasma jet pulse repetition rate allows controlling the penetration kinetics. Such ex vivo results agree with previous in vitro experiments also exhibiting a transient permeabilization time window. A preliminary demonstration of human skin wettability modulation with a low-power, user-friendly dielectric barrier discharge setup is documented, opening perspectives for plasma-based home cosmetic care device development. To the best of our knowledge, this work is one of the first demonstrations of safe and controlled plasma-assisted active ingredients’ skin penetration in the context of cosmetic applications.

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Journal articles on the topic 'LOW-POWER PULSE-TRIGGERED'

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