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Academic literature on the topic 'LOW-POWER PULSE-TRIGGERED'

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Published: 11 September 2023

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Journal articles on the topic "LOW-POWER PULSE-TRIGGERED"

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Karimi, Ahmad, Abdalhossein Rezai, and Mohammad Mahdi Hajhashemkhani. "Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop." IEEE Transactions on Nanotechnology 18 (2019): 756–61. http://dx.doi.org/10.1109/tnano.2019.2929233.

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HU, YINGBO, and RUNDE ZHOU. "LOW CLOCK-SWING TSPC FLIP-FLOPS FOR LOW-POWER APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 01 (February 2009): 121–31. http://dx.doi.org/10.1142/s0218126609004971.

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In this paper, two types of Low Clock-Swing True Single Phase Clock (TSPC) Flip-Flops suitable for low-power applications are proposed. One is Low Clock-Swing Edge-Triggered TSPC Flip-Flop (LCSETTFF), constructed with a negative TSPC split out latch and a positive TSPC split out latch. The other is Low Clock-Swing Pulse-Triggered TSPC Flip-Flop (LCSPTTFF), developed in several styles. A double-edge triggered pulse generator is also developed for LCSPTTFF. With low threshold voltage clock transistors adopted, great power efficiency can be obtained in the clock network. Both types of Flip-Flops have advantages of simple structure, low power and much lower clock network power dissipation. All proposed circuits are simulated in HSPICE with 0.18 μm CMOS technology. Simulation results show that the power of LCSETTFF can be reduced by 42%, while the power dissipation, Power-Delay Product (PDP) and Area-Power-Delay Product (APDP) of LCSPTTFF can be reduced by 45–60%, 11–27% and 58–65%, respectively. In addition, the power consumptions of clock network of LCSPTTFF and LCSETTFF are estimated to be reduced by 78% and 56%, respectively, compared with conventional Flip-Flops.
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Hwang, Yin-Tsung, Jin-Fa Lin, and Ming-Hwa Sheu. "Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 2 (February 2012): 361–66. http://dx.doi.org/10.1109/tvlsi.2010.2096483.

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S, Vinothini Jane, Senthilkumar J. P, and Ravi G. "Improved low power implicit pulse triggered flip-flop with reduced power dissipation." International Journal of Computational Complexity and Intelligent Algorithms 1, no. 1 (2018): 1. http://dx.doi.org/10.1504/ijccia.2018.10021267.

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Ravi, G., J. P. SenthilKumar, and S. Vinothini Jane. "Improved low power implicit pulse triggered flip-flop with reduced power dissipation." International Journal of Computational Complexity and Intelligent Algorithms 1, no. 2 (2019): 145. http://dx.doi.org/10.1504/ijccia.2019.103746.

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Verma, Shreya, Tunikipati Usharani, S. Iswariya, and Bhavana Godavarthi. "Implementation of MHLFF based low power pulse triggered flip flop." International Journal of Engineering & Technology 7, no. 1.1 (December 21, 2017): 483. http://dx.doi.org/10.14419/ijet.v7i1.1.10150.

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The present research paper proposes to implement a low power pulse-triggered flip-flop. The proposed design is MHLFF (modified hybrid latch flip-flop). In MHLFF method, the pulse generator will be altered concerning illustration inverters what’s more a pasquinade transistor. This technique will be comparative should understood kind about flip flop what’s more it utilizes a static lock structure. Should succeed Most exceedingly bad situation delay issue brought on Eventually Tom's perusing discharging way comprise from claiming three stacked transistor MHLFF may be presented. We can minimize the power and delay when compared to the existing models i.e, CDFF and SCDFF. The circuit was implementing using Cadence Virtuoso tool in 90-nm and 45-nm technology.
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Lokhande, Vinay R., and Sagar P. Soitkar. "Low Power Positive Edge Triggered Pulse Generater Using Ring Oscillator." Journal of Computational Intelligence and Electronic Systems 5, no. 1 (March 1, 2016): 54–57. http://dx.doi.org/10.1166/jcies.2016.1130.

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Mr. Kankan Sarkar. "Design and analysis of Low Power High Speed Pulse Triggered Flip Flop." International Journal of New Practices in Management and Engineering 5, no. 03 (September 30, 2016): 01–06. http://dx.doi.org/10.17762/ijnpme.v5i03.45.

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The main important aspect is to outline a high speed and utilization of low power pulse triggered flip-flop and simulate the same. Also, we have to minimize leakage in the consumption of power in a flip-flop by employing pulse triggering technique that is adopted for clocks. Here, to solve the problem in the discharging path of the similar flip flop implementations, we employ signal feed through technique. The discharge time is reduced by the proposed method. This design out performs all the other similar pulse triggered flip flop implementation both in speed and power consumption. Now, it is implemented by employing Cadence Virtuoso Schematic Composer in 90nm GPDK. Simulation is done by a simulator known as Spectre.
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Jyothula, Sudhakar. "Low power aware pulse triggered flip flops using modified clock gating approaches." World Journal of Engineering 15, no. 6 (December 3, 2018): 792–803. http://dx.doi.org/10.1108/wje-09-2017-0309.

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PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.
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kaala, D. S. R. Krishna. "Design of Low Power Negative Pulse-Triggered Flip-Flop with Enhanced Latch." IOSR Journal of VLSI and Signal Processing 3, no. 3 (2013): 06–12. http://dx.doi.org/10.9790/4200-0330612.

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Dissertations / Theses on the topic "LOW-POWER PULSE-TRIGGERED"

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Renukaiah, Vishwas. "Low-power pulse-triggered flip-flop design based on a signal feed-through scheme." Thesis, California State University, Long Beach, 2015. http://pqdtopen.proquest.com/#viewpdf?dispub=1601314.

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In this project, a novel pulse-triggered flip-flop design is proposed, which employs a modified True Single Phase Clock (TSPC) latch structure with a mixed style design consisting of pass transistor and pseudo nMOS logic. The proposed flip-flop design adopts a signal feed-through technique to improve the delay recovery, and achieves better performance in terms of speed and power consumption. The proposed flip-flop design has a weak pull-up pMOS transistor with gate connected to the ground in the first stage of TSPC latch. This structure is a pseudo nMOS logic style design. Post layout simulation results using CMOS 120nm technology affirms that in the proposed design delay is reduced when compared to existing system.

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KUMAR, VICKY. "STUDY OF LOW-POWER PULSE-TRIGGERED FLIP-FLOPS." Thesis, 2017. http://dspace.dtu.ac.in:8080/jspui/handle/repository/16014.

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Flip-flops and latches are important elements of a digital system design in terms of both a delay and energy stand point. The choice of flip-flop implementation is of essential importance in design of VLSI integrated circuits for high speed, low power and high performance CMOS circuits. In this work, low-power pulse triggered flip-flop (P-FF) designs namely Explicit Type Data-close-to-output (ep-DCO), Conditional Discharge Flip-flop (CDFF), static CDFF and a true single phase clock latch based on a signal feed-through scheme (SFTFF) are studied. Former three fall under conventional P-FF and have limitation of long discharging path issue whereas SFTFF design successfully resolves this and achieves better speed and power performance. The timing parameters for Simulation results are obtained using PTM BSIM4 CMOS 90-nm technology, SFTFF design performs better than the conventional P-FF designs in view of data-to-Q delay.
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Cho, Yu-Ru, and 卓育儒. "Design and application of low power pulse-triggered flip-flops." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/42558328998390817052.

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碩士
國立雲林科技大學
電子與資訊工程研究所
97
Low power design of VLSI circuits has been identified as a critical technological need. The power consumption of the clock system, which consists of the clock distribution networks and storage elements, is estimated as about 20% to 45% of the total system power. As a result, reducing the power consumed by flip flops has a huge impact on the total power consumption. In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF rich modules such as register file, shift register and FIFO. FFs thus contribute a significant portion of gate count and power consumption to the overall system design. In this thesis, a novel low power pulse-triggered based flip-flop is presented. By using a 2-transistor AND gate to control the pulse generation, the critical path of the design is effectively shortened. A conditional pulse enhancement technique is further incorporated to achieve a faster discharging along the critical path. Both design measures facilitate smaller transistor sizes in delay inverter and pulse generation circuit, which lead to better power performance against rival designs. Various post-layout simulation results based on UMC CMOS 90nm process technology reveal that, the proposed design can achieve over 17% saving in term of power and power-delay-product when compared with previous pulse-triggered based flip-flop designs. The reduction in leakage power consumption is as high as a factor of 2.4 due to the shrunken transistor size.
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Wang, Peng-Siang, and 王鵬翔. "Low Power Pulse-Triggered Flip-Flops Designs with Hybrid Logic Style." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/04631727021339755036.

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碩士
國立雲林科技大學
電子與資訊工程研究所
99
In recent years, power consumption is important issue on System on Chip and Very Large Scale Integration design. Besides the portable electronic products are indispensable on our life so that low-power IC design technique becomes a major trend. The clock system consists clock distribution network and storage elements (Flip-Flops、Latches), in which, storage elements power consumption account total power about 20~45% power of clock system. Therefore if we would reduce the flip-flops power consumption, the overall system could gain huge efficient on power consumption. Proposed circuits use a Hybrid-Logic technique that merge the PTL Logic to flip-flop successfully reduce the transistor counts and speed up the data propagation time and we employ TSMC 90nm and UMC 90nm to verify the proposed design performance, in dynamic latch part proposed design improved the PDP 25.9% and 27.94% respectively, further, in static latch part improved the PDP 12.6% and 11.68% respectively.
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Li, Miao-Shan, and 李妙善. "Low power pipelined array multiplier design using delay line controlled dynamic adders and embedded pulse triggered FFs." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/82705044381793041937.

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Pontikakis, Bill. "A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications." Thesis, 2003. http://spectrum.library.concordia.ca/2311/1/MQ83874.pdf.

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Clocking is an important aspect of digital VLSI system design. The design of high-performance and low-power clocked storage elements is essential and critical to achieving maximum levels of performance and reliability in modern VLSI systems such as Systems on Chips (SoCs). In this thesis, a pulse-clocked double edge-triggered D-flip-flop (PDET) is proposed. PDET uses a new split-output true single-phase clocked (TSPC) latch and when clocked by a short pulse train acts like a double edge-triggered flip-flop. The P-type version of the new TSPC split-output latch is compared with existing TSPC split-output latches in terms of robustness, area, and power efficiency at high-speeds. It is shown that the new split-output latch is more area-power efficient, and significantly more robust, than the existing split-output CMOS latches. The novel double edge-triggered flip-flop uses only eight transistors with only one N-type transistor being clocked. Compared to other double edge-triggered flip-flops, PDET offers advantages in terms of speed, power, and area. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Period-Power product is reduced by 56%-63% compared to other double edge-triggered flip-flops. Simulations are performed using HSPICE in CMOS 0.5 om technology. This design is suitable for high-speed, low-power CMOS VLSI design applications.
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Book chapters on the topic "LOW-POWER PULSE-TRIGGERED"

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Ma, Junjun, Fei Qiao, Huazhong Yang, and Hui Wang. "A PVT-Aware and Low Power Pulse-Triggered Flip-Flop." In Lecture Notes in Electrical Engineering, 11–20. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-5076-0_2.

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Sakthivel, Erulappan, and Rengaraj Madavan. "MAS: Maximum Energy-Aware Sense Amplifier Link for Asynchronous Network on Chip." In Network-on-Chip [Working Title]. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.95075.

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A real-time multiprocessor chip model is also called a Network-on-Chip (NoC), and deals a promising architecture for future systems-on-chips. Even though a lot of Double Tail Sense Amplifiers are used in architectural approach, the existing DTSA with transceiver exhibits a difficulty of consuming more energy than its gouged design during various traffic condition. Novel Low Power pulse Triggered Flip Flop with DTSA is designed in this research to eliminate the difficulty. The Traffic Aware Sense amplifier MAS consists of Sense amplifiers (SA’s), Traffic Generator, and Estimator. Among various SA’S suitable (DTSA and NLPTF -DTSA) SA are selected and information transferred to the receiver. The performance of both DTSA with Transceiver and NLPTF-DTSA with transceiver compared under various traffic conditions. The proposed design (NLPTF-DTSA) is observed on TSMC 90 nm technology, showing 5.92 Gb/s data rate and 0.51 W total link power.
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Conference papers on the topic "LOW-POWER PULSE-TRIGGERED"

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Samal, Lopamudra, Sauvagya Ranjan Sahoo, and Chiranjibi Samal. "A novel modified low power pulse triggered flip-flop." In 2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT). IEEE, 2017. http://dx.doi.org/10.1109/iceeccot.2017.8284552.

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Indira, P., and M. Kamaraju. "Low Power PVT robust area efficient pulse triggered Flip-Flop Design." In 2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE). IEEE, 2018. http://dx.doi.org/10.1109/icrieece44171.2018.9009201.

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Zhao Xianghong, Guo Jiankang, and Song Guanghui. "An improved low-power clock-gating pulse-triggered JK flip-flop." In 2010 International Conference on Information, Networking and Automation (ICINA 2010). IEEE, 2010. http://dx.doi.org/10.1109/icina.2010.5636463.

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Anjaneyulu, O., A. Veena, C. H. Shravan, and C. V. Krishna Reddy. "Self driven pass-transistor based low-power pulse triggered flip-flop design." In 2015 International Conference on Signal Processing And Communication Engineering Systems (SPACES). IEEE, 2015. http://dx.doi.org/10.1109/spaces.2015.7058266.

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Guang-Ping Xiang, Ji-Zhong Shen, Xue-Xiang Wu, and Liang Geng. "Design of a low-power pulse-triggered flip-flop with conditional clock technique." In 2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2013. http://dx.doi.org/10.1109/iscas.2013.6571797.

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Lin, Jin-Fa, Ming-Hwa Sheu, and Peng-Siang Wang. "A low power dual-mode pulse triggered flip-flop using pass transistor logic." In 2010 International Symposium on Next-Generation Electronics (ISNE). IEEE, 2010. http://dx.doi.org/10.1109/isne.2010.5669163.

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Parakundil, Liaqat Moideen, and N. Saraswathi. "Low power pulse triggered D-flip flops using MTCMOS and Self-controllable voltage level circuit." In 2014 International Conference on Advanced Communication, Control and Computing Technologies (ICACCCT). IEEE, 2014. http://dx.doi.org/10.1109/icaccct.2014.7019139.

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Kavali, Krishna, S. Rajendar, and P. Vamshi Bhargava. "A novel low power double edge triggered flip-flop based on clock gated pulse suppression technique." In 2015 International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO). IEEE, 2015. http://dx.doi.org/10.1109/eesco.2015.7253849.

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Aguirre-Hernandez, M., and M. Linares-Aranda. "A Clock-Gated Pulse-Triggered D Flip-Flop for Low-Power High-Performance VLSI Synchronous Systems." In 2006 International Caribbean Conference on Devices, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/iccdcs.2006.250876.

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Weiner, A. M., Y. Silberberg, H. Fouckhardt, D. E. Leaird, M. A. Saifi, M. J. Andrejco, and P. W. Smith. "Avoidance of Pulse Break-up in All-Optical Switching by Using Femtosecond Square Pulses." In Nonlinear Guided-Wave Phenomena. Washington, D.C.: Optica Publishing Group, 1989. http://dx.doi.org/10.1364/nlgwp.1989.pd5.

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All-optical switching devices may play an important role in future highspeed communications systems. Recently we demonstrated switching of 100-fsec pulses by a dual-core fiber all-optical switch [1]. One problem associated with short pulse operation of the dual-core fiber switch, or any all-optical switch triggered by instantaneous intensity, is pulse break-up: switching can occur within a pulse, so that low and high intensity portions of the same pulse are directed to different output ports [1,2]. Proposals have been made to solve the pulse break-up problem by using solitons [3]. A simpler solution is to use square optical pulses, in which the intensity across the pulse is constant, except for finite rise and fall times. Here we report the first application of femtosecond square pulses to avoid pulse break-up in alloptical switching. As a result we obtain enhanced power transfer and a sharper switching transition.
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