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Journal articles on the topic 'LOW POWER PERFORMANCE'

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Author: Grafiati

Published: 11 September 2023

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1

Cao, Qiang, Jiang Jiang, Chang Wang, and Yongxin Zhu. "FPGA Implementation of High Performance and Low Power VOD Server." International Journal of Future Computer and Communication 3, no. 3 (2014): 148–52. http://dx.doi.org/10.7763/ijfcc.2014.v3.286.

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2

Wu, A., and C. K. Ng. "High performance low power low voltage adder." Electronics Letters 33, no. 8 (1997): 681. http://dx.doi.org/10.1049/el:19970464.

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3

Han, Wei, Ahmet T. Erdogan, Tughrul Arslan, and Mohd Hasan Hasan. "High-Performance Low-Power FFT Cores." ETRI Journal 30, no. 3 (June 9, 2008): 451–60. http://dx.doi.org/10.4218/etrij.08.0107.0189.

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4

Deininger, W. D., G. Cruciani, and M. J. Glogowski. "Performance comparisons of low-power arcjets." Journal of Propulsion and Power 11, no. 6 (November 1995): 1368–71. http://dx.doi.org/10.2514/3.23982.

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5

Xu, Ning, Zhoughua Jiang, and Feng Huang. "Performance and Low Power Driven Floorplanning." Journal of Algorithms & Computational Technology 1, no. 2 (June 2007): 161–69. http://dx.doi.org/10.1260/174830107781389058.

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6

Yoshikawa, Masaya, and Hidekazu Terai. "Performance Driven Placement Procedure for Low Power." IEEJ Transactions on Electronics, Information and Systems 124, no. 1 (2004): 18–25. http://dx.doi.org/10.1541/ieejeiss.124.18.

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7

Andrew, R., and K. Venos. "Multiphase synchronous circuits for low power performance." Microelectronics Journal 29, no. 3 (March 1998): 105–11. http://dx.doi.org/10.1016/s0026-2692(97)00034-7.

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8

Yoshikawa, Masaya, and Hidekazu Terai. "Performance-driven placement procedure for low power." Electrical Engineering in Japan 151, no. 1 (2005): 56–65. http://dx.doi.org/10.1002/eej.20057.

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9

Vallem, Dr Sharmila, G. Tejaswi, Hrithik Sidharth, and Shilpa Reddy. "High Performance, Low Power Wallace Tree Multiplier." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 2 (July 30, 2023): 20–25. http://dx.doi.org/10.35940/ijrte.b7685.0712223.

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An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI applications is multipliers. To enhance the performance of circuits and systems, the design of multipliers is very important. The key feature of a high-performance Wallace tree multiplier lies in its efficient reduction of partial product additions. By utilising a combination of carry-save and carry-propagate adders, it minimises the critical path delay and maximises the speed of multiplication. Additionally, advanced optimisation techniques such as parallel prefix adders and parallel carry-save adders can be employed to further improve performance.

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10

Asna, M., H. Shareef, S. N. Khalid, A. O. Idris, A. N. Aldarmaki, and Basil Hamed. "Universal power converter for low power applications." International Journal of Power Electronics and Drive Systems (IJPEDS) 10, no. 4 (December 1, 2019): 2165. http://dx.doi.org/10.11591/ijpeds.v10.i4.pp2165-2172.

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A novel power converter that can perform both voltage and frequency conversion was proposed. Inappropriate power supply can damage sensitive sub-components and render the connected device inoperable. Henceforth, the proposed voltage–frequency converter acts as an interface to plug any electrical device directly into an electrical socket and provide the voltage and frequency required. The converter used a synchronous reference frame proportional–integral (SRFPI) controller to regulate the instantaneous output voltage and to improve steady state performance. Because the PI controller works together with the synchronous reference frame controller, it is difficult to tune the PI control parameters. To overcome this issue, a new meta heuristic optimization technique called lightening search algorithm (LSA) optimization was used to identify the optimum PI parameter values. A detailed description of the system operation and control strategy was presented. Finally, the performance of the converter was analyzed and verified by simulation and experimental results. The experimental result has shown that the proposed system has satisfactory output voltage and frequency under different input voltages.

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11

Srivastava, Richa, Urvashi Singh, Maneesha Gupta, and Devesh Singh. "Low-voltage low-power high performance current mode fullwave rectifier." Microelectronics Journal 61 (March 2017): 51–56. http://dx.doi.org/10.1016/j.mejo.2017.01.004.

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12

STORNELLI, VINCENZO. "LOW VOLTAGE LOW POWER FULLY DIFFERENTIAL BUFFER." Journal of Circuits, Systems and Computers 18, no. 03 (May 2009): 497–502. http://dx.doi.org/10.1142/s0218126609005319.

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In this paper a useful CMOS fully-differential buffer topology is presented. The proposed solution, performing the common mode feedback operation, shows a rail-to-rail characteristic, so it is particularly suitable for low-voltage (± 0.75 V) low-power (< 400 μW) applications. The simulated results have shown excellent general performance, evaluated in terms of suitable figures of merit.

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13

Tajalli, A., M. Alioto, and Y. Leblebici. "Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits." IEEE Transactions on Circuits and Systems II: Express Briefs 56, no. 2 (February 2009): 127–31. http://dx.doi.org/10.1109/tcsii.2008.2011603.

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14

Manyam, Venkata Narasimha, Dang-Kièn Germain Pham, Chadi Jabbour, and Patricia Desgreys. "A low-power high-performance digital predistorter for wideband power amplifiers." Analog Integrated Circuits and Signal Processing 97, no. 3 (June 27, 2018): 483–92. http://dx.doi.org/10.1007/s10470-018-1263-9.

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15

Cai, Wei, Cheng Li, and Heng Gu. "LOW POWER SI-BASED POWER AMPLIFIER FOR HEALTHCARE APPLICATION." International Journal of Pharmacy and Pharmaceutical Sciences 8, no. 9 (September 1, 2016): 307. http://dx.doi.org/10.22159/ijpps.2016v8i9.12141.

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<p><strong>Objective: </strong>The objective of this research was to design a 2.4 GHz class B Power Amplifier (PA), with 0.18um Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence software, for health care applications. The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design.</p><p><strong>Methods: </strong>This paper introduces the design of a 2.4GHz class B power amplifier designed as dual gate topology. This class B power amplifier could transmit 26dBm output power to a 50Ω load. The power added efficiency was 60% minimum and the power gain was 90dB, the total power consumption was 6.9 mW.</p><p><strong>Results:</strong> Besides, accurate device modeling, is needed, due to the leakage and process variations.</p><p><strong>Conclusion</strong>:<strong> </strong>The performance of the power amplifier meets the specification requirements of the desired.</p>

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16

Marimuthu, C. N., and P. Thangaraj. "Transmission Gate based High Performance Low Power Multiplier." Journal of Applied Sciences 10, no. 23 (November 15, 2010): 3051–59. http://dx.doi.org/10.3923/jas.2010.3051.3059.

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17

S.Kavale, Anupa, Prof Dinesh Rotake, and Prof M. M. Mahajan. "Performance Analysis of Low Power Bypassing-Based Multiplier." IOSR journal of VLSI and Signal Processing 4, no. 4 (2014): 53–58. http://dx.doi.org/10.9790/4200-04415358.

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18

S, Amulya. "Low Power, High Performance PMOS Biased Sense Amplifier." International Journal for Research in Applied Science and Engineering Technology 10, no. 7 (July 31, 2022): 1763–69. http://dx.doi.org/10.22214/ijraset.2022.45257.

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Abstract: The capacity, functionality, dependability, and durability of the memory sense circuits in the basic cell are all significantly impacted by sense amplifiers in the proposed experiment. We will create two novel circuits that have been suggested in this presentation. This project's suggested circuit is a PMOS biassed sense amplifier with a basic cell that has a high output impedance and reduces the circuit's sensing latency as well as its power dissipation. As a result, the developed circuit executes operations similarly to those of parallel circuits, reducing the sense latency and circuit power consumption. The performance of one of the recommended sense amplifiers may then be verified by simulation utilizing Tanner EDA and CTSA and 180nm technology, leading to a sense decoder employing advanced technology in the technique.

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19

Sakthivel, R., M. Vanitha, and Harish M Kittur. "Modified Low Power Dynamic Adder for High Performance." International Journal of Computer Applications 18, no. 1 (March 31, 2011): 43–47. http://dx.doi.org/10.5120/2310-1822.

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20

Vidhate, Ashok D., and Shruti Suman. "Low Power High Performance Current Mirror – A Review." Journal of Physics: Conference Series 1804, no. 1 (February 1, 2021): 012161. http://dx.doi.org/10.1088/1742-6596/1804/1/012161.

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21

Fujita, Kazuhisa, and Yoshihiro Arakawa. "Performance Computation of a Low-Power Hydrogen Arcjet." Journal of Propulsion and Power 15, no. 1 (January 1999): 144–50. http://dx.doi.org/10.2514/2.5403.

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22

Ueno, T. "Magnetostrictive low-cost high-performance vibration power generator." Journal of Physics: Conference Series 1052 (July 2018): 012075. http://dx.doi.org/10.1088/1742-6596/1052/1/012075.

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23

Hu, Haonan, Jialai Weng, and Jie Zhang. "Coverage Performance Analysis of FeICIC Low-Power Subframes." IEEE Transactions on Wireless Communications 15, no. 8 (August 2016): 5603–14. http://dx.doi.org/10.1109/twc.2016.2562619.

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24

Ludwig, G. O., M. C. R. Andrade, M. Gryaznevich, and T. N. Todd. "Physics performance analysis of low-power tokamak reactors." Nuclear Fusion 49, no. 8 (July 22, 2009): 085026. http://dx.doi.org/10.1088/0029-5515/49/8/085026.

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25

Fahim, A. M., and M. I. Elmasry. "Low-power high-performance arithmetic circuits and architectures." IEEE Journal of Solid-State Circuits 37, no. 1 (2002): 90–94. http://dx.doi.org/10.1109/4.974550.

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26

Eichelberger, E. B., and S. E. Bello. "Differential current switch—High performance at low power." IBM Journal of Research and Development 35, no. 3 (May 1991): 313–20. http://dx.doi.org/10.1147/rd.353.0313.

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27

Polzin, Kurt A., Thomas E. Markusic, Boris J. Stanojev, Amado DeHoyos, Yevgeny Raitses, Artem Smirnov, and Nathaniel J. Fisch. "Performance of a Low-Power Cylindrical Hall Thruster." Journal of Propulsion and Power 23, no. 4 (July 2007): 886–88. http://dx.doi.org/10.2514/1.28595.

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28

YAMAMOTO, Naoji, Toru EZAKI, and Hideki NAKASHIMA. "Thrust Performance of a Low Power Hall Thruster." TRANSACTIONS OF THE JAPAN SOCIETY FOR AERONAUTICAL AND SPACE SCIENCES, AEROSPACE TECHNOLOGY JAPAN 10, ists28 (2012): Tb_9—Tb_12. http://dx.doi.org/10.2322/tastj.10.tb_9.

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29

Banks, Mark J., and Sara E. Titus. "The promise and performance of low power television." Journal of Media Economics 3, no. 2 (September 1990): 15–25. http://dx.doi.org/10.1080/08997769009358195.

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30

Rama Sangireddy, H. Kim, and A. K. Somani. "Low-power high-performance reconfigurable computing cache architectures." IEEE Transactions on Computers 53, no. 10 (October 2004): 1274–90. http://dx.doi.org/10.1109/tc.2004.80.

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31

Yazdani, Reza, Jose-Maria Arnau, and Antonio Gonzalez. "A Low-Power, High-Performance Speech Recognition Accelerator." IEEE Transactions on Computers 68, no. 12 (December 1, 2019): 1817–31. http://dx.doi.org/10.1109/tc.2019.2937075.

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32

Shams, A. M., A. Chidanandan, W. Pan, and M. A. Bayoumi. "NEDA: a low-power high-performance DCT architecture." IEEE Transactions on Signal Processing 54, no. 3 (March 2006): 955–64. http://dx.doi.org/10.1109/tsp.2005.862755.

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33

de Galan, L., and P. S. C. van der Plas. "Low power ICP — physical principles and analytical performance." Fresenius' Zeitschrift für analytische Chemie 324, no. 5 (January 1986): 472–78. http://dx.doi.org/10.1007/bf00474119.

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34

Nehru, K., and A. Shanmugam. "Design of high-performance low-power full adder." International Journal of Computer Applications in Technology 49, no. 2 (2014): 134. http://dx.doi.org/10.1504/ijcat.2014.060524.

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35

Matos, Débora, Caroline Concatto, Márcio Kreutz, Fernanda Kastensmidt, Luigi Carro, and Altamiro Susin. "Reconfigurable Routers for Low Power and High Performance." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 11 (November 2011): 2045–57. http://dx.doi.org/10.1109/tvlsi.2010.2068064.

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36

Fan, Jiangfeng. "Performance Analysis of Low-Power CMOS Dynamic Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 62–71. http://dx.doi.org/10.54097/hset.v27i.3722.

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This paper studies four structures of CMOS dynamic comparators introduced in recent years. Based on conventional double-tail comparator, a comparator with a tail capacitor prevents output nodes of preamplifier from completely discharging to reduce energy consumption. Another comparator with a cross-coupled pairs achieves the same purpose of the first design. A comparator adds a floating inverter amplifier (FIA) to realize both dynamic bias and current reuse, achieve low energy consumption and be insensitive to the VCM. The triple-latch feed-forward (TLFF) comparator decreases delay conspicuously.

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37

Du, Chengze. "Performance analysis of high-speed, low-power comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 292–301. http://dx.doi.org/10.54097/hset.v27i.3770.

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This article mainly presents a summary of development of dynamic comparators and the optimization to conventional comparator in recent years. By comparing the design of two different comparators, the design method of less power consumption, high speed or small delay, and low input referred noise can be concluded. The Dynamic comparator is designed to have small delay and less power consumption compared with two-stage comparator. The dynamic-bias comparator spends less power for operation the circuit compared with double-tail comparator. The FIA comparator operates under the controlling of logic NOR gate.

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38

Abed, Sa'ed, Yasser Khalil, Mahdi Modhaffar, and Imtiaz Ahmad. "High-performance low-power approximate Wallace tree multiplier." International Journal of Circuit Theory and Applications 46, no. 12 (July 25, 2018): 2334–48. http://dx.doi.org/10.1002/cta.2540.

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39

Kowsalya, P., M. Malathi, and Palaniappan Ramanathan. "Low Power Parallel Prefix Adder." Applied Mechanics and Materials 573 (June 2014): 194–200. http://dx.doi.org/10.4028/www.scientific.net/amm.573.194.

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Addition is a fundamental operation of all Arithmetic and Logic Units (ALU).The speed of addition operation decides the computational frequency of ALU. In order to improve the performance of the binary adder, the parallel prefix adder are preferred. There are various parallel prefix adders available. This work focuses on designing 8-bit prefix adders such as Brent Kung ,Kogge Stone and Sklansky adders using GDI technique. The performance of these GDI based prefix adders are compared with that of CMOS based prefix adder. GDI based prefix adders out performs CMOS based prefix adders in terms of power delay product (PDP). The design is implemented and simulated by DSCH2 and MICROWIND tool .The simulation result reveal about 31%,40% and 50 % of power saving is attained and the number of transistors also reduced.

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40

Rana, Charu, Neelofer Afzal, and Dinesh Prasad. "A low voltage low power high performance FGMOS based current mirror." Contemporary Engineering Sciences 10 (2017): 263–71. http://dx.doi.org/10.12988/ces.2017.512313.

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41

COBOS, J. A., O. GARCÍA, J. SEBASTIÁN, and J. UCEDA. "LOW VOLTAGE POWER ELECTRONICS." Journal of Circuits, Systems and Computers 05, no. 04 (December 1995): 575–88. http://dx.doi.org/10.1142/s0218126695000357.

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This paper summarizes some of the current solutions to fulfil the requirements of the new low voltage power systems. On one hand, microelectronics evolution demands lower supply voltage. On the other hand, the portability of the new communication systems demands lighter and smaller power electronics. The improvement of the performance of low power and low output voltage converters is carried out in this paper. Topics like power density, efficiency, thermal management, battery life, hard and soft switching, magnetics integration, synchronous rectification and power factor correction affect each other in these kinds of converters. Although all the relations among the previous terms are difficult to assess, this paper reviews some aspects of the current situation.

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42

Prabhu, C. M. R., Tan Wee Xin Wilson, and T. Bhuvaneswari. "Low Power 11T Adder Comparator Design." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 1 (March 1, 2020): 28. http://dx.doi.org/10.11591/ijres.v9.i1.pp28-33.

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Comparator is a basic arithmetic component in a digital system and adders are the basic block of processor unit, the performance of adder will improve the system performance. The proposed 11T adder comparator is consists of three main components, namely XOR, inverter, and MUX logic. The circuit is designed and implemented based on top-down approach with 11 transistors. The proposed cell can be used at higher temperature with minimal power loss. It also gives faster response for the carry output. The proposed comparator circuit shows 63.80% improvement in power consumption than other circuits.

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43

Navarro-Botello, Victor, Juan A. Montiel-Nelson, and Saeid Nooshabadi. "Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications." Journal of Low Power Electronics 2, no. 2 (August 1, 2006): 300–307. http://dx.doi.org/10.1166/jolpe.2006.066.

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44

Prakash, Shruti, William E. Mustain, and Paul A. Kohl. "Performance of Li-ion secondary batteries in low power, hybrid power supplies." Journal of Power Sources 189, no. 2 (April 2009): 1184–89. http://dx.doi.org/10.1016/j.jpowsour.2008.12.146.

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45

Ragavendran, U., M. Ramachandran, and . "Low Power and Low Area Junction-less Tunnel FET Design." International Journal of Engineering & Technology 7, no. 3.1 (August 4, 2018): 155. http://dx.doi.org/10.14419/ijet.v7i3.1.17076.

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We present Junction less Tunnel FET with Si:SiGe, Si:AlGaAs and Si:InGaAsP and investigate their DC characteristics. The proposed structures present tremendous performance at a very low supply voltage. The key idea is to study device performance, which can be exploited as a digital switching device for 22 nm technology. Comparison of different heterostructures numerical simulations indicates that ION increases from 0.0024345 to 0.006532 A/μm, when Si:SiGe is replaced with Si:InGaAsP for 22nm channel with supply voltage of 0.5V at a temperature of 300K.

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46

CHAO, KAI-YUAN, and D. F. WONG. "FLOORPLAN DESIGN WITH LOW POWER CONSIDERATIONS." International Journal of High Speed Electronics and Systems 07, no. 02 (June 1996): 305–22. http://dx.doi.org/10.1142/s012915649600013x.

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In this paper, a floorplanner for low power design is presented. Our objective is to optimize total power consumption and area during the selection and placement of various implementations for circuit modules. Furthermore, the proposed method considers performance requirements, power line noises, and distribution of power consumption in order to generate lower and evenly distributed power dissipation over the resulting circuit floorplan with a specified performance. For a set of benchmark circuits we tested, on the average, our floorplanner can achieve decreases of total power consumption, wire-length, and power/ground network size by 18.3%, 4.6%, and 24%, respectively, at the cost of an area increase of 8.8% when compared with an existing area/wire-length driven floorplanner.

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47

Nagarjuna.V, Author, and Harish M Kittur. ""Low Power, Low Area and High Performance Hybrid Type Dynamic CAM Design"." International Journal of Computer Applications 22, no. 6 (May 31, 2011): 39–43. http://dx.doi.org/10.5120/2585-3571.

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48

Aloisi, W., G. Giustolisi, and G. Palumbo. "Exploiting the high-frequency performance of low-voltage low-power SC filters." IEEE Transactions on Circuits and Systems II: Express Briefs 51, no. 2 (February 2004): 77–84. http://dx.doi.org/10.1109/tcsii.2003.821525.

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49

De Souza, Michelly, Bertrand Rue, Denis Flandre, and Marcelo A. Pavanello. "Performance of Ultra-Low-Power SOI CMOS Diodes Operating at Low Temperatures." ECS Transactions 35, no. 5 (December 16, 2019): 325–30. http://dx.doi.org/10.1149/1.3570813.

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50

Angelov, L., N. Wadefalk, J. Stenarson, E. L. Kollberg, P. Starski, and H. Zirath. "On the performance of low-noise low-DC-power-consumption cryogenic amplifiers." IEEE Transactions on Microwave Theory and Techniques 50, no. 6 (June 2002): 1480–86. http://dx.doi.org/10.1109/tmtt.2002.1006408.

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