Dissertations / Theses on the topic 'LOW POWER PERFORMANCE'
To see the other types of publications on this topic, follow the link: LOW POWER PERFORMANCE.
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'LOW POWER PERFORMANCE.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Zhu, Haikun. "High-performance low-power VLSI design." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3250072.
Full textAbstract:
Thesis (Ph. D.)--University of California, San Diego, 2007.Title from first page of PDF file (viewed April 4, 2007). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 97-101).
2
Lee, Sunghyuk. "Techniques for low-power high-performance ADCs." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/87928.
Full textAbstract:
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 127-133).
Analog-to-digital converters (ADCs) are essential building blocks in many electronic systems which require digital signal processing and storage of analog signals. Traditionally, ADCs are considered a power hungry circuit. This thesis investigates ADC design techniques to achieve high-performance with low power consumption. Two designs are demonstrated. The first design is a voltage scalable zero-crossing based pipelined ADC. The zero-crossing based circuit technique is modified and optimized to improve the limited ADC resolution in nano-scaled CMOS technology. The proposed unidirectional charge transfer scheme allows faster and more energy efficient operation by eliminating unnecessary charging and discharging of the capacitors. Furthermore, the reduced transient disturbance at the beginning of the fine charge transfer phase improves the accuracy of operation. Power supply scaling enhances power efficiency at low sampling rates much like in digital circuits and widens the conversion frequency range where the ADC operates with highest efficiency. The second design is a high speed time-interleaved (TI) SAR ADC with background timing-skew calibration. A time-interleaved structure is employed to improve the effective sampling rate without sacrificing energy efficiency. SAR ADCs are used for each channel to make good use of device scaling. The proposed ADC architecture incorporates a flash ADC operating at the full sampling rate of the TI ADC. The flash ADC output is multiplexed to resolve MSBs of the SAR channels. Because the full-speed flash ADC does not suffer from timing-skew errors, the flash ADC output is also used as the timing reference to estimate the timing-skew of the SAR ADCs.
by Sunghyuk Lee.
Ph. D.
3
Bystrøm, Vebjørn. "Low power/high performance dynamic reconfigurable filter-design." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8899.
Full textAbstract:
The main idea behind this thesis was to optimize the multipliers in a finite impulse response (FIR) filter. The project was chosen because digital filters are very common in digital signal processing and is an exciting area to work with. The first part of the text describes some theory behind the digital filter and how to optimize the multipliers that are a part of digital filters. The substantial thing to emphasize here is the use of Canonical Signed Digits (CSD) encoding. CSD representation for FIR filters can reduce the delay and complexity of the hardware implementation. CSD-encoding reduces the amount of non-zero digits and will by this reduce the multiplication process to a few additions/subtractions and shifts. In this thesis it was designed 4 versions of the same filter, that was implemented on an FPGA, where the substantial and most interesting results were the differences between coefficients that was CSD-encoded and coefficients that was represented with 2's complement. It was shown that the filter version that had CSD-encoded coefficients used almost 20% less area then the filter version with 2's complement coefficients. The CSD-encoded filter could run on a maximum frequency of 504,032 MHz compared the other filter that could run on a maximum frequency of 249,123 MHz. One of the filters that was designed was designed using the * operator in VHDL, that proved to be the most efficient when it came to the use of number of slices and speed. The reason for this was because an FPGA has built-in multipliers, so if one has the opportunity to use the multiplier they will give the best result instead of using logic blocks on the FPGA It was also discussed a filter that has the ability to change the coefficients at run-time without starting the design from the beginning. This is an advantage because a constant coefficient multiplier requires the FPGA to be reconfigured and the whole design cycle to be re-implemented. The drawback with the dynamic multiplier is that is uses more hardware resources.
4
Ma, Albert. "Circuits for high-performance low-power VLSI logic." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37906.
Full textAbstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 85-88).
The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two. PSSL is better than domino in terms of energy and robustness, and is better than static CMOS in terms of delay. PSSL works by partially overlapping the execution of consecutive iterations through speculative evaluation. This is accomplished by presetting nodes at register boundaries before input arrival.
by Albert Ma.
Ph.D.
5
Zhang, Ling. "Low power high performance interconnect design and optimization." Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p3368979.
Full textAbstract:
Thesis (Ph. D.)--University of California, San Diego, 2009.Title from first page of PDF file (viewed September 17, 2009). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 113-118).
6
NEUPANE, USHA. "PERFORMANCE ANALYSIS OF LOW-POWER, SHORT-RANGE WIRELESS TRANSCEIVERS." Master's thesis, University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4169.
Full textAbstract:
To address the various emerging standards like BluetoothTM, Home RF, Wi-fiTM (IEEE 802.11), ZigBeeTM etc., in the field of wireless communications, different transceivers have been designed to operate at various frequencies such as 450 MHz, 902-920 MHz, 2.4 GHz, all part of designated ISM band. Though, the wireless systems have become more reliable, compact and easy to develop than before, a detailed performance analysis and characterization of the devices should be done. This report details the performance analysis and characterization of a popular binary FSK transceiver TRF6901 from Texas Instruments. The performance analysis of the device is done with respect to the TRF/MSP430 demonstration and development kit.M.S.E.E.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
7
Yazdani, Aminabadi Reza. "Ultra low-power, high-performance accelerator for speech recognition." Doctoral thesis, Universitat Politècnica de Catalunya, 2019. http://hdl.handle.net/10803/667429.
Full textAbstract:
Automatic Speech Recognition (ASR) is undoubtedly one of the most important and interesting applications in the cutting-edge era of Deep-learning deployment, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost, requiring huge memory storage and computational power, which is not affordable for the tiny power budget of mobile devices.
Hardware acceleration can reduce power consumption of ASR systems as well as reducing its memory pressure, while delivering high-performance.
In this thesis, we present a customized accelerator for large-vocabulary, speaker-independent, continuous speech recognition. A state-of-the-art ASR system consists of two major components: acoustic-scoring using DNN and speech-graph decoding using Viterbi search. As the first step, we focus on the Viterbi search algorithm, that represents the main bottleneck in the ASR system.
The accelerator includes some innovative techniques to improve the memory subsystem, which is the main bottleneck for performance and power, such as a prefetching scheme and a novel bandwidth saving technique tailored to the needs of ASR.
Furthermore, as the speech graph is vast taking more than 1-Gigabyte memory space, we propose to change its representation by partitioning it into several sub-graphs and perform an on-the-fly composition during the Viterbi run-time. This approach together with some simple yet efficient compression techniques result in 31x memory footprint reduction, providing 155x real-time speedup and orders of magnitude power and energy saving compared to CPUs and GPUs.
In the next step, we propose a novel hardware-based ASR system that effectively integrates a DNN accelerator for the pruned/quantized models with the Viterbi accelerator. We show that, when either pruning or quantizing the DNN model used for acoustic scoring, ASR accuracy is maintained but the execution time of the ASR system is increased by 33%. Although pruning and quantization improves the efficiency of the DNN, they result in a huge increase of activity in the Viterbi search since the output scores of the pruned model are less reliable. In order to avoid the aforementioned increase in Viterbi search workload, our system loosely selects the N-best hypotheses at every time step, exploring only the N most likely paths. Our final solution manages to efficiently combine both DNN and Viterbi accelerators using all their optimizations, delivering 222x real-time ASR with a small power budget of 1.26 Watt, small memory footprint of 41 MB, and a peak memory bandwidth of 381 MB/s, being amenable for low-power mobile platforms.Los sistemas de reconocimiento automático del habla (ASR por sus siglas en inglés, Automatic Speech Recognition) son sin lugar a dudas una de las aplicaciones más relevantes en el área emergente de aprendizaje profundo (Deep Learning), specialmente en el segmento de los dispositivos móviles. Realizar el reconocimiento del habla de forma rápida y precisa tiene un elevado coste en energía, requiere de gran capacidad de memoria y de cómputo, lo cual no es deseable en sistemas móviles que tienen severas restricciones de consumo energético y disipación de potencia. El uso de arquitecturas específicas en forma de aceleradores hardware permite reducir el consumo energético de los sistemas de reconocimiento del habla, al tiempo que mejora el rendimiento y reduce la presión en el sistema de memoria. En esta tesis presentamos un acelerador específicamente diseñado para sistemas de reconocimiento del habla de gran vocabulario, independientes del orador y que funcionan en tiempo real. Un sistema de reconocimiento del habla estado del arte consiste principalmente en dos componentes: el modelo acústico basado en una red neuronal profunda (DNN, Deep Neural Network) y la búsqueda de Viterbi basada en un grafo que representa el lenguaje. Como primer objetivo nos centramos en la búsqueda de Viterbi, ya que representa el principal cuello de botella en los sistemas ASR. El acelerador para el algoritmo de Viterbi incluye técnicas innovadoras para mejorar el sistema de memoria, que es el mayor cuello de botella en rendimiento y energía, incluyendo técnicas de pre-búsqueda y una nueva técnica de ahorro de ancho de banda a memoria principal específicamente diseñada para sistemas ASR. Además, como el grafo que representa el lenguaje requiere de gran capacidad de almacenamiento en memoria (más de 1 GB), proponemos cambiar su representación y dividirlo en distintos grafos que se componen en tiempo de ejecución durante la búsqueda de Viterbi. De esta forma conseguimos reducir el almacenamiento en memoria principal en un factor de 31x, alcanzar un rendimiento 155 veces superior a tiempo real y reducir el consumo energético y la disipación de potencia en varios órdenes de magnitud comparado con las CPUs y las GPUs. En el siguiente paso, proponemos un novedoso sistema hardware para reconocimiento del habla que integra de forma efectiva un acelerador para DNNs podadas y cuantizadas con el acelerador de Viterbi. Nuestros resultados muestran que podar y/o cuantizar el DNN para el modelo acústico permite mantener la precisión pero causa un incremento en el tiempo de ejecución del sistema completo de hasta el 33%. Aunque podar/cuantizar mejora la eficiencia del DNN, éstas técnicas producen un gran incremento en la carga de trabajo de la búsqueda de Viterbi ya que las probabilidades calculadas por el DNN son menos fiables, es decir, se reduce la confianza en las predicciones del modelo acústico. Con el fin de evitar un incremento inaceptable en la carga de trabajo de la búsqueda de Viterbi, nuestro sistema restringe la búsqueda a las N hipótesis más probables en cada paso de la búsqueda. Nuestra solución permite combinar de forma efectiva un acelerador de DNNs con un acelerador de Viterbi incluyendo todas las optimizaciones de poda/cuantización. Nuestro resultados experimentales muestran que dicho sistema alcanza un rendimiento 222 veces superior a tiempo real con una disipación de potencia de 1.26 vatios, unos requisitos de memoria modestos de 41 MB y un uso de ancho de banda a memoria principal de, como máximo, 381 MB/s, ofreciendo una solución adecuada para dispositivos móviles.
8
Oskuii, Saeeid Tahmasbi. "Comparative study on low-power high-performance flip-flops." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2077.
Full textAbstract:
This thesis explores the energy-delay space of eight widely referred flip-flops in a 0.13µm CMOS technology. The main goal has been to find the smallest set of flip-flop topologies to be included in a “high performance” flip-flop cell library covering a wide range of power-performance targets. Based on the comparison results, transmission gate-based flip-flops show the best powerperformance trade-offs with a total delay (clock-to-output + setup time) down to 105ps. For higher performance, the pulse-triggered flip-flops are the fastest (80ps) alternatives suitable to be included in a flip-flop cell library. However, pulse-triggered flip-flops consume significantly larger power (about 2.5x) compared to other fast but fully dynamic flip-flops such as TSPC and dynamic TG-based flip-flops.
9
Mohan, Nitin. "Low-Power High-Performance Ternary Content Addressable Memory Circuits." Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/2873.
Full textAbstract:
Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of TCAMs, high power consumption is one of the most critical challenges faced by TCAM designers. This work proposes circuit techniques for reducing TCAM power consumption. The main contribution of this work is divided in two parts: (i) reduction in match line (ML) sensing energy, and (ii) static-power reduction techniques. The ML sensing energy is reduced by employing (i) positive-feedback ML sense amplifiers (MLSAs), (ii) low-capacitance comparison logic, and (iii) low-power ML-segmentation techniques. The positive-feedback MLSAs include both resistive and active feedback to reduce the ML sensing energy. A body-bias technique can further improve the feedback action at the expense of additional area and ML capacitance. The measurement results of the active-feedback MLSA show 50-56% reduction in ML sensing energy. The measurement results of the proposed low-capacitance comparison logic show 25% and 42% reductions in ML sensing energy and time, respectively, which can further be improved by careful layout. The low-power ML-segmentation techniques include dual ML TCAM and charge-shared ML. Simulation results of the dual ML TCAM that connects two sides of the comparison logic to two ML segments for sequential sensing show 43% power savings for a small (4%) trade-off in the search speed. The charge-shared ML scheme achieves power savings by partial recycling of the charge stored in the first ML segment. Chip measurement results show that the charge-shared ML scheme results in 11% and 9% reductions in ML sensing time and energy, respectively, which can be improved to 19-25% by using a digitally controlled charge sharing time-window and a slightly modified MLSA. The static power reduction is achieved by a dual-VDD technique and low-leakage TCAM cells. The dual-VDD technique trades-off the excess noise margin of MLSA for smaller cell leakage by applying a smaller VDD to TCAM cells and a larger VDD to the peripheral circuits. The low-leakage TCAM cells trade off the speed of READ and WRITE operations for smaller cell area and leakage. Finally, design and testing of a complete TCAM chip are presented, and compared with other published designs.
10
Duewer, Bruce Eliot. "A Low-Power, High Performance MEMS-based Switch Fabric." NCSU, 2001. http://www.lib.ncsu.edu/theses/available/etd-20011015-145122.
Full textAbstract:
DUEWER, BRUCE ELIOT. A Low-Power, High Performance MEMS-based Switch Fabric. (Under the direction of Paul D. Franzon.)An approach with the potential for building large low power high performance crossbar networks is presented. Thin film polysilicon MEMS devices are developed to provide crosspoints. These devices are vertically moving plates that serve as variable capacitors. Addressing of large arrays using 2n rather than n-squared lines despite no active circuitry on the MEMS chips is facilitated by bistable device operation. Derivations of equations for bistable device operation are presented. Low power operation is possible as the devices are electrostatically controlled and are stationary except during reconfiguration. Early devices are fabricated using the MUMPS process. The bistability and array addressability properties are demonstrated. The substrate effect on device operation is measured and modeled; methods for utilizing the substrate effect to tune device operation are presented. Later devices are fabricated using the SUMMiT process. Changes in the SUMMiT design rules to increase allowable vertical motion range are proposed and designs using them fabricated. S-parameter characteristics of devices in both `on' and `off' states are measured. Addition of metallization after chip fabrication and release is necessary to lower the resistance of interconnect. A self masking method for applying this metallization allowing for decreased resistance at line crossings is proposed. This method is tested using each of sputtering and evaporation as the deposition technique for a gold and adhesion layer stack. Effectiveness of the method with each technique is evaluated. Chips suitable for providing high voltage control for large MEMS arrays are fabricated in a 2um feature size CMOS process. Architectures suitable for building large crossbars employing variable capacitor arrays are discussed. Optimization of hybrid CMOS/MEMS Clos arrays on the basis of criteria other than minimization of crosspoints is discussed. Array sizings to provide 192*192 and 256*256 crossbars are presented, and software examples for sizing and controlling Clos networks are provided. Evaluation of the suitability of the MEMS devices developed for use as digital or broadband crosspoints is evaluated, and potential future directions are proposed.
11
Park, Sunghyun Ph D. Massachusetts Institute of Technology. "Towards low-power yet high-performance networks-on-chip." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/93776.
Full textAbstract:
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 144-154).
A network-on-chip (NoC), the de-facto communication backbone in manycore processors, consumes a significant portion of total chip power, competing against the computation cores for the limited power and thermal budget. On the other hand, overall system performance of manycore chips increasingly relies on on-chip latency and bandwidth as core counts scale. This thesis aims to design low-power yet high-performance NoCs through circuit and microarchitecture co-design contrary to the traditional approaches where NoCs sacrifice latency and/or bandwidth for low-power operation; then demonstrate such design concepts through test chip prototyping, enabling detailed measurements for rigorous analysis of the pros and cons of the proposed NoCs. The thesis starts with a 4x4 mesh NoC chip prototype that tries to simultaneously optimize energy, latency and throughput for all kinds of traffic (unicasts, multicasts and broadcasts). Its extensive experiment results make it possible to accurately analyze energy/performance benefits and timing/area overheads of the virtually bypassed, multicast-optimized router design; energy savings, area overheads and reduced reliability of the clocked low-swing datapath circuits; and a power gap between simulated estimations and measurement results. Next demonstrated is a link test chip of two clockless low-swing repeater designs, a self-resetting logic repeater (SRLR) optimized for transmission energy and a voltage-locked repeater (VLR) for transmission delay. This second chip prototype shows that the clockless, single-ended low-swing signaling of SRLRs armed with variation-robust circuit techniques has lower energy and smaller area than clocked, differential lowswing signaling. Featured with lower delay than full-swing repeaters, VLRs provide the fundamental building block to the single-cycle reconfigurable NoC that enables potential power saving at architecture level through single-cycle multi-hop asynchronous link traversal on dynamically configurable routes. The last one-third of this thesis explores a 3D-IC chip prototype of a throughsilicon via (TSV) interconnect that can support simultaneously bi-directional (SBD) signaling. While TSVs, as 3D-IC NoC links, offer an appealing solution to manycore architectures that require huge off-die bandwidth, existing TSV technologies impose considerable power and area overheads (using spare TSVs) to improve reliability. The proposed SBD TSV circuit shows better energy efficiency and smaller area than unidirectional TSVs, thus providing reliable 3D signaling within tight power/silicon budget. Such SBD signaling also enables configurable off-die bandwidth, and hence, can be the basis of a bandwidth-adaptive 3D NoC that efficiently supports highly dynamic traffic on manycore chips.
by Sunghyun Park.
Ph. D.
12
Kadasur, Rao Nikil. "A Comparative Performance Evaluation of Low-Power Gesture Sensors." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229454.
Full textAbstract:
Low-power gesture sensors offer users a simple way to interact with technology using basic everyday gestures, making the interaction between humans and technology more natural. The various technologies used in these sensors along with the different features offered by each one make it difficult for companies and researchers to compare them in order to choose a sensor for any kind of a project. This thesis offers an insight into the different technologies used in low-power gesture sensors and provides a comprehensive and comparative performance evaluation of the most common types of low-power gesture sensors available in the market. Three of the mainly used technologies in these kinds of sensors i.e. infrared distance, time-of-flight and imaging, were chosen for testing. A further investigation was also carried out on the images obtained by the imaging sensor. The time-of-flight sensor offers very high accuracy of 99.3% and performs well at large distances but offers a very limited number of recognizable gestures. The Infrared distance sensor offers a bigger set of recognizable gestures but gives high accuracy only at small distances from the sensor. The imaging sensor offers a 98.9% accuracy and performs well at larger distances. However, due to its larger set of gestures it is prone to a higher number of incorrectly detected gestures. The image mode analysis of the imaging sensor shows how brightness of the surroundings affect the gesture detection capability of the sensor. The findings of this thesis can be used by any researcher to get an overview of the strengths and weaknesses of each sensor and choose one of them according to their requirements. The image mode analysis done in this thesis can be used as a base to implement better gesture detection algorithms and decrease the number of incorrectly detected gestures.Low power gesture sensors erbjuder användaren ett enkelt sätt att använda teknologi genom enkla rörelser, så att samverkan mellan människor och teknologi blir naturligare. De olika teknologiska teknikerna som används i dessa sensorer och de olika funktioner som var och en av dem kan erbjuda gör det svårt för företag och forskare att jämföra dem för att kunna välja en sensor för ett visst ändamål. Denna tesis erbjuder en kännedom om de olika teknologiska tekniker som används i low power gesture sensors och utgör en förståelig och en jämförelig uppskattning av effektiviteten av de vanligaste low power sensors som finns på marknaden. Tre av de mest använda teknologierna i dessa sensorer till exempel infrared distance, time-offlight och imaging valdes att testas. En vidare undersökning gjordes också av bilder tagna av en imaging sensor. Time-of–flight sensorerna erbjuder en mycket hög precision på 99,3% och fungerar bra på långa avstånd men fungerar dock endast med ett begränsat antal igenkännliga rörelser. De infrared distance sensors erbjuder ett större antal igenkännliga rörelser men fungerar med hög precision bara på avstånd nära sensorn. Imaging sensorerna erbjuder precision på 98,9 % och fungerar bra på långa avstånd. På grund av att de används med flera olika rörelser brukar de uppfatta dessa felaktigt. Analysen av bilderna frân bildsensorn visar hur ljuset i omgivningen pâverkar sensorns förmâga att uppfatta bilderna. Resultaten i denna tesis kan användas av olika forskare för att få en uppfattning om de olika sensorernas för- och nackdelar och för att lättare kunna välja en för ett visst behov. Image mode-analysen som gjorts i denna tesis kan användas som bas för att för bättre rörelse detekterade algoritmer och minska antalet feldetekterade rörelser.
13
Al-Tarawneh, Mutaz. "Worst-case performance analysis of low-power instruction caches /." Available to subscribers only, 2008. http://proquest.umi.com/pqdweb?did=1594486421&sid=9&Fmt=2&clientId=1509&RQT=309&VName=PQD.
Full text
14
MA, LIANG. "Low power and high performance heterogeneous computing on FPGAs." Doctoral thesis, Politecnico di Torino, 2019. http://hdl.handle.net/11583/2727228.
Full text
15
Yang, Ge. "Low power and high performance circuit design for process scalability /." Diss., Digital Dissertations Database. Restricted to UC campuses, 2004. http://uclibs.org/PID/11984.
Full text
16
Allam, Mohamed W. "New methodologies for low-power high-performance digital VLSI design." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0016/NQ53483.pdf.
Full text
17
Khasawneh, Shadi Turki. "Low-power high-performance register file design for chip multiprocessors." Diss., Online access via UMI:, 2006.
Find full text
18
QI, BIN. "PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM." University of Cincinnati / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1191423845.
Full text
19
Aboubakar, Moussa. "Efficient management of IoT low power networks." Thesis, Compiègne, 2020. http://www.theses.fr/2020COMP2571.
Full textAbstract:
Durant cette dernière décennie, plusieurs objets connectés tels que les ordinateurs, les capteurs et les montres intelligentes ont intégrés notre quotidien et forment aujourd’hui ce que l’on appelle l’Internet des Objets (IdO) ou Internet of Things (IoT) en anglais. L’IoT est un nouveau paradigme permettant une interaction entre les objets connectés afin d’améliorer notre qualité de vie, notre façon de produire des biens et notre façon d’interagir avec notre environnement. De nos jours, l’IoT se caractérise par la présence, de par le monde, de milliards d’objets connectés à faibles ressources (batterie, mémoire, CPU, bande passante disponible, etc) et hétérogènes, déployés pour permettre diverses applications couvrant de nombreux domaines de notre société tels que la santé, l’industrie, les transports, l’agriculture, etc. Cependant, en raison des contraintes lié aux ressources et de l’hétérogénéité des objets connectés, les réseaux IoT à faibles ressources présents font face à des problèmes de performance, notamment la dégradation de la qualité des liens radio, la défaillance (logicielle ou matérielle) de certains objets du réseau, la congestion du réseau, etc. Ainsi, il est donc important de gérer efficacement les réseaux IoT à faible ressources afin d’assurer leur bon fonctionnement. Pour ce faire, la solution de gestion du réseau doit être autonome (pour faire face à la nature dynamique des réseaux IoT), tenir compte de l’hétérogénéité des objets connectés et être moins consommatrice en énergie pour répondre aux défis de l’IoT. Dans cette thèse, nous nous sommes intéressés au problème de gestion des réseaux IoT à faibles ressources et avons proposés des solutions efficaces pour permettre une optimisation des performances de ces types de réseaux. Dans un premier temps nous avons procédé à une étude comparative des solutions de gestion des réseaux IoT à faibles ressources afin d’identifier les verrous techniques. Ensuite, nous avons proposé une solution intelligente qui se base sur un modèle de réseau de neurones profonds pour permettre une configuration de la portée radio dans les réseaux sans fil à faibles ressources de type RPL (IPv6 Routing Protocol for Low power and Lossy Networks). Une évaluation des performances de cette solution montre qu’elle est capable de déterminer la portée radio permettant une réduction de la consommation énergétique du réseau tout en garantissant une connectivité des objets connectés. Nous avons également proposé une solution efficace et adaptative pour configurer les paramètres de la couche MAC dans les réseaux dynamiques de type IEEE 802.15.4. Les résultats des simulations démontrent que notre solution améliore le délai de transmission bout en bout par rapport à l’utilisation des paramètres par défaut de la MAC IEEE 802.15.4. En outre, nous avons proposé une étude des solutions existante pour la gestion des problèmes de congestion des réseaux IoT à faibles ressources et par la suite nous avons proposé un procédé d’acheminement de l’information de congestion des objets connectés présents sur un chemin de routage donné dans des réseaux à ressources limitées. Cette méthode a pour but de permettre une réponse efficace aux problèmes de congestionIn these recent years, several connected objects such as computer, sensors and smart watches became part of modern living and form the Internet of Things (IoT). The basic idea of IoT is to enable interaction among connected objects in order to achieve a desirable goal. IoT paradigm spans across many areas of our daily life such as smart transportation, smart city, smart agriculture, smart factory and so forth. Nowadays, IoT networks are characterized by the presence of billions of heterogeneous embedded devices with limited resources (e.g. limited memory, battery, CPU and bandwidth) deployed to enable various IoT applications. However, due to both resource constraints and the heterogeneity of IoT devices, IoT networks are facing with various problems (e.g. link quality deterioration, node failure, network congestion, etc.). Considering that, it is therefore important to perform an efficient management of IoT low power networks in order to ensure good performance of those networks. To achieve this, the network management solution should be able to perform self-configuration of devices to cope with the complexity introduced by current IoT networks (due to the increasing number of IoT devices and the dynamic nature of IoT networks). Moreover, the network management should provide a mechanism to deal with the heterogeneity of the IoT ecosystem and it should also be energy efficient in order to prolong the operational time of IoT devices in case they are using batteries. Thereby, in this thesis we addressed the problem of configuration of IoT low power networks by proposing efficient solutions that help to optimize the performance of IoT networks. We started by providing a comparative analysis of existing solutions for the management of IoT low power networks. Then we propose an intelligent solution that uses a deep neural network model to determine the efficient transmission power of RPL networks. The performance evaluation shows that the proposed solution enables the configuration of the transmission range that allows a reduction of the network energy consumption while maintaining the network connectivity. Besides, we also propose an efficient and adaptative solution for configuring the IEEE 802.15.4 MAC parameters of devices in dynamic IoT low power networks. Simulation results show that our proposal improves the end-to-end delay compared to the usage of the standard IEEE 802.15.4 MAC. Additionally, we develop a study on solutions for congestion control in IoT low power networks and propose a novel scheme for collecting the congestion state of devices in a given routing path of an IoT network so as to enable an efficient mitigation of the congestion by the network manager (the device in charge of configuration of the IoT network)
20
Kidane, Berhane. "Low Power Wide Area Networks based on LoRA Technology." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017.
Find full textAbstract:
The demand for connected devices, according to the Internet of Things (IoT) paradigm, is expected to grow considerably in the immediate future. Various standards are currently contending to gain an edge over the competition and provide the massive connectivity that will be required by a world in which everyday objects are expected to communicate with each other. Among these standards, Low-Power Wide Area Networks (LPWANs) are continuously gaining momentum, mainly thanks to their ability to provide long-range coverage to devices, exploiting license-free frequency bands. The focus of this thesis is on one of the most prominent LPWAN technologies: LoRa™.
First, this thesis establishes a series of models that cover various aspects of a
LoRa network. Then, a new Network LoRaWAN Simulator is introduced to simulate a LoRa-based IoT network of four use cases. Finally, the performance of the LoRa system is evaluated and analyzed.
21
Betzler, August. "Improvements to end-to-end performance of low-power wireless networks." Doctoral thesis, Universitat Politècnica de Catalunya, 2015. http://hdl.handle.net/10803/321112.
Full textAbstract:
Over the last decades, wireless technologies have become an important part of our daily lives. A plentitude of new types of networks based on wireless technologies have emerged, often replacing wired solutions. In this development, not only the number and the types of devices equipped with wireless transceivers have significantly increased, also the variety of wireless technologies has grown considerably. Moreover, Internet access for wireless devices has paved the way for a large variety of new private, business, and research applications. Great efforts have been made by the research community and the industry to develop standards, specifications, and communication protocols for networks of constrained devices, we refer to as Wireless Sensor Networks (WSNs). The Institute of Electrical and Electronics Engineers (IEEE) defined the 802.15.4 standard for Personal Area Networks (PANs). With the introduction of an adaptation layer which makes IEEE 802.15.4 networks IPv6-capable, interconnecting billions of constrained devices has become possible and is expected to become a reality in the near future. The vision that embraces the idea of interweaving Internet technology with any type of smart objects, such as wearable devices or sensors of a WSN, is called the Internet of Things (IoT).
The main goal of this thesis is the improvement of the performance of low-power wireless networks. Given the wide scope of application scenarios and networking solutions proposed for such networks, the development and optimization of communication protocols for wireless low-power devices is a challenging task: The hardware restrictions of constrained devices, specific application scenarios that may vary from one network to another, and the integration of WSNs into the IoT require new approaches to the design and evaluation of communication protocols. To face these challenges and to find solutions for them, research needs to be carried out. Mechanisms and parameter settings of communication protocol stacks for WSNs that are crucial to the network performance need to be identified, optimized, and complemented by adding new ones.
The first contribution of this thesis is the improvement of end-to-end performance for IEEE 802.15.4-based PANs, where default parameter settings of common communication protocols are analyzed and evaluated with regard to their impact on the network performance. Physical evaluations are carried out in a large testbed, addressing the important question of whether the default and allowed range settings defined for common communication protocols are efficient or whether alternative settings may yield a better performance.
The second contribution of this thesis is the improvement of end-to-end performance for ZigBee wireless HA networks. ZigBee is an important standard for low-power wireless networks and the investigations carried out address the crucial lack of investigation the ZigBee HA performance evaluations through physical experiments and potential ways to improve the network performance based on these experiments.
Eventually, this thesis focuses on the improvement of the congestion control (CC) mechanism applied by the Constrained Application Protocol (CoAP) used in IoT communications. For the handling of the possible congestion in the IoT produced by the plethora of the devices and/or link errors innate to low-power radio communications, the default CC mechanism it lacks an advanced CC algorithm. Given CoAP's high relevance for IoT communications, an advanced CC algorithm should be capable of adapting to these particularities of IoT communications. This thesis contributes to this topic with the design and optimization of the CoAP Advanced Congestion Control/Simple (CoCoA) protocol, an advanced CC mechanism for CoAP.The investigations of advanced CC mechanisms for CoAP involve extensive performance evaluations in simulated networks and physical experiments in real testbeds using different communication technologies.En les últimes dècades, les tecnologies sense fils s'han convertit en una part important de la nostra vida quotidiana. Una àmplia varietat de nous tipus de xarxes basades en tecnologies sense fils han sorgit, sovint reemplaçant solucions cablejades. En aquest desenvolupament, no només el nombre i els tipus de dispositius equipats amb transceptors sense fils han augmentat significativament, també la varietat de tecnologies sense fils ha crescut de manera considerable. D'altra banda, l'accés a Internet per als dispositius sense fils ha donat pas a una gran varietat de noves aplicacions privades, comercials i d'investigació. La comunitat científica i la indústria han fet grans esforços per desenvolupar normes, especificacions i protocols de comunicació per a xarxes de sensors sense fils (WSNs). L'Institut d'Enginyeria Elèctrica i Electrònica (IEEE) defineix l'estàndard 802.15.4 per a xarxes d'àrea personal (PAN). Amb la introducció d'una capa d'adaptació que possibilita les IEEE 802.15.4 xarxes compatibles amb IPv6, la interconnexió de milers de milions de dispositius restringits s'ha fet possible. La idea d'entreteixir la tecnologia d'Internet amb qualsevol tipus d'objectes intel·ligents, com els dispositius o sensors d'una WSN és coneguda com la Internet de les Coses (IoT). L'objectiu principal d'aquesta tesi és la millora del rendiment de les WSNs. Donada l'àmplia gamma d'escenaris d'aplicacions i solucions de xarxes proposats per a aquest tipus de xarxes, el desenvolupament i l'optimització dels protocols de comunicació per a dispositius de WSNs és una tasca difícil: les limitacions de capacitats dels dispositius restringits, escenaris d'aplicació específics que poden variar d'una xarxa a l'altra, i la integració de les WSNs a la IoT requereixen nous enfocaments per al disseny i avaluació de protocols de comunicació. Cal identificar mecanismes i configuracions de paràmetres de les piles de protocols de comunicació per a WSNs que són elementals per al rendiment de la xarxa, optimitzar-los, i complementar-los amb l'addició d'altres de nous. La primera contribució d'aquesta tesi és la millora del rendiment extrem a extrem per PANs basat en IEEE 802.15.4, on s'analitza la configuració de paràmetres que es fan servir per defecte en protocols de comunicació comuns i s'avalua el seu impacte en el rendiment de la xarxa. Avaluacions físiques en una xarxa de sensors permeten fer front a la important qüestió de si els valors estàndards dels paràmetres són eficients o si ajustant-los es pot proporcionar un millor rendiment. La segona contribució d'aquesta tesi és l'optimització del rendiment extrem a extrem de xarxes ZigBee domòtiques (HA) sense fils. ZigBee és un estàndard important per a WSNs. Els estudis duts a terme cobreixen la important falta d'investigació d'avaluacions de rendiment de xarxes HA de ZigBee mitjançant experiments físics i mostrant formes per millorar el rendiment de la xarxa en base d'aquests experiments. Finalment, aquesta tesi es centra en la millora del mecanisme bàsic de control de congestió (CC) aplicada pel Constrained Application Protocol (CoAP) utilitzat en les comunicacions de la IoT. És necessari un algoritme de CC avançat per al control de la possible congestió en la IoT produïda per la plètora de dispositius i/o errors d'enllaç naturals per a les comunicacions de ràdio de baixa potencia. Donada l'alta rellevància de CoAP per a les comunicacions en la IoT, un algoritme CC avançat ha de ser capaç d'adaptar-se a les particularitats de les comunicacions de la IoT. Aquesta tesi contribueix al problema amb el disseny i l'optimització Control de Congestió Avançat / Simple del CoAP (CoCoA), un mecanisme de CC avançat per CoAP. Les investigacions de mecanismes de CC avançats per CoAP impliquen avaluacions extenses en xarxes simulades i experiments físics en xarxes reals utilitzant diferents tecnologies de comunicacions.
22
Tatapudi, Suryanarayana Bhimeshwara. "A high performance low power mesochronous pipeline architecture for computer systems." Online access for everyone, 2006. http://www.dissertations.wsu.edu/Dissertations/Spring2006/s%5Ftatapudi%5F042706.pdf.
Full text
23
Swaminathan, Ashok. "Enabling techniques for low power, high performance fractional-N frequency synthesizers." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3222048.
Full textAbstract:
Thesis (Ph. D.)--University of California, San Diego, 2006.Title from first page of PDF file (viewed September 20, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references.
24
Mukherjee, Tonmoy Shankar. "High performance, low-power and robust multi-gigabit wire-line design." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/39515.
Full textAbstract:
The object of this research is to develop robust wire-line systems which demonstrate high performance while simultaneously consuming low power. The main focus of this work is the Clock and Data Recovery (CDR) system, which is the primary circuit of any modern wire-line transceiver. Different techniques starting from circuit-level to system-level have been investigated in this work to improve the performance of multi-gigabit CDRs. A 62 GHz bandwidth amplifier has been presented to address the need for a scalable amplifier for CDR needs. A new technique has been proposed to improve the radiation immunity of latches, to reduce the BER in CDRs occurring due to package radiations. An injection-lock based clock recovery method was investigated as an alternative to PLL based CDRs as they can be used for burst-mode wire-line communication. The investigation yielded the vulnerability of the method to jitter (false-locking and high jitter transfer), the attenuation of which is critical to commercial CDRs. A novel false-lock detector system has been proposed and demonstrated for the first time as a robust solution to the issue of false-locking of CDRs due to repetitive patterns. The implementation of the final CDR system required the use of an L-C tank VCO, the components of which are generic for all commercial CDRs. A new systematic layout technique for the VCO has been proposed and demonstrated in this work to substantially improve the layout area and the associated parasitics, approximately by 70 %. This new layout addresses a critical yet often neglected part of VCO design. Furthermore, a new concept has been proposed to optimize static dividers with respect to their power consumption and number of devices.
25
Zhou, Huisheng. "Performance Evaluation of Small TCP/IP Stack on Low Power Processor." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-98662.
Full textAbstract:
The uIP is an open source TCP/IP stack capable of being used with tiny 8- and 16-bit microcontrollers. Leon3 is a low power, high performance 32-bit processor. In this thesis, a port of uIP to Leon3 has implemented in order to see the performance of a minimal TCP/IP stack on a low power, high performance processor. An improved checksum calculation for uIP is implemented in order to utilize the 32-bit architecture resources. The purposes of making this analysis is to see how much the performance improvement can be achieved by using more advanced processor and more improved checksum calculation instead of the original 8- and 16-bit processors and generic 8-bit checksum calculation. A detailed performance test has performed. The test results show a detailed analysis of performance improvement in processing and energy consumption.
26
Jin, Jie. "Low power design for high performance wireless digital baseband building blocks /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20JIN.
Full text
27
Petrov, Peter. "Application specific embedded processor customizations for low power and high performance /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2004. http://wwwlib.umi.com/cr/ucsd/fullcit?p3137218.
Full text
28
Gasparini, Leonardo. "Ultra-low-power Wireless Camera Network Nodes: Design and Performance Analysis." Doctoral thesis, Università degli studi di Trento, 2011. https://hdl.handle.net/11572/368297.
Full textAbstract:
A methodology for designing Wireless Camera Network nodes featuring long lifetime is presented. Wireless Camera Networks may nd widespread application in the elds of security, animal monitoring, elder care and many others. Unfortunately, their development is currently thwarted by the lack of nodes capable of operating autonomously for a long period of time when powered with a couple of AA batteries. In the proposed approach, the logic elements of a Wireless Camera Network node are clearly identied along with their requirements in terms of processing capabilities and power consumption. For each element, strategies leading to significant energy savings are proposed. In this context, the employment of a custom vision sensor and an ecient architecture are crucial. In order to validate the methodology, a prototype node is presented, mounting a smart
sensor and a ash-based FPGA. The node implements a custom algorithm for counting people, a non trivial task requiring a considerable amount of on-board processing. The overall power consumption is limited to less than 5 mW, thus achieving a two orders of magnitude improvement with respect
to the state of the art. By powering the system with two batteries providing 2200 mAh at 3.3 V, the expected lifetime of the system exceeds two months even in the worst-case scenario.
29
Gasparini, Leonardo. "Ultra-low-power Wireless Camera Network Nodes: Design and Performance Analysis." Doctoral thesis, University of Trento, 2011. http://eprints-phd.biblio.unitn.it/553/1/PhDThesis_v0_0.pdf.
Full textAbstract:
A methodology for designing Wireless Camera Network nodes featuring long lifetime is presented. Wireless Camera Networks may nd widespread application in the elds of security, animal monitoring, elder care and many others. Unfortunately, their development is currently thwarted by the lack of nodes capable of operating autonomously for a long period of time when powered with a couple of AA batteries. In the proposed approach, the logic elements of a Wireless Camera Network node are clearly identied along with their requirements in terms of processing capabilities and power consumption. For each element, strategies leading to significant energy savings are proposed. In this context, the employment of a custom vision sensor and an ecient architecture are crucial. In order to validate the methodology, a prototype node is presented, mounting a smart
sensor and a ash-based FPGA. The node implements a custom algorithm for counting people, a non trivial task requiring a considerable amount of on-board processing. The overall power consumption is limited to less than 5 mW, thus achieving a two orders of magnitude improvement with respect
to the state of the art. By powering the system with two batteries providing 2200 mAh at 3.3 V, the expected lifetime of the system exceeds two months even in the worst-case scenario.
30
Canal, Corretger Ramon. "Power- and Performance - Aware Architectures." Doctoral thesis, Universitat Politècnica de Catalunya, 2004. http://hdl.handle.net/10803/5984.
Full textAbstract:
The scaling of silicon technology has been ongoing for over forty years. We are on the way to commercializing devices having a minimum feature size of one-tenth of a micron. The push for miniaturization comes from the demand for higher functionality and higher performance at a lower cost. As a result, successively higher levels of integration have been driving up the power consumption of chips. Today, heat removal and power distribution are at the forefront of the problems faced by chip designers.In recent years portability has become important. Historically, portable applications were characterized by low throughput requirements such as for a wristwatch. This is no longer true.
Among the new portable applications are hand-held multimedia terminals with video display and capture, audio reproduction and capture, voice recognition, and handwriting recognition capabilities. These capabilities call for a tremendous amount of computational capacity. This computational capacity has to be realized with very low power requirements in order for the battery to have a satisfactory life span. This thesis is an attempt to provide microarchitecture and compiler techniques for low-power chips with high-computational capacity.
The first part of this work presents some schemes for reducing the complexity of the issue logic. The issue logic has become one of the main sources of energy consumption in recent years. The inherent associative look-up and the size of the structures (crucial for exploiting ILP), have led the issue logic to a significant energy budget. The techniques presented in this work eliminate or reduce the associative logic by determining producer-consumer relationships between the instructions or by scheduling the instructions according to the latency of the operations.
An important effort has been deployed to reduce the energy requirements and the power dissipation through novel mechanisms based on value compression. As a result, the second part of this thesis introduces several ultra-low power and high-end processor designs. First, the design space for ultra-low power processors is explored. Several designs are developed (at the architectural level) from scratch that exploit value compression at all levels of the data-path.
Second, value compression for high-performance processors is proposed and evaluated. At the end of this thesis, two compile-time techniques are presented that show how the compiler can help in reducing the energy consumption. By means of a static analysis of the program code or through profiling, the compiler is able to know the size of the operands involved in the computation. Through these analyses, the compiler is able to use narrower operations (i.e. a 64-bit addition can be converted to an 8-bit addition due to the information of the size of the operands).
Overall, this thesis compromises the detailed study of one of the most power hungry units in a processor (the issue logic) and the use of value compression (through hardware and software) as a mean to reduce the energy consumption in all the stages of the pipeline.
31
Yang, Boyi. "High Performance Low Voltage Power MOSFET for High-Frequency Synchronous Buck Converters." Doctoral diss., University of Central Florida, 2012. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5582.
Full textAbstract:
Power management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and optimizing high performance low voltage power MOSFETs for high frequency applications. With an inherently large gate charge, the trench MOSFET suffers significant switching power losses and cannot continue to provide sufficient performance in high frequency applications. Moreover, the influence of parasitic impedance introduced by device packaging and PCB assembly in board level power supply designs becomes more pronounced as the output voltage continues to decrease and the nominal current continues to increase. This eventually raises the need for highly integrated solutions such as power supply in package (PSiP) or on chip (PSoC). However, it is often more desirable in some PSiP architectures to reverse the source/drain electrodes from electrical and/or thermal point of view. In this dissertation, a stacked-die Power Block PSiP architecture is first introduced to enable DC-DC buck converters with a current rating up to 40 A and a switching frequency in the MHz range. New high- and low-side NexFETs are specially designed and optimized for the new PSiP architecture to maximize its efficiency and power density. In particular, a new NexFET structure with its source electrode on the bottom side of the die (source-down) is designed to enable the innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. It is also observed that in synchronous buck converter very fast switching of power MOSFETs sometimes leads to high voltage oscillations at the phase node of the buck converter, which may introduce additional power loss and cause EMI related problems and undesirable electrical stress to the power MOSFET. At the same time, the synchronous MOSFET plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact the performance of the SyncFET. This dissertation introduces a new approach to effectively overcome the aforementioned challenges associated with the state-of-art technology. The threshold voltage of the low-side NexFET is intentionally reduced to minimize the conduction and body diode related power losses. Meanwhile, a monolithically integrated gate voltage pull-down circuitry is proposed to overcome the possible Cdv/dt induced turn-on issue inadvertently induced by the low VTH SynFET. Through extensive modeling and simulation, all these innovative concepts are integrated together in a power module and fabricated with a 0.35[micro]m process. With all these novel device technology improvements, the new power module delivers a significant improvement in efficiency and offers an excellent solution for future high frequency, high current density DC-DC converters. Megahertz operation of a Power Block incorporating these new device techniques is demonstrated with an excellent efficiency observed.ID: 031001367; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Adviser: Weiwei Deng.; Title from PDF title page (viewed May 8, 2013).; Thesis (M.S.M.E.)--University of Central Florida, 2012.; Includes bibliographical references (p. 84-88).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
32
Khan, Zahid. "Optimization of advanced telecommunication algorithms from power and performance perspective." Thesis, University of Edinburgh, 2011. http://hdl.handle.net/1842/5784.
Full textAbstract:
This thesis investigates optimization of advanced telecommunication algorithms from power and performance perspectives. The algorithms chosen are MIMO and LDPC. MIMO is implemented in custom ASIC for power optimization and LDPC is implemented on dynamically reconfigurable fabric for both power and performance optimization. Both MIMO and LDPC are considered computational bottlenecks of current and future wireless standards such as IEEE 802.11n for Wi-Fi and IEEE 802.16 for WiMax applications. Optimization of these algorithms is carried out separately. The thesis is organized implicitly in two parts. The first part presents selection and analysis of the VBLAST receiver used in MIMO wireless system from custom ASIC perspective and identifies those processing elements that consume larger area as well as power due to complex signal processing. The thesis models a scalable VBLAST architecture based on MMSE nulling criteria assuming block rayleigh flat fading channel. After identifying the major area and power consuming blocks, it proposes low power and area efficient VLSI architectures for the three building blocks of VBLAST namely Pseudo Inverse, Sorting and NULLing & Cancellation modules assuming a 4x4 MIMO system. The thesis applies dynamic power management, algebraic transformation (strength reduction), resource sharing, clock gating, algorithmic modification, operation substitution, redundant arithmetic and bus encoding as the low power techniques applied at different levels of design abstraction ranging from system to architecture, to reduce power consumption. It also presents novel architectures not only for the constituent blocks but also for the whole receiver. It builds the low power VBLAST receiver for single carrier and provides its area, power and performance figures. It then investigates into the practicality and feasibility of VBLAST into an OFDM environment. It provides estimated data with respect to silicon real estate and throughput from which conclusion can easily be drawn about the feasibility of VBLAST in a multi carrier environment. The second part of the thesis presents novel architectures for the real time adaptive LDPC encoder and decoder as specified in IEEE 802.16E standard for WiMax application. It also presents optimizations of encoder as well as decoder on RICA (Reconfigurable Instruction Cell Architecture). It has searched an optimized way of storing the H matrices that reduces the memory by 20 times. It uses Loop unrolling to distribute the instructions spatially depending upon the available resources to execute them concurrently to as much as possible. The parallel memory banks and distributed registers inside RICA allow good reduction in memory access time. This together with hardware pipelining provides substantial potential for optimizing algorithms from power and performance perspectives. The thesis also suggests ways of improvements inside RICA architecture.
33
Chang, Albert Hsu Ting. "Low-power high-performance SAR ADC with redundancy and digital background calibration." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/82177.
Full textAbstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (p. 195-199).
As technology scales, the improved speed and energy eciency make the successive- approximation-register (SAR) architecture an attractive alternative for applications that require high-speed and high-accuracy analog-to-digital converters (ADCs). In SAR ADCs, the key linearity and speed limiting factors are capacitor mismatch and incomplete digital-to-analog converter (DAC)/reference voltage settling. In this the- sis, a sub-radix-2 SAR ADC is presented with several new contributions. The main contributions include investigation of using digital error correction (redundancy) in SAR ADCs for dynamic error correction and speed improvement, development of two new calibration algorithms to digitally correct for manufacturing mismatches, design of new architecture to incorporate redundancy within the architecture itself while achieving 94% better energy eciency compared to conventional switching algorithm, development of a new capacitor DAC structure to improve the SNR by four times with improved matching, joint design of the analog and digital circuits to create an asynchronous platform in order to reach the targeted performance, and analysis of key circuit blocks to enable the design to meet noise, power and timing requirements. The design is fabricated in standard 1P9M 65nm CMOS technology with 1.2V supply. The active die area is 0.083mm² with full rail-to-rail input swing of 2.4V p-p . A 67.4dB SNDR, 78.1dB SFDR, +1.0/-0.9 LSB₁₂ INL and +0.5/-0.7 LSB₁₂ DNL are achieved at 50MS/s at Nyquist rate. The total power consumption, including the estimated calibration and reference power, is 2.1mW, corresponding to 21.9fJ/conv.- step FoM. This ADC achieves the best FoM of any ADCs with greater than 10b ENOB and 10MS/s sampling rate.
by Albert Hsu Ting Chang.
Ph.D.
34
Kim, Jina. "Low-Power System Design for Impedance-Based Structural Health Monitoring." Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/40400.
Full textAbstract:
Maintenance of the structural integrity and damage detection are critical for all massive and complicated new and aging structures. A structural health monitoring (SHM) system intends to identify damage on the structure under monitoring, so that necessary action can be taken in advance to avoid catastrophic results. Impedance-based SHM utilizes a piezoelectric ceramic as a collocated actuator and sensor, which measures the electrical impedance of the piezoelectric ceramic over a certain frequency range. The impedance profile of a structure under monitoring is compared against a reference profile obtained from the healthy structure. An existing approach called the sinc method adopts a sinc wave excitation and performs traditional discrete Fourier transform (DFT) based structural condition assessment. The sinc method requires rather intensive computing and a digital-to-analog converter (DAC) to generate a sinc excitation signal. It also needs an analog-to-digital converter (ADC) to measure the response voltage, from which impedance profile is obtained through a DFT. This dissertation investigates system design approaches for impedance-based structural health monitoring (SHM), in which a primary goal is low power dissipation.
First, we investigated behaviors of piezoelectric ceramics and proposed an electrical model in order to enable us to conduct system level analysis and evaluation of an SHM system. Unloaded and loaded piezoelectric ceramics were electrically modeled with lumped linear circuit components, which allowed us to perform system level simulations for various environmental conditions. Next, we explored a signaling method called the wideband method, which uses a pseudorandom noise (PN) sequence for excitation of the structure rather than a signal with a particular waveform. The wideband method simplifies generation of the excitation signal and eliminates a digital-to-analog converter (DAC). The system form factor and power dissipation is decreased compared to the previously existing system based on a sinc signal. A prototype system was implemented on a digital signal processor (DSP) board to validate its approach. Third, we studied another low-power design approach which employs binary signals for structural excitation and structural response measurement was proposed. The binary method measures only the polarity of a response signal to acquire the admittance phase, and compares the measured phase against that of a healthy structure. The binary method eliminates the need for a DAC and an ADC. Two prototypes were developed: one with a DSP board and the other with a microcontroller board. Both prototypes demonstrated reduction of power dissipation compared with those for the sinc method and for the wideband method. The microcontroller based prototype achieved an on-board SHM system. Finally, we proposed an analytical method to assess the quality of the damage detection for the binary method. Using our method, one can obtain the confidence level of a damage detection for a given damage distance.Ph. D.
35
Bishnoi, Rajendra Kumar [Verfasser], and M. [Akademischer Betreuer] Tahoori. "Reliable Low-Power High Performance Spintronic Memories / Rajendra Kumar Bishnoi ; Betreuer: M. Tahoori." Karlsruhe : KIT-Bibliothek, 2017. http://d-nb.info/1136021795/34.
Full text
36
Shang, Pengju. "Research in high performance and low power computer systems for data-intensive environment." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5033.
Full textAbstract:
According to the data affinity, DAFA re-organizes data to maximize the parallelism of the affinitive data, and also subjective to the overall load balance. This enables DAFA to realize the maximum number of map tasks with data-locality. Besides the system performance, power consumption is another important concern of current computer systems. In the U.S. alone, the energy used by servers which could be saved comes to 3.17 million tons of carbon dioxide, or 580,678 cars {Kar09}. However, the goals of high performance and low energy consumption are at odds with each other. An ideal power management strategy should be able to dynamically respond to the change (either linear or nonlinear, or non-model) of workloads and system configuration without violating the performance requirement. We propose a novel power management scheme called MAR (modeless, adaptive, rule-based) in multiprocessor systems to minimize the CPU power consumption under performance constraints. By using richer feedback factors, e.g. the I/O wait, MAR is able to accurately describe the relationships among core frequencies, performance and power consumption. We adopt a modeless control model to reduce the complexity of system modeling. MAR is designed for CMP (Chip Multi Processor) systems by employing multi-input/multi-output (MIMO) theory and per-core level DVFS (Dynamic Voltage and Frequency Scaling).; TRAID deduplicates this overlap by only logging one compact version (XOR results) of recovery references for the updating data. It minimizes the amount of log content as well as the log flushing overhead, thereby boosts the overall transaction processing performance. At the same time, TRAID guarantees comparable RAID reliability, the same recovery correctness and ACID semantics of traditional transactional processing systems. On the other hand, the emerging myriad data intensive applications place a demand for high-performance computing resources with massive storage. Academia and industry pioneers have been developing big data parallel computing frameworks and large-scale distributed file systems (DFS) widely used to facilitate the high-performance runs of data-intensive applications, such as bio-informatics {Sch09}, astronomy {RSG10}, and high-energy physics {LGC06}. Our recent work {SMW10} reported that data distribution in DFS can significantly affect the efficiency of data processing and hence the overall application performance. This is especially true for those with sophisticated access patterns. For example, Yahoo's Hadoop {refg} clusters employs a random data placement strategy for load balance and simplicity {reff}. This allows the MapReduce {DG08} programs to access all the data (without or not distinguishing interest locality) at full parallelism. Our work focuses on Hadoop systems. We observed that the data distribution is one of the most important factors that affect the parallel programming performance. However, the default Hadoop adopts random data distribution strategy, which does not consider the data semantics, specifically, data affinity. We propose a Data-Affinity-Aware (DAFA) data placement scheme to address the above problem. DAFA builds a history data access graph to exploit the data affinity.; The evolution of computer science and engineering is always motivated by the requirements for better performance, power efficiency, security, user interface (UI), etc {CM02}. The first two factors are potential tradeoffs: better performance usually requires better hardware, e.g., the CPUs with larger number of transistors, the disks with higher rotation speed; however, the increasing number of transistors on the single die or chip reveals super-linear growth in CPU power consumption {FAA08a}, and the change in disk rotation speed has a quadratic effect on disk power consumption {GSK03}. We propose three new systematic approaches as shown in Figure 1.1, Transactional RAID, data-affinity-aware data placement DAFA and Modeless power management, to tackle the performance problem in Database systems, large scale clusters or cloud platforms, and the power management problem in Chip Multi Processors, respectively. The first design, Transactional RAID (TRAID), is motivated by the fact that in recent years, more storage system applications have employed transaction processing techniques Figure 1.1 Research Work Overview] to ensure data integrity and consistency. In transaction processing systems(TPS), log is a kind of redundancy to ensure transaction ACID (atomicity, consistency, isolation, durability) properties and data recoverability. Furthermore, high reliable storage systems, such as redundant array of inexpensive disks (RAID), are widely used as the underlying storage system for Databases to guarantee system reliability and availability with high I/O performance. However, the Databases and storage systems tend to implement their independent fault tolerant mechanisms {GR93, Tho05} from their own perspectives and thereby leading to potential high overhead. We observe the overlapped redundancies between the TPS and RAID systems, and propose a novel reliable storage architecture called Transactional RAID (TRAID).ID: 030423445; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 119-128).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Science
37
Guo, Shuibao. "High performance digital controller for high-frequency low-power integrated DC/DC SMPS." Lyon, INSA, 2009. http://theses.insa-lyon.fr/publication/2009ISAL0033/these.pdf.
Full textAbstract:
Bien qu'un sujet de recherché important, le contrôle numérique n'a pas encore été appliqué en pratique aux convertisseurs de tension à découpage basse-puissance. Les appareils portables sont encore conçus avec des convertisseurs de tension à boucle de contrôle analogique. Ceci est dû à la complexité de l'implémentation d'un contrôleur numérique, aux contraintes de coût et l'absente d'architecture de contrôleur ayant prouvé leur efficacité pour de hautes fréquences de découpage. Les compromis entre performances, consommation, coût silicium limitent encore le développement des contrôleurs numériques. Les outils de développement efficaces existent pour concevoir des structures de contrôle numérique dans le contexte de la haute intégration (VLSI), dont des ASICs et des FPGAs. Il est plus commode d'aborder la conception de boucles de contrôles numériques dans l'environnement des régulateurs de tension à découpage pour les circuits intégrés sur batterie. Les travaux dans ce contexte sont généralisables à celui des FPGAs et à plus large échelle à des dispositifs de conversion d'énergie continue de plus forte puissance. L'objet des travaux de thèse concerne l'exploitation de diverses architectures des blocs constituants un contrôleur numérique : les lois de commande et la traduction en largeur d'impulsion des décisions en temps-réel du contrôleur (Digital pulse-width modulation). Par ailleurs, faute d'un accès matériel suffisant à une vérification expérimentale sous la forme d'ASICs, les résultats concernent en premier lieu la méthodologie de développement et la vérification couvre un grand nombre de besoins industriels et prépare la perspective de travaux dans un contexte d'intégration ultime basse puissanceDespite being a popular research topic, digital control is still seldom applied in practical low-power high-frequency integrated SMPS converters. Phones, PDAs and music/video players are still mainly designed with analog PWM control inside the voltage regulator blocks. This is mainly due to the apparent complexity of implementation, cost constraint and absence of digital controller architectures that can support operation at switching frequencies significantly higher than 1MHz with low-power consumption features. Broader acceptance of digital techniques in low-power high-frequency SMPS is still hampered by practical problems of the combination of cost issues, trade-off performances and power consumption. However, with the rapid development of Very Large-Scale Integration (VLSI) technologies and CMOS manufacturing technique, and associated with their design tools in the last decade, it is now very possible to realize the high performance digital control in power electronics system by high-speed low-power digital devices (FPGA, ASIC, etc). With these advantages, the implementation of digital controller has become more feasible for low-power high-frequency SMPS design in portable electronics applications. The research interest of the thesis is to explore practical ways of incorporating advantages of digital control in practical implementation, investigates issues of digital controller implementation at lower power levels, gives detailed guidelines for digital controller design and hardware selection, and proposes new hardware solutions for the main functional digital controller blocks. Two main objectives of this work focus the implementation of high-resolution high-frequency digital PWM (DPWM) and high-performance digital control algorithms for SMPS in FPGA-based realization
38
Li, Hao. "Low power technology mapping and performance driven placement for field programmable gate arrays." [Tampa, Fla.] : University of South Florida, 2004. http://purl.fcla.edu/fcla/etd/SFE0000523.
Full text
39
Chemanchula, Hemanth Kumar. "A NEW LOW-POWER AND HIGH PERFORMANCE SINUSOIDAL THREE PHASE CLOCK DYNAMIC DESIGN." OpenSIUC, 2015. https://opensiuc.lib.siu.edu/theses/1809.
Full textAbstract:
Important characteristic of any VLSI design circuit is its power reliability, high operating speed and low silicon area implementation. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. The use of pipelines can also provide high circuit operating speeds. However, as the operating frequency increases, the number of pipeline stages should also increase and so the memory elements. These memory elements increases the area of implementation and restricts the maximum achievable frequency due to their delays. Memoryless pipelines based on dynamic design address these issues but, still requires high power consumption for the clock signal. In this thesis we present a sinusoidal three-phase clocking scheme that reduces the power required by the clock and offers high circuit operating frequencies. Thus the proposed technique provides advantages over preexisting techniques in terms of power requirement, area over head and operating speed.
40
Hansson, Martin. "Low-Power Multi-GHz Circuit Techniques for On-chip Clocking." Licentiate thesis, Linköping : Linköping University, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7545.
Full text
41
Værnes, Magne. "Trade-offs between Performance and Robustness for Ultra Low Power/Low Energy Subthreshold D flip-flops in 65nm CMOS." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2013. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-22704.
Full textAbstract:
The need for Ultra Low Power systems has increased with increasing number of portable devices. The maintenance costs of battery powered systems can be greatly reduced by improving the battery time, especially in places where battery replacement is hard or impossible. Implementation of subthreshold D flip-flops in layout is one step closer to having a subthreshold building block library. The task for this thesis is to implement D flip-flop blocks, which are highly suitable for subthreshold operation in layout. These are the PowerPC 603, C$^2$MOS, a Classic NAND-based D flip-flop, and two Minority3-based D flip-flops. The D flip-flops are first custom designed for $250mV$ in schematic at transistor level, and then implemented in layout. The implementation in layout focuses on high robustness against process variations, by using high regularity for the cost of area.The D flip-flops are simulated in both schematic and layout, and the results are compared to each other and earlier results found in papers. The results show that the PowerPC 603 has the lowest PDP, the lowest power consumption, very low propagation delay, and an average relative standard deviation for delay. The C$^2$MOS has the lowest propagation delay, low power consumption and low PDP results. However, it has the highest relative standard deviation on delay. The Minority3-based D flip-flops have a very low relative standard deviation for delay, which makes them the most robust against process variations in this sense. However, they have the highest propagation delay, highest power consumption and PDP, and consumes the highest chip area. The Classic NAND-based D flip-flop has good PDP and power consumption results, but a high delay and average standard deviation for delay.Earlier papers show similar results for the C$^2$MOS and the PowerPC 603, but no results are found for the rest. Future work consists of implementing and testing forced-stacked blocks, body biasing, high threshold voltage transistors, and tape-out measurements.
42
Saluru, Sarat K. "Projection of TaSiOx/In0.53Ga0.47As Tri-gate transistor performance for future Low-Power Electronic Applications." Thesis, Virginia Tech, 2017. http://hdl.handle.net/10919/78028.
Full textAbstract:
The aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistor over the past 50 years has resulted in an exponential increase in device density, which consequentially has increased computation power rapidly. This has pronounced the necessity to scale the device's supply voltage (VDD) in to order to maintain low-power device operation. However, the scaling of VDD can degrade drive current significantly due to the low carrier mobility of Si. To overcome the key challenges of dimensional and voltage scaling required for low-power electronic operation without degradation of device characteristics, the adoption of alternate channel materials with low bandgap with superior transport properties will play a crucial role to improve the computation ability of the standard integrated circuit (IC). The requirement of high-mobility channel materials allows the industry to harness the potential of III-V semiconductors and germanium. However, the adoption of such high mobility materials as bulk substrates remains cost-prohibitive even today. Hence, another key challenge lies in the heterogeneous integration of epitaxial high-mobility channel materials on the established cost-effective Si platform. Furthermore, dimensional scaling of the device has led to a change in architecture from the conventional planar MOSFET to be modified to a 3-D Tri-gate architecture which provides fully depleted characteristics by increasing the inversion layer area and hence, providing superior electrostatic control of the device channel to address short channel effects such as subthreshold slope (SS) and drain induced barrier lowering (DIBL). The Tri-gate configuration provides a steeper SS effectively reducing leakage current (IOFF), thereby decreasing dynamic power consumption and increasing device performance. Recently, Tantalum silicate (TaSiOx) a high-k dielectric has been shown to exhibit superior interfacial quality on multiple III-V materials. However, there is still ambiguity as to the potential of short-channel devices incorporating alternate channel (III-V) materials which is the basis of this research, to demonstrate the feasibility of future high-mobility n-channel InGaAs material integration on Si for high- speed, low-power, high performance CMOS logic applications.Master of Science
43
Reehal, Gursharan Kaur. "Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240.
Full text
44
Betowski, David James. "Optimizing the performance of direct digital frequency synthesizers for low-power wireless communication systems." Online access for everyone, 2004. http://www.dissertations.wsu.edu/Thesis/Fall2004/d%5Fbetowski%5F111104.pdf.
Full text
45
Opoku, Agyeman Michael. "Optimizing heterogeneous 3D networks-on-chip architectures for low power and high performance applications." Thesis, Glasgow Caledonian University, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.688307.
Full text
46
Pastorek, Matej. "Fabrication and characterization of III-V MOSFETs for high performance and low power applications." Thesis, Lille 1, 2017. http://www.theses.fr/2017LIL10186/document.
Full textAbstract:
La réduction de la taille des circuits CMOS vers des dimensions extrêmement petites est telle que son élément constitutif, le MOSFET à base de Silicium, commence à souffrir d’une faible efficacité de puissance. L’une des alternatives qui ne peut être écartée est le concept du transistor MOSFET à base de matériaux III-V. Ses propriétés de transport extraordinaires, apportées par les matériaux III-V, promettent de réduire la tension d’alimentation des circuits CMOS sans réduire leur performance. Cette transition technologique pourrait aboutir non seulement à des circuits CMOS plus petits, plus écologiques mais aussi à des circuits co-intégrés avec des technologies RF. C’est dans ce contexte que nous présentons, dans ce travail de thèse, la fabrication et la caractérisation des transistors MOSFET Ultra-Thin Body (UTB) à base d’InAs et du transistor FinFET à base d’InAs. La combinaison d’une longueur de grille extrêmement réduite, d’une faible résistance d’accès et d’une mobilité impressionnante dans le canal d’InAs a permis d’obtenir des courants importants (IMAX=2000mA/mm pour LG=25nm). Egalement, l‘utilisation des architectures du canal de type ultra mince et FinFET permet d’obtenir un bon contrôle électrostatique. De plus, une spécificité du procédé technologique présentée dans ce travail est les réalisations des contacts et du canal par une épitaxie par jets moléculaires (MBE) localiséeScaling the size of CMOS circuits to extremely small dimensions gets the semiconductor industry to a point where its cornerstone, Silicon-based MOSFET starts to suffer a poor power efficiency. In the quest for alternative solutions cannot be omitted a concept of III-V MOSFET. Its outstanding transport properties hold a promise of reduced CMOS supply voltage without compromising the performance. This can path a way not only to the smaller, greener electronics but also to more co-integrated RF and CMOS electronics. In this context, we present fabrication and characterization of Ultra-Thin body InAs MOSFETs and InAs FinFET. Synergy of a deeply scaled gate length, low access resistance and a high mobility of InAs channel enabled to obtain impressively high drain currents (IMAX=2000mA/mm for LG=25nm). Equally, the introduction of Ultra-Thin body and FinFET channel design provides an improved electrostatic control. A specific feature of the process presented in this work is a fabrication of contacts and channel by localized molecular beam epitaxy MBE epitaxy
47
Lin, Wen-Hsin, and 林文信. "A Study in Performance Improvement of Low-Power Switching Mode Power SupplyA Study in Performance Improvement of Low-Power Switching Mode Power SupplyA Study in Performance Improvement of Low-Power Switching Mode Power Supply." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/82453183666610198843.
Full textAbstract:
碩士國立高雄應用科技大學
電機工程系
99
This thesis examines the power converter framework, and adopt the flyback converter is a schema. Used with a new analog PWM control IC (TEA1532) of Fixed Frequency Mode and Cycle Skipping Mode. Design of a range of input voltages of 90VAC to 264VAC, input frequency 47Hz arrives at 63Hz, output voltage +24VDC, total power output 25W, and conforms to the energy laws and regulations. In the article except for one of the important components for the provision of detailed design, characteristics of prototype machine authentication, to results and its comparison with older models have been proposed, as an important reference cooperative enterprises improve the performance of existing products.
48
Wu, Chia-Cho, and 吳家徹. "A High-Performance and Low-Power Viterbi Decoder." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/84820792617170034987.
Full textAbstract:
碩士國立交通大學
電子工程系
91
The mobile and wireless systems become more and more important these years. Therefore, a low power design is the main issue of the overall system. In lots of mobile or wireless systems, the computing complexity is concentrated in the Viterbi decoder. So, to reduce the computing complexity of the Viterbi decoder is equivalent to reduce most of the power consumption in overall communication system. However, most designers trade the throughput rate for power consumption. This kind of the designs can't satisfy the high data rate application nowadays. Thus, we propose a 133Mb/s, 64-state, radix-4, 16-level soft decision Viterbi decoder with the path merging and prediction techniques. In the prediction algorithm, over 90\% survivor path can be forecasted. And, the memory access reduces more than 70\% on the average with the aid of path merging property. Thus the proposed design not only considers the error correction capacity, but also provides a high speed and low power solution. A test chip is fabricated in 0.35 $\mu m$ 1P4M CMOS process, and can achieve the maximum throughout rate of 133Mbit/s under 3.3V. The measured power consumption is below 55mW under 66Mb/s throughput rate at 2.2V.
49
Lin, Sheng-kai, and 林聖凱. "Design of High-Performance Low-Power Adder Cores." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/88635681380747350476.
Full textAbstract:
碩士逢甲大學
資訊電機工程碩士在職專班
100
To overcome the full adder without driving outputs structure of that carries signal attenuation issue and improve the full adder with driving outputs structure issue of circuit performance, this paper presents the structure of four complementary binary full adder and four design methods of adder modules. We use four complementary binary full adder circuit structure FA_A, FA_B, FA_C and FA_D adder with four kinds of tree construction techniques, design of M1 ~ M8 eight kinds of high-performance adder cores. In order to compare the performance of all adder circuits, this paper using TSMC 0.18-μm CMOS process technology and HSPICE circuit simulation software to experiment. This paper will M1 ~ M8 adder cores with conventional CMOS full adder, N-HPSC adder, Hybrid-CMOS, DPL-FA and SR-CPL full adder are cascaded into a 12-bit ripple carry adder to do analysis and comparison. We designed the adder modules regardless of the transistor count, the average power consumption, critical path delay time and power-delay product and so have a good advantage. When the operating voltage Vdd = 1.8V when, M2, M3 and M6 with the least transistor count (Tr. #), you can save 38% ~ 62%, M6 power consumption (Pd) decreased -2% ~ 19%, M8 propagation delay time (Td) minimum, reduce the 8% ~ 54%, M2 power delay product (PDP) best reduced by 17% to 58%. When the operating voltage Vdd = 0.6V when, M4 also has the shortest propagation delay time (Td) and the minimum power delay product (PDP), decreased 13% to 30% and 35% to 68%, while the M6 can save 20 % to 53% of power consumption (Pd). When M1 ~ M8 eight kinds of adder cores connected in series to 18-bit RCA, its experimental results with the series into a 12-bit RCA trend is the same.These results confirm our adder design approach is both practical and effective, if these adder modules applied to arithmetic circuit and electronic system, will be able to improve electronic system overall performance.
50
Chen, Ci-An, and 陳麒安. "Design of High Performance Low Power Delay-Locked Loops." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/k633es.
Full textAbstract:
碩士國立東華大學
電機工程學系
100
In recent years, because of the advances in integrated circuit process technology, a size of device is reduced continuously. A high speed clock signal for more and more complicated and high-speed systems are needed. Delay-locked loop (DLL) with easy to design and the advantages of inherent stability is a suitable for use in clock generators. In this thesis, two architecture of delay-locked loop (DLL) are proposed. The first circuit is applied for frequency multiplier. The second one is applied for wide locking range. The proposed circuit is simulated using TSMC standard 0.18um CMOS process technology provided by Chip Implementation Center (CIC). The circuit simulation tool is used to the hspice 2008 software and the layout tool is used to the laker layout editor software. The first circuit is based on multiple output frequency multipliers with automatic reset function for delay-locked loop. Besides low power, the proposed frequency multiplier has wide output frequency range and multiple output ports. The phase detector and charge pump are modified and combined to be a simplified charging circuit model, which makes the designed DLL to achieve the locked state without discharging step. The wide output frequency range is from 125MHz to 3GHz. The peak-to-peak jitter is 9.13ps at the output frequency of 2.5GHz. At a supply voltage of 1.8V, the power consumption is 5.6mW or 16.5mW with or without buffer respectively. The second circuit is based on delay-locked loop for wide locking range. A feedback signal detection circuit is added to judge whether the feedback signal enters into the locked state or not. Using a simple signal reverse, the overall circuit can achieve a wide locking range. The operating frequency of the proposed circuit is from 100MHz to 1GHz. The static phase error is 1.93ps at the operating frequency of 1GHz. At a supply voltage of 1.8V, the power consumption is 12mW. Two circuits are proposed in this thesis. The first circuit is a frequency multiplier to achieve low power consumption and wide output frequency range and is a suitable for application in the system circuit with multiple signals. The second circuit uses a simple signal reverse to achieve low power consumption and wide locking range for wide locking range, the wide locking range is a suitable for application in the system circuit with multiple signal synchronization. The two circuits help to reduce power consumption in the overall system.