Dissertations / Theses on the topic 'Low power high-speed links'
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Fang, Yuan [Verfasser], Klaus [Akademischer Betreuer] Hofmann, Franko [Akademischer Betreuer] Küppers, Marius [Akademischer Betreuer] Pesavento, Christian [Akademischer Betreuer] Hochberger, and Gersem Herbert [Akademischer Betreuer] De. "PHY Link Design and Optimization For High-Speed Low-Power Communication Systems / Yuan Fang. Betreuer: Klaus Hofmann ; Franko Küppers ; Marius Pesavento ; Christian Hochberger ; Herbert De Gersem." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2015. http://d-nb.info/1111112444/34.
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Saadallah, Nisrine. "High-speed low-power asynchronous circuits." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=80140.
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This thesis presents several design experiments for high-performance power-efficient asynchronous circuits.In Chapter two we present a new asynchronous pipeline logic family with improved latency and throughput compared to several other asynchronous pipeline circuits. The channels between pipeline stages use data encoding and a small set of minimum-delay timing constraints that permit modular design with few dependencies on technology and layout. We develop circuit blocks that implement linear pipelines as well as forking, joining and data-dependent decisions. An implementation in 0.18mum CMOS exhibits a latency of 56ps per pipeline stage and throughput of 4.8-giga data item per second (GDI/s) in Hspice simulation.
We also present the design of a low-control-overhead asynchronous microprocessor integrated with a high-speed sampling FIFO. This is an experiment in exploring the benefits of asynchronous design in high-speed embedded DSP applications. It reports on the design approach, implementation and performance, including a comparison with the synchronous version of the microprocessor.
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Ibrahim, Sameh Ahmed Assem Mostafa. "High-speed low-power equalizers for high-loss channels." Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=2026920921&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Jiang, Hao. "High-power, high-speed p-i-n- photodiodes for analog fiber optic links /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2000. http://wwwlib.umi.com/cr/ucsd/fullcit?p9970665.
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Nho, Hyunwoo. "A high-speed, low-power 3D-SRAM architecture /." May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
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Zheng, Shijie M. Eng Massachusetts Institute of Technology. "A low cost asynchronous eye diagram reconstruction system for high speed links." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/85233.
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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 97-98).
As link communication data rate increases, there is an increasing need for a more cost eective way to test and monitor signal integrity in link communication systems. Specifically, eye diagrams are valuable visual aids to analyze and quantify digital signal quality. This thesis presents a novel low cost eye diagram reconstruction system using asynchronous undersampling technique, which solves a key problem in performance monitoring in systems where synchronous sampling is not available, such as video switches. Existing works are studied and compared to this work in performance and cost. The proposed system is designed as a system-on-chip (SOC) and contains an undersampling ADC, aliased frequency estimator and a simple reconstruction algorithm. Major building blocks are implemented and simulated in 65nm CMOS process. Extensive system level analysis and simulations demonstrate functionality and performance of the system working at 10Gb/s maximum data rate.
by Shijie Zheng.
M. Eng.
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Wolfe, Kurt A. "Radiation tolerant, high speed, low power gallium arsenide logic." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1993. http://handle.dtic.mil/100.2/ADA277293.
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Zargaran, Yazd Arash. "Design techniques for high-speed low-power wireline receivers." Thesis, University of British Columbia, 2013. http://hdl.handle.net/2429/44660.
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High-speed data transmission through wireline links, either copper or optical based, has become the backbone for modern communication infrastructure. Since at multi-Gb/s data rates the transmitted signal is attenuated and distorted by the channel, sophisticated analog front-end and/or digital signal processing are required at the receiver (RX) to recover data and clock from the received signal.
In this thesis, both analog- and digital-based receivers are investigated, and power-reduction techniques are exploited at both system- and circuit levels. A speculative successive-approximation register (speculative/SAR) digitization algorithm is proposed for use at the receiver front-end of digital receivers that combines equalization and data recovery with the digitization step at the front-end analog-to-digital converter (ADC). Furthermore, architecture for quadrature clock generation is proposed which is of use in both analog and digital receivers. Then, an analog clock and data recovery (CDR) architecture suitable for high data rates (e.g., beyond 10 Gb/s) is proposed that utilizes a wideband data phase generation technique to facilitate mixer-based phase detection. The CDR architecture is implemented and experimentally validated for a 12.5 Gb/s system. Finally, a mixed-mode hardware-efficient CDR architecture is proposed that exploits both analog and digital design techniques to reach a robust operation suited for long-haul optical link communications. Proof-of-concept prototypes of the proposed RX architectures are designed and implemented in 65 nm and 90 nm CMOS processes. The prototypes are successfully tested. Note that although individual performance merits of the each prototype may not necessarily outperform that of the state-of-the-art, however, the prototypes confirm the feasibility of the proposed structure. Furthermore, the proposed architectures can be used at higher data rates particularly if more advanced technologies with higher device transit frequency, (fT), is used.
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Safi-Harab, Mouna. "Low-power low-voltage high-speed delta-sigma analog-to-digital converters." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79258.
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The increasingly stringent requirements of today's communication systems and portable devices are imposing two challenges on the design of Analog-to-Digital Converters (ADC) and delta-sigma modulators (DeltaSigmaM) architecture in particular.The first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range.
This challenge in extending the operational speed of DeltaSigmaM is further rendered more complicated by the ever shrinking transistor dimension. As predicted by the Semiconductor Industry Association (SIA) Roadmap for CMOS technology, the transistor dimension will reach 0.05 mum in 2011. With this dramatic shrink in the transistor length, and as a result in the supply voltage, device modelling becomes ambiguous and circuit non-idealities more pronounced. The design of the main analog building blocks that minimize the time-to-market is therefore becoming very complicated.
These two issues will be addressed in this thesis, namely a new design method that will minimize the design cycle of delta-sigma analog-to-digital converters (DeltaSigma ADCs) intended for high-speed applications. This method will be demonstrated efficient in the implementation of two state-of-the-art modulators in terms of performance using a widely adopted figure of merit.
The validity of the top-down design methodology was verified through the fabrication of two prototype integrated circuits (ICs), both in TSMC 0.18 mum CMOS technology. In the first chip, a single-bit, fourth-order DeltaSigma ADC was implemented achieving more than 12-bit resolution. The second chip further validated the methodology to include higher resolution, in the range of 13 bits, multi-bit DeltaSigma ADCs. The experimental results from both prototype ICs closely mimic the system-level behavior of the designed modulator.
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Avadhanam, Karthik. "A new high speed low power Dynamic Programmable Logic Array /." Available to subscribers only, 2007. http://proquest.umi.com/pqdweb?did=1453188921&sid=5&Fmt=2&clientId=1509&RQT=309&VName=PQD.
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Sundström, Timmy. "Design of High‐Speed, Low‐Power, Nyquist Analog‐to‐Digital Converters." Licentiate thesis, Linköping University, Linköping University, Electronic Devices, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-51375.
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The scaling of CMOS technologies has increased the performance of general purposeprocessors and DSPs while analog circuits designed in the same process have not been ableto utilize the process scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. In order to design efficient analog‐to‐digital converters in nanoscale CMOS there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of what the process has tooffer.
This thesis explores the power dissipation of Nyquist rate analog‐to‐digital converters andtheir lower bounds, set by both the thermal noise limit and the minimum device and feature sizes offered by the process. The use of digital error correction, which allows for lowaccuracy analog components leads to a power dissipation reduction. Developing the bounds for power dissipation based on this concept, it is seen that the power of low‐to‐medium resolution converters is reduced when going to more modern CMOS processes, something which is supported by published results.
The design of comparators is studied in detail and a new topology is proposed which reduces the kickback by 6x compared to conventional topologies. This comparator is used in two flash ADCs, the first employing redundancy in the comparator array, allowing for the use of small sized, low‐power, low‐accuracy comparators to achieve an overall low‐power solution. The flash ADC achieves 4 effective bits at 2.5 GS/s while dissipating 30 mW of power.
The concept of low‐accuracy components is taken to its edge in the second ADC which oes not include a reference network, instead relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference‐free ADC achieves a resolution of 3.69 bits at 1.5 GS/s while dissipation 23 mW showing that process variations not necessarily must be seen as detrimental to circuit performance but rather can be seen as a source of diversity.
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Sundström, Timmy. "Design of high-speed, low-power, Nyquist analog-to-digital converters /." Linköping : Department of Electrical Engineering, Linköping University, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-51375.
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Zhong, Jian Yu. "Design of high-speed power-efficient SAR-type ADCs." Thesis, University of Macau, 2017. http://umaclib3.umac.mo/record=b3691882.
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Atkinson, M. J. "The design of efficient radial turbines for low power applications." Thesis, University of Sussex, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.262695.
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Alloatti, Luca [Verfasser]. "High-Speed, Low-Power and Mid-IR Silicon Photonics Applications / Luca Alloatti." Karlsruhe : KIT Scientific Publishing, 2013. http://www.ksp.kit.edu.
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Katyal, Vipul. "Low power high speed and high accuracy design methodologies for pipeline Analog-to-Digital Converters." [Ames, Iowa : Iowa State University], 2008.
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Margarit, Taulé Josep Maria. "Low-power CMOS digital-pixel Imagers for high-speed uncooled PbSe IR applications." Doctoral thesis, Universitat Politècnica de Catalunya, 2015. http://hdl.handle.net/10803/336094.
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This PhD dissertation describes the research and development of a new low-cost medium wavelength infrared MWIR monolithic imager technology
for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapour phase deposition (VPD)
PbSe-based medium wavelength IR (MWIR) detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector.
The work supports on the hypothesis that, by the use of the preceding design techniques, current standard inexpensive CMOS technologies fulfill all
operational requirements of the VPD PbSe detector in terms of connectivity, reliability, functionality and scalability to integrate the device. The resulting monolithic PbSe-CMOS camera must consume very low power, operate at kHz frequencies, exhibit good uniformity and fit the CMOS read-out active pixels in the compact pitch of the focal plane, all while addressing the particular characteristics of the MWIR detector: high dark-to-signal ratios, large input parasitic capacitance values and remarkable mismatching in PbSe integration.
In order to achieve these demands, this thesis proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation.
The main aim is to potentiate the integration of PbSe-based infra-red (IR)-image sensing technologies so as to widen its use, not only in distinct scenarios, but also at different stages of PbSe-CMOS integration maturity. For this purpose, we posit to investigate a comprehensive set of functional blocks distributed in two parallel approaches:
• Frame-based “Smart” MWIR imaging based on new DPS circuit topologies with gain and offset FPN correction capabilities. This research
line exploits the detector pitch to offer fully-digital programmability at pixel level and complete functionality with input parasitic capacitance compensation and internal frame memory.
• Frame-free “Compact”-pitch MWIR vision based on a novel DPS lossless analog integrator and configurable temporal difference, combined with asynchronous communication protocols inside the focal plane. This strategy is conceived to allow extensive pitch compaction and readout speed increase by the suppression of in-pixel digital filtering, and the use of dynamic bandwidth allocation in each pixel of the FPA.
In order make the electrical validation of first prototypes independent of the expensive PbSe deposition processes at wafer level, investigation is extended as well to the development of affordable sensor emulation strategies and integrated test platforms specifically oriented to image read-out integrated circuits. DPS cells, imagers and test chips have been fabricated and characterized in standard 0.15μm 1P6M, 0.35μm 2P4M and 2.5μm 2P1M CMOS technologies, all as part of research projects with industrial partnership.
The research has led to the first high-speed uncooled frame-based IR quantum imager monolithically fabricated in a standard VLSI CMOS technology, and has given rise to the Tachyon series [1], a new line of commercial IR cameras used in real-time industrial, environmental and transportation control systems. The frame-free architectures investigated in this work represent a firm step forward to push further pixel pitch and system bandwidth up to the limits imposed by the evolving PbSe detector in future generations of the device.La present tesi doctoral descriu la recerca i el desenvolupament d'una nova tecnologia monolítica d'imatgeria infraroja de longitud d'ona mitja (MWIR), no refrigerada i de baix cost, per a usos industrials d'alta velocitat. El treball pren el relleu dels últims avenços assolits pel soci industrial NIT S.L. en el camp dels detectors MWIR de PbSe depositats en fase vapor (VPD), afegint-hi coneixement fonamental en la investigació de noves tècniques de disseny de circuits VLSI analògics i mixtes pel desenvolupament del dispositiu integrat de lectura unit al detector pixelat. Es parteix de la hipòtesi que, mitjançant l'ús de les esmentades tècniques de disseny, les tecnologies CMOS estàndard satisfan tots els requeriments operacionals del detector VPD PbSe respecte a connectivitat, fiabilitat, funcionalitat i escalabilitat per integrar de forma econòmica el dispositiu. La càmera PbSe-CMOS resultant ha de consumir molt baixa potència, operar a freqüències de kHz, exhibir bona uniformitat, i encabir els píxels actius CMOS de lectura en el pitch compacte del pla focal de la imatge, tot atenent a les particulars característiques del detector: altes relacions de corrent d'obscuritat a senyal, elevats valors de capacitat paràsita a l'entrada i dispersions importants en el procés de fabricació. Amb la finalitat de complir amb els requisits previs, es proposen arquitectures de sensors de visió de molt baix acoblament interpíxel basades en l'ús d'una matriu de pla focal (FPA) de píxels actius exclusivament digitals. Cada píxel sensor digital (DPS) està equipat amb mòduls de comunicació d'alta velocitat, autopolarització, cancel·lació de l'offset, conversió analògica-digital (ADC) i correcció del soroll de patró fixe (FPN). El consum en cada cel·la es minimitza fent un ús exhaustiu del MOSFET operant en subllindar. L'objectiu últim és potenciar la integració de les tecnologies de sensat d'imatge infraroja (IR) basades en PbSe per expandir-ne el seu ús, no només a diferents escenaris, sinó també en diferents estadis de maduresa de la integració PbSe-CMOS. En aquest sentit, es proposa investigar un conjunt complet de blocs funcionals distribuïts en dos enfocs paral·lels: - Dispositius d'imatgeria MWIR "Smart" basats en frames utilitzant noves topologies de circuit DPS amb correcció de l'FPN en guany i offset. Aquesta línia de recerca exprimeix el pitch del detector per oferir una programabilitat completament digital a nivell de píxel i plena funcionalitat amb compensació de la capacitat paràsita d'entrada i memòria interna de fotograma. - Dispositius de visió MWIR "Compact"-pitch "frame-free" en base a un novedós esquema d'integració analògica en el DPS i diferenciació temporal configurable, combinats amb protocols de comunicació asíncrons dins del pla focal. Aquesta estratègia es concep per permetre una alta compactació del pitch i un increment de la velocitat de lectura, mitjançant la supressió del filtrat digital intern i l'assignació dinàmica de l'ample de banda a cada píxel de l'FPA. Per tal d'independitzar la validació elèctrica dels primers prototips respecte a costosos processos de deposició del PbSe sensor a nivell d'oblia, la recerca s'amplia també al desenvolupament de noves estratègies d'emulació del detector d'IR i plataformes de test integrades especialment orientades a circuits integrats de lectura d'imatge. Cel·les DPS, dispositius d'imatge i xips de test s'han fabricat i caracteritzat, respectivament, en tecnologies CMOS estàndard 0.15 micres 1P6M, 0.35 micres 2P4M i 2.5 micres 2P1M, tots dins el marc de projectes de recerca amb socis industrials. Aquest treball ha conduït a la fabricació del primer dispositiu quàntic d'imatgeria IR d'alta velocitat, no refrigerat, basat en frames, i monolíticament fabricat en tecnologia VLSI CMOS estàndard, i ha donat lloc a Tachyon, una nova línia de càmeres IR comercials emprades en sistemes de control industrial, mediambiental i de transport en temps real.
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Mohiuddin, Muhammad. "InGaAs/InA1As Double Heterojunction Bipolar transistors for high-speed, low-power digital applications." Thesis, University of Manchester, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.511942.
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Oka, Tohru. "Novel GaAs Heterojunction Bipolar Transistor Technologies for High-Speed and Low-Power Applications." 京都大学 (Kyoto University), 2003. http://hdl.handle.net/2433/148898.
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Ramakrishnan, Hiran K. "Feasibility study of strained silicon technology for low-power high-speed circuit applications." Thesis, University of Newcastle upon Tyne, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.516434.
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Shaik, Khajaahmad. "High-speed low-power 0.5-V 28-nm FD-SOI 5T-cell SRAMs." Thesis, Paris 6, 2016. http://www.theses.fr/2016PA066046.
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L'objectif de cette thèse est d'atteindre 0,5 V haute vitesse faible puissance SRAM. Pour ce faire, les cellules SRAM de pointe, des tableaux et des architectures de bus sont examinées. Les questions difficiles sont alors précisées. Pour répondre aux exigences, une cellule de 5T d'alimentation statique de puissance boostée, combiné avec WL boosté et milieu point de détection et d'un tableau de multi divisé BL ouvert sont proposées et évaluées. Pour encore accélérer l'opération d'écriture, un tableau de 4Kb sélectivement stimulé puissance alimentation 5T cell est proposé et évalué par simulation. Nous découvrons que le point milieu de détection avec moitié VDD BL precharge est plus stable lors de lire que la VDD complet conventionnelle precharge. En outre, pour atteindre un bus robuste à grande vitesse de faible puissance 0,5-V,une architecture de bus dynamique avec un bus factice, qui se compose d'un pilote de dynamique et d'un récepteur dynamique, est proposée. Le pilote dynamique permeten particulier de grande vitesse même à 0,5 V avec overdrive porte accrue enchangeant les lignes électriques de VDD/2 en mode veille avec VDD en mode actif. Ilaccélère encore avec l'aide du bus factice cette impulsion gena pour suivre le point dedétection tension du bus pour réduire l'oscillation de l'autobus. Ensuite, unearchitecture de bus 0,5-V 28 nm FD-SOI 32 bits à l'aide de la proposition estevaluaevaluated par simulation. Il s'avère que l'architecture a un potentiel à exploiterun bus 1-pF à 50-mV swing, 1,2 GHz et un courant de veille de 1,1 µA, avec x3-5 plus rapidement et plus de deux ordre plus faible courant de veille que l'architecture statique conventionnelleThe goal of the thesis is to achieve 0.5-V high-speed low-power SRAMs. To do so, state-of-the-art SRAM cells, arrays, and bus-architectures are reviewed. The challenging issues are then clarified as 1) reduction of the minimum operating voltage VDD (Vmin) of the cell, 2) reducing bitline (BL)-active power, and 3) achieving low-power bus architecture. To meet the requirements, a static boosted-power-supply 5T cell, combined with boosted-WL and mid-point-sensing, and an open-BL multi-divided-array are proposed and evaluated. Layout and post-layout simulation with a 28-nm fully-depleted planar-logic SOI MOSFET reveal that a 0.5-V 5T-cell 4-kb array in a 128-kb SRAM core is able to achieve x2-3 faster cycle time and x11 lower power than the counterpart 6T-cell array, suggesting a possibility of a 730-ps cycle time at 0.5 V.To further speed up the write operation, a selectively-boosted-power-supply 5T-cell 4-kb array is proposed and evaluated by simulation, showing that the 4-kb array operates at 350-ps cycle with x6 faster cycle time and x13 lower power than the 6T-cell array, while maintaining a small leakage current. We find out that the mid-point-sensing with half-VDD BL-precharging is more stable during read than the conventional full-VDD precharging. Furthermore, to achieve a 0.5-V low-power high-speed robust bus, a dynamic bus architecture with a dummy bus, which consists of a dynamic driver and a dynamic receiver, is proposed. In particular, the dynamic driver enables high speed even at 0.5 V with increased gate-over-drive by changing the power lines from VDD/2 in the standby mode to VDD in the active mode. It further speeds up with the help of the dummy bus that generates a pulse to track the bus-voltage detecting point for reducing the bus swing. Then, a 0.5-V 28-nm-FD-SOI 32-bit bus architecture using the proposal is evaluated by simulation. It turns out that the architecture has a potential to operate a 1-pF bus at about 50-mV swing, 1.2 GHz, and a standby current of 1.1 µA, with x3-5 faster and more than two-order lower standby current than the conventional static architecture. Based on the results, further challenges to 0.5-V and sub-0.5-V SRAMs are described
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Haroun, Mostafa. "Low-power high-speed high-resolution delta-sigma modulators for digital TV receivers in nanometer CMOS." Thesis, McGill University, 2014. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=123106.
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The use of high-speed high-resolution analog-to-digital converters (ADCs) allows part of the signal processing to be done in the digital domain allowing for higher system integration and cheaper fabrication. Becoming more in use, hand-held devices have low-power requirements to allow for longer battery life. Also, designing ADCs in nanometer digital CMOS technologies make them more integrable with digital processing blocks and cheaper. This thesis aims at designing a high-speed (16MS/s conversion rate) high-resolution (12bits) Delta-Sigma modulator with low-power consumption in nanometer CMOS. Delta-Sigma modulators can achieve high resolution in low and medium speed applications. For higher speed applications, the oversampling ratio (OSR) will have to be kept low to avoid inefficient design. However, lowering the OSR requires special care in the design starting from the architecture until the full circuit implementation. In nanometer CMOS technologies, analog properties, such as intrinsic gain, degrade which might result in a higher power consumption. Moreover, the low nominal supply voltages associated with such technologies adds more challenges to the design of a low distortion power-efficient Delta-Sigma modulator. Targeting a specic resolution, lowering the voltage supply usually results in a higher power consumption. This thesis suggests possible solutions to achieve low power consumption while targeting high-speed applications in nanometer low-voltage-supply environment.This thesis presents a low-power Discrete-Time (DT) Delta-Sigma modulator making use of a single-loop multibit DT digital input-feedforward Delta-Sigma architecture. The main feature of this architecture is the reduced signal swings at the output of the integrators which allows the use of a low voltage supply. The low-power Switched-Capacitor (SC) implementation is ensured by using a novel opamp switching technique, optimizing simultaneous opamp's settling in cascaded nondelaying SC integrators, and using non-overlapping clock phases with unequal duty-cycles. The novel opamp switching technique is based on a current-mirror opamp with switchable transconductances. The current-mirror opamp works with full current during the charge-transfer phase while the output current is partially switched off during the sampling phase. Power saving can be achieved while ensuring that the opamp output is available during both phases. The simultaneous settling of series opamps in a two cascaded nondelaying SC integrators scheme is looked at as a two-pole system where power optimization is necessary to ensure minimum power consumption while meeting the settling requirements. The use of clock phases with unequal duty-cycles gives the designer an extra degree of freedom to further power optimize the design. The experimental Delta-Sigma ADC is a 4th-order 5.5bits single-loop Delta-Sigma modulator with an OSR of 8. The design starts with the structural-level aspects in which system-level decisions are made and simulations are carried-out with behavioral models to find the suitable circuit parameters. Circuit-level design in then considered to design each block and simulate the full-system. Fabricated in 1V 65nm CMOS, the Delta-Sigma modulator prototype occupies an active area of 1.2mm2. Although the targeted resolution is about 12bits, the experimental results shows a dynamic range (DR) of 66dB (11bits) over an 8MHz bandwidth while consuming 26mW and a peak SNR/SNDR of 64/58.5dB. The proposed opamp switching technique brings the total power consumption from 29mW to 26mW without affecting the performance (SNDR stays at 58.5dB). The deviation in experimental performance, from simulations, in thought to be due to higher parasitic capacitance requiring higher bias currents which results in drop of opamp dc gain. Compared to state of the art high-speed high-resolution Delta-Sigma modulators operated from 1V supply and fabricated in CMOS, it achieves a reasonable Figure-of-Merit.L'utilisation des convertisseurs analogique-numérique (CAN) à haute vitesse et à haute résolution permet à une partie du traitement du signal d'être accompli dans le domaine numérique permettant une meilleure intégration du système et un cout de fabrication moins élevé. De plus en plus utilisés, les appareils portatifs ont des exigences de faible consommation pour permettre une plus longue durée de vie de la batterie. En plus, la conception CAN en technologies CMOS numériques les rendent plus intégrable avec les blocs de traitement numérique et les rendent moins cher.Cette thèse vise à concevoir un modulateur Delta-Sigma à haute vitesse (de 16MS/s) et à haute résolution (12bits) et aussi à faible consommation tout en étant fabriquée en technologie CMOS nanométrique. Les modulateurs Delta-Sigma peuvent atteindre une résolution élevée dans les applications de basse et de moyenne vitesse. Dans les technologies CMOS nanométriques, les propriétés analogiques, telles que le gain intrinséque, se dégradent ce qui pourrait se traduire à une consommation de puissance plus élevée. En outre, les tensions d'alimentation nominales basses associées à ces technologies ajoutent de nouveaux défis à la conception d'un modulateur Delta-Sigma à distorsion faible et consommation faible. Cette thèse suggère des solutions possibles pour atteindre une faible consommation tout en ciblant les applications à haute vitesse en milieu nanométrique avec une alimentation à basse tension.Cette thèse présente un modulateur Delta-Sigma à faible consommation utilisant une architecture multi-bits à entrée "feedforward" numérique. La principale caractéristique de cette architecture est la réduction de la dynamique de signal à la sortie des intégrateurs, ce qui permet l'utilisation d'une alimentation à basse tension. La mise en œuvre du circuit à condensateurs commutées (SC) à faible consommation de puissance est assurée par l'utilisation d'une nouvelle technique de commutation pour l'amplificateur opérationnel (opamp), l'optimisation de la stabilisation simultanée des intégrateurs SC sans délais en cascade, et l'utilisation des phases d'horloge à rapports cycliques inégaux. La technique de commutation de l'opamp est basée sur un opamp à miroir de courant avec transconductances commutables. L'opamp fonctionne en plein courant pendant la phase de transfert de charge tandis que le courant est partiellement commutée pendant la phase d'échantillonnage ce qui réduit la consommation de puissance. La stabilisation simultanée des opamps en série dans le cas de deux intégrateurs SC sans délais en cascade est traitée comme un système à deuxième ordre oû l'optimisation de puissance est nécessaire. L'utilisation de phases d'horloge avec rapports cycliques inégaux donne au concepteur un degrée de libertée supplémentaire.Le modulateur expérimental de cette thèse est un modulateur Delta-Sigma de 4eme ordre avec 5.5bits et un taux de suréchantillonnage égal à 8. La conception commence avec les aspects structurels dans lequel des décisions au niveau du système sont prises et des simulations sont rapportées sur des modèles comportementaux pour trouver les paramètres de circuit appropriés. La conception au niveau circuit est examinée pour concevoir chaque bloc et simuler l'ensemble du système. Fabriquée en 65nm CMOS à 1V, ce prototype occupe une surface active de 1,2 mm2. Bien que la résolution ciblée est de 12bits, les résultats expérimentaux montrent une gamme dynamique (DR) de 66dB (11bits) sur une bande de 8MHz tandis que la consommation est de 26mW et le SNR/SNDR maximal est 64/58.5dB. L'écart de performance semble être d^u à l'augmentation des condensateurs parasites nécessitant des courants plus élevés, ce qui entra^ne la chute de gain de l'opamp. Par rapport aux modulateurs Delta-Sigma à haute vitesse et à haute résolution des travaux de pointe opérés à partir d'1V et fabriqués en technologies CMOS, le prototype réealise une figure-de-mérite raisonnable.
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Kim, Jaehyuck. "Variable-Speed Switched Reluctance Motor Drives for Low-Cost, High-Volume Applications." Diss., Virginia Tech, 2010. http://hdl.handle.net/10919/77320.
Full textAbstract:
Demand for energy-saving variable speed drives in low-cost, high-volume appliances has increased due to energy and environmental concerns and hence the need to comply with new regulations. Switched reluctance motor (SRMs) have been considered by many as attractive alternatives for brush commutated motors or permanent magnet brushless dc motors (PMBDCMs) in such cost-sensitive applications. The SRMs' unique features such as simple and fault-tolerant structure and unidirectional flow of their phase currents endow them with the possibility of various configurations on both machine and converter topologies for different applications. In the present study, three different variable-speed motor drive systems are proposed, studied, and implemented for their deployment in low-cost, high-volume applications with the power rating of 1.5kW or less. Two different two-phase SRMs and three different power converters are employed to realize three different low-cost drive systems. The first drive system is realized using a novel converter requiring only a single-controllable switch and an asymmetric two-phase 8/4 SRM capable of self-starting and four-quadrant operation. The second drive system is realized using another novel converter requiring two controllable switches, that way to achieve better control and utilization of the asymmetric 8/4 motor. The target applications for both drive systems are low power, low performance drives such as fans, hand tools, small appliances, etc. The third system is realized using a high-speed two-phase 4/2 SRM and a split ac source converter, which is designed for high-speed applications such as vacuum cleaners, ultracentrifuges, etc. The control and design aspects for each drive system are studied. Selection of optimal firing angles and optimal number of winding turns are also investigated. All of the drive systems are first demonstrated on the position sensor-based speed-control scheme. To make the drive system even more cost-competitive, operation without the position sensor using the novel parameter insensitive sensorless control scheme is proposed and implemented. Concept, analysis, simulation, and experimental verification of the proposed sensorless scheme are discussed in detail.Ph. D.
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Shar, Ahmad. "Design of a High-Speed CMOS Comparator." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10446.
Full textAbstract:
This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V.
The comparator is designed for time-interleaved bandpass sigma-delta ADC.
Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less than half the clock cycle which means it does not effect the functionality of the bandpass sigma-delta ADC in terms of speed.
The simulation results are derived using Cadence environment. The results show that the comparator has 6-bit resolution and power consumption of 4.13 mW for the worst-case frequency of 250 MHz. It fulfills all the performance requirements, most of them with large margins.
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Shehata, Khaled Ali. "Low-power high-speed dynamic logic families for complementary gallium arsenide (CGaAs) fabrication processes." Diss., Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1996. http://handle.dtic.mil/100.2/ADA319534.
Full textAbstract:
Dissertation (Ph.D. in Electrical and Computer Engineering) Naval Postgraduate School, Sepember 1996.Dissertation superviso(s): Douglas J. Fouts. "September 1996." Includes bibliographical references. Also available online.
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Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.
Full textAbstract:
Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.
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Younis, Choudhry Jabbar. "Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77178.
Full textAbstract:
Modern communication systems require higher data rates which have increased thedemand for high speed transceivers. For a system to work efficiently, all blocks ofthat system should be fast. It can be seen that analog interfaces are the main bottleneckin whole system in terms of speed and power. This fact has led researchersto develop high speed analog to digital converters (ADCs) with low power consumption.Among all the ADCs, flash ADC is the best choice for faster data conversion becauseof its parallel structure. This thesis work describes the design of such a highspeed and low power flash ADC for analog front end (AFE) of a transceiver. Ahigh speed highly linear track and hold (TnH) circuit is needed in front of ADCwhich gives a stable signal at the input of ADC for accurate conversion. Twodifferent track and hold architectures are implemented, one is bootstrap TnH andother is switched source follower TnH. Simulations show that high speed with highlinearity can be achieved from bootstrap TnH circuit which is selected for the ADCdesign.Averaging technique is employed in the preamplifier array of ADC to reduce thestatic offsets of preamplifiers. The averaging technique can be made more efficientby using the smaller number of amplifiers. This can be done by using the interpolationtechnique which reduces the number of amplifiers at the input of ADC. Thereduced number of amplifiers is also advantageous for getting higher bandwidthsince the input capacitance at the first stage of preamplifier array is reduced.The flash ADC is designed and implemented in 150 nm CMOS technology for thesampling rate of 1.6 GSamples/sec. The bootstrap TnH consumes power of 27.95mW from a 1.8 V supply and achieves the signal to noise and distortion ratio(SNDR) of 37.38 dB for an input signal frequency of 195.3 MHz. The ADC withideal TnH and comparator consumes power of 78.2 mW and achieves 4.8 effectivenumber of bits (ENOB).
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Bero, Brent C. "Bridging the ultra-low power and high speed regions using a tunable body biasing approach." Online access for everyone, 2006. http://www.dissertations.wsu.edu/Thesis/Spring2006/b%5Fbero%5F041006.pdf.
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Tauqeer, Tauseef. "Low Power, High Speed InP-Based Digital Intergrated Circuits for Ultra Wide Band Communicatiopn Systems." Thesis, University of Manchester, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.508526.
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Sheng, Hong. "Modelling, fabrication and characterisation of InP-HBTs for future high-speed, low power optical telecommunications." Thesis, King's College London (University of London), 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.368106.
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Fang, Yuan. "PHY Link Design and Optimization For High-Speed Low-Power Communication Systems." Phd thesis, 2015. https://tuprints.ulb.tu-darmstadt.de/4437/1/2013_11_21_dissertation_yuan.pdf.
Full textAbstract:
The ever-growing demands for high-bandwidth data transfer have been pushing towards advancing research efforts in the field of high-performing communication systems. Studies on the performance of single chip, e.g. faster multi-core processors and higher system memory capacity, have been explored. To further enhance the system performance, researches have been focused on the improvement of data-transfer bandwidth for chip-to-chip communication in the high-speed serial link. Many solutions have been addressed to overcome the bottleneck caused by the non-idealties such as bandwidth-limited electrical channel that connects two link devices and varieties of undesired noise in the communication systems. Nevertheless, with these solutions data have run into limitations of the timing margins for high-speed interfaces running at multiple gigabits per second data rates on low-cost Printed Circuit Board (PCB) material with constrained power budget. Therefore, the challenge in designing a physical layer (PHY) link for high-speed communication systems turns out to be power-efficient, reliable and cost-effective. In this context, this dissertation is intended to focus on architectural design, system-level and circuit-level verification of a PHY link as well as system performance optimization in respective of power, reliability and adaptability in high-speed communication systems.
The PHY is mainly composed of clock data recovery (CDR), equalizers (EQs) and high- speed I/O drivers. Symmetrical structure of the PHY link is usually duplicated in both link devices for bidirectional data transmission. By introducing training mechanisms into high-speed communication systems, the timing in one link device is adaptively aligned to the timing condition specified in the other link device despite of different skews or induced jitter resulting from process, voltage and temperature (PVT) variations in the individual link. With reliable timing relationships among the interface signals provided, the total system bandwidth is dramatically improved. On the other hand, interface training offers high flexibility for reuse without further investigation on high demanding components involved in high costs.
In the training mode, a CDR module is essential for reconstructing the transmitted bitstream to achieve the best data eye and to detect the edges of data stream in asynchronous systems or source-synchronous systems. Generally, the CDR works as a feedback control system that aligns its output clock to the center of the received data. In systems that contain multiple data links, the overall CDR power consumption increases linearly with the increase in number of links as one CDR is required for each link. Therefore, a power-efficient CDR plays a significant role in such systems with parallel links. Furthermore, a high performance CDR requires low jitter generation in spite of high input jitter. To minimize the trade-off between power consumption and CDR jitter, a novel CDR architecture is proposed by utilizing the proportional-integral (PI) controller and three times sampling scheme.
Meanwhile, signal integrity (SI) becomes critical as the data rate exceeds several gigabits per second. Distorted data due to the non-idealties in systems are likely to reduce the signal quality aggressively and result in intolerable transmission errors in worst case scenarios, thus affect the system effective bandwidth. Hence, additional trainings such as transmitter (Tx) and receiver (Rx) EQ trainings for SI purpose are inserted into the interface training. Besides, a simplified system architecture with unsymmetrical placement of adaptive Rx and Tx EQs in a single link device is proposed and analyzed by using different coefficient adaptation algorithms. This architecture enables to reduce a large number of EQs through the training, especially in case of parallel links. Meanwhile, considerable power and chip area are saved.
Finally, high-speed I/O driver against PVT variations is discussed. Critical issues such as overshoot and undershoot interfering with the data are primarily accompanied by impedance mismatch between the I/O driver and its transmitting channel. By applying PVT compensation technique I/O driver impedances can be effectively calibrated close to the target value. Different digital impedance calibration algorithms against PVT variations are implemented and compared for achieving fast calibration and low power requirements.
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Fu, Yuan-Ting, and 傅遠廷. "High-Speed and Low-Power SIMD Multipliers." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/40978123925215337912.
Full textAbstract:
碩士國立中正大學
電機工程研究所
93
Among high performance processors, it is multiplier which needs the longer operation time and which is used with high frequency. Therefore, for multiplier， low power and high speed are of importance. Also, due to the needs of the multi-media operation, multiplier needs Single Instruction Multi Data mode, that is, SIMD mode. This essay aims at providing many novel designs to meet the various needs of SIMD multiplier, and these designs are integrated into IC type-out. According to Post layout simulation, compared with those references it shows that my design is faster in speed about 30%, is less in routed area about 22, and is lower in power dissipation about 30%.
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Cheng, Sheng-Yuan. "The Design of Low-Power High-Speed Low-Noise PFD_CP_SC_PLL." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0002-1701200720083900.
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Cheng, Sheng-Yuan, and 鄭慎元. "The Design of Low-Power High-Speed Low-Noise PFD_CP_SC_PLL." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/45711131777665560014.
Full textAbstract:
碩士淡江大學
電機工程學系碩士在職專班
95
The Low-Power High-Speed Low-Noise PLL is a significant circuit for portable consumer devices. There are many sorts of PLLs due to its huge market demand. Its main applications are portable phones and GPS devices. It requires low-power for allowing the battery has long-used time. Also it demands fast-download speed for text transmission or graphic transmission. Furthermore, it needs low-noise quality to assure excellent sound received quality. PFD_CP_SC_PLL can reach 4 Giga Hz, 1.47E-02 Watts, and 6.9E-19 SQ V/HZ composed by a Phase Frequency Detector, a Chare Pump Filter, a Source Couple VCO and a 64 Divider. This thesis offers a complete low-power, high-speed, and low-noise PFDCPSC PLL design concept and detailed circuits, allowing communication designers to have a great reference.
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Liu, Yen-Ting, and 劉彥廷. "Low-Power High-Speed Analog-to-Digital Converters." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/36805976798418829033.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
94
For multi-band OFDM UWB, we propose two low-power high-speed analog-to-digital converters (ADCs). The first design is a 5-bit 1-Gsample/s flash ADC fabricated in TSMC 0.18-mm 1P6M CMOS process. The measurement results show that the effective number of bits (ENOB) is 4 and power consumption is 60 mW with the sampling rate of 600 MHz. The second design is a 6-bit 1-Gsample/s ADC implemented in TSMC 0.13-mm 1P8M CMOS process. Instead of continuous time flash ADC, we use two-step subranging structure. In addition, we employ offset cancellation, pipelining, and interpolation techniques. The post-layout simulation shows that ENOB is above 5.2 bits when the input frequency is up to Nyquist rate. The differential nonlinearity (DNL) and integral nonlinearity (INL) are smaller than 0.3 LSB (Least Significant Bit). The power consumption is 62 mW and figure-of-merit (FOM) 1.38 pJ/conversion-step.
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Huang, Cheng-Chieh, and 黃政傑. "Study on High-speed Low-power SAR ADC." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/65587942319732896750.
Full textAbstract:
碩士國立暨南國際大學
電機工程學系
98
This research proposes a high-speed and low-power DAC, which is apply to Successive Approximation ADC. Compared with general redistribution capacitor DAC which has to charge each capacitor under sampling condition, DAC proposed in this research charges only one capacitor and effectively promotes the speed. As to the reference voltage, DAC takes only half of the general one, and obviously reduces the power consumption. According to the simulation result, the designed SAR ADC can operate at 2MHz. The Signal-to-Noise and Distortion Ratio is 59.95dB when the input frequency is 100KMz and the effective number of bit is 9.67 bit. The Integral Nonlinearity is 0.7LSB. The Differential Nonlinearity is 0.4LSB. The power dissipation is 1.8mW. The chip layout area is 1030um*1030um.
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Chen, Hsin Liang, and 陳信良. "Design of Low-Power High-Resolution Sigma-Delta Modulators for Low-Speed Low-Noise and High-Speed Multi-Mode Applications." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/88519854440606209851.
Full textAbstract:
博士淡江大學
電機工程學系博士班
97
With the progressing semiconductor process, the signal reduces with the decreasing power supply. Therefore, the only way to implement the high-resolution SDM in the modern process is to reduce the noise power. For reaching the high-resolution, the physical noises of the flicker and thermal ones have to be analyzed, controlled, and cancelled. Meanwhile, to model the circuit nonidealities and noise phenomena into the system design process can optimize the system coefficients for reducing power dissipation. In this dissertation, low power and high-resolution SDMs are verified with the optimizing system and circuit design for the low and high bandwidth applications. The proposed pseudorandom chopper stabilization technique reduces the flicker noise and the offset voltage for low noise bio-signal SDMs. On the other hand, with switchable operational amplifier, the double-sampled multi-stage noise shaped (MASH) SDM optimizes power dissipation for multi-mode software-defined ratio (SDR) front-end receiver. The proposed SDMs are descript briefly as follows: The proposed low noise bio-signal SDM is implemented with TSMC 0.35-um process. Using the proposed technique, the modulator achieves 92 dB of dynamic range and −135 dB of noise floor while consuming 950 μW from a 3 V supply. Based on the experimental results, the pseudorandom chopper-stabilization technique has a DC offset voltage that is 6 dB lower than that of the chopper-stabilization technique, and retains a thermal noise floor that is 1.6 dB lower than that of the correlated double sampling technique. The proposed switchable double-sampled fourth-order MASH SDM is implemented with TSMC 0.13-um process. Using the switchable operational amplifier technique and proposed architecture, the modulator achieves 100/72/75 dB of dynamic range and 96/68/71 dB of signal to noise and distortion ratio while consuming 4.2/11.3/20.2 mW from a 1.2 V supply. Based on the power-optimized strategy from the views of circuit and system, the proposed SDM is a low power multi-mode modulator for the future SDR front-end receiver.
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Hsien-Han, Chiang. "Low Power and High Speed FFT Design for UWB." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0016-1303200709320749.
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Tyshchenko, Oleksiy. "Circuits for low-power high-speed content-addressable memories." 2006. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=442190&T=F.
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Lingam, Naga Sasidhar. "Low power design techniques for high speed pipelined ADCs." Thesis, 2009. http://hdl.handle.net/1957/10294.
Full textAbstract:
Real world is analog but the processing of signals can best be done in digital
domain. So the need for Analog to Digital Converters(ADCs) is ever rising as
more and more applications set in. With the advent of mobile technology, power
in electronic equipment is being driven down to get more battery life. Because of
their ubiquitous nature, ADCs are prime blocks in the signal chain in which power
is intended to be reduced. In this thesis, four techniques to reduce power in high
speed pipelined ADCs have been proposed. The first is a capacitor and opamp
sharing technique that reduces the load on the first stage opamp by three fold.
The second is a capacitor reset technique that aids removing the sample and hold
block to reduce power. The third is a modified MDAC which can take rail-to-rail
input swing to get an extra bit thus getting rid of a power hungry opamp. The
fourth is a hybrid architecture which makes use of an asynchronous SAR ADC
as the backend of a pipelined ADC to save power. Measurement and simulation
results that prove the efficiency of the proposed techniques are presented.Graduation date: 2009
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Lien, Yu-Chang, and 連昱彰. "Low-Power High-Speed Flash Analog-to-Digital Converters." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/01613899949492304196.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
96
The performance and power consumption of analog-to-digital converters (ADCs) affect the efficiency of the ultra wideband (UWB) systems. In this thesis, we focus on the design techniques development of high speed ADCs, and propose a 6-bit high speed ADC design for the applications of UWB systems. In this design, a design methodology for pre-amplifier is used to achieve the maximum bandwidth while consuming the fixed power. Also, the non-ideality of comparators can be suppressed by improving the comparator’s timing. This proposed design adopts the offset cancellation, capacitive interpolation and distributed sample-and-hold techniques to solve the problems in designing flash ADCs. This proposed ADC is designed in TSMC 0.13�慆 process, and the experimental results show that the effective number of bit (ENOB) is 5.3 in the sampling frequency of 700MHz. The power consumption is 112mW, and the resolution bandwidth (ERBW) is 500MHz. Due to the high input bandwidth and low power consumption, this ADC is very suitable to UWB systems.
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Chiang, Hsien-Han, and 江協翰. "Low Power and High Speed FFT Design for UWB." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/39223606688749331599.
Full textAbstract:
碩士國立清華大學
通訊工程研究所
94
ULTRA WIDE BAND(UWB) communication systems, which enable one to deliver data from a rate of 110 Mb/s at a distance of 10 m to a rate of 480 Mb/s at a distance of 2 m in realistic multipath environment while consuming very little power and silicon area, are currently the focus of research and development of wireless personal area networks(WPANs). The data sampling rate from the analog-to-digital converter to the physicallayer is up to 528 Msample/s or more, it is a challenge to realize the physical layer of the UWB system, especially the components with high computational complexity－FFT/IFFT. This thesis deals with the efficient realization of a 128-pt FFT/IFFT processor for application in IEEE 802.15.3a standard. The 128-pt FFT/IFFT architecture has been designed by radix-2(3) and proposed radix-2(4) algorithm and we applied this design in Single-Delay-Feedback(SDF) architecture.
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Kuo, Tien-Shang, and 郭添賞. "study of high speed and low power SiGe pMOSFET." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/18095534341513162137.
Full textAbstract:
碩士國立中央大學
電機工程研究所
91
Study of high speed and low power SiGe pMOSFET Abstract We have demonstrated a high performance Si1-xGex pMOSFET technology for low power and low noise circuit applications. The incorporation of 30% Ge in the strained Si1-xGex channel provides a drive current enhancement by a factor of 2.5 over its counterpart Si bulk pMOSFETs and manifests a marked advantage of two decade in exponential operating region allowing both lower power consumption and a wider dynamic range for low power circuit applications. Body effects on DC and low frequency noise characteristics in Si1-xGex pMOSFETs have also been investigated. The relative spectral density of low frequency noise in SiGe pMOSFET’s is found to be significantly lower than in Si devices. The experimental results promise the potential of SiGe/Si heterostructure MOSFETs in radio-frequency micropower applications.
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Tseng, Chien-Jian, and 曾千鑑. "High Speed, Low Power Pipeline Analog-to-Digital Converter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/66654894049881545902.
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博士國立臺灣大學
電子工程學研究所
104
Opamp is a critical and power-hungry block in high performance pipeline ADC design. Unfortunately, opamp design is getting challenging in advanced deep submicron process. The techniques proposed in the dissertation aim to ease opamp design effort or simply remove opamp usage in pipeline ADC design. The first and second designs employ incomplete settling technique to realized high speed ( > GS/s ) pipeline ADC design. Two novel design concepts, sampling point calibration and sub-radix conversion, are adopted to calibrate stage gain error. Thus, low gain and low bandwidth opamps can be used in pipeline ADC design to save power consumption. The third design extends the usage of capacitor sharing technique, not only between the 1st and 2nd MDACs but also between the 2nd and the 3rd MDACs. By reducing the effective capacitance loading at opamp output node, the bandwidth requirement of the opamp can be loosen. The final design tries to get rid of opamp usage in the pipeline ADC design. The MDAC function, i.e. subtraction and amplification, can be realized by merely constant charging current source, capacitors and comparators. In addition, processing signal in time domain instead of in voltage domain takes advantage of increasing timing resolution in advanced process and thus fits the process trend.
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Yang, Mi-Ti, and 楊蜜迪. "Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/bu4g43.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
105
As the advantage of wireless communication system, the requirement for high speed sampling rate and medium resolution gradually increase. A 10-bit 1GS/s time-interleaved SAR ADC is presented in 40nm general process of CMOS technology in this thesis. This thesis proposes a low-skew bootstrap to solve the timing skew problem between channels without digital calibration. In order to improve the energy-efficiency of the sub-channel, the subranging SAR ADC is used for lowing the FOM. This time-interleaved SAR ADC achieves an ENOB of 7.9 at the conversion rate of 1GS/s with 250MHz input signal. The active area is only 0.0459 mm2. It consumes 3.0245mW and gets the good FoM of 19.83fJ/conversion-step. It is suitable for the energy-efficient wireless communication and Ethernet network application.
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Wang, Shang-Ming, and 王上銘. "Low Power and High Speed SRAM with Current-Mode Techniques." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/77r2df.
Full textAbstract:
博士國立交通大學
電子工程系所
92
This thesis explores the design and analysis of Static Random Access Memories (SRAMs) and focuses on low power operation. The SRAM access path is split into three portions: from address input to word line rise (the write operation), from word line rise to data output (the read path) and memory cell. The techniques to optimize both of these paths are investigated. The voltage-controlled negative-differential-resistance device by using a merged integrated circuit of n-channel MOSFET and parasitic NPN bipolar transistor, called Lambda bipolar transistor (LBT), is known for its memory application. In this thesis, a new LBT structure is developed and its characteristics are derived by simple circuit model and device physics. A novel single-sided memory cell based on the proposed LBT’s is presented. High performance and low power SRAM design always focuses on reducing dynamic power dissipation at the operating state and decreasing DC current and leakage current at the standby state. To reduce operation power without decreasing read/write speed, we propose special current-mode read/write mechanism instead of conventional voltage-mode circuits. In this thesis, a new current-mode sense amplifier is proposed to sense the bit-line signal even though the voltage swing of the bit-line is small, and the non-floating design reduces noise produced during sensing in the standby mode. The current-mode write driver can reduce the bit-line swing when data write in, not only decreasing power consumption but also speeding up writing access time. Using new current-mode techniques for read and write operation, the sensing speed and write pulse width are insensitive to the bit-line and data-line capacitances and a separated positive feedback technique is used to enable the circuit to operate at high-speed and low-power. These techniques always keep the voltage swing of the bit-line and data-line quite small. Based on current-mode operation, a memory cell that operates at low-power current-mode is developed. The memory cell has almost equally sized access and inverter transistors, which can be toggled using a small differential bit-line voltage. The presented techniques were demonstrated to be useful by evaluating an experimental 32Kx8 SRAM chip using 0.35um 1P2M CMOS process technology. An experimental 32Kx8 CMOS SRAM with a 9ns access time at a supply voltage of 3V is described to evaluate the new current-mode techniques. The active current is 28mA at 100MHz and 25℃.
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Su, Wei-chiang, and 蘇偉強. "A New High Speed Low Power Counter Based Viterbi Decoder." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/28857455994198132795.
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碩士國立雲林科技大學
電子與資訊工程研究所
94
In the digital communication system, Viterbi Algorithm is a well-known solution for efficient approximate convolution code decoding, and has already used it on personal mobile communication equipment extensively. Because of portable appliances designer trends, it is important to let the circuit designed with high-speed and low-power capabilities. A lot of high-speed researches have done in architecture improving. In order to speed-up decoding procedure of decoder, common hardware architecture is used such as pipelined or parallel technique. However these techniques will all consume quite big chip-area and power consumptions. This thesis proposed putting forward the speed improving Viterbi decoder with new circuit architecture without area and power sacrifices. From our study, the main speed bottleneck of Viterbi decoder lies in its Add-Compare-Select unit. For not increasing hardware and power consumption, we replace adders with binary counters, and use double-edge-trigger pulse generator to replace Branch Metric Unit. It is the example in TSMC 0.35-μm process with convolution code (3, 1, 2), using the new circuit skill can be carried and reached 660 Mb/s speed. In addition total transistor count reduces by 11% than the decoding architecture. In TSMC 0.18-μm IC process, using the new circuit skill, speed can be improved and reached 990 Mb/s. When compare with the traditional parallel high-speed architecture, our proposed new-type circuit can save more than 50% of the power.
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Lee, Chi Chou, and 李季洲. "Design of High-Speed and Low-Power CMOS Miniature Equalizers." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/95820565662964715174.
Full textAbstract:
碩士國立清華大學
電子工程研究所
102
In this thesis, an ultra-low-power miniature 20Gb/s passive/active hybrid equalizer and a novel 20Gb/s adaptive bias equalizer are proposed. In the first work, a compact and low-power passive/active hybrid equalizer is presented. By sharing the loading of high frequency peaking with the active equalizing stage, the passive filtering stage reduces the power significantly. To achieve a small area, the 3D inductor and active inductor techniques have also been incorporated in this design. Implemented in a standard 90 nm CMOS process, this passive/active hybrid equalizer has a very small power consumption of 10.8 mW and occupies a core chip area of only 0.017mm2. It can successfully equalize for the data transmitted through 180-cm coaxial cable line up to 22Gb/s in the measurement, where the peak-to-peak jitter is about 19 ps. In the second work, a novel adaptive bias equalizer is proposed. By adopting adaptive bias control circuit, the equalization is able to fulfill adaptive compensation without using a complex feedback loop. The proposed scheme also eliminates the conflict problem in traditional dual loop control, the speed limitation of comparator, and all the additional circuits in the servo loop. The proposed adaptive bias equalizer is able to transmit 22Gb/s data for a cable loss of 7dB, 9dB, and 11dB at 11GHz, where the peak-to-peak jitter is about 9ps, 11ps and 23ps, respectively.
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Lee, Ying-Ju, and 李映儒. "A low-power low-cost OOK transceiver and a high speed low- power SAR ADC for Powerline communication system." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/23354092905878762006.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
103
This dissertation proposes a pre-switching technique for high-speed energy-efficient successive-approximation register (SAR) analog-to-digital converters (ADCs), and a low-power and low-cost On-Off Keying(OOK) transceiver for powerline communication (PLC) system. The pre-switching method speeds up the SAR ADC. The OOK modulation not only save the power consumption but also save the area cost. Furthermore, the OOK transceiver improves the reliability of PLC system. A 10-bit 100MS/s SAR ADC with pre-switching method was implemented in TSMC 90nm CMOS technology. In measurement results, when the SAR ADC operate at 50MS/s sampling rate with 20MHz input frequency, the measured ENOB and SFDR is 8.28 and 64.72dB. In 100MS/s sampling rate with 50MHz input frequency, the measured ENOB is 7.77 and SFDR is 58.66dB respectively. The ADC consumes 1.8mW from 1-V supply when the sampling rate is 100MS/s, the resulting figure of merit (FOM) is 79fJ/conversion-step. The OOK PLC transceiver was fabricated in TSMC 0.25um CMOS technology. In measurement results, the maximum data rate is 45Kbps. When data rate is 10Kbps, the power consumption is 25mW. Moreover, the transceiver can recover the NRZ data by power line with 1 meter and 5 meters.
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Patnala, Mounica. "High Performance GNRFET Devices for High-Speed Low-Power Analog and Digital Applications." Thesis, 2019. http://hdl.handle.net/1805/18945.
Full textAbstract:
Indiana University-Purdue University Indianapolis (IUPUI)Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices o ered alternative approach, featuring small size and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed signals based systems. Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation. GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.