Dissertations / Theses on the topic 'Low Power ESD Protection'
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Moghadasiriseh, Amirhasan. "Analysis and Modeling of Advanced Power Control and Protection Requirements for Integrating Renewable Energy Sources in Smart Grid." FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2469.
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Attempts to reduce greenhouse gas emissions are promising with the recent dramatic increase of installed renewable energy sources (RES) capacity. Integration of large intermittent renewable resources affects smart grid systems in several significant ways, such as transient and voltage stability, existing protection scheme, and power leveling and energy balancing. To protect the grid from threats related to these issues, utilities impose rigorous technical requirements, more importantly, focusing on fault ride through requirements and active/reactive power responses following disturbances. This dissertation is aimed at developing and verifying the advanced and algorithmic methods for specification of protection schemes, reactive power capability and power control requirements for interconnection of the RESs to the smart grid systems. The first findings of this dissertation verified that the integration of large RESs become more promising from the energy-saving, and downsizing perspective by introducing a resistive superconducting fault current limiter (SFCL) as a self-healing equipment. The proposed SFCL decreased the activation of the conventional control scheme for the wind power plant (WPP), such as dc braking chopper and fast pitch angle control systems, thereby increased the reliability of the system.
A static synchronous compensator (STATCOM) has been proposed to assist with the uninterrupted operation of the doubly-fed induction generators (DFIGs)-based WTs during grid disturbances. The key motivation of this study was to design a new computational intelligence technique based on a multi-objective optimization problem (MOP), for the online coordinated reactive power control between the DFIG and the STATCOM in order to improve the low voltage ride-through (LVRT) capability of the WT during the fault, and to smooth low-frequency oscillations of the active power during the recovery. Furthermore, the application of a three-phase single-stage module-integrated converter (MIC) incorporated into a grid-tied photovoltaic (PV) system was investigated in this dissertation. A new current control scheme based on multivariable PI controller, with a faster dynamic and superior axis decoupling capability compared with the conventional PI control method, was developed and experimentally evaluated for three-phase PV MIC system. Finally, a study was conducted based on the framework of stochastic game theory to enable a power system to dynamically survive concurrent severe multi-failure events, before such failures turn into a full blown cascading failure. This effort provides reliable strategies in the form of insightful guidelines on how to deploy limited budgets for protecting critical components of the smart grid systems.
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Latzo, Curtis Thomas. "Approaches to Arc Flash Hazard Mitigation in 600 Volt Power Systems." Scholar Commons, 2011. http://scholarcommons.usf.edu/etd/3198.
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ABSTRACT
Federal regulations have recognized that arc flash hazards are a critical source of potential injury. As a consequence, in order to work on some electrical equipment, the energy source must be completely shut-down. However, power distribution systems in mission critical facilities such as hospitals and data centers must sometimes remain energized while being maintained. In recent years the Arc Flash Hazard Analysis has emerged as a power system tool that informs the qualified technician of the incident energy at the equipment to be maintained and recommends the proper protective equipment to wear. Due to codes, standards and historically acceptable design methods, the Arc Flash Hazard is often higher and more dangerous than necessary.
This dissertation presents detailed methodology and proposes alternative strategies to be implemented at the design stage of 600 volt facility power distribution systems which will decrease the Arc Flash Hazard Exposure when compared to widely used code acceptable design strategies. Software models have been developed for different locations throughout a power system. These software model simulations will analyze the Arc Flash Hazard in a system designed with typical mainstream code acceptable methods. The model will be changed to show implementation of arc flash mitigation techniques at the system design level. The computer simulations after the mitigation techniques will show significant lowering of the Arc Flash Hazard Exposure.
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Li, You. "Design of low-capacitance and high-speed electrostatic discharge (ESD) devices for low-voltage protection applications." Doctoral diss., University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4551.
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Electrostatic discharge (ESD) is defined as the transfer of charge between bodies at different potentials. The electrostatic discharge induced integrated circuit damages occur throughout the whole life of a product from the manufacturing, testing, shipping, handing, to end user operating stages. This is particularly true as microelectronics technology continues shrink to nano-metric dimensions. The ESD related failures is a major IC reliability concern and results in a loss of millions dollars to the semiconductor industry each year. Several ESD stress models and test methods have been developed to reproduce the real world ESD discharge events and quantify the sensitivity of ESD protection structures. The basic ESD models are: Human body model (HBM), Machine model (MM), and Charged device model (CDM). To avoid or reduce the IC failure due to ESD, the on-chip ESD protection structures and schemes have been implemented to discharge ESD current and clamp overstress voltage under different ESD stress events. Because of its simple structure and good performance, the junction diode is widely used in on-chip ESD protection applications. This is particularly true for ESD protection of low-voltage ICs where a relatively low trigger voltage for the ESD protection device is required. However, when the diode operates under the ESD stress, its current density and temperature are far beyond the normal conditions and the device is in danger of being damaged. For the design of effective ESD protection solution, the ESD robustness and low parasitic capacitance are two major concerns. The ESD robustness is usually defined after the failure current It2 and on-state resistance Ron. The transmission line pulsing (TLP) measurement is a very effective tool for evaluating the ESD robustness of a circuit or single element. This is particularly helpful in characterizing the effect of HBM stress where the ESD-induced damages are more likely due to thermal failures.; The recent industry data indicates the charged device model (CDM) ESD event becomes increasingly important in today's manufacturing environment and packaging technology. This event generates highly destructive pulses with a very short rise time and very small duration. TLP has been modified to probe CDM ESD protection effectiveness. The pulse width was reduced to the range of 1-10 ns to mimic the very fast transient of the CDM pulses. Such a very fast TLP (VFTLP) testing has been used frequently for CDM ESD characterization. The overshoot voltage and turn-on time are two key considerations for designing the CDM ESD protection devices. A relatively high overshoot voltage can cause failure of the protection devices as well as the protected devices, and a relatively long turn-on time may not switch on the protection device fast enough to effectively protect the core circuit against the CDM stress. The overshoot voltage and turn-on time of an ESD protection device can be observed and extracted from the voltage versus time waveforms measured from the VFTLP testing. Transient behaviors of polysilicon-bound diodes subject to pulses generated by the VFTLP tester are characterized for fast ESD events such as the charged device model. The effects of changing devices' dimension parameters on the transient behaviors and on the overshoot voltage and turn-on time are studied. The correlation between the diode failure and poly-gate configuration under the VFTLP stress is also investigated. Silicon-controlled rectifier (SCR) is another widely used ESD device for protecting the I/O pins and power supply rails of integrated circuits. Multiple fingers are often needed to achieve optimal ESD protection performance, but the uniformity of finger triggering and current flow is always a concern for multi-finger SCR devices operating under the post-snapback region.; Two types of diodes with different anode/cathode isolation technologies will be investigated for their ESD performance: one with a LOCOS (Local Oxidation of Silicon) oxide isolation called the LOCOS-bound diode, the other with a polysilicon gate isolation called the polysilicon-bound diode. We first examine the ESD performance of the LOCOS-bound diode. The effects of different diode geometries, metal connection patterns, dimensions and junction configurations on the ESD robustness and parasitic capacitance are investigated experimentally. The devices considered are N+/P-well junction LOCOS-bound diodes having different device widths, lengths and finger numbers, but the approach applies generally to the P+/N-well junction diode as well. The results provide useful insights into optimizing the diode for robust HBM ESD protection applications. Then, the current carrying and voltage clamping capabilities of LOCOS- and polysilicon-bound diodes are compared and investigated based on both TCAD simulation and experimental results. Comparison of these capabilities leads to the conclusion that the polysilicon-bound diode is more suited for ESD protection applications due to its higher performance. The effects of polysilicon-bound diode's design parameters, including the device width, anode/cathode length, finger number, poly-gate length, terminal connection and metal topology, on the ESD robustness are studied. Two figures of merits, FOM_It2 and FOM_Ron, are developed to better assess the effects of different parameters on polysilicon-bound diode's overall ESD performance. As latest generation package styles such as mBGAs, SOTs, SC70s, and CSPs are going to the millimeter-range dimensions, they are often effectively too small for people to handle with fingers.; Without a proper understanding of the finger turn-on mechanism, design and realization of robust SCRs for ESD protection applications are not possible. Two two-finger SCRs with different combinations of anode/cathode regions are considered, and their finger turn-on uniformities are analyzed based on the I-V characteristics obtained from the transmission line pulsing (TLP) tester. The dV/dt effect of pulses with different rise times on the finger turn-on behavior of the SCRs are also investigated experimentally. In this work, unless noted otherwise, all the measurements are conducted using the Barth 4002 transmission line pulsing (TLP) and Barth 4012 very-fast transmission line pulsing (VFTLP) testers.ID: 029050342; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2010.; Includes bibliographical references (p. 92-100).
Ph.D.
Doctorate
Department of Electrical Engineering and Computer Science
Engineering and Computer Science
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Cao, Yiqun [Verfasser], Stephan [Akademischer Betreuer] Frei, and Bernd [Gutachter] Deutschmann. "High-voltage ESD structures and ESD protection concepts in smart power technologies / Yiqun Cao ; Gutachter: Bernd Deutschmann ; Betreuer: Stephan Frei." Dortmund : Universitätsbibliothek Dortmund, 2019. http://d-nb.info/1200209605/34.
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Baum, Keith Warren 1959. "ESD effects on the radiation response of low power vertical DMOS N-channel transistors." Thesis, The University of Arizona, 1991. http://hdl.handle.net/10150/277850.
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The effect of non-catastrophic human body model positive electrostatic discharge pulses on the radiation response of low power VDMOS N-channel transistors is explored. The effect of multiple pulses of HBM ESD is to cause a change in threshold-voltage shifts between stressed and non-stressed devices when exposed to Co₆₀ gamma radiation. This difference is due to the build-up of a space charge region next to the Si/SiO₂ interface. This space charge region reduces the net electric field across the gate oxide when biased with a positive voltage and thus reduces the formation of holes and interface traps. Therefore, the ESD stressed devices appear to be less sensitive to radiation.
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Salomonsson, Daniel. "Modeling, Control and Protection of Low-Voltage DC Microgrids." Doctoral thesis, Stockholm : Elektriska energisystem, Electric Power Systems, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4666.
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袁綺珊 and Yee-shan Cherry Yuen. "High impedance fault detection and overvoltage protection in low voltage power systems." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B31222146.
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Yuen, Yee-shan Cherry. "High impedance fault detection and overvoltage protection in low voltage power systems /." Hong Kong : University of Hong Kong, 1998. http://sunzi.lib.hku.hk/hkuto/record.jsp?B20735297.
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Gammon, Tammy Lea. "Improved arcing-fault current models for low-voltage power systems (<1kV)." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15675.
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Muhammad, Wasim. "CMOS LNA Design for Multi-Standard Applications." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7841.
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This thesis discusses design of narrowband low noise amplifiers for multi¬standard applications. The target of this work is to design a low noise ampli¬fier(LNA) for DCS1800 and Bluetooth standard frequency bands. Various designs for narrowband multi-standard LNAs have been studied and a new design for tunable multi-standard LNA has been presented and designed using accumulation mode MOS varactors.
As this design includes on-chip spiral inductors, the design, modelling and layout of on-chip inductors have been discussed briefly. The tool used for this purpose is ASITIC.
Also ESD protection techniques for RF circuits and their effect on LNA per¬formance has been discussed.
Finally fully differential LNA has been designed in O.35um AMS thick metal CMOS process using Cadence SpectreRF. The design also includes ESD pro¬tection at the input of LNA.
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Kotulič, Dominik. "Záznamového zařízení pro oblast civilního letectví." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2018. http://www.nusl.cz/ntk/nusl-376993.
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In the thesis the design of the Data Storage System (DSS) is proposed with the respect to the V-Model methodology. The design is based on users requirements, from which the system requirements are created and the technical specification of the DSS is developed. In the technical specifications the functionality of the DMM and HMI DSS subsystems are described and sub-system requirements are assigned to them, then they are subdivided and assigned to individual DMM (Data memory module) and HMI hardware items. Moreover, requirements are analyzed on hardware items, specific electronic components, are selected and implemented into the block design of the DMM hardware. Based on the block design of hardware, the hardware of the DMM subsystem is designed, selectively simulated and implemented along with the printed circuit board. On the implemented hardware of the DMM subsystems measurements are performed in order to verify the basic functionality of the hardware and the calculated, assimilated and measured values are compared as well. At the end of the thesis there is a short description of the implementation of the software design and its use for basic initialization of the selected processor, together with the verification of its basic function - measuring the frequency of the internal clock sources and the clock domains. The work is completed by sending a message of defined parameters to the selected communication line and sapling it by an oscilloscope, so that the basic function of the DMM subsystem is verified.
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Bassi, Welson. "Estudo de surtos em redes secundárias de distribuição devido a descargas atmosféricas diretas na rede primária." Universidade de São Paulo, 1999. http://www.teses.usp.br/teses/disponiveis/3/3143/tde-10102017-100131/.
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Este trabalho apresenta uma análise dos surtos em redes aéreas secundárias de distribuição causados por descargas atmosféricas diretas no circuito primário. Alguns trabalhos publicados sobre o fenômeno são comentados, sendo também analisados vários outros estudos relativos à modelagem de componentes. No trabalho, os principais componentes da rede foram modelados e incluídos na representação de uma topologia típica (com as linhas primária e secundária). Assim, foram considerados: transformador de distribuição, isoladores, pára-raios, cargas (consumidores) e resistências de aterramento. Os modelos foram validados, quando possível, através de ensaios em laboratório. Algumas alternativas de proteção da rede secundária foram consideradas. Foi verificada a influência de alguns parâmetros relevantes tais como amplitude e tempo de frente da corrente da descarga, resistências de aterramento, modelos de cargas e posição da descarga. Os resultados foram obtidos por simulações computacionais realizadas através do programa ATP (Alternative Transients Program). São apresentadas formas de onda de sobretensões nos consumidores. Também são apresentados e discutidos valores de corrente e energia nos dispositivos de proteção, fornecendo informações sobre as alternativas de proteção.This work presents an evaluation of surges in low-voltage overhead distribution lines caused by direct lightning strikes in medium voltage lines. Some publications concerning the phenomenon are commented and several other studies used during the process of modeling of the components are also analysed. The main components of the distribution system were modeled and included. So, a typical distribution network topology (with the primary and secondary lines) was represented including its components: distribution transformer, insulators, surge arresters, loads and ground resistances. The performance of the developed models, whenever possible, was verified by laboratory tests. Some possibilities of the secondary protection were included. Parameters having major effect on the results, such as the lightning current amplitude and front time, the values of grounding resistances, the models of the loads and the lightning strike position were taken into consideration in the study. The results were obtained by simulations performed using the ATP (Alternative Transients Program). Waveforms are presented in order to provide information on the characteristics of the overvoltages in the consumers along the line. Currents, as well as energy absorbed by the low-voltage surge arresters are aldo presented and discussed, providing useful information about the performance of some protection alternatives.
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Bassi, Welson. "Caracterização de equipamentos e instalações residenciais de baixa tensão aplicada ao estudo de transitórios de origem atmosférica." Universidade de São Paulo, 2005. http://www.teses.usp.br/teses/disponiveis/3/3143/tde-10102017-111817/.
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Este trabalho apresenta um estudo de caracterização das impedâncias de entrada, em função da frequência, de instalações residenciais de baixa tensão e diversos equipamentos eletro-eletrônicos comumente encontrados. As respostas em frequência medidas são ajustadas e modeladas por redes RLC simples, mas efetivas, que podem ser utilizadas em qualquer programa computacional para simulações de transitórios. A faixa de frequências, até 5 MHz, permite o uso desses modelos em estudos associados a transitórios atmosféricos ou causados por chaveamentos. É importante ressaltar a existência de muito poucos trabalhos nesse assunto, pois, usualmente, as instalações de baixa tensão, ou os equipamentos conectados, são representadas por simples elementos concentrados, resistores, indutores ou capacitores. Por outro lado, sabe-se que os níveis de sobretensões em um sistema, ou instalação, são fortemente dependentes das cargas conectadas e, quanto mais precisos os modelos, melhores e mais confiáveis simulações são obtidas. Este trabalho inclui simulações com o programa computacional ATP utilizando os modelos desenvolvidos para avaliação de surtos em uma rede de distribuição típica submetida a descargas atmosféricas diretas no circuito primário. Além disso, utilizando o programa Pspice, são realizadas simulações da resposta interna de uma instalação residencial, com diversos equipamentos conectados, e submetida a surtos atmosféricos em sua entrada. O trabalho concentra informações práticas e úteis sobre estudos de surtos em sistemas e instalações de baixa tensãoThis work presents a study of impedance characteristics, over a wide range of frequencies, of residential low-voltage installations and electric-electronic appliances, commonly found in residential installations. The measured frequency responses are fitted and modeled by simple, but effective, RLC networks, that can be used in any software for transient simulations. The range of frequencies, up to 5 MHz, allows the use of these models considering lightning or switching studies. It is of importance to point the lack of publications focusing this topic, because usually the low-voltage installations, or connected equipment, are represented by simple lumped components inductances, resistances or capacitances. Otherwise, it is well known that the overvoltage level of a system, or installation, is strongly dependent on the connected loads and for more precise models, better and more reliable simulation results are obtained. This work includes ATP software simulations using the developed models for evaluation of surges in a typical distribution network subjected to direct lightning strikes at the primary circuit. Furthermore, simulations of internal response of a low-voltage installation with connected equipment and subjected to lightning surges in its entrance is performed using the Pspice software. The work summarizes practical and useful information about the low-voltage surge studies on low-voltage systems.
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Searle, Deane. "Low Intensity Conflict: Contemporary Approaches and Strategic Thinking." The University of Waikato, 2007. http://hdl.handle.net/10289/2591.
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Low Intensity Conflict (LIC) is a significant feature of the contemporary world and it is a particular challenge to the armed forces of many states which are involved is such conflict, or are likely to become so. This thesis is not concerned with how such difficult conflict situations arise. Rather it is concerned with how, from the point of view of the state, they may be contained and ultimately brought to a satisfactory resolution. The work is thus concerned with the practicalities of ending LIC. More specifically, the purpose of this research is to establish a framework of doctrinal and military principles applicable to the prevention and resolution of LIC. The principles of this thesis are based in numerous historical examples of LIC and six in depth case studies. These distilled principles are analysed in two central chapters, and are then applied in two latter defence force chapters so as to ensure there practicality and resilience. Numerous defence academics and military practitioners have been consulted in the production of this thesis; their contribution has further reinforced the functionality of the principles examined in this research. The research illustrates the criticality of a holistic approach to LIC. The function of this approach is to guarantee the stability of the sovereign state, by unifying civil, police, intelligence and military services. The effectiveness of the military elements must also be ensured, as military force is central to the suppression of LIC. Consequently, the research makes strategic and operational prescriptions, so as to improve the capability of defence forces that are concerned with preventing or resolving LIC.
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Foltýn, Petr. "Řešení elektrizace nové lokality elektrickou energií." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219030.
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This master’s thesis is concerned with the proposal of new locality electrification. There are 59 detached houses. The thesis is divided into theoretical part and computational part. In the theoretical part, there are all documents necessary for the successful proposal of the electrification. In the computational part is drafted distribution substation, high voltage power cable, proposal of low voltage power cables and protection. Each part is made for two versions (for the degree of electrification A and for the degree of electrification C) and recorded in cadastral maps. The proposal of distribution substation and high voltage power cable is made by traditional method - all calculations are processed by the designer. Low-voltage power cables and protection are implemented in a computer program Sichr (version 11.01) OEZ company.
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Caramel, Christian. "Nouvelles fonctions interrupteurs intégrées pour la conversion d'énergie." Phd thesis, Université Paul Sabatier - Toulouse III, 2007. http://tel.archives-ouvertes.fr/tel-00160966.
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Les systèmes de conversion de l'énergie électrique sont présents dans beaucoup de domaines de la vie quotidienne. On peut citer le secteur du transport, l'électronique grand public, la médecine, et la distribution de l'énergie. Une défaillance dans une application est le plus souvent ressentie comme étant liée à l'électronique. Adjoignons à cela des besoins en énergie grandissants et une évolution vers une plus grande mobilité, il devient aisé de déduire que les systèmes de conversion de l'énergie modernes doivent êtres plus compacts, plus fiables et plus performants. L'intégration en électronique de puissance est une réponse adéquate à ces problématiques tant elle vise à fiabiliser, à miniaturiser et à améliorer les performances des fonctions de conversion de l'énergie. Les travaux de recherche présentés dans cette thèse traitent de ma contribution à l'amélioration de la fiabilité et des performances d'un composant de puissance largement usité : l'Insulated Gate Bipolar Transistor. Pour cela l'association de deux IGBT aux caractéristiques différentes pour réaliser une architecture dite " faibles pertes " est présentée. Son concept est explicité, son intérêt exposé et son intégration monolithique détaillée. Dans un deuxième temps, une structure de protection monolithiquement intégrable contre les courts-circuits est dévoilée. Son fonctionnement et sa conception en vue de son intégration monolithique sont exposés.
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Wang, Chang-Tzu, and 王暢資. "Low-Leakage Power-Rail ESD Protection Designs in CMOS Integrated Circuits." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/52376894170912771445.
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博士國立交通大學
電子研究所
98
Continually scaling down the CMOS technologies into nanoscale generation imposes significant challenges in integrated circuit (IC) reliability, where electrostatic discharge (ESD) protection has become one of the major concerns. To meet such reliability specifications are necessary for IC product qualification. From the perspective of ESD, the similar gate oxide breakdown voltage and trigger voltage of MOSFET devices increased the design difficulty. Moreover, the secondary device characteristics of MOSFET have been considered in nanoscale CMOS generations. The most important impact for ESD is the gate direct tunneling current, which happens between the gate and silicon beneath the gate oxide, occurs while MOSFET implementing in a nanoscale CMOS process. Such gate tunneling current could induce a substantial fraction of overall leakage current in a chip. The traditional ESD protection circuit with a large gate oxide dimension suffers serious gate leakage issue. The on-chip ESD protection circuit in nanoscale CMOS process should be design with consideration of gate tunneling current to achieve a low standby leakage current during the normal circuit operation condition. During the ESD stress, the on-chip ESD protection circuit should provide efficient protection capability to assure the safety of the internal circuit which has a small gate oxide breakdown voltage in nanoscale CMOS process. For the mixed-voltage I/O interfaces with thin gate-oxide devices, the on-chip ESD protection designs will meet design difficulties, such as gate-oxide reliability constraints and undesired leakage current paths. In high-voltage Bipolar-CMOS-DMOS (BCD) technology, high-voltage transistors have been widely used for display driver ICs, power supplies, and power management ICs. The high-trigger-voltage and low-holding-voltage characteristics of HV transistor have been found to cause latchup or latchup-like failure and insufficient ESD efficiency. Therefore, how to develop an efficient on-chip ESD protection design is an important challenge for high-voltage IC products. In this dissertation, the ESD design constraints in nanoscale CMOS process, mixed-voltage I/O interfaces, and high-voltage CDMOS technology are presented. Furthermore, the novel design solutions for on-chip ESD protection circuit have been developed to meet the design constraints in such technologies and applications. To provide effective on-chip ESD protection with low standby leakage current in nanoscale CMOS technology, a new power-rail ESD clamp circuit by using the silicon controlled rectifier (SCR) device and ESD detection circuit with substrate-triggered technique is proposed. The SCR device without poly-gate structure has good immunity against the gate leakage current. The special ESD detection circuit is designed with consideration of gate current to reduce the standby leakage current. The new proposed design has been fabricated and verified in a 65nm fully-silicided CMOS process. The new proposed power-rail ESD clamp circuit can achieve 7kV in human-body-model (HBM) and 325V in machine-model (MM) ESD levels while consuming only a standby leakage current of 96nA at room temperature under 1-V bias. In order to protect the mixed-voltage I/O interfaces in nanoscale CMOS technology, a new high-voltage-tolerant ESD clamp circuit is proposed to protect the mixed-voltage I/O circuits for receiving signals with 2?eVDD voltage level. The devices used in the high-voltage-tolerant ESD protection design are all low-voltage thin gate-oxide devices. The gate current of each thin gate devices in the high-voltage-tolerant ESD detection circuit has also been considered. By using the ESD protection scheme with the ESD bus and the proposed high-voltage-tolerant ESD clamp circuit, the mixed-voltage I/O circuit can be well protected. The new proposed circuit has been fabricated in a 1-V 65-nm CMOS process for experimental verification. In high integrated electronic system, the mixed-voltage I/O design with NMOS blocking technique is applied for receiving 3×VDD, 4×VDD, and even 5×VDD input signals without the gate-oxide reliability issue. In this dissertation, two new ESD protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffer with 3×VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD protection designs have been successfully verified in two different 130nm 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers. In high voltage CDMOS technology, the high-voltage DMOS is widely used as on-chip ESD protection devices. The trigger voltage of the high-voltage devices is too high to protect the output buffer. Such characteristics will cause the high-voltage DMOS susceptible to the latchup or ESD danger in the practical applications. To greatly improve ESD performance of the high-voltage DMOS devices, gate-driven and substrate-triggered circuit techniques are applied. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-?慆 5V/40V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs. In this dissertation, the novel ESD protection circuits have been developed for nanoscale CMOS process, mixed-voltage I/O interfaces and high-voltage BCD process with high ESD robustness. Each of the ESD protection circuits has been successfully verified in the testchips. The proposed ESD protection circuits in this dissertation can achieve the benefits of low standby leakage current, high ESD performance, and latchup-free characteristics for whole chip ESD design in CMOS ICs.
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Bhattacharya, Prasenjit. "Adaptive Dielectric Thin Film Transistor : A Self-Configuring Device for Low Power Electrostatic Discharge Protection." Thesis, 2020. https://etd.iisc.ac.in/handle/2005/4696.
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Large area and flexible electronic systems are widely used in applications such as displays, image sensors, wearable electronics, and energy harvesting systems. One of the fundamental functional blocks in these systems is the thin-film transistor (TFT), which suffers from poor field-effect mobility, electrical instability, etc. due to the state localization at low-temperature fabrication process, a criterion that enables system realization on glass or flexible substrate, such as plastic.
The electrostatic discharge (ESD) is a rapid transfer of static charge between two objects of dissimilar potentials, one of which is typically grounded. An electronic device could suffer ESD damage during different stages of its lifetime including manufacturing and product usage leading to a loss of billions of dollars annually to the electronics industry. Since the ESD phenomenon is unavoidable, on-chip ESD protection devices or circuits are required.
An ideal ESD protection device should offer a low resistance path to the surge current during an ESD event, but a high resistance path to the signal during the normal operation to minimize the power loss. In the crystalline CMOS technology, the parasitic bipolar turn-on (snapback) is effectively used to design the ESD protection device. However, most of the TFT technologies do not exhibit any bipolar turn-on owing to the poor mobility and lack of complementary devices. Hence, the conventional protection circuit uses large aspect-ratio diode-connected TFTs that offer a low resistance path to the surge current but also does the same to signals during normal system operation resulting in power loss. Additional circuits are required to keep the protection devices turned off during normal operation, but it leads to higher routing complexity, layout area, and multi-component reliability issues. This thesis investigates the feasibility of a novel idea for ESD protection involving an adaptive-dielectric TFT (adTFT) that self-configures itself to a low resistance state during an ESD event and a high resistance state during normal operation without external control.
The adTFT device is designed to differentiate between an ESD pulse, which is typically nanoseconds order, and a normal operation signal, which is either a static dc (e.g. in power line) or a pulse of width microseconds to milliseconds order (e.g. in data/address line of a switch matrix). This is achieved using a time-dependent gate field masking mechanism, which is enabled by modifying the gate dielectric of a conventional TFT to a dielectric-semiconductor-dielectric stack and attaching a charge injection/extraction terminal to the sandwiched semiconductor layer. A first-order model of the masking dynamics under a gate step-bias input is developed using the space-charge-limited-current and threshold voltage modulation. TCAD simulations are performed using poly-Si adTFT to get a detailed insight into the device operation. The HBM (human body model) ESD robustness and normal mode leakage current of the diode-connected adTFTs are evaluated and compared against that of the conventional TFTs.
Next, the adTFT and an experimental control (behaving similar to the conventional TFT) are fabricated using ZnO as the semiconductor material and Al2O3 as the dielectric material. The device operation is investigated using dc I-V, C-V, and transient pulse characterizations that eventually lead to the device layout optimization for ESD protection device design. The response of the protection device during normal circuit operation is evaluated in terms of both, the constant bias and the pulsed bias. The ESD robustness is evaluated using the transmission line pulse (TLP) measurements. Finally, the performance of the adTFT is compared to that of the conventional TFT in terms of the power to thermal breakdown during ESD and the power leakage during normal operation to highlight the primary advantage of the adTFT as an ESD protection device over the conventional one. The fabricated diode-connected adTFTs result in 1000-10000 times the power savings compared to the diode-connected conventional TFTs without sacrificing the ESD robustness. Therefore, the adTFT condenses the operation of an entire circuit into a single device and shows promise as a versatile building block for ESD protection and other circuit designs.
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Lubana, Sumanjit Singh. "CDM Robust & Low Noise ESD protection circuits." Thesis, 2009. http://hdl.handle.net/10012/4200.
Full textAbstract:
In spite of significant progress during last couple of decades, ESD still affects production yields, manufacturing costs, product quality, product reliability and profitability. The objective of an ESD protection circuit is to create a harmless shunting path for the static electricity before it damages the sensitive electronic circuits. As the devices are scaling
down, while ESD energy remains the same, VLSIs are becoming more vulnerable to ESD
stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower
parasitic capacitance of the ESD protection circuits. Hence, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Furthermore with scaling, the integration of analog blocks such as ADC, PLL’s, DLL’s, oscillator etc. on digital chips has provided cheap system on chip (SOC) solutions. However, when analog and digital chip are combined into single mixed-signal chip, on-chip noise coupling from the digital to the analog circuitry through ESD protection circuits becomes a big concern. Thus, increasing supply noise isolation while ensuring the ESD protection robustness is also a big challenge. In this thesis, several ESD protection circuits and devices have been proposed to address the critical issues like increased leakage current, slower turn-on time of devices, increased
susceptibility to power supply isolation etc. The proposed ESD protection circuits/devices have been classified into two categories: Pad based ESD protection in which the ESD protection circuits are placed in the I/O pads, and Rail based ESD in which ESD protection circuit is placed between power supplies. In our research, both these aspects have been investigated. The Silicon Controlled Rectifier (SCR) based devices have been used for Pad ESD protection as they have highest ESD protection level per unit area. Two novel devices Darlington based SCR (DSCR) and NMOS Darlington based SCR (NMOS-DSCR) having faster turn-on time, lower first breakdown voltage and low capacitance have been proposed.
The transient clamps have been investigated and optimized for Rail based ESD protection. In this research, we have addressed the issue of leakage current in transient clamps. A methodology has been purposed to reduce the leakage current by more than
200,000 times without having major impact on the ESD performance. Also, the issue of noise
coupling from digital supply to analog supply through the ESD protection circuits has been addressed. A new transient clamp has been proposed to increase the power supply noise isolation. Finally, a new methodology of placement of analog circuit with respect to transient clamp has been proposed to further increase the power supply noise isolation.
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蒙國軒. "ESD PROTECTION DESIGN FOR RADIO-FREQUENCY POWER AMPLIFIER." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/td8ydz.
Full textAbstract:
碩士國立交通大學
電子工程系所
96
The aim of this thesis is to design the ESD protection circuits which are suitable in radio-frequency (RF) power amplifiers (PA). The ESD protection capability and the influence on the performance of the RF PA circuit after inserting the ESD protection circuit needs to be considered simultaneously. This thesis includes two RF PA ESD protection strategies which have been verified through two individual chips fabricated in standard 0.13-μm CMOS process. The first RF PA ESD protection strategy is to use an inductive ESD clamp which can be co-designed with the RF PA output matching network. An inductive device can distinguish ESD event which occupies the lower frequency spectrum from the normal RF signals. It acts as the low impedance discharging path for ESD current and provides specific impedance for RF signal. A MIMCAP in series of the signal line can block out the ESD current from directly penetrating into the active devices in RF PA core. The measurement results have verified this ESD protection strategy and proved that the proposed ESD protection technique indeed provides excellent ESD robustness of up to 8kV HBM ESD level and 400V MM ESD level. The second RF PA ESD protection strategy is to use capacitive ESD devices with low parasitic capacitances. Waffle-structured SCR and diodes are utilized to provide maximum discharging peripheral within a given layout area for minimizing the parasitic capacitance. The waffle-structured SCR is designed with ESD detection and trigger circuit to provide the best ESD protection capability while contributing minimal parasitic capacitance to the RF PA. The measurement results have verified the effectiveness of the proposed ESD protection strategy and proved that this ESD protection technique indeed provides excellent ESD robustness of up to 8kV HBM ESD level and 800V MM ESD level. Further, the measurement results also verify that an unprotected RF PA can not survive any single ESD zapping. RF PA circuitry is in urgent need of ESD protection with low parasitic effect.
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Chang, Tai-Hung, and 張台宏. "On Chip ESD Protection Design In A Power Chip." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/28290813888272543142.
Full textAbstract:
碩士國立交通大學
電子工程系
88
The damages to CMOS VLSI circuits caused by static electronics is a very serious issue to CMOS VLSI design technologies. Especially, as the the technology is getting progress, the techniques that are used to improve the operation speed of CMOS circuits such as short channel length, thinner gate oxides, utilization of polyside and silicide, as well as the techniques to reduce the Hot-carrier effects such as LDD(Lightly Doped Drain) dramatically degrade the barring ability of ESD circuits. Due to the semiconductor process difference between high power CMOS circuits and low power CMOS circuits, we first implement a test chip with various high power CMOS process devices, then we measure all the characteristics that are related to ESD of the devices on the test chip. By analyzing these device characteristics, we can charactrize the effectiveness of ESD protection circuits and proposed new ESD protection circuits that are more efficient, especially for circuits with high power CMOS process. The ESD protection circuits we proposed can safely protect the CMOS circuits and make the ESD level confined to industrial application standard.
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Chen, Szu Han, and 陳思瀚. "ESD Protection Circuit for High Gain Low Noise Amplifier Applications." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/24359832594332861870.
Full textAbstract:
碩士長庚大學
電子工程學系
98
The major cause of most damaged devices or systems is electrostatic discharge(ESD). This damage will impact the characteristics of IC circuits. The device reliability is one of the most important key point when we design the IC circuit. We expect to design ESD protection circuit to protect low noise amplifier circuit of RF front-end receiver. The ESD protection circuit of this thesis is designed with four serial diodes with discharging circuit and the low noise amplifier is designed with common source. In this thesis, low noise amplifier with ESD protection circuit has a gain of 21 dB and noise figure of 3.3 dB. Input and output return losses are -29 dB and -18 dB, respectively. Power consumption is 11.7 mW. The frequency and voltage of operation are 5GHz and 1 volt, respectively. All of the circuits are simulated by Agilent Advanced Design System (ADS) and fabricated with TSMC 0.18µm 1P6M CMOS process which supplied from CIC.
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Jeff, Liao, and 廖健富. "ESD Protection Circuit Design for Power Pins in Integrated Circuits." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/55907770429366446991.
Full textAbstract:
碩士大葉大學
電機工程學系碩士班
93
In order to protect IC from the damage from ESD during the producing of IC, there are special circuits which can prevent ESD damage in the IC. This ESD protection circuits provide anther pathway to relief ESD electric current. Therefore, ESD electric current will not enter IC and no damage will be done. In this paper, we will present ESD protection circuits. First, there kinds of ESD models and motheds of ESD testing are mentioned. Then, we introduce ESD protection circuits. Last and the most important, we mimic and analize the VCC of RC with HSPICE.
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Li, Guan-Yi, and 李冠儀. "On-Chip ESD Protection Design for Radio-Frequency Power Amplifier." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/3662v4.
Full textAbstract:
碩士國立臺灣師範大學
電機工程學系
105
In this thesis, the diode string with embedded silicon-controlled rectifier (DSSCR) is designed to provide electrostatic discharge (ESD) protection of radio-frequency (RF) power amplifiers (PAs). To examine and evaluate the performance of the DSSCR, ESD protection circuits using the diode string (DS) and the diode-triggered SCR (DTSCR) are also designed and implemented for comparison with the proposed DSSCR protection circuit. To validate the effectiveness of the designed ESD protection circuits, radio-frequency power amplifiers which equipped with the above-mentioned ESD protection circuits were designed and fabricated in this research. The measured results show that the protection circuit using DSSCR will not cause undesired signal degradation and distortion, and meanwhile can offer instant and effective protection to the RF PAs. All of the ESD protection circuits designed in this thesis were fabricated using 0.18-um CMOS process. It is found in measurement that the RF PA equipped with the DSSCR protection circuit can bear 7-kV human-body-model (HBM) test.
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Lee, Zong Hao, and 李宗豪. "ESD protection circuits design and simulation for the low noise amplifier." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/65095002548989413063.
Full textAbstract:
碩士大葉大學
電機工程學系碩士班
93
Low Noise Amplifiers(LNA) are the backbone of radio frequency(RF) communications receivers.Cascode topologies of the LNA are quietly popular for the wireless communication system. In this thesis, the 2.4GHz CMOS LNA uses a TSMC standard 1P6M 0.18μm CMOS process. The high loss of silicon substrate and the low quality of passive devices fabricated on chip are the obstacles to be overcome for high frequency circuit designs using CMOS process. Selecting suitable devices and tuning parameters of each element, we can get the optimal value in this LNA. ESD(Electrostatic Discharge) protection circuit design becomes a challenging IC design problem, particularly for RF IC application. In order to avoid the ESD damage, which could be caused the breakdown of gate oxidation. The whole ESD design includes power rail ESD clamp circuit between VDD to VSS. A typical ESD protection structure consisting of two diodes at each I/O pin and a supply clamp for RF applications. In the section of fourth chapter, the thesis compares different ESD protection devices and shows that a suitable ESD performance target for RF applications.Finally, the ESD protected LNA can pass a HBM(Human-Body Mode) ESD level of 2kV.
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Chen, Mainn-Gow, and 陳面國. "A Comprehensive Study of Low Voltage Triggering SCR ESD Protection Structures." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/58291238209126672766.
Full textAbstract:
碩士國立交通大學
電子研究所
84
The thesis presents for the first time a comprehensive study of lowvoltage triggering SCR (Silicon-Controlled Rectifier) ESD (Electro-StaticDischarge) protection structures in a CMOS process. This merged protectionstructure consists of an n-MOSFET triggering device and a p-n-p-n SCR primaryprotection device. Experimental test chip has been fabricated with n-MOSFETgate length and SCR anode-to cathode spacing both as parameters, and havebeen characterized under Human-Body-Model (HBM) and Machine- Model (MM) condi-tions. A failure model has been established and has successfully reproducedthe measured HBM and MM failure threshold voltages. The assumption for deriv-ation of this model has been validated by SEM results. From the model, layoutguidelines can be drawn and the anode-to-cathode spacing has been judged asa key factor determining the failure threshold. Transient characterizationof the protection structure has further been performed, which can essentiallyprovide quantitative understanding of the high-level injection behavior inthe ESD event as well as can be utilized to determine the effect of the SCRprotection on the normal circuit operation. Also studied is the mixed-modecircuit and device simulation considering the lattice temperature, offeringin-depth insight into the response of the protection structure under ESDstress.
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Chang, Wei-Jen, and 張瑋仁. "High-Voltage-Tolerant ESD Protection Design in Low-Voltage CMOS Processes." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/70232955293959803259.
Full textAbstract:
博士國立交通大學
電子工程系所
96
The scaling trend of the CMOS technology is toward the nanometer region to increase the speed and density of the transistors in integrated circuits. Due to the reliability issue, the power supply voltage is also decreased with the advanced technologies. However, in an electronic system, some circuits could be still operated at high voltage levels. If the circuits realized with low-voltage devices are operated at high voltage levels, the gate-oxide breakdown and leakage issues will occur. Therefore, for the CMOS integrated circuits (ICs) with the mixed-voltage I/O interfaces, the on-chip electrostatic discharge (ESD) protection circuits will meet more design constraints and difficulties. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths during normal circuit operating operation. During ESD stress condition, the on-chip ESD protection circuit should provide effective ESD protection for the internal circuits. In high-voltage CMOS technology, high-voltage transistors have been widely used for display driver ICs, power supplies, power management, and automotive electronics. The high-voltage MOSFET was often used as the ESD protection device in the high-voltage CMOS ICs, because it can work as both of output driver and ESD protection device simultaneously. With an ultra-high operating voltage, the ESD robustness of high-voltage MOSFET is quite weaker than that of low-voltage MOSFET. Hence, how to improve the ESD robustness of HV NMOS with a reasonable silicon area is indeed an important reliability issue in HV CMOS technology. In this thesis, some new ESD protection structures are proposed to improve ESD robustness of the high-voltage IC products fabricated in CMOS technology. To protect the mixed-voltage I/O interfaces for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS), ESD protection design with the low-voltage-triggered PNP (LVTPNP) device in CMOS technology is proposed. The LVTPNP is realized by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the PNP device. The LVTPNP devices with different structures have been investigated and compared in CMOS processes. The experimental results in a 0.35-um CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device. Furthermore, layout on LVTPNP device for ESD protection in mixed-voltage I/O interfaces is also optimized in this work. The experimental results verified in both 0.35-um and 0.25-um CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the single finger layout style. Moreover, one of the LVTPNP devices drawn with the multi-finger layout style has been used to successfully protect the input stage of an ADSL IC in a 0.25-um salicided CMOS process. To increase the system-on-chip ESD immunity of micro-electronic products against system-level ESD stress, the chip-level ESD/EMC protection design should be enhanced. Considering gate-oxide reliability, a new ESD protection scheme with ESD_BUS and high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed in this chapter. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage NMOS/PMOS devices which can be safely operated under the 2.5 V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (PS, NS, PD, and ND) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13 um CMOS process have confirmed that the proposed new ESD protection scheme has high human-body-model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low-voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces. To greatly improve ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications, a new electrostatic discharge protection structure of high-voltage P-type silicon controlled rectifier (HVPSCR) embedded into the high-voltage PMOS device is proposed. By only adding the additional N+ diffusion into the drain region of high-voltage PMOS, the TLP-measured secondary breakdown current (It2) of output driver has been greatly improved greater than 6A in a 0.5-µm high-voltage CMOS process. Such ESD-enhanced VFD driver IC, which can sustain HBM ESD stress of up to 8kV, has been in mass production for automotive applications in car without latchup problem. Moreover, with device widths of 500um, 600um, and 800um, the MM ESD levels of the HVPSCR are as high as 1100V, 1300V, and 1900V, respectively. The dependences of drift implant and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the HV MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased. It was also demonstrated that a specific test structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the excellent TLP-measured It2 and ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the dependences of the TLP-measured It2 and HBM ESD levels on the spacing from the drain diffusion to polygate are different. In this thesis, the novel ESD protection circuits have been developed for mixed-voltage I/O interfaces and high-voltage CMOS process with high ESD robustness. Each of the ESD protection circuits has been successfully verified in the testchips.
28
Chen, Jie-Ting, and 陳界廷. "Low-Capacitance and High-Reliable ESD Protection Designs in CMOS Technology." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/6m2xcc.
Full textAbstract:
博士國立交通大學
電子研究所
107
With the continuous evolution of communication technology and integrated circuit (IC), wireless and wireline communication devices had become essential in daily life. All microelectronic products must meet the reliability specifications to be safely used and provide moderate life time. Electrostatic discharge (ESD) protection ability has become one of the important concerns on the reliability of IC products. Most of the failures and damages found in ICs were demonstrated to be related to ESD events. On-chip ESD protection circuits must be added for all I/O pads in IC products to sustain the HBM 2 kV and CDM 500 V for the reliability specifications. However, applying ESD protection devices at the I/O pads inevitably introduce some negative impacts to the high-speed circuit performance due to their parasitic effects. The parasitic capacitance caused by ESD protection devices will strongly degrade the bandwidth in normal high-frequency operation. Thus, the parasitic effects of the ESD protection devices should be minimized. Besides, to sustain good ESD robustness, the active power-rail ESD clamp circuit plays an important role in whole-chip ESD protection design. Unfortunately, the traditional RC-based power-rail ESD clamp with NMOS of large size often suffered a mis-triggering issue in hot plug-in condition. The power-rail ESD clamp circuit should be designed to sustain good ESD robustness without influencing the circuit performance. In Chapter 2, a new SCR-based ESD protection device is used to meliorate the ESD protection effectiveness and parasitic capacitance for high-speed I/O applications. By using a P+ and N+ junction contact with silicide to shorten the path of the SCR, the trigger voltage and turn-on resistance can be reduced to get good ESD robustness. In Chapter 3, a new distributed ESD protection structure with the stacked diodes with embedded SCR (SDSCR) is proposed to improve the bandwidth and input resistance of ESD protection circuit for broadband RF applications. The ESD protection devices of the proposed circuit are put under the I/O pad to reduce layout area and can discharge the ESD current immediately. From the experimental results, the proposed distributed ESD protection circuit with the SDSCRs can effectively sustain the HMM stress of 5 kV without influencing RF performance. In Chapter 4, a new power-rail ESD clamp circuit with both timing and voltage-level detection is proposed against false trigger events. The experimental results in a 0.18-μm 1.8-V CMOS process have successfully verified that the proposed power-rail ESD clamp circuit can sustain good ESD robustness (HBM 5.2 kV) without suffering the false trigger issue (high immunity for transient waveform with 10 ns rise time). The standby leakage current along the proposed power-rail ESD clamp circuit under the normal circuit operating condition has been also effectively reduced (270 nA) by adding a feedback NMOS in series into the diode string. In Chapter 5, a new diode-triggered quad-silicon-controlled rectifier (DTQSCR) is proposed and realized in a 0.18-μm 1.8-V/3.3-V CMOS process to effectively protect the interface circuit between separated power domains. Comparing to the traditional ESD protection design with GGNMOS, and the FOM (ESD level / layout area) of the proposed design is significantly improved ~36% to protect the interface circuits across separated power domains. In Chapter 6, a simple structure for power-rail ESD clamp circuit with both timing and voltage-level detection is proposed against false trigger events. A RC stage is used for dv/dt detection and a diode string is used to detect the over-stress voltage level during ESD events. The experimental results in a 0.18-μm 1.8-V CMOS process have successfully verified that the proposed power-rail ESD clamp circuit can sustain good ESD robustness (HBM 4.8 kV) without suffering the false trigger issue (high immunity for transient waveform with 10 ns rise time). By using fully isolated polysilicon diodes, the standby leakage current of the proposed power-rail ESD clamp can be effectively reduced (below 1 μA). Chapter 7 summarizes the results of this dissertation, where the future works based on the new proposed designs and test structures are discussed as well. The related works in this dissertation have been published in several international journals or conferences.
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Chu, Chi-Ling, and 朱季齡. "A Study of ESD Protection Circuit Design in Power MOSFET ICs." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/60343278231877993465.
Full textAbstract:
碩士大葉大學
電機工程研究所
88
In recent years, power MOSFETs are widely used in many electric systems such as automatic electronics, power switching, power rectifier, and display driver. Two kinds of efficient ESD protection circuit design in lateral DEMOS(LDMOS) power transistor will be presented in this thesis. One kind of the test samples fabricated by our design was using gate-coupled technique, which was well designed the overlap between the drain and the gate for optimum the gate potential transient corresponding to maximum substrate current generated by ESD pulse, meanwhile, it can subsequently lead to forward biasing of the substrate-source junction and then turn on the parasitic bipolar transistor. Also, the other of the test samples were with an SCR structure, which is the most efficient of all protection devices in terms of ESD performance per unit area. Eventually, a SCR with polygate which will have a small trigger voltage under ESD event, and then it can obtain an efficient ESD protection.
30
Tang, Kai-Neng, and 湯凱能. "Stacks of Low-Voltage Devices for ESD Protection in High-Voltage Applications." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/09343673113740855581.
Full textAbstract:
碩士國立交通大學
電子工程學系 電子研究所
103
Nowadays, many integrated circuits (ICs) of electrical products are fabricated in a high-voltage process. For example, driver ICs for various display panels, power management ICs and automotive ICs are commonly fabricated in a HV process. In a high-voltage process, HV transistors are born with complicated structure for the increase of the operating range and breakdown voltage, and that makes electrostatic discharge (ESD) protection design more difficult and challenging. In ESD protection design for HV applications, it is common to use lateral diffused MOS (LDMOS) as an ESD protection device. LDMOS is a general HV MOS, and its ESD robustness is worse than a low-voltage device’s. It has to enlarge LDMOS, and be aware of uniformity for ESD protection. In ESD protection design for HV applications, holding voltage of a device is an important factor. When holding voltage of a device is lower than supply voltage, it is possible that latchup occurs in applications. In some noisy environment, this factor should be paid more attention. Low-voltage devices are proved for good ESD robustness per area, and the devices can be enhanced by many methods. Stacking makes the devices’ trigger voltage and holding voltage increase so that the devices meet the conditions for HV applications. For area and ESD robustness concerns, stacking can be one of the best ways. In this thesis, stacks for ESD protection are implemented and verified, and it is discussed for the problems and improvement. Stacked configuration in different shapes is also examined. Increasing turn-on speed by replacing with other devices will be discussed.
31
Chiu, Po-Yen, and 邱柏硯. "LOW-LEAKAGE POWER-RAIL ESD CLAMP CIRCUIT IN NANOSCALE CMOS TECHNOLOGY." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/66617011935518793997.
Full textAbstract:
碩士國立交通大學
電機學院IC設計產業專班
96
The aim in this thesis is to design the low-leakage power-rail ESD clamp in nanoscale CMOS technology. The principles are using circuit and component characteristics to minimize leakage of the circuit. Besides having the lowest leakage current, it also can have high robustness of ESD protection. This thesis includes three topics; the main parts are through the circuit simulation and experimental measurements to verify the new proposed design. The first part is to introduce the evolution of gate-tunneling research. With the gate-oxide thickness become thinner and thinner in CMOS processes, the phenomena become more and more serious. In the past research, the mechanisms and formulas of gate-tunneling have been observed. The model of gate-tunneling also has been applied into advance CMOS processes. The second part is to simulate circuits and components in the 65-nm CMOS process with thin-oxide devices. Besides simulating the leakage current of MOS capacitor, the further discusses are what it will influence if MOS capacitor is applied to traditional power-rail ESD clamp circuits and new proposed power-rail ESD clamp circuit. In the simulation results, the leakage of MOS capacitor causes incorrect function which causes another leakage path and leak more current in the circuit. Although there have other methods to reduce the leakage current, but there is still have a leakage path through MOS capacitor. However, with a voltage drop across MOS capacitor, the MOS capacitor always leaks some current. The leakage current is still very huge. The new proposed design was designed to have lower leakage current when it is under normal circuit operating conditions and discharge ESD current in time when it is under ESD transient. As the simulation result, the new proposed design has lower leakage current than traditional designs. The third part is measured results. In this thesis, a new low-leakage power-rail ESD clamp circuit designed with the consideration of gate-leakage issue has been proposed and verified in 90-nm and 65-nm CMOS processes. According to the measured results, the gate leakage issue needs to be taken into consideration. The traditional designs have more leakage current because the leakage of MOS capacitor, so the traditional designs can not be used if it is implemented in nanoscale CMOS process with thin-oxide device. The new proposed design has the lowest leakage current (228 nA at 25 oC) and good robustness of ESD tests. It has ESD robustness of over 8 kV in HBM and 750 V in MM.
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Chou, Chien-I., and 周千譯. "ESD Protection Design with Impedance Isolation Technique for CMOS RF Low Noise Amplifier." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/83056830904121068689.
Full textAbstract:
碩士國立交通大學
電子工程系
91
A CMOS RF LNA with high ESD sustain ability is presented in this thesis. A novel LC tank ESD protected LNA based on impedance isolation is proposed. The whole ESD design includes power rail ESD clamp circuit between VDD to VSS. In the second part, a detailed and comprehensive noise analysis of the LNA without and with input ESD protection has been investigated, including modified power gain by ESD devices, input matching property, noise figure and the portion of the noise power generated by ESD devices. We provide some noise equation and simulation results in this section. In the third part, three types of 5.2GHz CMOS RF LNA are designed and implement in 0.25-μm CMOS process, including pure LNA without any ESD protection, LNA with novel LC tank ESD protection and LNA with conventional diode ESD protection. We also develop some on-chip inductor modeling. The experimental results show that the center frequencies of ESD protected LNA are shifting. After adding proper output matching network, the ESD protected LNA will have the same center frequency. Re-simulation results based on measured S-parameter show that LC tank protected LNA has better RF performance than diode protected one. And measured noise figure also shows that LC tank protected LNA has lower noise level than diode protected one. Thus the ESD protection with LC tank is more suitable for RF application of higher operating frequency in the future. The LC tank ESD protected LNA can pass a HBM ESD level of 4.9kV and a MM ESD level of 275V.
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Wu, Yi-Han, and 吳易翰. "Design of Low-Voltage-Trigger SCR for ESD Protection in 28nm CMOS Process." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/33171201008431051012.
Full textAbstract:
碩士國立交通大學
電子研究所
105
With advanced CMOS technology, CMOS devices have been fabricated with thinner gate oxide, and the operation ability of integrated circuits can attain to high speed and low power consumption. However, with the scaling of CMOS technologies, the ESD robustness decreases and the reliability of production is unstable. In addition, ESD protection is more challenge to overcome because thinner gate oxide are equipped with the characteristic of low breakdown voltage. The layout area of advanced CMOS process would spend a huge cost. In other word, companies will spend a huge additional budget because the layout of ESD protection cells occupies large area. In this thesis, small layout area and decent ESD robustness are our targets to realize on our novel devices. A typical whole chip ESD protection scheme forms Positive to VDD mode (PD mode), Negative to VDD mode (ND mode), Positive to VSS mode (PS mode) and Negative to VSS mode (NS mod) which modes are discharge paths. However, ND mode and PS mode have relatively weak ability of ESD robustness, especially in advanced CMOS process. The ability of Power-rail ESD clamp circuits the main reason to influence ND and PS mode of ESD robustness. In chapter 2, we propose novel I/O ESD devices equipped with the advantage of low leakage and low trigger voltage. The I/O ESD devices are modified by Silicon-Controlled Rectifier (SCR). Meanwhile, we add the structure of PMOS/NMOS and dummy gate on our proposed I/O ESD devices. The advantage of gate-control method makes novel SCR devices have low trigger voltage (Vt1), while the benefit of attached dummy gate is Shallow Trench Isolation (STI) structure cannot form in our proposed devices. In addition, our proposed devices contain parasitic diode and parasitic SCR as discharge paths which can be usefully applied on whole chip ESD protection scheme. Moreover, the drawback of typical ND and PS mode are removed. From above all, our proposed design have been realized in 28-nm high-k/metal gate CMOS process. In chapter 3, we modify the novel devices described in chapter 2 and its modified devices can be applied on Power Rail ESD clamp circuit. Moreover, modified devices with additional Silicide Blocking (SAB) area to acquire better ESD robustness, smaller trigger voltage and faster turn-on speed. Modified devices combing with ESD transient detection circuit can efficiently turn on while ESD phenomenon occurs. We add traditional Silicon-Controlled Rectifier (SCR) and Substrate-Trigger SCR (ST-SCR) devices to compare with modified devices. Decent ESD robustness for HBM and MM, uniformly and fast trun-on, small layout area and the avert of latch-up risky are advantages for our modified devices in 28-nm CMOS process. In chapter 4, we predict that our proposed devices can be realized on Fin-FET structures for future investigation.
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Chang, Hsin-Yi, and 張欣怡. "Bonding technique for power flip-chip light emitting diode with ESD protection substrates." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/67403114298035821209.
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Liao, Seian-Feng, and 廖顯峰. "Optimization of Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Layout Consideration." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/27130130262768377247.
Full textAbstract:
碩士國立交通大學
電子工程學系 電子研究所
104
Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. ESD may occur accidentally during the fabrication, package, and assembling processes of IC products, which often caused serious damages on ICs. During normal circuit operation, the noise might unpredictably trigger the parasitic BJT of the ESD devices. Furthermore, to avoid latchup issue, the holding voltage (Vh) should be larger than the supply voltage of the internal circuits in ESD protection design for HV applications. Lateral DMOS (LDMOS) was often used as ESD protection device in HV process, but the holding voltage (Vh) of LDMOS after snapback was smaller than the circuit operating voltage (VCC). Thus, the LDMOS was sensitive to latchup issue. Therefore, the stacked configuration of LV devices is a way to achieve a high holding voltage for ESD protection in HV circuits. By adjusting the stacking numbers of stacked PMOSs, it can provide effective ESD protection for various HV applications. In this thesis, stacks for ESD protection are implemented and verified, and it is discussed about different layout parameters to effectively improve ESD robustness of ESD devices. The guard-ring layout on the stacked LV devices was further investigated holding voltage in silicon chip. In addition, the pulse width of the transmission line pulsing (TLP) system was also investigated holding voltage in silicon chip. Decreasing the layout area to get high ESD robustness and latchup-free immunity for HV applications.
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Lin, Chih-wen, and 林志威. "The Parameters Design and Analysis of ESD Protection Circuit for an Intelligent Power Device." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/14075417515105668273.
Full textAbstract:
碩士大葉大學
電機工程學系碩士班
93
By the advancement of the process technology, power electronic devices（or to name the power devices）use broadly in every kind of power extent. However, due to the process scale down, the ESD immunity level is very poor for power devices. The technique of LDD （Lightly- Doped Drain）, more thinner gate oxide, and the shallow junction depth ... etc., resulting in devices have some reliability and the life-time shortened problems. In this thesis, we will use the process simulator（TSUPREM-4）and the device electrical simulator（Medici）to design the ESD protection circuits for the LIGBT. From these results of simulation to improve the capability of against ESD zapping, meanwhile, we will accurately design the device structure and the process parameter, and to reach the design of optimization and the ESD protection of target.
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Altolaguirre, Federico Agustin, and 艾飛. "DESIGN OF LOW-LEAKAGE POWER-RAIL ESD CLAMP CIRCUITS IN NANOSCALE CMOS TECHNOLOGY." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/05350925268466126146.
Full textAbstract:
碩士國立交通大學
電機資訊國際學位學程
99
The aim of this thesis is to design an ultra-low leakage power-rail ESD clamp in an advanced CMOS technology. The principle is using circuit techniques to reduce the leakage current of the circuit, without undermining the ESD robustness. This thesis is divided in three main parts The first part introduces the evolution of gate-tunneling research. With the gate-oxide thickness become thinner and thinner in CMOS processes, the phenomena become more and more serious. In the past research, the mechanisms and formulas of gate-tunneling have been observed. The model of gate-tunneling also has been applied into advance CMOS processes. In the second part, the proposed solution is presented and the simulation results are shown, using the SPICE models for a 65-nm CMOS process with thin-oxide devices. In the traditional power-rail ESD clamp, the leakage through the MOS capacitor is extremely high. The proposed solution includes a novel design technique to reduce this leakage, and a series of implementations are presented and detailed. In the third part, a test chip is realized and sent to tape-out to realize further analysis. The standby leakage of the circuits is measured, and the ESD robustness is measured by several parameters, such as TLP, turn-on verification, and HMB/MM simulation. The proposed circuits can lead to a leakage current as low as 112nA under 1V-bias at 25°C (opposed to 21.6µA of the traditional power-rail ESD clamp), while the ESD robustness is not changed.
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Wu, Woei-Lin, and 吳偉琳. "Design on the Low-Leakage-Current Diode String for ESD Protection in SiGe BiCMOS Process." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/01499332664721657589.
Full textAbstract:
碩士國立交通大學
電子工程系所
93
The aim in this thesis is to design the ESD protection circuits in SiGe BiCMOS process. In this design, the leakage current of the diode string can be effectively reduced and a high ESD robustness can be achieved. There are three parts in this thesis. The first part investigates the ESD robustness of the diodes and heterojunction bipolar transistors (HBTs) by different device structures and layout parameters. The transmission line pulse generator (TLPG) is also used to investigate the characteristics of these devices under high-current stress. In addition, the ESD robustness of HBTs for low-voltage, high-voltage, and high-speed applications are also investigated. For the traditional diode string, the parasitic p-n-p bipolar junction transistor (BJT) devices in the diode string will induce a large leakage current into the substrate, especially under high temperature condition. In the second part, a new diode structure in SiGe process is proposed and low-leakage-current diode string (LLCDS) is formed by this new diode structure. Furthermore, the leakage current of LLCDS can be effectively reduced by extra circuit design. Because the diode string is designed to sustain the ESD stress under forward-biased condition, a high ESD robustness can be achieved in a small silicon layout area. In the third part, the optimum design on the circuit to minimize the leakage current of LLCDS as the power-rail ESD clamp circuit is evaluated by calculating the physical formulas of the parasitic devices in the diode string and the simulation results. The experimental results are also performed to verify the simulation results. Furthermore, the second design on the diode string as the power-rail ESD clamp circuit is proposed to further reduce the leakage current. In addition, the power-rail ESD clamp circuit with new diode string as the trigger circuit of HBT is also proposed and verified. In summary, LLCDS as the power-rail ESD clamp circuit are developed in SiGe process with low leakage current and high ESD robustness. Each of the design has been successfully verified in the testchips and also published in the international conference papers.
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Hung, Tao-Yi, and 洪道一. "ESD Protection Design of 900–1800MHz High-Power CMOS T/R Switch for GSM Cellular Applications." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/u5r2j2.
Full textAbstract:
碩士國立交通大學
電子研究所
106
In recent years, radio-frequency integrated circuits (RFICs) have been successfully implemented in CMOS process thanks to the fast development of CMOS technologies. In this way, the RFICs can be integrated in a system on chip (SOC) for mass production with lower cost of IC manufacturing. As the transistors scale down rapidly, the oxide thickness becomes thinner and provide faster logic operations with lower energy consumption. However, the threat from electrostatic discharge (ESD) phenomenon was not alleviated as technology advances. In RFICs, the ESD protection circuit must provide enough ESD robustness without disturbing the normal circuit operations. Thus, the ESD protection design must be strictly conducted in order to minimize the parasitic effect of the ESD devices lest it should degrade the performance of the high-speed RF signal. There are two major parts in this thesis. The first part of the thesis targets on the T/R switch which is applied for cellular device. In a high-power T/R switch, traditional ESD protection method cannot be used since the large amplitude and high frequency of the RF signal will mis-trigger the traditional ESD protection design. As a consequence, in this work, there is no additional discharging path employed to discharge the ESD current. Instead, by identifying the behavior of the ESD transients and the normal RF signal, the transistors in the proposed ESD protection design can trigger the inherent transistors of the T/R switch in the PS-mode zapping event and discharge the ESD current. The proposed ESD protection design for high-power T/R switch has been fabricated in a 0.18-µm CMOS process and achieved good ESD levels. RF performance and ESD characteristics are measured and analyzed in the thesis. The second part focuses on an ESD protection device for typical T/R switch applications. By using the diodes and MOS transistors which are already designed in the T/R switch with conventional ESD protection, embedded silicon-controlled rectifiers (embedded SCR) are implemented in a 90-nm CMOS process by layout skill. The proposed ESD protection with embedded SCRs and power-rail ESD clamp triggered can enhance the PS-mode ESD robustness of the T/R switch successfully.
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王有諒. "Investigation on the Improvement of ESD Protection Circuits for Low Temperature Polycrystalline Silicon Thin Film Transistor Panels." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/12574867961513364560.
Full textAbstract:
碩士國立交通大學
平面顯示技術碩士學位學程
103
In the information developed time, LCD in addition to enhance the resolution to cope with the purposes of access information and documents processing, but also need to take into account the design of energy saving and the use of safety; High-resolution LCD panel resulted in the internal metal traces and the circuit operation becomes narrower and complex, not only panel current consumption increased, but also increase the probability of LCD internal circuit electrostatic hazards from the production process. Up to today, MOS-Diode ESD protection circuit used in the LCD industry widely, Because of its connect directly to the panel Power line circuit, therefore even it is not in the operating mode, it still to be a pathway of leakage current, and its through ESD stress, but also has a high leakage currents and characteristics variation worries, affecting subsequent production processes yield rate , even more endanger to the safety of LCD products what used in the automotive and aerospace. Based on the particular NMOS and PMOS character of LTPS process and the higher turn-on current of PIN diode, this paper was researched the PIN diode , the Single MOS-diode ,and the Multi MOS-diode of ESD protection circuit for finding out the best one of them. According to experimental result for comparing the leakage current condition of ESD protection circuit, the PIN diode circuit would be the lowest of them before ESD stress , but the Multi MOS-diode circuit would be the lowest after ESD stress. And for the ability of ESD protection, the PIN-diode circuit would be the best one, the second was the Single MOS-diode circuit, and the Multi MOS-diode was the worst. The three types of ESD protection circuit have advantage and weakness respectively, our experimental data can be referred in ESD protection of LCD panel future.
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Yen, Chia Yi, and 顏嘉逸. "Enhancement of the Output Efficiency, Heat Dissipation Capability and ESD Protection for Flip-Chip Power LED Fabrication." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/22007994233903224457.
Full textAbstract:
碩士長庚大學
光電工程研究所
97
At present, all the light emitting diodes (LED) related researches focus on the topic of improving their output efficiency for white light applications. In this work we used ultrasonic flip-chip method to achieve the goals of high efficiency flip-chip power LED fabrication. In this thesis, three important aspects of flip-chip LED fabrication, such as the output efficiency, heat dissipation characteristics and anti electrostatic discharge capability are studied and detailed. First of all, we use silicon and AlN as submouts. For they both have good thermal conductivity. At high current operating, the flip-chip LED on AlN submount exhibits better output efficiency due to its high thermal conductivity 320W/mk. Meanwhile, we also change the number of gold bumps on the p-pad and n-pad of LED to study their heat dissipation performance. The IR thermography is used to measure the surface temperature of varied bumps flip-chip LED. We find that flip-chip LEDs with more the gold bumps and the less temperature rises. Finally, we also adopted a metal-insulator-metal (MIM) structure submount for flip-chip LED fabrication, it works like a shunt capacitor which can enhance the anti electrostatic discharge capability. And it is proven that our MIM structure can protect LED from electrostatic discharge damage effectively.
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Yeh, Yu-Chen, and 葉宇晨. "Adaptive Triggered Voltage (Vt1) and Holding Voltage (Vh) Stacked SCRs for ESD Protection in High Voltage Power Clamp Circuit." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/v28utx.
Full textAbstract:
碩士國立交通大學
電子工程學系 電子研究所
104
In our daily lives, electrostatic discharge can be seen everywhere. However, the ESD protection capability of device is decreased with the progress of process technology. For example, in human body model, the ESD protection capability of device with LDD structure is lower than 2000V in feature size equal to 1μm. Hence, the device will be destroyed easily by ESD. In this thesis, our propose is to make a ESD protection device to protect the internal circuit of ICs. First, we will engage in the characteristic of SCR, include the I-V curve discussion, the breakdown mechanism, and some of the key specific parameters related to breakdown voltage. According to the above discussion, we propose some advices to prevent the issue of latch-up. Another part of our study is to apply SCR into HV-ICs. The operating voltage of HV-ICs is equal to 30V. We will face the challenge to apply SCR into HV-ICs because the phenomenon of snapback will reduce the holding voltage of SCR. We will propose some advices to increase the holding voltage of SCR to make it can be used in HV-ICs.
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Kannangara, Indunil Chanaka. "Low cost integrated substation protection and control system." Thesis, 1994. https://vuir.vu.edu.au/17909/.
Full textAbstract:
With the recent developments in the digital equipment associated with the power
system such as digital relays and transducers the development of integrated substation
protection and control systems were possible. In this thesis the use of the currently
available very sophisticated and reliable, yet inexpensive high level third generation
software to develop such application is dicussed. Low cost integrated system does
not depend on any particular power protection or control manufacturers protocol but
uses standard IEEE '802.3 Carrier Sense Multiple Accesses/Collision Detection
(CSMA/CD) protocol (Ethernet). Data Acquisition and control is done directly so that
it could be used on a range of different manufacturers' equipment. These capabilities
make this development to act as a system integrator for substation protection and
control and will overcome many disadvantages associated with the traditional
protection and control systems.
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Jeng, Guan-Wei, and 鄭冠偉. "An 11-bit single-ended inverter-based successive approximation analog to digital converter for low power and ESD design." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/04785883289646723693.
Full textAbstract:
碩士國立中興大學
電機工程學系所
102
By the progression of technology, the size of CMOS devices have been reduced constantly, which effectively shrinks the area of chip and let the standard of Analog to Digital Converters have completely new development, a low speed ADC can be widely used in Biomedical Systems and portable electronics products, the appearance of many electronic products have became light, thin, short and small so that we find the quantity of electric charge is limited, and that’s why we have to design a low power consumption circuit to improve this problem. In addition, our laboratory had used the process by 90nm to carry out high-speed analog to digital converters in last two years, the device size in advancing process is smaller than others, and gate oxide layer tends to suffer from external Electrostatic damage such as HBM and MM, as a result, we start to construct ESD protection circuit in order to protecting Internal circuit from Electrostatic damage. This essay realizes a Analog to Digital Converters, the process used TSMC 0.35μm CMOS Technology, the resolution of 11 bits, the framework for the successive approximation analog to digital converter, the goal of this designation is to reduce the power consumption, which mainly improve comparator and capacitor array’s switch consumption, comparator used inverter-based, Taking capacitor array and switch apart A-side and B-side, we can carry out the first comparison without switching any after sampling phase, In addition let sample and hold circuit used Bootstrapped switch can improve the decrease SNDR range when Input frequency closes Nyquist Rate. In Supply voltage is 1.2V、Input Frequency is 1.64kHz、VPP is 3V、Sampling frequency is 25kS/s；the result of the survey is that DNL is 0.88/-0.90 LSB、INL is 0.72/-1.14 LSB、SNDR is 63.76 dB、SFDR is 73.99dB、ENOB is 10.28bit、power consumption is 3.37μW、FOM is 181 fJ/Conv.-setp、chip area is 1.41mm2（exclusive of PAD）.In ESD protection circuit, the process is TSMC 0.18μm CMOS Technology, and in the mode of HBM, the endurance capacity of input pin is about ±150V, and the endurance capacity of output pin is about ±450V.
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Hsiao, Yu-Yi, and 蕭育宜. "Innovative Design of Smart and Safe Protection for Low Voltage Distribution Power System." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/8dmwj9.
Full textAbstract:
碩士國立臺灣科技大學
電機工程系
106
The purpose of this thesis is to study the design and planning an innovative smart and safe protection for low voltage distribution power system. Enormous and various home appliances are widely used to seek better quality of life and safer living environment during economy growth ages. However, if the overloaded existed in the distribution branches for a long time and the protective devices, such as No Fuse circuit Breaker (NFB), could not normally activated, disasters with high losses of life and property damage may occur, due to the electrical wiring malfunction. To prevent an electricity crisis, a set of safety and energy source management protection coordination mechanism has to be built into the power distribution system of the building. It can inform the uses indoor in advance. In this thesis, the load current of the socket outlet is measured by the instantaneous current measurement of the Hall effect sensor, and the signal is transmitted through the single-chip interface circuit to the internal power source distribution box by power line communication (PLC) to evaluate the overall load condition of the distribution branch, and then transmitting the safety margin message returns to the branch socket outlets, which will show the socket outlet load conditions with different color indication by LED. It is proven the protective algorithm and innovative design to inform the user not to use the overload socket outlets are helpful for achieving raising the overload protection of the branches, and reducing electric fire hazards.
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Lukic, Zdravko. "Design and Practical Implementation of Advanced Reconfigurable Digital Controllers for Low-power Multi-phase DC-DC Converters." Thesis, 2012. http://hdl.handle.net/1807/33855.
Full textAbstract:
The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response.
The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts.
A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved.
At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.
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Huang, Chia-Ming, and 黃佳民. "A 67% Output Voltage Ripple Reduction and True-Random-Noise Injection Stacked Digital Low Dropout Regulator for Power-Side Channel Attack Protection." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/rxw82q.
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