Dissertations / Theses on the topic 'Low noise amplifier'
To see the other types of publications on this topic, follow the link: Low noise amplifier.
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'Low noise amplifier.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Ganesan, Sivakumar. "Highly linear low noise amplifier." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5928.
Full textAbstract:
The CDMA standard operating over the wireless environment along with various other
wireless standards places stringent specifications on the RF Front end. Due to possible
large interference signal tones at the receiver end along with the carrier, the Low Noise
Amplifier (LNA) is expected to provide high linearity, thus preventing the intermodulation
tones created by the interference signal from corrupting the carrier signal.
The research focuses on designing a novel LNA which achieves high linearity without
sacrificing any of its specifications of gain and Noise Figure (NF). The novel LNA
proposed achieves high linearity by canceling the IM3 tones in the main transistor in both
magnitude and phase using the IM3 tones generated by an auxiliary transistor. Extensive
Volterra series analysis using the harmonic input method has been performed to prove the
concept of third harmonic cancellation and a design methodology has been proposed. The
LNA has been designed to operate at 900MHz in TSMC 0.35um CMOS technology. The
LNA has been experimentally verified for its functionality. Linearity is usually measured
in terms of IIP3 and the LNA has an IIP3 of +21dBm, with a gain of 11 dB, NF of 3.1 dB
and power consumption of 22.5 mW.
2
Cherukumudi, Dinesh. "Ultra-Low Noise and Highly Linear Two-Stage Low Noise Amplifier (LNA)." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71355.
Full textAbstract:
An ultra-low noise two-stage LNA design for cellular basestations using CMOS is proposed in this thesis work. This thesis is divided into three parts. First, a literature survey which intends to bring an idea on the types of LNAs available and their respective outcomes in performances, thereby analyze how each design provides different results and is used for different applications. In the second part, technology comparison for 0.12µm, 0.18µm, and 0.25µm technologies transistors using the IBM foundry PDKs are made to analyze which device has the best noise performance. Finally, in the third phase bipolar and CMOS-based two-stage LNAs are designed using IBM 0.12µm technology node, decided from the technology comparison. In this thesis a two-stage architecture is used to obtain low noise figure, high linearity, high gain, and stability for the LNA. For the bipolar design, noise figure of 0.6dB, OIP3 of 40.3dBm and gain of 26.8dB were obtained. For the CMOS design, noise figure of 0.25dB, OIP3 of 46dBm and gain of 26dB were obtained. Thus, the purpose of this thesis is to analyze the LNA circuit in terms of design, performance, application and various other parameters. Both designs were able to fulfill the design goals of noise figure < 1 dB, OIP3 > 40 dBm, and gain >18 dB.
3
Adl, Sanaz. "Low noise pre-amplifier/amplifier chain for high capacitance sensors." College Park, Md. : University of Maryland, 2007. http://hdl.handle.net/1903/7303.
Full textAbstract:
Thesis (Ph. D.) -- University of Maryland, College Park, 2007.Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
4
Midtflå, Nils Kåre. "A 2.4 GHz Ultra-Low-Power Low-Noise-Amplifier." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2010. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10955.
Full textAbstract:
In this thesis different aspects of general low power design and LNA-design have been studied. A new architecture for an ultra low power LNA is proposed and simple simulation results are presented. Simulations show that there should be possible to design a 2.4 GHz LNA that works sufficiently at 200 µA. The proposed architecture achieved a voltage gain over 20 dB from 2.32 to 2.5 GHz, a noise figure of 4.65 dB, IIP3 of -15.45 dBm and a input match of -9.5 dB. There is still a lot of work do and many simulations to perform before one can inconclusively conclude that the proposed architecture is a feasible solution, although the results generated in this thesis seem promising.
5
Zheng, Wei. "Low-power low-noise DC-coupled sensor amplifier IC." Pullman, Wash. : Washington State University, 2008. http://www.dissertations.wsu.edu/Thesis/Summer2008/w_zheng_070908.pdf.
Full textAbstract:
Thesis (M.S. in electrical engineering)--Washington State University, August 2008.Title from PDF title page (viewed on Mar. 11, 2009). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 48-49).
6
Cunningham, Michael Lawrence. "A High Temperature Wideband Low Noise Amplifier." Thesis, Virginia Tech, 2016. http://hdl.handle.net/10919/78388.
Full textAbstract:
As the oil industry continues to drill deeper to reach new wells, electronics are being required to operate at extreme pressures and temperatures. Coupled with substantial real-time data targets, the need for robust high speed electronics is quickly on the rise. This paper presents a high temperature wideband low noise amplifier (LNA) with zero temperature coefficient maximum available gain (ZTCMAG) biasing for a downhole communication system. The proposed LNA is designed and prototyped using 0.25μm GaN on SiC RF transistor technology, which is chosen due to the high junction temperature capability. Measurements show that the proposed LNA can operate reliably up to an ambient temperature of 230°C with a minimum noise figure (NF) of 2.0 dB, gain of 16.1 dB, and P1dB of 19.1 dBm from 230.5MHz — 285.5MHz. The maximum variation with temperature from 25°C to 230°C is 1.53dB for NF and 0.65dB for gain.Master of Science
7
Qun, Wu, Qiu Jinghui, and an Deng Shaof. "AN INTEGRATED LOW-NOISE BLOCK DOWNCONVERTER." International Foundation for Telemetering, 1995. http://hdl.handle.net/10150/608420.
Full textAbstract:
International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, NevadaIn this paper, a small-sized low-noise integrated block downconverter (LNB) used for Ku-band direct reception from broadcasting satellites (DBS) is proposed. The operating frequency of the LNB is from 11.7 to 12.2GHz. The outlook dimension is 41 X 41 X 110mm^3. Measured results show that the average gain of the LNB is 57dB, and noise figures are less than 1.7dB. It has been found that clear TV pictures have been received using the LNB for the experiment of receiving the "BS-2b" (Japanese broadcasting satellite) at Harbin region, Heilongjiang Province, P. R. China.
8
Mohammad, Afzal. "Low noise amplifier design for dense phased arrays." Thesis, University of Gävle, Department of Technology and Built Environment, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-518.
Full textAbstract:
Radio Astronomers demand for highly sensitive astronomical facility. Their demand is a radio telescope that can detect the weakest and deepest radio signal. To fulfill the demand of high sensitive telescope, an entirely new way of realizing a radio telescope is required. One of the most important components in the RF front end that determines the sensitivity of a radio telescope is the Low Noise Amplifier (LNA).
The project has the selected process technologies which was searched and about the different noise matching topologies, input matching topology, wide band noise and input matching topologies has discussed by the author to the requirement of LNA in Astronomical purposes.
In this report, the best process technology candidate was chosen apart from selected technology candidates to obtain the minimum noise temperature over broad range frequency upon the modern era of Astronomical LNAs.
The work was continued to design a single ended LNA to obtain desired transistor parameters while using different noise matching topologies, input matching topologies, wideband noise and input matching topologies to have an LNA achievement with the design goal.
Further two stage amplifier was implemented to obtain minimum noise temperature, good stability, high gain, good input and output reflection coefficient with less power consumption.
9
Bandla, Atchaiah. "Highly Linear 2.45 GHz Low-Noise Amplifier Design." Thesis, Linköpings universitet, Fysik och elektroteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-119982.
Full textAbstract:
One critical component of the communication receiver of front-end system is the low-noise amplifier (LNA). For good sensitivity and dynamic range, the LNA should provide a low noise figure and maximum attainable power gain. Another concern is the linearity of the LNA. Strong signals produce intermodulation products in a frequency band close to the operating frequency that might affect the performance of the receiver. In many cases, the intermodulation products can be reduced by increasing the current through the active device. Hence, a trade-off between power consumption and linearity must be considered when designing the LNA. The thesis includes the bias network design, stability analysis, matching network design and layout design of the LNA RF module with layout simulation. The simulation has been performed using Advanced Design System (ADS) simulation software. After implementation of LNA on a PCB, the LNA is measured with the help of the power supply unit and vector network analyzer. The proposed design aim is to provide a low noise figure (NF) and high gain while maintaining the low power consumption.
10
Zhang, Xiaomeng. "Multi-finger MOSFET Low Noise Amplifier Performance Analysis." Wright State University / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=wright1420814124.
Full text
11
Rolo, Manuel Dionísio da Rocha. "A low-noise CMOS amplifier for medical imaging." Master's thesis, Universidade de Aveiro, 2010. http://hdl.handle.net/10773/4394.
Full textAbstract:
Mestrado em Engenharia Electrónica e TelecomunicaçõesA presente dissertação aborda o projecto de um frontend analógico integrado para sincronização e amplificação de sinais produzidos por um fotomultiplicador de silício. A solução proposta pretende possibilitar medidas de tempo com resoluções na ordem dos picosegundos, para implementação em equipamentos compactos dedicados à Tomografia por Emissão de Positrões, com capacidade para medida do tempo de voo de fotões (TOFPET). O canal de frontend completo foi implementado em tecnologia CMOS 130nm, e compreende blocos de préamplificação, integração de carga, equilíbrio dinâmico do ponto de operação, bem como circuitos geradores de correntes de referência, para uma área total em silício de 500x90 μm. A discussão de resultados é baseada em simulações póslayout, e as linhas de investigação futuras são propostas.
An analogue CMOS frontend for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) is proposed. The solution intends to achieve picosecond resolution timing measurements for compact timeofflight Positron Emission Tomography (TOFPET) medical imaging equipments. A 130nm technology was used to implement such frontend, and the design includes preamplification, shaping, baseline holder and biasing circuitry, for a total silicon area of 500x90 μm. Postlayout simulation results are discussed, and ways to optimize the design are proposed.
12
Boglione, Luciano. "Low noise microwave feedback amplifier design with simultaneous signal and noise matching." Thesis, University of Leeds, 1998. http://etheses.whiterose.ac.uk/900/.
Full textAbstract:
This thesis looks into the problem of simultaneous signal and noise match at the input port of low noise amplifiers; feedback LNAs are considered because previous works show that they can achieve the simultaneous match condition. The investigation analyses the influence of both parallel and series feedback elements on the amplifier. Matrices are used to describe signal and noise parameters of each component of the model - parallel admittance, series impedance, active device. This approach allows the analysis to be applied to a wide range of networks, as long as noise and signal matrices are available. For this reason, the results are not limited to active devices in the microwave region of the spectrum but they are applicable to any linear 2-port circuit. The noise parameters of feedback networks are investigated thoroughly. Analytical expressions are worked out as functions of the feedback immittances and have been used to support experimental evidence previously published. A duality property for feedback networks is pointed out; new circles for constant equivalent noise resistance are devised; optimum values for the feedback impedance are determined; an investigation of a well-known noise model is carried out and its validity is extended. Based on the closed form expressions of the noise parameters, an original analytical procedure for the design of the optimum noise source reflection coefficient is presented. To the author's knowledge, no technique was available before. The design for simultaneous signal and noise match is now possible, because the input reflection coefficient can be set independently by properly choosing the load. Different devices are considered and their different behaviour is highlighted. A remarkable feature of the new design technique is to avoid the need of input matching when designing low noise amplifiers. Finally, experimental results are also presented and the performance of aI GHz single stage BJT LNA is shown. The fundamental achievement is that the noise figure of the LNA is equal to its minimum value within the measurement uncertainty.
13
Silva, Clara Maria Apolinário Lucas da. "Low noise amplifiers' design for radioastronomy." Master's thesis, Universidade de Aveiro, 2014. http://hdl.handle.net/10773/14549.
Full textAbstract:
Mestrado em Engenharia Electrónica e TelecomunicaçõesSpace exploration has always been an ambition to human kind. Nowadays the new technologies that could be used in radioastronomy field have made this goal even more attainable. The big manufacturers that produce the equipment and the necessary components have made a big reinforcement that boosted the creation of new colossal projects, such as the SKA. Within this bold project stands this thesis with the intention of establishing a new approach to the implementation of the recent technologies on the design of low noise amplifiers. This work has the objective of filling the need of decreasing the cost of the numerous components that incorporate the reception's systems. The low noise amplifier is inserted on the radiometer which follows the antenna and is the first electronic device reached by the electromagnetic radiation coming from space. The construction's importance of an amplifier that introduces a low level of noise at reduced cost is due to the massive amount of this type of elements that exists on a project of this magnitude. It is also due to the high quality that this device must have to assure the consequent decoding that follows.
A exploração do espaço sempre foi uma ambição do ser humano. Hoje em dia as novas tecnologias aplicadas na área de radioastronomia tornaram possível que esta última meta ficasse cada vez mais atingível. O reforço fornecido pelas grandes empresas que produzem o equipamento e os componentes necessários, impulsionou o avanço de novos projectos grandiosos tais como o SKA. No âmbito deste projecto arrojado apresenta-se esta dissertação com o intuito de estabelecer uma nova aproximação à implementação de recentes tecnologias no desenho de amplificadores de baixo ruído. O enquadramento deste trabalho bem colmatar a necessidade de diminuir o custo dos vários componentes que integram os sistemas de recepção. O amplificador de baixo ruído está inserido no radiómetro, que, após a antena, é o primeiro dispositivo a ser alcançado pela radiação electromagnética proveniente do espaço. A importância da construção de um amplificador que introduza um nível de ruído baixo com um custo reduzido deve-se principalmente à quantidade massiva destes elementos num projecto desta envergadura e à necessidade da sua qualidade ter de ser elevada para garantir a consequente descodificação do sinal recebido.
14
Zhu, Zhineng. "Low Noise Offset Operational Amplifier for Nanopore-based Gene Sequencer." Fogler Library, University of Maine, 2007. http://www.library.umaine.edu/theses/pdf/ZhuZ2007.pdf.
Full text
15
Hossain, Mohammad Billal. "6-9 GHz Low-Noise Amplifier Design and Implementation." Thesis, Linköpings universitet, Fysik och elektroteknik, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79580.
Full textAbstract:
Low-noise amplifier design (LNA) is a critical step when designing a receiver front- end. For the broadband technologies and particularly ultra-wideband (UWB) system, designing the LNA becomes more challenging. This master thesis mainly focuses on the LNA design for the European UWB recommendation, i.e. LNA covering the 6 - 9 GHz spectrum. Moreover, better understandings of the design process in correlation with the implementing of the LNA on a printed circuit board (PCB) were expected. The LNA was manufactured, assembled and measured with network analyzer. This report presents a complete functional design of an UWB LNA.
16
Chakravarthi, Praveen. "Low-noise amplifier design for ultra-wideband OFDM receiver." Ann Arbor, Mich. Proquest, 2005. http://proquest.umi.com/pqdweb?index=0&did=997895751&SrchMode=1&sid=1&Fmt=2&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1188227851&clientId=57025.
Full text
17
Wu, Ching-Kuo, and 吳經國. "Low Noise Amplifier Design." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/97216610304384643214.
Full textAbstract:
碩士國立交通大學
電信研究所
83
A new design approach for matching a low-noise amplifier (LNA) is presented in this thesis. This novel impedance-matching technique will use series matching elements only without shunt elements. On the basis of this unique technique for matching networks, as well as the aid of the conventional Smith chart manipulation and the convenient facilities available from microwave computer-aided design (CAD) program, the design tasks hence can be accomplished easily and efficiently. Five LNA prototypes with different frequency bands and configurations were designed by using this design approach and fabricated practically by the mature microwave integrated circuit (MIC) technique in our laboratory. As compared with the measured data and simulation results, it was shown that the performances of these LNAs can be predicted. Moreover, we designed four monolithic microwave integrated circuits (MMICs) by using the electromagnetic simulator to accurately simulate their components and fabricated them by the mature and well- controlled GaAs fabrication techniques supported by the Hexawave Inc. It indicates that this new coplanar matching approach can be utilized in every area.
18
Chang, Chia Hou, and 張家豪. "UWB Low Noise Amplifier and Distributed Amplifier." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/90922085400609242301.
Full textAbstract:
碩士長庚大學
電子工程學系
99
Abstract This thesis presents the development of RF CMOS circuits for 10-30-GHz UWB (ultra-wide band) transceivers including low noise amplifier and distributed amplifier. For the demands of indoor wireless applications, the CMOS RF receiver is focused on low power consumption, and operated at 10~30-GHz to increase transmission rate. This paper includes low noise amplifier and distributed amplifier. Planning the arrangement of the system, the RF operating frequency is from 10 to 30-GHz, 15 to 25-GHz, and 2.4 to 5.8-GHz. The supply voltage is 1.2V, 0.8V, and 0.65V. In this thesis, the 10~30-GHz high isolation low noise amplifier shows a power gain of 8.105dB and noise figure is smaller than 5.458dB. Both input and output return losses are smaller than -9.036dB and -6.11dB. Power consumption is 19.56mW and chip size is 0.664mm2. The 15~25-GHz variable gain distributed amplifier shows a power gain of 8.212dB and noise figure is smaller than 5.588dB. Both input and output return losses are smaller than -6.004dB and -7.295dB. Power consumption is 12.74mW and chip size is 1.061mm2. Finally the 2.4~5.8-GHz distributed amplifier has a power gain of 11.563dB and noise figure is smaller than 5.862dB. Both input and output return losses are smaller than -6.009dB and -6.178dB. Power consumption is 23.74mW and chip size is 1.789mm2.All of the circuits are designed and simulated by ADS(Advanced Design System) software with TSMC 90 nm 1P9M CMOS process, TSMC 0.18 µm 1P6M CMOS process, and Vanguard 0.25 µm 1P5M CMOS process, respectively.
19
Tsai, Cheng-lung, and 蔡政龍. "Noise Analysis and Low Noise Amplifier Implementation." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/33450042710218931896.
Full textAbstract:
碩士國立雲林科技大學
光學電子工程研究所
95
In this thesis，we employed the TSMC 0.18um CMOS processes and TSMC 0.35um SiGe processes to design and implement the low noise amplifiers. Among these amplifiers, three circuits are suitable for the applications of IEEE 802.15.3a ultra wide band standard. The low noise amplifier is a key component for the front end of receivers. Sufficient gain, low noise, good input and output matching, low power consumption are important performances of a low noise amplifier. The feedback topology is generally used in my design. By this way, gain flatness and input matching can be attained. Especially, the broadband matching is very difficult in the input terminal. Input impedance matching and noise matching are usually trade-off. Though feedback topology decreases the gain, but the intrinsic gain of modern active devices is enough to face the persecution. Another circuit is a 24GHz low noise amplifier, using the common gate topology as the input stage. By the Common Gate Resister Feedback (CGRF) skill, we can suppress noise of the first stage and then overall noise can be lower. In the first chip, a folded-cascode 3-5GHz UWB LNA is designed with feedback technologies to enhance gain flatness. The area of the chip is 1.21 mm × 1.15 mm. In the second chip, a 24GHz LNA is implemented by using three-stage technology. In addition, noise contribution of the first stage is analyzed. The whole area of the chip is 1.08 mm × 0.96 mm. In the third chip, the TSMC 0.35um SiGe processes is used to implement a current-reused LNA. The feedback topology is added to attain the gain flatness. The whole area of the chip is 1.26 mm × 1.18 mm. In the fourth chip, the traditional cascode technology with feedback technology is used to attain the input matching. In addition, the body-biasing technology is used to enhance the MOS tranconductance. The area of the chip is 1.27 mm × 1.12 mm.
20
Li, Cheng-Hung, and 李政鴻. "Noise Decoupling System and Low Noise Amplifier." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57013953093420825203.
Full textAbstract:
碩士臺灣大學
電子工程學研究所
98
Noise usually causes signal distortion, thus degrading the circuit performance. In this thesis we discuss various sources of noise and the models of the substrate and power line at first. Then, a noise decoupling circuit is implemented using the PSC (Powerchip Semiconductor Corp.) high voltage process. The circuit has noise select, noise sources and the noise decoupling system. There are two types of experiments. First, on-chip noise sources are used to generate the internal noise. The magnitude of the substrate noise and power noise are measured with the noise decoupling system activated or deactivated. Then an external noise is applied through bias-T to observe the efficiency of noise suppression. There is about 40% reduction of noise. Secondly, a 5.8G low noise amplifier with an active inductor and noise decoupling system is implemented using 0.35um CMOS process. An active inductor is adopted to reduce chip area and costs. As to noise decoupling, it could reduce the noise figure of the LNA, so the circuit has better performance. The LNA exhibits input matching less than -11 dB, output matching less than -11 dB, 18 dB gain, 2.8 dB noise figure, -4 dBm IIP3, and 25 mW power consumption. Finally, an 8-12 GHz X-band broadband amplifier is implemented using 90 nm CMOS process. On-chip probing is used to measure the performance of the LNA. A shunt-feedback resistor and noise cancellation method are used in the amplifier designed to lower the noise figure. The LNA exhibits input matching less than -10 dB, output matching is less than -10 dB, 11dB gain, 2.5~4 dB noise figure, -7 dBm IIP3, and 8 mW power consumption.
21
WEI-SONG, YEH, and 葉維崧. "Low noise amplifier MMIC design." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/04113032121413601782.
Full textAbstract:
碩士中正理工學院
電機工程研究所
87
The laptop computers and the portable communications excite the development of the products in wireless local area network in recent years. Additionally, MMICs for reducing the cost, size, and weight used in the related products have been prompted by the great advance of semi-conductor technologies. We propose a new approach for the design of MMICs low noise amplifier since it is necessary in the products. GaAs transistors have better noise performances in microwave band than Si transistors. We thus design a GaAs MMIC low noise amplifier to verify the effectiveness of the approach. The traditional design approach is applied in the beginning to obtain suitable matching networks as well as their element values in the light of Smith chart manipulation and the characteristics of devices. The matching networks in MMICs generally include the integrated low Q inductors. The added loss can not be ignored and may be more than that added by FETs. Therefore, after the design of traditional approach, these inductors must be reexamined and adjusted through the noise matching. Two-stage amplifiers operated at 2.4 and 5.7GHz are simulated by SuperCompact. The applied models are obtained, via the help of CIC, from the cell library provided by Haxewave Inc. The noise figures are 2.7dB(2.4GHz) and 3.6dB(5.7GHz) under a single power supply of 4V.
22
Liu, Che-Yuan, and 劉哲源. "A Tunable Low Noise Amplifier." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/ysxn9k.
Full textAbstract:
碩士國立臺北科技大學
電腦與通訊研究所
99
In this thesis, a tunable low noise amplifier is proposed and implemented by Taiwan Semiconductor Manufacturing Company 0.18 μm CMOS process. This amplifier achieves power-saving by current reuse topology, which is suitable for power detection application. Tradeoff between noise and linearity is also optimized through adjusting bias voltage. The performances show that input and output return loss is below -10dB, the gain is 13~15dB, noise figure is 2.95~3.2dB, and IIP3 is -14~-20dBm. It consumes 12mW and occupies 0.97×1.3mm2 silicon area. Besides, an inductorless low noise amplifier with noise cancellation for LTE is discussed as well. Its bandwidth is 900MHz~3.5GHz. Broadband matching and noise reduction can be achieved by resistor feedback topology. Relationship between feedback topology and noise is derived and verified by Mathematica and Cadence Spectre. Simulation results show noise reduction results from feedback configuration instead of noise cancellation. By realizing relationship between noise source and noise figure, design time can be saved.
23
Liu, Sang-En, and 柳頌恩. "MMIC Low Noise Amplifier Design." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/10482949130156822165.
Full textAbstract:
碩士國立交通大學
電信工程研究所
84
A system design approach for designing a multi-stage low noise amplifier is presented. It is based on the conventional Smith chart manipulation and the unique termination technique for matching networks. And it takesadvantages of the facilities available from microwave computer-aided design(CAD) programs, the design tasks hence can be accomplished easily and efficiently. By using this design approach, the peototype of a 1.9 GHz two-stage amplifier(LNA) was designed. We simulate the circuit with models of the cell library provided by Hexawave Inc. . The results for the 1.9 GHz amplifier show a small-signal gain of 15.4dB and Noise Figure of 2.3dB with a 5V power supply while drawing 60mA current. The LNA is now being fabricated by Hexawave Inc. .
24
Chen, Huang-Wei, and 陳皇瑋. "2.4GHz Low noise Amplifier Design." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/73220370919615358757.
Full textAbstract:
碩士崑山科技大學
電子工程研究所
92
In this thesis, 2.4 GHz LNAs (low noise amplifiers) have been proposed and investigated. Three LNAs with different topologies including a cascode LNA, a two-stage cascade LNA, and a current reused LNA have been designed. The process used is a commercially available 0.25 mm CMOS process from TSMC, and furthermore using simulation tool, Agilent EEsof ADS (Advance Design System) 2003a and Ansoft Designer, to simulate and analyze proposed circuits. According to simulation results of three LNAs each with about 10 mW power consumption at the center frequency of 2.4 GHz, noise figures of them are 2.6dB, 2.75 dB, and 2.9 dB, respectively, and moreover, small signal gains of them are 13.3 dB, 19 dB, and 20 dB, respectively. Additionally, measured results of noise figure and small signal gain of the proposed cascode LNA are 2.97 dB and 9.6 dB, respectively. Finally, reasons about deviations between measured results and simulation results have been discussed.
25
SU, RUI-YANG, and 蘇瑞揚. "Broadband Low Noise Amplifier Designs." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/m26v66.
Full textAbstract:
碩士國立高雄師範大學
電子工程學系
106
Abstract This paper mainly designs a wideband low noise amplifier circuit, and performs input matching analysis, noise analysis and gain analysis. It is developed by TSMC 0.18um CMOS process and can be used in the 2.4 GHz band of WiFi 802.11 b/g/n. In addition, an impedance converter (Regulated Cascade) was added to the front end of the LNA for research to reduce the system noise figure (Noise Figure) to improve sensitivity. This study is divided into three parts. The first part of the study is a low noise amplifier with a bandwidth of 05 to 3 GHz, the power consumption is 16.20 mW, an input reflection loss (S11) value of -13.94 dB, and an output reflection loss (S22) value of -18.15 dB, gain (S21) value is 12.28 dB to 8.92 dB, isolation (S12) value is -34 dB, noise index value is 3.4 dB, and at 3 GHz, 1 dB gain compression point (P1dB) is - 18 dBm, third order intercept point (IIP3) is -5 dBm. The second part of the study is a low input impedance converter. The design is based on the need to work with industry and academia and has actually designed an impedance converter. The power consumption is 20.2 mW, the real part of the input impedance is -183.71 Ω, the imaginary part of the output impedance is 67.5 Ω, the input reflection loss (S11) is -1.73 dB, and the output reflection loss (S22) is -7.16 dB. The value of (S21) is -3.52 dB. The third part of the study is also required to match the industry-university cooperation, but the actual design of low input impedance amplifier. The real part of the input impedance is 3.63 Ω, the imaginary part of the output impedance is -3.07 Ω, the input reflection loss (S11) is -9.04 dB, the output reflection loss (S22) is -12.18 dB, and the gain (S21) is 1.48 dB. The noise index value is 4.4 dB.
26
Pond, Jun Xi, and 池俊熙. "Low Voltage Active Inductor Low Noise Amplifier." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/58406392109616402263.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
100
This paper is the use of the active inductor instead of passive inductors to save area, enter the match aspects of the use of the feedback capacitor in parallel with the resistor to achieve matching with the control input voltage, in addition to adjusting the feedback resistor can control the noise. The LNA dissipates 13.2 mW power and achieves input return loss (S11) below -10dB, output return loss (S22) below -10 dB, forward gain (S21) of 11.3~14.5dB, reverse isolation (S12) below -40dB, and noise figure (NF) of 3~3.18 dB. 1-dB compression point (P1dB) of -24 dBm and input third-order inter-modulation point (IIP3) of -14 dBm .
27
Yao, Hu-Kai, and 胡凱堯. "Noise Analysis of Ultra Wideband Low Noise Amplifier." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/48539857582380565023.
Full textAbstract:
碩士中原大學
電子工程研究所
102
In this paper, based on the existing ultra wideband low noise amplifier architecture discussed noise response. Considering the noise source of the main circuit, including resistance thermal noise and MOS thermal Noise, the noise model from the thermal noise generated by these components. The implementation of ultra wideband low noise amplifier circuit equivalent to the noise model circuit, get the most simple noise circuit, in order to facilitate the circuit noise analysis. The ultra wideband low noise amplifier was implemented in TSMC 0.18μm CMOS process. An ultra wideband 2.7 to 10.8 GHz low noise amplifier and the power consumption is 18mW in a 1.8 V power supply. The measured results are: the gain (S21) ranges from 10.5dB-13.4dB, the noise figure (NF) ranges from 3dB-4.64dB, the Input reflection coefficient (S11) under the -5.3dB, the Output reflection coefficient (S22) under the -4.79dB, the 1db Compression Point (P1dB) is -6dBm, the input third-order intercept point (IIP3) is -2.5dBm. The active layout area is 0.419 mm2.
28
Chang, Chia-Feng, and 張嘉峯. "Highly Integrated Bandpass Low Noise Amplifier." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/35v728.
Full textAbstract:
碩士國立中央大學
電機工程學系
103
This study investigates the systematic method in designing a highly-integrated RF front-end system based on the integration of bandpass filter and low-noise amplifier (LNA). The target is to integrate the LNA, balun and band-pass filter into a single circuit. By this integrated design we can improve the mismatch loss of conventional RF front end system, and achieve the goal of circuit miniaturization and improve the level of system integration in RF front-end design. The proposed design is based on the insertion loss method for filter design with complex load, such that the impedance matching network of the LNA can have a band-pass response. The passive parts of the proposed bandpass LNA are realized by a low-loss integrated passive device (IPD) process, while the AVAGO ATF-54143 transistor can be mounted on the IPD chip to achieve integration of bandpass filter and LNA in a single circuit with compact circuit size. Then, a new design of balun bandpass filter is proposed. The selectivity and stopband rejection of balun bandpass filter can be improved by the additional transmission zeros. It is then served as the basis of proposed single-to-balanced bandpass LNA designs. The first design is realized using the IPD process along with the AVAGO VMMK-1218 transistor. The second design is realized by the GaAs pseudomorphic high-eletron mobility transistor (PHEMT) process such that both the active and passive parts of the circuit can be realized on a single chip, and thus a higher level of integration can be achieved. The proposed bandpass LNA designs feature simple design flow with explicit design equations. Their performances are verified using the IPD and GaAs pHEMT process. They can help minimize the circuit size, improving the system performance, and also reduce the complexity of system assembly for RF front-end designs.
29
LIU, WEI-FAN, and 劉偉帆. "Low noise amplifier design and layout." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/562tq5.
Full textAbstract:
碩士明新科技大學
積體電路佈局產業碩士專班
105
Low Noise Amplifier (LNA) has been known as one of the most important part in the RF communication system. It dominates the receiver in the front end and takes control of the noise as RF carrier wave carrying the signals from the air is sensed and amplified. In this study, an optimized LNA circuit is taken into account and the feasible layout for the pre-designed circuit is to be prepared. Before the layout is completed, the process flow is carefully examined and expressed graphically step by step. Ones consider the design rules using 0.18-micron process mainly to reduce the cost and stabilize the process capability. At the same time, minimizing the whole layout area including active and passive devices has been imposed as the cost is more or less important. Of course, the intrinsic noise is planned to be lowered as possible as it can be. Especially,inductors are pretty much concerning because the areas of them are normally much larger. Finally, Design Rule Check and Layout versus SPICE are also implemented to enhance the availability of circuit design and layout design.
30
Chung, Yu-hsuan, and 鍾育軒. "Microwave Bandpass Low Noise Amplifier Design." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/53865597791796090203.
Full textAbstract:
碩士國立中央大學
電機工程研究所
97
Microwave bandpass low noise amplifier design that combines the functions of bandpass filter (BPF) and low noise amplifier (LNA) is proposed in this thesis. It’s believed to have great potential in revising the general receiver structure and largely reducing the circuit area of transceiver by higher level of system integration. In this work, the design of BPF with complex load is applied to the matching network design of an LNA so as to achieve LNA with BPF-like response. In order to verify the effectiveness of proposed design equations and procedure, several bandpass LNAs with bandwidth from 2.3~2.5 GHz are fabricated on microwave laminate. The selectivity and stopband rejection of bandpass LNAs are achieved by bandpass matching network with transmission zeros. Optimum circuit layout is investigated through the comparison of lumped and distributed designs. Specifically, the two-stage cascade distributed bandpass LNA with passband from 2.3 to 2.5 GHz has a noise figure of 1.6±0.14 dB and small signal gain of 25.2±0.7 dB. In addition, the stopband rejection below 1.81 GHz and from 3.12 to 20 GHz are all better than 40 dB. Compared to related previous works, the proposed bandpass LNAs indeed demonstrate features of low noise figure, flat gain and high selectivity. Single chip design of K-Band bandpass LNA is also implemented with GaAs PHEMT process. It can be used for reducing module size of FMCW automobile radar system module by higher level of system integration. The proposed bandpass LNA features simple and explicit design flows. From the measurement results of bandpass LNAs with bandwidth from 2.3~2.5 GHz, design goals are successfully achieved. Although measurement results of K-Band bandpass LNAs using GaAs PHEMT process aren’t in good agreement with simulation results, the possible cause has been found out, which can be applied to the design revision of bandpass LNAs in the future.
31
馮志光. "The 6.5GHz~10GHz Low Noise Amplifier." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/80706314040540327298.
Full textAbstract:
碩士明新科技大學
電子工程研究所
97
The receiver needs low noise amplifiers (LNA) to control the noise issues during amplifying the signals. One uses Advanced Noise System provided by Agilent to design LNA circuits. One also refers to the model of devices produced in TSMC through 0.18μm CMOS process to serve circuit designs. The center working frequencies 6.5 GHz ~ 12 GHz are taken into account. To enhance gains, a lot of work is to be done on impedance matching. In addition, good linearity and low self-interference shall be taken into account, too. Inductor-capacitor tank (LC tank) and inductor-capacitor in series are two main mechanisms for choosing the center working frequencies. Two amplifying units are responsible for the gains. S21’s are above 25 dB and noise figures (NF) are controlled under 2 dB.
32
Huang, Yao-I., and 黃耀毅. "Ultra-widwband CMOS Low Noise Amplifier." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/83811095113637232049.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
94
Ultra-wideband (UWB) radio is a new wireless technology that can be used for high-speed data transmission at low cost with relative power. One of the most critical components in an UWB radio system is the front-end low-noise amplifier (LNA) because it needs to provide low noise figure (~3 dB) and high gain (~20 dB) over a very broad frequency range. It is a new and difficult challenge to design an usable broadband low- noise amplifier for UWB transceiver. This thesis presents the systematic design approaches to realizing a low-noise amplifier over a wide operation frequency range. The resistor shunt-feedback is used to constitute the broadband matching conditions for both noise and gain performance. The network synthesis is an approach of realizing broadband matching network by designing a bandpass filter. The gain compensation technique is applied on the interstage network to provide compensation for the gain roll-off of the active devices. A fully-integrated 3.0-7.5 GHz UWB low-noise amplifier is implemented using UMC 0.18μm CMOS technology. The measured noise figure is lower than 3.8 dB from 3.1 to 7.5 GHz. Operated on a 1.8V supply, the LNA delivers 19dB power gain and dissipates 32mW of power.
33
陳仰鵑. "Broadband Tunable Low Noise Amplifier for." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/37064337693227048632.
Full textAbstract:
碩士國立交通大學
電子工程系所
93
The objective of this thesis is aimed at design of low noise amplifier (LNA) with tunable output frequency for the ultra-wideband (UWB) receiver system using standard 0.18um CMOS process. Three LNA circuits have been implemented. In the first chip, a wideband tunable low noise amplifier is analyzed and designed using the Chebyshev filter design to achieve broadband input impedance matching and a MOS varactor provides frequency tuning capability. The measured data show that the tunable frequency range is from 5.1GHz to 6.8GHz, narrower and lower as compared to the designed values. The frequency drift is due to the inconsistency of the varactor models in the circuit simulator and the circuit layout. Therefore, the second chip is designed to revise the tunable mechanism. The measurement data of the second chip shows that the frequency tunable range is 6.3GHz to 9.3GHz. To extend the tunable frequency range to 3GHz to 8GHz and still maintain the high power gain is limited by the poor quality factor of the large MIM capacitor value. Therefore, the high Q micromachined inductors are integrated with the third chip to achieve the wideband tunable range and good noise performance. Furthermore, power consumption is reduced by an external capacitor placed across the gate and the source ports of the input transistor.
34
Ezhilmaran, Parasuraman, and 伊馬蘭. "RFID Rectifier and Low Noise Amplifier." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/vmf346.
Full textAbstract:
碩士國立交通大學
電機資訊國際學程
106
This thesis investigates two types of works: Low Noise Amplifier at 35GHz and RFID Rectifier at 5.8GHz. Low noise amplifier (LNA) is the main module in any receiver architecture. There are several properties (i.e., noise figure, gain, linearity and low IP3 and so on) to be investigated in LNA design. To meet our requirements, 3-stage Millimeter Wave Inductor Degenerated low noise amplifier was designed in GaAs - 0.15um pHEMT technology to achieve the 17dB gain and 2.6dB noise figure at the 35GHz frequency. The ultra-low power Rectifier plays a vital role to supply the power in many applications such as RFID, Bio-medical and so on. In any rectifier design, most dominant eventual issues are threshold voltage of MOSFET, reverse leakage current and input voltage swing. To overcome these constraints, Adapted In-phase gate boosting rectifier (AIGR) was implemented. In this method, 30 stage rectifier was designed by using TSMC 65nm technology to achieve the higher sensitivity about 260mv at -25dBm RF input power. Moreover, a separate 5.8GHz LTCC based bridge type rectifier with new matching approach was discussed.
35
Lin, Chih-Ming, and 林志民. "Design of C-Band Low Noise Amplifier and Power Amplifier." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/71874483987284061467.
Full textAbstract:
碩士國立成功大學
微電子工程研究所碩博士班
91
This thesis presents the design and implementation of C-band low noise amplifier and power amplifier. In the communication system, low noise amplifier and power amplifier are the key components at the receiving and transmitting end. Due to high data rate requirement, many C-band wireless applications have been proposed and developed. Hybrid MIC ( Microwave Integrated Circuit ) and microstrip-line configuration are employed in this design. Matching networks are realized on the alumina substrates. The low noise amplifier was realized in a housing which was comprised of two MIC low noise modules. In order to achieve minimum noise figure and good input and output VSWR ( Voltage Standing-Wave Ratio ) simultaneously, each module was developed with balanced amplifier configuration using two discrete 300μm GaAs pHEMTs. The module was assembled on a Kovar carrier. It attains 0.9 dB noise figure and 12 dB small signal gain from 5.3 to 5.9 GHz band. The complete amplifier reveals noise figure as low as 0.95 dB with associated gain over 23.5 dB from 5.3 to 5.9 GHz. This low noise amplifier shows excellent noise performance enough for various C-band applications such as high data rate wireless LAN ( Local Area Network ) and ISM ( Industrial, Scientific, and Medical ) applications. The power amplifier was developed using 12 mm GaAs pHEMT device. It delivers over 4 watt of output power from 5.7 to 6.3 GHz band, with 10 dB power gain and 40％ power-added efficiency. The design employed the internally matched FET approach to match the lower input and output impedance of the power device. To achieve optimum power match, we utilized Cripps’s load-line theory to predict optimum output impedance. The complete amplifier was mounted on a CuW carrier. This power amplifier is intended to be used in the transceiver for C-band wireless and satellite communication systems.
36
Li, Chien-Yu, and 李建佑. "Study of W-Band Low Noise Amplifier and Power Amplifier." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/17630200589760249665.
Full textAbstract:
碩士國立暨南國際大學
電機工程學系
103
This thesis aim is to design and implement the W-band low noise amplifiers and W-band power amplifier. The thesis can be divided into three parts： In the first part, a 77~81 GHz low noise amplifier is designed for W-band system. For the sake of reducing chip size and cost, we design a two stage cascade amplifier. In the first stage we use a common source circuit. In order to get sufficient gain, we use a cascode circuit in the second stage. Then we use “T-matching” technique at the input and output term to achieve flat high gain (S21), low noise figure and better “S-Parameter” performances. Finally, we put bypass capacitances at the ”VDD” and “VGS” term to make our circuit more stable. The second part is on the design and implement of a high added efficiency power amplifier for 79GHz applications in 90nm CMOS technology. In this circuit, we used the cascade-stage structure as first stages to eliminate the Miller effect and improve the reverse isolation. But linearity and power consumption are worse than common source stage. Therefore, the second stage is using common source topology. In the cause of improving the output power and power added efficiency, we use the power divider/combiner to implement final stage. In the third part, a 94 GHz low noise amplifier is implemented for the weather radar system. In order to obtain the high gain and wide bandwidth, we used three common source and conjugate matching techniques between interstage. We design a high gain, wideband and low noise LNA in TSMC 90 nm CMOS technology. The experimental results showed that the 3 dB bandwidth of 8 GHz, flat gain of 14.1±1.5 dB and power consuming of 7.22 mW and figure of merit (FOM) is 1.22, this results show that this LNA is suitable for weather radar systems. In final, a wideband low noise amplifier is implemented. Input and Output have wideband matching. It can be applied to 77~81 GHz automotive radar and 94 GHz cloud radar instrumentation. In addition, its P1dB and IIP3 have improved.
37
HSIEH, MING-HSIANG, and 謝明翔. "Implementation of 60GHz Power Amplifier and Low Noise Amplifier Modules." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/05263176840739628845.
Full textAbstract:
碩士中華大學
電機工程學系
105
60GHz commercial power amplifier or low noise amplifier currently available on the market are mostly in bare DIE form rather than in IC package. This type of IC is more difficult for mmWave system integration. This thesis was focused on three different interconnection methods including Wire Bonding, Flip-Chip and Ribbon Bonding for DIE to PCB. We also design the matching circuit for amplifier system optimization and propose a cheaper system integration structure to ensure that IC in mmWave frequency characteristics and performance are improved. Keywords:60GHz,power amplifier,low noise amplifier,DIE,Interconnection,Wire Bonding,Flip-Chip,Ribbon Bonding,matching circuit.
38
Huang, Chien-Tsung, and 黃乾宗. "Low Noise Amplifier and Programmable Gain Amplifier for DVB-T." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/72340233050754811300.
Full textAbstract:
碩士臺灣大學
電子工程學研究所
96
This thesis is focused on a wideband low noise amplifier and a programmable gain amplifier for DVB-T fabricated with TSMC 0.18μm CMOS process. The wideband low noise amplifier is designed by the resistor feedback technique. It is divided into two stages. The first stage is designed by current-reuse topology to improve gain and to reduce power consumption. There is good input matching in the first step by choosing an appropriate resistor of the feedback resistors. The second stage is designed to increase the whole amplifier gain. It is also designed by the resistor feedback method to improve bandwidth performance. It uses a PMOS device which operates in linear region to provide a good output impedance matching. According to the measurement results, the amplifier gain is 21.5dB to 21.8dB. It simply varies 0.3dB in the bandwidth. S11 is smaller than -12.7dB. S22 is smaller than -12dB. NF is 3dB~4.7dB. And IIP3 is -5dBm~-5.6dBm in the bandwidth. The operating frequency of the programmable gain amplifier is 50MHz to 860MHz. The structure of the amplifier is differential. And it is divided into two stages. The first stage is designed by current-reuse topology to improve gain and to reduce power consumption. It is also designed by the resistor feedback technique to improve bandwidth. By changing feedback resistors, it can change gain value. The topology of the output buffer is common drain. And it provides a good output impedance matching at the second stage. And using the current source of the second stage and the amplifier of the first stage achieves the thermal noise canceling result. Based on the measured results, the gain is -6dB to 14dB with 1dB gain step. S11 is smaller than -8dB. S22 is smaller than -8.5dB. NF is 6.5dB~8.5dB when the gain is 14dB. IIP3 is -8dBm when the gain is 14dB and IIP3 is 8dBm when the gain is -6dB.
39
Chung, Chi-Kuei, and 鍾繼逵. "A New Low-Voltage Low-Power Wideband Low Noise Amplifier." Thesis, 2015. http://ndltd.ncl.edu.tw/cgi-bin/gs32/gsweb.cgi/login?o=dnclcdr&s=id=%22103MIT00442020%22.&searchmode=basic.
Full textAbstract:
碩士明志科技大學
電機工程系碩士班
103
This thesis presents a 0.1GHz to 3.5GHz wideband low noise amplifier (LNA). This circuit can be used in Long Term Evolution (LTE) and Global System for Mobile Communications (GSM) / General Packet Radio Service (GPRS) wireless communication system, the low noise amplifier circuit mainly utilizes feedback, current-reused and common source (CS) architecture to composition. In this thesis we use inductive peaking technology to improve the gain flatness of the circuit, and use the current-reused technology to improve the circuit gain and reduce the power consumption. In this thesis, we use the 0.18μm processing parameters of TSMC CMOS to design the circuit, in this design of wideband low noise amplifier circuit the supply voltage is 1V, power consumption is 8mW, in 0.1GHz to 3.5GHz bandwidth can offer 16.5dB ~ 23.5dB of gain (S21), below -7.4dB of input return loss (S11), and the noise figures (NF) is less than 5.5dB, as well as input third order intercept point (IIP3) is -7dBm. In this thesis, we particularly focus on the analog integrated circuit layout. Due to the integrated circuit layout must consider many element, such as matching、noise shielding、latch-up、reduce etch effect、ESD, etc. The integrated circuits layout is the most important stages for analog IC, which can be highly result to the wafer success or not.
40
Yu, Yueh-Hua, and 游岳華. "An Ultra-Low Voltage Ultra-wideband Low Noise Amplifier." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/09314893507941438880.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
94
This thesis presents an ultra-low voltage low noise amplifier for ultra-wide band application in UMC 0.18um 1P6M CMOS technology. Using the architecture of distributed amplifier with the inductive source degeneration, the LNA is demonstrated to achieve broadband and low noise. The common-source single-stage amplifier is cascaded to the conventional distributed amplifier to improve the gain at high frequency. Excellent noise performance of LNA is obtained by applying suitable source degeneration inductance and selecting proper device geometry and bias. The measured gain of the fully-integrated LNA is 10dB with the 3dB bandwidth from 2.7 to 9.1 GHz. The input and output return-losses are more than 10dB within the 3dB-band. The average noise figure is 4.65dB. The measured IIP3 at 6GHz is 0dBm. Operated at 0.6V, the UWB CMOS LNA consumes 7mW.
41
Kuo, Chun-Liang, and 郭俊良. "The Design of CMOS Low-Voltage Low Noise Amplifier." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/56317704058809678921.
Full textAbstract:
碩士國立雲林科技大學
電子與資訊工程研究所
95
In this thesis, we design a CMOS cascode low-noise amplifier for use in the front-end of a global positioning system (GPS) receiver. The CMOS cascode low-noise amplifier at 1.575GHz were design and implementated in a standard TSMC 0.18μm CMOS process, and we simulate the proposed circuit by Agilent Advance Design System (ADS). The design of the low noise amplifiers, we use the single-stage cascode architecture, which exhibits the lower power dissipation and higher gain, and given by Professor Thomas Lee’s method, inductive source degeneration is used to match the input impedance while providing better noise figure. The simulation results for the cascode low noise amplifier at 1.575GHz are as follows: input and output return losses are -37.5dB and -29.2dB, respectively, gain is 17.7dB, noise figure is 2.3dB, P1dB(output) is -3.2dBm and the IP3(output) is 12.4dBm. Designed in 1.5-V supply, its power consumption is about 5mW.
42
Du, Jhih-Huei, and 杜志輝. "Design of Low Voltage Dual-Wideband Low Noise Amplifier." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/82140360685402294650.
Full textAbstract:
碩士雲林科技大學
電子與資訊工程研究所
97
This thesis presents the research and implement on low noise amplifier for Ultra wide band and IEEE 802.11a WLAN。The chips are fabricated by TSMC 0.18um CMOS process. The efficiency of the circuit was demonstrated by measurement. In first chip, I utilize the principle of Multiple-gated transistors to design a low noise amplifier for IEEE 802.11a application. Measurement results at 5.8GHz is shown that gain of 9.4dB, noise figure (NF) of 4.9dB, S11 of -11dB, and S22 of about -12dB with the DC power dissipation 5.6mW under 1.8V power supply. The IIP3 improvement is from -3dBm to 1dBm. In second chip, we utilize the principle of current-reused and notch filter to design a low noise amplifier for UWB application. The minimum noise figure is 5 dB and maximum gain is 15dB from 3 to 12 GHz while drawing 5.6mW from a 1V supply voltage. The input and output return loss are both better than -10dB, isolation better than -39dB, respectively. The input third-order intercept point IIP3 is -7dBm.
43
LeeGuan-Sung and 李冠松. "2.4/5.2GHz Dual Band Low Noise Amplifier." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/03040422447529025963.
Full textAbstract:
碩士崑山科技大學
電子工程研究所
93
The multi-mode receiver system has been widely used in the wireless communication field. Therefore, the development of dual-band devices is especially important. The wireless products with the smaller size, lower power consumption, lower cost and high integration are the major stream of the current market. Hence, it has become an inevitable trend to use the CMOS technologies to implement the RF transceivers. In this thesis, we have studied the techniques of design and implementation of the dual- band LNAs which are applied to the WLAN systems. The dual-band LNAs enable concurrent support for 2.4GHz (IEEE802.11b) and 5GHz (IEEE802.11a) WLAN systems. We have successfully designed three different structures of dual-band LNA in this thesis. They are one low voltage dual-band LNA, one variable gain dual-band LNA and one folded cascode dual-band LNA, respectively. The supply voltage for the low voltage dual-band and folded cascode dual-band LNAs can be reduced, and is as long as half that for the traditional cascade LNA. On receiving a higher-power signal, the low gain mode of the variable gain dual-band LNA can be enabled to obtain the better linearity. The studied circuits have been designed under the TSMC 0.18um CMOS processes. These Chips have also been fabricated by the support of CIC in Taiwan.
44
Hsu, Wen-Chiu, and 許文秋. "Design and Implementation of Low Noise Amplifier." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/40073724039356873205.
Full textAbstract:
碩士龍華科技大學
電子系碩士班
93
The low-noise amplifier (LNA) becomes the quite important implementation of front-ended circuit in a communication system. It provides enough gain and minimized noise figure, and then determines the sensitivity and noise figure of the transceiver. This thesis uses TSMC 0.18μm 1P6M CMOS process’s RF model to design the low-noise amplifiers which are applied on the 802.11a/b/g wireless LAN (WLAN). The low-cost and high-integration CMOS techniques are used to design these monolithic microwave integrated circuits (MMICs). To obtain lower power dissipation, large linearity and better isolation ,we use the cascade configuration to design the LNA In this thesis, we deal with three kinds of LNAs. First, we design a 5.25GHz single-ended cascode configuration with source degeneration. Second, we design a 5.25GHz differential cascode configuration by using a pair of matching single-ended stages with a common current mirror. Due to virtual ground of the differential pair, we obtain a very large CMRR and even-order harmonic cancellation. At last, we design a 2.45GHz and 5.25GHz dual band low noise amplifier with image rejection. Since this LNA realize dual band by way of a single cascade circuit and image rejection without back-staged filter, the area can be reduced and the cost is save.
45
Liao, Wen-Yu, and 廖文裕. "The Study of CMOS Low Noise Amplifier." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/23994670211140243225.
Full text
46
Syu, Jain-Yang, and 許建揚. "Design of Ultra Wideband Low-Noise Amplifier." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/78m6cu.
Full textAbstract:
碩士國立臺北科技大學
電腦與通訊研究所
102
Thesis research can be divided into two parts. The first part introduces that design of a low supply voltage, low power of 0.18-μm CMOS ultra wideband (UWB) low noise amplifier (LNA). Employing the common-source configuration with the RC negative feedback and source degeneration of three-stage cascade circuit to achieve an amplifier is applied for ultra wideband system. Simulation results about high gain of 25.04dB and low noise figure of 2.9dB. Moreover, the transistor works in low supply voltage of 0.3V that it can reduce the drain current to achieve the low DC power consumption of 3.7mW. The second part introduce the design of 0.18-μm CMOS UWB LNA with notch filter to reject the specific bandwidth while you not need, and it can reduce the signal interference of the transceiver. Then, design of the notch filter implemented by the passive circuit with the inductor and the capacitor series. The inductance is replaced by active inductor, and characteristic of active inductor is high quality factor to achieve a highly selective passive band reject filter. The capacitance is replaced by varactor, and characteristic of varactor can change the capacitance by voltage to achieve the notch filter of the rejection frequency adjusted.
47
Lai, Wei-ni, and 賴韋霓. "Investigation of Dual-band Low Noise Amplifier." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/51502515087842488218.
Full text
48
JIN, JSI-JIE, and 金施杰. "The design of low-noise operational amplifier." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/37528801721313129099.
Full text
49
Chang, Wan-Ci, and 張萬賜. "Simulation of Balanced Microwave Low Noise Amplifier." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/01515176544730214770.
Full textAbstract:
碩士國立海洋大學
電子工程學系
82
Recently, the balanced amplifier is usually used as the circuit configuration in the design of broadband microwave amplifier. The main advantages of the circuit configuration include the flat gain,low input and output voltage standing-wave ratio and high reliability. In the balanced amplifier, two identical couplers are used as the power divider and power combiner, re- spectively. In this thesis, the characteristics of the Lange, traditional and improved branch couplers are analyzed and simulated firstly. Secondly, under the consideration of low noise, the single-ended amplifier is designed, the characteristics of microwave device are analyzed through the plot of constant gain and noise figure circles. Finally, the circuit configuration and characteristics of the balanced microwave low noise amplifier are studied, and the practical circuit layout is completed.
50
簡偉翔. "Low Noise Amplifier Design for Ultrawideband Receivers." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/78865416813790009259.
Full text