Dissertations / Theses on the topic 'LOW NOISE ADC'

Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 1994.
"December 1994." Thesis advisor(s): Phillip E. Pace, Douglas J. Fouts. Bibliography: p. 103. Also available online.

A low-noise, variable gain amplier chain was constructed for interfa-cing a sensor to an ADC. During the course of the work two dierent methods -switched-capacitor circuits and chopping circuits - for dealing with 1/f noise wereinvestigated during the course of the work. The resulting circuit did not quitemeet the performance required by the specication, some possible improvementsare suggested.

This thesis presents a study of impedance optimisation of active microstrip patch antennas to multiple frequency points. A single layered aperture coupled microstrip patch antenna has been optimised to match the source reflection coefficient of a transistor in designing an active antenna. The active aperture coupled microstrip patch antenna was optimised to satisfy Global Positioning System (GPS) frequency specifications. A rudimentary aperture coupled microstrip patch antenna consists of a rectangular antenna element etched on the top surface of two dielectric substrates. The substrates are separated by a ground plane and a microstrip feed is etched on the bottom surface. A rectangular aperture in the ground plane provides coupling between the feed and the antenna element. This type of antenna, which conveniently isolates any circuit at the feed from the antenna element, is suitable for integrated circuit design and is simple to fabricate. An active antenna design directly couples an antenna to an active device, therefore saving real estate and power. This thesis focuses on designing an aperture coupled patch antenna directly coupled to a low noise amplifier as part of the front end of a GPS receiver. In this work an in-house software package, dubbed ACP by its creator Dr Rod Waterhouse, for calculating aperture coupled microstrip patch antenna performance parameters was linked to HP-EEsof, a microwave computer aided design and simulation package by Hewlett-Packard. An ANSI C module in HP-EEsof was written to bind the two packages. This process affords the client the benefit of powerful analysis tools offered in HP-EEsof and the fast analysis of ACP for seamless system design. Moreover, the optimisation algorithms in HP-EEsof were employed to investigate which algorithms are best suited for optimising patch antennas. The active antenna design presented in this study evades an input matching network, which is accomplished by designing the antenna to represent the desired source termination of a transistor. It has been demonstrated that a dual-band microstrip patch antenna can be successfully designed to match the source reflection coefficient, avoiding the need to insert a matching network. Maximum power transfer in electrical circuits is accomplished by matching the impedance between entities, which is generally acheived with the use of a matching network. Passive matching networks employed in amplifier design generally consist of discrete components up to the low GHz frequency range or distributed elements at greater frequencies. The source termination for a low noise amplifier will greatly influence its noise, gain and linearity which is controlled by designing a suitable input matching network. Ten diverse search methods offered in HP-EEsof were used to optimise an active aperture coupled microstrip patch antenna. This study has shown that the algorithms based on the randomised search techniques and the Genetic algorithm provide the most robust performance. The optimisation results were used to design an active dual-band antenna.

碩士
國立臺北科技大學
電資碩士班
97
Due to the portable computer, communication, and consuming electronic grew up extensively. In the application of the display and wireless communication ,as to the low power, and high speed, that the interface circuit of analog to digit converter has indispensable demands. The pipelined analog to digital converter is a better choice at present which has high speed conversion ratio and high resolution for the analog to digital converter. The main structure used the 9 stages pipelined ADC. In this thesis the 10 bits pipelined ADC is composed of the first 8 stages which each stage 1.5 bit and the last stage that has 2 bit. In order to get low power, high speed, and high resolution , each stage used the dual channel 1.5bit Flash ADC. Because of the 1.5bit flash ADC have high-speed operation advantage and the dual channel structure can decrease the power consumption and reduce the noise when it work in positive and negative duty cycle respectively. We descript the basic principle of pipelined analog to digital converter and realize from designing to the circuit. We adopt the TSMC 0.18 μm CMOS technology to simulation the circuit of system and implement it. the core area is about 0.6 1.47 mm2, and the power consumption is about 21.6mW. If the bandwidth of the input signal is 44.1 kHz sine wave, we obtain the 41.5 dB peak signal to noise and distortion ratio, and simulation results ENOB=6.6 bits.

The information extracted from the bio-potential signals such as ECG, EEG, ECoG, ERG and ENG is extensively used for health care and medical treatment purposes. The use of bio-potential acquisition systems is not only limited to the hospitals but also extended to the homes for ubiquitous health care. Therefor the demand of portable bio-signal measurement system is increasing. The key constituent to this kind of systems is the analog front-end (AFE). The analog readout front-end extracts the bio-signals directly from human body through electrodes and defines the extracted signal quality. The most critical block in an bio-potential acquisition system is the AFE as it is connected directly to the human body and the output this should be ready to feed the subsequent stages that are ADCs and DSPs. This block must operate under low power consumption with minimal added noise to ensure the better signal quality with enhanced battery life, when incorporated in portable bio-signal acquisition systems. In this dissertation a novel multi-function Analog Front-End is proposed. This analog readout front end is oriented to be employed in flexible and portable bio-potential signal acquisition systems. The essential contribution of this work is the new Forward Body Biased Current Mode Amplifier (FBBCMA) based on convention forward body biased technique for low-voltage operation. The proposed FBBCMA achieves very low noise performance because of inherent properties of current mode topology. Forward body biasing of MOS devices further reduces the flicker noise that is a critical concern in circuits operating at low frequencies. Low power consumption and other advantages are achieved by the aid of the forward body biasing and current mode topology. A complete analog readout front end is implemented and simulated using the standard TSMC 180nm parameters and P-Spice as simulator. This AFE consist of a pre amplifier followed by a band pass filter to enhance in band signals and reject the signals that are laying out of the band of interest. Tuneable bandwidth of AFE enables it to serve as the first stage in variety of bio-signal acquisition systems. The simulation results show that the designed circuits meet the basic requirements of the low power consumption under low noise operation for long time portable bio-potential recorders.

碩士
淡江大學
電機工程學系
84
The new design of a switched-capacitor(SC) delta-sigma modulator(DSM) is proposed. Generally speaking, the performance of a DSM is degraded due to theop-amp gain and clock feedthrough noise, and the right or error of chargetrnsfering between capcitors. The SC integrator is the main architecture ofa DSM, therefor, the performance of the SC integrator decides the performanceof DSM. The finite op-amp gain causes the inverting input of the op-amp notto the virture ground. If the op-amp gain is high enough that makes the voltageof inverting inputs of the op-amp approach zero, the performance of the DSM orSC integrator will be good. However, the op-amp with high gain, about 90dB, isvery difficult to design, so the performace of the DSM is poor if the op-ampwith low gain is used. Clock feedthrough noise and charge transfering areanother important nonideal properties for DSM and SC integrator.The chargetransfer depends on switches in DSM and switchs are controled by the clock.Sometime the clock feedthrough noise is caused by the clock signal is mixedwith the input signal and makes the output performance be reduced and DSM evencause error. The charge is stored in capacitors in a DSM and transfers chargeto another capacitors in the next phase, in case that is in error then it willmake the output performance degrade and even cause error.In this thesis, a new design of DSM is proposed to overcome the three nonideal properties as mentioned. We design a DSM by using a finite gain(about 60dB) and it achieves the same performance as a 100dB-gain op-amp does. Thisalso reduces the clock feedthrough noise and makes charge transfering betweencapacitors more exactly.

碩士
國立中央大學
電機工程學系
104
Recent years, long-term care or digital personal healthcare secretary is necessary. By improving the multi-purpose of biomedical instruments, reliability and reducing power consumption, equipment size and cost are conducive to today's society. Therefore, this thesis will present a biomedical circuit design and describe how to achieve simplification, miniaturization, low power consumption, multi-purpose and high reliability. Finally hope this research will make everyone be better. This thesis consists of two parts, the first part introduces our research about biomedical analog front-end low-noise amplifier (LNA), which has operational bandwidth of 5 KHz, covering the EEG, ECG and other bio-signals. The CCIA architecture is used to block DC offset from electrode, taking the high impedance of Pseudo-Resistor to achieve miniaturization and extremely low frequency pole. Moreover, the current-reusing technique is used to maintain low power consumption and keep flicker noise and thermal noise to lower level. Behind the main block LNA, a programmable gain amplifier (PGA) is used. Hence not just only one bio-signal can be measured, but a variety of bio-signals measured can be applied. In the second part, the successive approximation analog-to-digital converter (SAR ADC) is introduced which can meet the low-power consumption requirement. The function of SAR ADCs is converting the LNA analog signal to digital signal. The main idea of SAR ADCs is Monotonic Capacitor Switching Procedure which can effectively reduce energy loss to 19% of conventional architecture. On the other hand, by using monotonic switching procedure which can directly compare MSB, the overall capacitance array occupies only half of the conventional architecture, which can greatly reduce the chip area. The bootstrapped-switch is used to make input signal and sampling switch independent. The Ron of sampling switch will be fixed and make the S/H achieving high linearity. The main part of SAR ADCs is comparator. In this research the dynamic comparator is better for our research. Because the dynamic comparator only works in the conversion phase, by doing so the static power consumption can be saved. Our design achieves a 10-bit SAR ADC, the primary consideration of SAR ADCs design is low power requirement. These circuits are designed in TSMC 0.18 μm CMOS 1P6M process. The first circuit is LNA, when input signal frequency is 250 Hz and 1 kHz, 500 μV input amplitude, the mid-band gain of analog front-end low-noise amplifier can be programmed from 35.917 dB to 53.979 dB. The post layout simulation shows that the input-referred noise is 1.811 μV rms, the Noise efficiency factor (NEF) is 1.39, the chip area (including ESD PAD) is 1.322 mm2, the overall chip consumes 2.19 μW. The second circuit is the SAR. When input signal frequency is 250 Hz and input amplitude 250mV, ENOB is 9.638 bits, SNDR is 60.1969 dB, the overall merit FOM is 0.55 pJ per conversion-step, the chip area (including ESD PAD) is 1.33 mm2, the overall chip consumes 2.602 μW.

碩士
國立中央大學
電機工程學系
105
With the increment of average age of people, various bio-medical wearable devices have been launched, especially for the elders. Therefore, how to reduce the power consumption and area to achieve the portability as well as the long battery life-time requirements are demands of this thesis. This thesis consists of three parts, the first part designs a continuous-time delta-sigma modulator (CTDSM) for bio-medical application to ease the requirements of hardware rather than discrete-time DSM using an OPA to achieve the second-order integration. Besides, the current-reusing technique is used to maintain flicker noise and thermal noise to lower level and to keep low power consumption. In the second part, a bandgap voltage reference (BGR) is introduced to meet low-noise and low supply voltage requirements. It can provide a stale voltage reference without the variation of temperature for feedback reference of DSM and other sub-circuits. Third, the drawback of a CTDSM is the dependence on the variation of environment temperature and process. Therefore, the RC Time-Constant Calibration method is proposed for detecting and compensating the variation of RC time-constant. Finally, by introducing a decimation, we integrate all sub-circuits to a complete continuous-time delta-sigma ADC. Designs in this thesis are fabricated in the UMC 0.18 μm 1P6M CMOS process. In order to pursue low-power consumption, the supply voltage is all set up as low as 1.2 V. First, the measurement of CTDSM achieves 78.42 dB SNDR, 12.73 bits ENOB, and power consumption 15.97 μW at 10 kHz signal bandwidth with X128 OSR, 0.6 Vp-p amplitude and chip area is 0.67mm*0.56mm, including PAD and seal-ring. Second, BGR generates a stable 0.6 V voltage reference which is tunable with flicker and thermal noise 0.496nV^2/(0.1~10 kHz) in the bandwidth for 17.3 μW. Finally, the simulation of the complete CT delta-sigma ADC achieves 81.31 dB SNDR, 13.21 bits ENOB, and power consumption 71.82 μW, including CTDSM, BGR, RC Time-Constant Calibration and buffers. The whole chip area is 1.74mm*1.11mm, including PAD and seal-ring.

About 50 million people worldwide suffer from epilepsy and one third of them have seizures that are refractory to medication. In the past few decades, deep brain stimulation (DBS) has been explored by researchers and physicians as a promising way to control and treat epileptic seizures. To make the DBS therapy more efficient and effective, the feedback loop for titrating therapy is required. It means the implantable DBS devices should be smart enough to sense the brain signals and then adjust the stimulation parameters adaptively. This research proposes a signal-sensing channel configurable to various neural applications, which is a vital part for a future closed-loop epileptic seizure stimulation system. This doctoral study has two main contributions, 1) a micropower low-noise neural front-end circuit, and 2) a low-power configurable neural recording system for both neural action-potential (AP) and fast-ripple (FR) signals. The neural front end consists of a preamplifier followed by a bandpass filter (BPF). This design focuses on improving the noise-power efficiency of the preamplifier and the power/pole merit of the BPF at ultra-low power consumption. In measurement, the preamplifier exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of bandwidth (BW), 5.86-μVrms input-referred noise in AP mode, while showing 39.4-dB DC gain, 0.36 Hz to 1.3 kHz of BW, 3.07-μVrms noise in FR mode. The preamplifier achieves noise efficiency factor (NEF) of 2.93 and 3.09 for AP and FR modes, respectively. The preamplifier power consumption is 2.4 μW from 2.8 V for both modes. The 6th-order follow-the-leader feedback elliptic BPF passes FR signals and provides -110 dB/decade attenuation to out-of-band interferers. It consumes 2.1 μW from 2.8 V (or 0.35 μW/pole) and is one of the most power-efficient high-order active filters reported to date. The complete front-end circuit achieves a mid-band gain of 38.5 dB, a BW from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. The power efficiency of the complete front-end is 0.75 μW/pole. The chip is implemented in a standard 0.6-μm CMOS process with a die area of 0.45 mm^2. The neural recording system incorporates the front-end circuit and a sigma-delta analog-to-digital converter (ADC). The ADC has scalable BW and power consumption for digitizing both AP and FR signals captured by the front end. Various design techniques are applied to the improvement of power and area efficiency for the ADC. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-μm CMOS process. The die size is 11.25 mm^2. The proposed circuits can be extended to a multi-channel system, with the ADC shared by all channels, as the sensing part of a future closed-loop DBS system for the treatment of intractable epilepsy.

Tese de mestrado integrado, Engenharia Física, Universidade de Lisboa, Faculdade de Ciências, 2019
O sistema atual de distribuição de alta tensão do calorímetro hadrónico central da experiência ATLAS do CERN, TileCal, foi fabricado no final dos anos 90. Este foi projectado para estar em funcionamento durante 10 anos, no entanto jáa se encontra em funcionamento há cerca de 20 anos. Atualmente, muitos dos componentes utilizados encontram-se obsoletos o que impossibilita a sua reparação e reutilização. Por outro lado, o sistema atual encontra-se no interior da caverna ATLAS, logo encontra-se exposto a altos níveis de radiação. Esta exposição contínua a altos níveis de radiação resultantes das colisões entre os feixes de partículas, que ocorrem no LHC (Large Hadron Collider), afeta todo o sistema. O facto de o sistema se encontrar na caverna suscita ainda outros problemas, tais como, a dificuldade de reparar ou mesmo substituir qualquer componente ou placa constituinte do sistema eletrónico, danificado pela radiação ou devido ao envelhecimento eletrónico. Para se efetuar a reparação ou a substituição de componentes ou placas é necessário que o LHC pare o seu funcionamento durante alguns meses, de modo a que os níveis de radiação diminuam o suficiente para permitir que um técnico possa entrar na caverna, porém esta pausa de meses só oferece um tempo muito limitado para executar esta tarefa. Para além destes problemas tem-se ainda como um dos objetivos o aumento da luminosidade do LHC, o que vai implicar um aumento do nível de radiação na caverna ATLAS. Outro dos objetivos, é a diminuição do intervalo de tempo entre as colisões de partículas, levando à necessidade de electrónica mais rápida. Todos estes problemas e novos objetivos fazem com que seja necessário atualizar e/ou modificar toda a electrónica do TileCal. De forma a superar estes problemas, foi proposta uma actualização: um novo sistema de distribuição de alta tensão (HVDS) será colocado fora da caverna onde se encontra o detetor, passando este a ser um sistema remoto que não é afetado pela radiação, maximizando assim a fiabilidade e a robustez do sistema. A eletrónica deste novo sistema será colocada numa sala sem radiação, localizada 100 metros acima da caverna ATLAS, o que permitirá o acesso permanente ao sistema de distribuição de altas tensões. Assim, deixa de ser necessária a existência de uma paragem do funcionamento do LHC para executar reparações no sistema. Outra vantagem inerente ao sistema remoto é deixar de haver uma limitação de tempo disponível para realizar as reparações e/ou substituições, diminuindo também o risco a que o técnico está sujeito quando as executa. Para este novo sistema é necessário produzir uma placa dedicada que forneça as alimentações primárias necessárias, alta e baixa tensão, dado que no sistema atual as fontes de alimentação primárias de baixa tensão encontram-se na caverna ATLAS e as de alta tensão embora se encontrem na sala sem radiação já referida são fontes lineares de elevado custo. O trabalho apresentado nesta dissertação insere-se na colaboração portuguesa no projeto ATLAS/CERN. Este consiste no desenvolvimento de uma placa de alimentação, designada por Power Supplies, capaz de fornecer tanto a alta tensão (HV), - 830 V a -950 V, como as baixas tensões ,±12 V e 3; 3 V, sendo imperativo que todas as tensões produzidas tenham baixo ruído. Para produzir estas tensões recorreu-se à utilização de quatro conversores DC/DC, sendo que dois dos conversores DC/DC são utilizados para produzir a alta tensão, -830 V a -950 V @ 10 mA, e os restantes dois para as baixas tensões, um para os 3:3 V @ 0:8 A, e o outro que é um conversor DC/DC duplo para os ±12 @ 2:5 A. Cada HVDS fornece a alimentação para 48 fotomultiplicadores (PMTs) do detetor. Devido à corrente necessária para alimentar todos os PMTs, é necessário recorrer ao uso de dois conversores DC/DC para produzir a alta tensão. Os valores da tensão de saída dos conversores DC/DC de alta tensão são controlados digitalmente, podendo fornecer dois valores diferentes, -830 V ou -950 V. Estes valores de tensão distintos permitem que cada PMT do detetor possa receber a tensão adequada para funcionar corretamente. Dado que não existe um único componente que seja igual a outro, cada PMT terá as suas características próprias e, portanto, a sua tensão de alimentação deve ser ajustada para se obter o melhor desempenho do detetor. Estes dois valores de tensão permitem a correta calibração de todos os PMTs efetuada pelo sistema de distribuição das altas tensões. A placa que fornecerá as alimentações ao HVDS, deverá ainda oferecer algumas funcionalidades extra, tais como: a possibilidade de uma monitorização em tempo real do consumo em tensão e corrente de cada conversor, a leitura da temperatura em dois pontos diferentes da placa, a capacidade de ligar/desligar digitalmente cada um conversores DC/DC individualmente e ligar/desligar manualmente todos os conversores DC/DC ao mesmo tempo, através de um interruptor. Este último serviáa como medida de segurança caso o método digital não funcione ou em caso de substituição ou manutenção do sistema sem necessidade de recorrer ao sistema de controlo digital do ATLAS. O controlo digital da placa Power Supplies será baseado num protocolo de comunicação SPI e num expansor série/paralelo. Os sinais de saída do referido expansor serão os sinais para ligar/desligar os conversores, os sinais de seleção de tensão de saída dos conversores de alta tensão e os sinais que permitem a leitura adequada e em tempo real dos consumos de tensão e de corrente e dos sensores de temperatura utilizados. Estas leituras são efetuadas recorrendo ao controlo digital de um multiplexador analógico e a um conversor analógico digital (ADC). Ainda no âmbito desta tese, à apresentada a interface gráfica de utilizador (GUI) desenvolvida na linguagem de programação Python. Esta foi utilizada para facilitar a comunicação entre a placa Power Supplies e o utilizador. A interface gráfica está dividida em três secções diferentes, de forma a ser mais intuitiva para o utilizador. A primeira secção é a secção responsável por ligar/desligar os conversores DC/DC, sendo que esta apresenta quatro caixas de seleção, uma para cada conversor, que quando selecionadas pelo utilizador, executam o código responsável por enviar a instrução ao expansor para enviar o sinal de ligar/desligar para os conversores DC/DC selecionados. Na segunda secção encontram-se representadas duas barras deslizantes, às quais se encontra associado um cursor que se pode deslocar entre duas posições distintas, associadas à selecção da tensão de saída de cada um dos conversores DC/DC de alta tensão. Associada à posição do cursor encontra-se também um texto informativo que permite que o utilizador verifique se a tensão seleccionada é a pretendida. A terceira e última secção é a da leitura dos consumos de tensão e de corrente assim como das duas temperaturas lidas por dois sensores de temperatura colocados em pontos distintos da carta. Esta leitura pode ser feita de duas formas diferentes, pode ser feita uma única medida através da seleção de botões dedicados que apenas permitem selecionar uma opção de cada vez, sendo o resultado da leitura apresentado em duas caixas. A primeira caixa com a leitura em contagens do ADC, que é o valor que o ADC fornece diretamente, e a segunda caixa com a leitura do valor correspondente ao que se está efetivamente a medir com a respetiva unidade física. A outra forma envolve um conjunto várias medições contínuas de uma das grandezas anteriormente referidas, sendo que o utilizador pode escolher o número de medições pretendidas e o intervalo de tempo entre cada medida. Os valores lidos/medidos através deste método são apresentados em gráficos diferentes em função do tempo atualizados em tempo real, sendo possível guardar estes dados num ficheiro do tipo csv. O trabalho desta dissertação consistiu no desenvolvimento de uma placa que irá fornecer as alimentações primárias necessárias para o novo sistema de distribuição de alta tensão, e no desenvolvimento da interface gráfica de utilizador dedicada para esta placa que permitirá o seu teste funcional e que será mais tarde migrada para o teste de controlo digital do ATLAS.
The current system that distributes high voltage to the hadronic calorimeter TileCal of the ATLAS experiment at CERN was manufactured in the late 1990s and now many of its components are obsolete. In addition to this, the continuous exposition to high levels of radiation that results from the LHC collision affects the whole system. The calorimeter itself will be upgraded and a faster and low noise electronic will be needed. Given this, an update was proposed to mitigate these problems: a new high voltage distribution system (HVDS) placed outside of the detector, a remote system which will not be affected by the radiation, that maximize the reliability and robustness of the system. For this new system it is necessary to produce a dedicated board that provides the necessary primary supplies. Therefore, the presented work consists in the development of a power supply board capable of providing both high voltage (HV), 􀀀830 V and 􀀀950 V, and low voltage, _12 V and 3:3 V, with low noise, resorting to DC/DC converters. Each HVDS provides the supply to 48 photomultipliers tubes (PMTs) of the detector. Due to the current needed, two high voltage sources are available, each one to supply just half of the PMTs. The values of the provided HV supplies are digitally controlled to one of the referred values, so each PMT of the detector can receive the right voltage to work correctly. Besides that, this board is controlled by a serial peripheral interface (SPI) communication protocol and has an analog to digital converter (ADC) and an analog multiplexer that are used to provide the user monitoring of all supply voltages and currents in real-time as well as the temperature, in two different positions of the board, in real time. A graphical user interface (GUI) has also been developed which allows easy communication between the power supply board and the user.

Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures. In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs.
Graduation date: 2011

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has driven the need for electronic store cord neural signals from many neurons. The continuous increase in demand of data from more number of neurons is challenging for the design of an efficient neural recording frontend(NRFE). Power consumption per channel and data rate minimization are two key problems which need to be addressed by next generation of neural recording systems. Area consumption per channel must be low for small implant size. Dynamic range in NRFE can vary with time due to change in electrode-neuron distance or background noise which demands adaptability. In this thesis, techniques to reduce power-per-channel and area-per-channel in a NRFE, via new circuits and architectures, are proposed. An area efficient low power neural LNA is presented in UMC 0.13 μm 1P8M CMOS technology. The amplifier can be biased adaptively from 200 nA to 2 μA , modulating input referred noise from 9.92 μV to 3.9μV . We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier. It obviates the need of large input coupling capacitance in the amplifier which saves considerable amount of chip area. In vitro experiments were performed to validate the applicability of the neural LNA in neural recording systems. ADC is another important block in a NRFE. An 8-bit SAR ADC along with the input and reference buffer is implemented in 0.13 μm CMOS technology. The use of ping-pong input sampling is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the output data rate, the A/D process is only enabled through a proposed activity dependent A/D scheme which ensures that the background noise is not processed. Based on the dynamic range requirement, the ADC resolution is adjusted from 8 to 1 bit at 1 bit step to reduce power consumption linearly. The ADC consumes 8.8 μW from1Vsupply at1MS/s and achieves ENOB of 7.7 bit. The ADC achieves FoM of 42.3 fJ/conversion in 0.13 μm CMOS technology. Power consumption in SARADCs is greatly benefited by CMOS scaling due to its highly digital nature. However the power consumption in the capacitive DAC does not scale as well as the digital logic. In this thesis, two energy-efficient DAC switching techniques, Flip DAC and Quaternary capacitor switching, are proposed to reduce their energy consumption. Using these techniques, the energy consumption in the DAC can be reduced by 37 % and 42.5 % compared to the present state-of-the-art. A novel concept of code-independent energy consumption is introduced and emphasized. It mitigates energy consumption degradation with small input signal dynamic range.

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has driven the need for electronic store cord neural signals from many neurons. The continuous increase in demand of data from more number of neurons is challenging for the design of an efficient neural recording frontend(NRFE). Power consumption per channel and data rate minimization are two key problems which need to be addressed by next generation of neural recording systems. Area consumption per channel must be low for small implant size. Dynamic range in NRFE can vary with time due to change in electrode-neuron distance or background noise which demands adaptability. In this thesis, techniques to reduce power-per-channel and area-per-channel in a NRFE, via new circuits and architectures, are proposed. An area efficient low power neural LNA is presented in UMC 0.13 μm 1P8M CMOS technology. The amplifier can be biased adaptively from 200 nA to 2 μA , modulating input referred noise from 9.92 μV to 3.9μV . We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier. It obviates the need of large input coupling capacitance in the amplifier which saves considerable amount of chip area. In vitro experiments were performed to validate the applicability of the neural LNA in neural recording systems. ADC is another important block in a NRFE. An 8-bit SAR ADC along with the input and reference buffer is implemented in 0.13 μm CMOS technology. The use of ping-pong input sampling is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the output data rate, the A/D process is only enabled through a proposed activity dependent A/D scheme which ensures that the background noise is not processed. Based on the dynamic range requirement, the ADC resolution is adjusted from 8 to 1 bit at 1 bit step to reduce power consumption linearly. The ADC consumes 8.8 μW from1Vsupply at1MS/s and achieves ENOB of 7.7 bit. The ADC achieves FoM of 42.3 fJ/conversion in 0.13 μm CMOS technology. Power consumption in SARADCs is greatly benefited by CMOS scaling due to its highly digital nature. However the power consumption in the capacitive DAC does not scale as well as the digital logic. In this thesis, two energy-efficient DAC switching techniques, Flip DAC and Quaternary capacitor switching, are proposed to reduce their energy consumption. Using these techniques, the energy consumption in the DAC can be reduced by 37 % and 42.5 % compared to the present state-of-the-art. A novel concept of code-independent energy consumption is introduced and emphasized. It mitigates energy consumption degradation with small input signal dynamic range.

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.

In the current digital age, electronic devices are becoming increasingly more critical, especially mobile devices and "always-listening" devices such as virtual personal assistants. To gather data from the real world, which in this case is voice audio, digital devices need to convert the analog input signals captured by a microphone to a digital stream. The process of data conversion is usually an energy expensive process, where lower power drawing implementations would benefit battery powered devices and provide less energy consuming "always-listening" devices. One of the most appealing Analog to Digital Converter (ADC) implementations are done using Sigma-Delta Modulators ( Ms) due to their use of oversampling that allows the noise to be transferred to higher frequencies that can be posteriorly eliminated by a decimation filter. In discrete time Ms, implemented with Switched-Capacitor (SC), the full capacitor charging consumes a considerable amount of power; to improve this aspect, a partial capacitor charge could be implemented, allowing less energy to be used in each clock cycle. In this thesis, a Multi-stAge Noise SHaping (MASH) 2+1 M is implemented with Metal-Insulator-Metal (MIM) capacitors and Unsilicided P+ Polysilicon resistors with a sampling frequency of 10 MHz and a bandwidth of 20 kHz, to evaluate the practical feasibility of the architecture. Due to the expected decrease in performance when compared to the original circuit, the Mis improved and stabilized through the temperature range. The finalized MASH 2+1 M achieves 86.755 dB of Signal-to-Noise-and-Distortion Ratio (SNDR) with 2 kHz, 300 mV input signal while using an active silicon area of 96439.127 μm2 or around 0.0964 mm2 (this active area does not contain the Digital Cancellation Logic (DCL) circuitry).

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected.
Graduation date: 2010

Разработан прототип приемника-декодера сигналов стандарта ADS-B. В ходе разработки предложена структурная схема выполнения устройства, а так же проведено комплексное исследование элементов устройства. Предложены принципиальные схемы и прототипы печатных плат для таких устройств как усилитель, инжектор питания, малошумящий усилитель, логарифмический детектор, а так же рассмотрена топология фильтра с двойной комплементарной спиралью. Приводятся результаты моделирования в различных пакетах программного обеспечения перечисленных выше устройств, а так же результаты их экспериментального исследования. Для обеспечения симуляции сигналов стандарта, а так же для обработки создано программное обеспечение.
A prototype of the receiver-decoder for the ADS-B system. During the development the block diagram of the device was proposed and a comprehensive study of elements of the device was done. Circuit schematics and layouts of printed circuit boards for devices such as amplifier, power injector, low noise amplifier, logarithmic detector and filter with a double complementary spiral were proposed. The results of the simulation of the listed above devices in a variety of software packages, as well as the results of an experimental study are presented. In order to simulate the signals, as well as for processing them special software was created.