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Journal articles on the topic 'Low latency'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 June 2024

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1

Hasbrouck, Joel, and Gideon Saar. "Low-latency trading." Journal of Financial Markets 16, no. 4 (November 2013): 646–79. http://dx.doi.org/10.1016/j.finmar.2013.05.003.

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2

Murtala, I., and O. A. Tiamiyu. "Comparative Analysis of Low Latency Anonymous Communication Systems." Proceedings of Telecommunication Universities 4, no. 3 (2018): 85–97. http://dx.doi.org/10.31854/1813-324x-2018-4-3-85-97.

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Riley, Holly, Rebecca B. MacLeod, and Matthew Libera. "Low Latency Audio Video." Update: Applications of Research in Music Education 34, no. 3 (November 17, 2014): 15–23. http://dx.doi.org/10.1177/8755123314554403.

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4

Roy, Pratanu, Jens Teubner, and Rainer Gemulla. "Low-latency handshake join." Proceedings of the VLDB Endowment 7, no. 9 (May 2014): 709–20. http://dx.doi.org/10.14778/2732939.2732944.

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5

Liu, Qing, Heming Wang, Fangxu Lyu, Geng Zhang, and Dongbin Lyu. "A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0." Electronics 12, no. 14 (July 17, 2023): 3102. http://dx.doi.org/10.3390/electronics12143102.

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As the PCIe 6.0 specification places higher requirements on signal integrity and transmission latency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuits are a key component of high-speed serial interfaces, and their delay and jitter size directly affect the overall performance of PCIe. For the typical retimer circuit with large-latency and low-jitter performance, this paper proposes a low-latency and low-jitter Retimer circuit based on CDR + PLL architecture for PCIe 6.0, using a jitter-canceling filter circuit to eliminate the frequency difference between the retiming clock and data, reduce the retiming clock jitter, and improve the quality of Retimer output data. The data are sampled using the retiming clock and then output, avoiding the problem of large penetration latency of typical retimer circuits. The circuit is designed using the CMOS 28 nm process. Simulation results show that when 112 Gbps PAM4 data are input to the retimer circuit, the Retimer penetration latency is 27.3 ps, which is 83.5% lower than the typical Retimer structure; the output jitter data are 741 fs, a 31.4% reduction compared to the typical retimer structure.
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6

Marinšek, Alexander, Daan Delabie, Lieven De Strycker, and Liesbet Van der Perre. "Physical Layer Latency Management Mechanisms: A Study for Millimeter-Wave Wi-Fi." Electronics 10, no. 13 (July 3, 2021): 1599. http://dx.doi.org/10.3390/electronics10131599.

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Emerging applications in fields such as extended reality require both a high throughput and low latency. The millimeter-wave (mmWave) spectrum is considered because of the potential in the large available bandwidth. The present work studies mmWave Wi-Fi physical layer latency management mechanisms, a key factor in providing low-latency communications for time-critical applications. We calculate physical layer latency in an ideal scenario and simulate it using a tailor-made simulation framework, based on the IEEE 802.11ad standard. Assessing data reception quality over a noisy channel yielded latency’s dependency on transmission parameters, channel noise, and digital baseband tuning. Latency in function of the modulation and coding scheme was found to span 0.28–2.71 ms in the ideal scenario, whereas simulation results also revealed its tight bond with the demapping algorithm and the number of low-density parity-check decoder iterations. The findings yielded tuning parameter combinations for reaching Pareto optimality either by constraining the bit error rate and optimizing latency or the other way around. Our assessment shows that trade-offs can and have to be made to provide sufficiently reliable low-latency communication. In good channel conditions, one may benefit from both the very high throughput and low latency; yet, in more adverse situations, lower modulation orders and additional coding overhead are a necessity.
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Arribas, Victor, Zhenda Zhang, and Svetla Nikova. "LLTI: Low-Latency Threshold Implementations." IEEE Transactions on Information Forensics and Security 16 (2021): 5108–23. http://dx.doi.org/10.1109/tifs.2021.3123527.

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8

Hurtig, Per, Karl-Johan Grinnemo, Anna Brunstrom, Simone Ferlin, Ozgu Alay, and Nicolas Kuhn. "Low-Latency Scheduling in MPTCP." IEEE/ACM Transactions on Networking 27, no. 1 (February 2019): 302–15. http://dx.doi.org/10.1109/tnet.2018.2884791.

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9

Chen, Kwang-Cheng, Tao Zhang, Richard D. Gitlin, and Gerhard Fettweis. "Ultra-Low Latency Mobile Networking." IEEE Network 33, no. 2 (March 2019): 181–87. http://dx.doi.org/10.1109/mnet.2018.1800011.

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10

Oesch, Christian, and Dietmar Maringer. "Low-latency liquidity inefficiency strategies." Quantitative Finance 17, no. 5 (November 4, 2016): 717–27. http://dx.doi.org/10.1080/14697688.2016.1242765.

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11

Shukla, Rohit, and Kailash Chandra Ray. "Low Latency Hybrid CORDIC Algorithm." IEEE Transactions on Computers 63, no. 12 (December 2014): 3066–78. http://dx.doi.org/10.1109/tc.2013.173.

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12

Giard, Pascal, Gabi Sarkis, Camille Leroux, Claude Thibeault, and Warren J. Gross. "Low-Latency Software Polar Decoders." Journal of Signal Processing Systems 90, no. 5 (July 11, 2016): 761–75. http://dx.doi.org/10.1007/s11265-016-1157-y.

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13

Zhao, W., P. M. Melliar-Smith, and L. E. Moser. "Low Latency Fault Tolerance System." Computer Journal 56, no. 6 (October 2, 2012): 716–40. http://dx.doi.org/10.1093/comjnl/bxs131.

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14

Timmermann, D., H. Hahn, and B. J. Hosticka. "Low latency time CORDIC algorithms." IEEE Transactions on Computers 41, no. 8 (1992): 1010–15. http://dx.doi.org/10.1109/12.156543.

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15

Han, Feixue, Mowei Wang, Yong Cui, Qing Li, Ru Liang, Yashe Liu, and Yong Jiang. "Future Data Center Networking: From Low Latency to Deterministic Latency." IEEE Network 36, no. 1 (January 2022): 52–58. http://dx.doi.org/10.1109/mnet.102.2000622.

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16

Litz, Heiner, Javier Gonzalez, Ana Klimovic, and Christos Kozyrakis. "RAIL: Predictable, Low Tail Latency for NVMe Flash." ACM Transactions on Storage 18, no. 1 (February 28, 2022): 1–21. http://dx.doi.org/10.1145/3465406.

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Flash-based storage is replacing disk for an increasing number of data center applications, providing orders of magnitude higher throughput and lower average latency. However, applications also require predictable storage latency. Existing Flash devices fail to provide low tail read latency in the presence of write operations. We propose two novel techniques to address SSD read tail latency, including Redundant Array of Independent LUNs (RAIL) which avoids serialization of reads behind user writes as well as latency-aware hot-cold separation (HC) which improves write throughput while maintaining low tail latency. RAIL leverages the internal parallelism of modern Flash devices and allocates data and parity pages to avoid reads getting stuck behind writes. We implement RAIL in the Linux Kernel as part of the LightNVM Flash translation layer and show that it can reduce read tail latency by 7× at the 99.99th percentile, while reducing relative bandwidth by only 33%.
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17

Ge, Jun Wei, Hai Ming Zheng, and Yi Qiu Fang. "A Hybird Virtual Machine Placement Aglrithm for Virtualized Desktop Infrastructure." Advanced Materials Research 760-762 (September 2013): 1906–10. http://dx.doi.org/10.4028/www.scientific.net/amr.760-762.1906.

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As we all kown, The virtual machine placement is one kind of bin-packing problem. By optimizing placement of virtual machine. We can improve VM performance, enhance resource utilization, reduce energy comsumption. After analysis the existing virtual machine placement aglrithm. We propose a hybird virtual machine placement aglrithm (HTA) which based on network latency threshold for the requirement of low network latence and low VM migraiton ratio in Virtualized Desktop Infrastructure. It elect qualified node set based on network latency threshold and palce the virtual machines with load-balance policy, taking into account the preformance of the network and vitual machines. According to analysis and comparison. The simulation result show that the algorithm can effectively lessen the network latency and reduce the VM migration ratio.
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18

Gürel, O., and M. U. Çakır. "XMPP Based Applications under Low Bandwidth and High Latency Conditions." Lecture Notes on Software Engineering 3, no. 4 (2015): 314–17. http://dx.doi.org/10.7763/lnse.2015.v3.211.

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19

Renfei Liu and K. K. Parhi. "Low-Latency Low-Complexity Architectures for Viterbi Decoders." IEEE Transactions on Circuits and Systems I: Regular Papers 56, no. 10 (October 2009): 2315–24. http://dx.doi.org/10.1109/tcsi.2008.2012217.

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20

Chiola, G., and G. Ciaccio. "Implementing a low cost, low latency parallel platform." Parallel Computing 22, no. 13 (February 1997): 1703–17. http://dx.doi.org/10.1016/s0167-8191(96)00072-5.

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21

Shin, Ho, and Eui-Young Chung. "In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs." Micromachines 10, no. 2 (February 14, 2019): 124. http://dx.doi.org/10.3390/mi10020124.

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Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%.
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22

Jiang, Xiaolin, Hossein Shokri-Ghadikolaei, Gabor Fodor, Eytan Modiano, Zhibo Pang, Michele Zorzi, and Carlo Fischione. "Low-Latency Networking: Where Latency Lurks and How to Tame It." Proceedings of the IEEE 107, no. 2 (February 2019): 280–306. http://dx.doi.org/10.1109/jproc.2018.2863960.

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23

Avranas, Apostolos, Marios Kountouris, and Philippe Ciblat. "Energy-Latency Tradeoff in Ultra-Reliable Low-Latency Communication With Retransmissions." IEEE Journal on Selected Areas in Communications 36, no. 11 (November 2018): 2475–85. http://dx.doi.org/10.1109/jsac.2018.2874143.

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24

Halbhuber, David, Philipp Schauhuber, Valentin Schwind, and Niels Henze. "The Effects of Latency and In-Game Perspective on Player Performance and Game Experience." Proceedings of the ACM on Human-Computer Interaction 7, CHI PLAY (September 29, 2023): 1308–29. http://dx.doi.org/10.1145/3611070.

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Previous work shows that high latency, a prolonged delay between player in- and system output, negatively affects player experience and performance. However, previous work also comes to contrary conclusions about how the in-game perspective alters the latency sensitivity of video games. Currently, it is unclear if the in-game perspective independently modulates latency's effects. To investigate how a game's in-game perspective interacts with latency, we developed a shooting game incorporating three perspectives (First-Person-, Third-Person-, and Bird's-Eye-View). In a study, participants (N = 36) played with two levels of latency (low and high) and the three perspectives. We show that latency reduces performance and experience, independent of the perspective. Moreover, Bayesian analysis suggests that the in-game perspective does not interact with latency and does not affects performance or experience. We conclude that more robust means to categorize latency sensitivity of video games than the in-game perspective are required.
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25

FAROOQ, SHEZA, AMAN KUMAR, SUMAN CHAUDHARY, and SUSHILA MAAN. "Development of TaqMan probe-based RT-qPCR assays for detection of BoHV-1 latency in Bovine." Indian Journal of Animal Sciences 94, no. 3 (March 11, 2024): 247–50. http://dx.doi.org/10.56093/ijans.v94i3.143188.

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Bovine herpesvirus-1 is highly contagious virus of cattle and buffaloes all over the world. It establishes lifelong latency in ganglionic neurons of the peripheral nervous system. Since, trigeminal ganglia are the main sites of latency, therefore, it is challenging to detect BoHV-1 in latently infected live animals. No research work has been done to correlate the sero-prevalence and latency in peripheral blood mononuclear cells (PBMC). The present study was designed to detect BoHV-1 latency related transcript or microRNA in peripheral blood mononuclear cells of sero-positive animals. The highly sensitive RT-qPCR assays based on TaqMan chemistry have been developed for the detection of transcripts of BoHV-1 latency. The limit of detection (LOD) of the assays for ORF-1 specific RT-qPCR and miRNA specific RT-qPCR was 460 copies and 117 copies respectively. The efficiency of the developed assays was 93.5% for ORF-1 and 97.93% for miRNA transcript. None of the PBMC samples of seropositive animals found positive for ORF-1 and miRNA transcripts in developed assays.The absence of latency specific transcripts in PBMC might be due to very low expression i.e. beyond the LOD of newly developed assays or absence of latency in PBMC of seropositive animal. However, further studies are required to establish the fact. To the best of authors knowledge, this is the first report of latency-specific RT-qPCR assay development and its application in PBMC of BoHV-1 seropositive cattle.
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26

Das, Debajyoti, Easwar Vivek Mangipudi, and Aniket Kate. "OrgAn: Organizational Anonymity with Low Latency." Proceedings on Privacy Enhancing Technologies 2022, no. 3 (July 2022): 582–605. http://dx.doi.org/10.56553/popets-2022-0087.

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There is a growing demand for network-level anonymity for delegates at global organizations such as the UN and Red Cross. Numerous anonymous communication (AC) systems have been proposed over the last few decades to provide anonymity over the internet; however, they introduce high latency overhead, provide weaker anonymity guarantees, or are difficult to deploy at the organizational networks. Recently, the PriFi system introduced a client/relay/server model that suitably utilizes the organizational network topology and proposes a low-latency, strong-anonymity AC protocol. Using an efficient lattice-based (almost) keyhomomorphic pseudorandom function and Netwon’s power sums, we present a novel AC protocol OrgAn in this client/relay/server model that provides strong anonymity against a global adversary controlling the majority of the network. OrgAn’s cryptographic design allows it to overcome several major problems with any realistic PriFi instantiation: (a) unlike PriFi, OrgAn avoids frequent, interactive, slot-agreement protocol among the servers; (b) a PriFi relay has to receive frequent communication from the servers, which can not only become a latency bottleneck but also reveal the access pattern to the servers and increases the chance of server collusion/coercion, while OrgAn servers are absent from any real-time process. We demonstrate how to make this public-key cryptographic solution scale equally well as the symmetric-cryptographic PriFi with practical pre-computation and storage requirements. Through a prototype implementation, we show that OrgAn provides similar throughput and end-to-end latency guarantees as PriFi, while still discounting the setup challenges in PriFi.
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27

Usui, Soichiro, Shinji Fukatsu, Eiichiro Matsumoto, Maiko Imoto, Daisuke Shirai, and Shingo Kinoshita. "Marathon × Ultra-low-latency Communication Technology." NTT Technical Review 19, no. 12 (December 2021): 78–84. http://dx.doi.org/10.53829/ntr202112fa10.

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28

NGUYEN, Hong-Thu, Xuan-Thuan NGUYEN, and Cong-Kha PHAM. "A Low-Latency Parallel Pipeline CORDIC." IEICE Transactions on Electronics E100.C, no. 4 (2017): 391–98. http://dx.doi.org/10.1587/transele.e100.c.391.

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29

Dong, Jialin, Kai Yang, and Yuanming Shi. "Blind Demixing for Low-Latency Communication." IEEE Transactions on Wireless Communications 18, no. 2 (February 2019): 897–911. http://dx.doi.org/10.1109/twc.2018.2886191.

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30

Thomas, Yannis, Merkourios Karaliopoulos, George Xylomenos, and George C. Polyzos. "Low Latency Friendliness for Multipath TCP." IEEE/ACM Transactions on Networking 28, no. 1 (February 2020): 248–61. http://dx.doi.org/10.1109/tnet.2019.2961759.

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31

Chan, R. P. K., O. C. S. Choy, C. F. Chan, and K. P. Pun. "A Low-Latency Asynchronous Shift Register." IEEE Transactions on Circuits and Systems II: Express Briefs 51, no. 5 (May 2004): 217–21. http://dx.doi.org/10.1109/tcsii.2004.824051.

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32

Friston, Sebastian, and Jim Foley. "Low-Latency Rendering With Dataflow Architectures." IEEE Computer Graphics and Applications 40, no. 3 (May 1, 2020): 94–104. http://dx.doi.org/10.1109/mcg.2020.2980183.

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33

Brook, Andrew. "Low-latency distributed applications in finance." Communications of the ACM 58, no. 7 (June 25, 2015): 42–50. http://dx.doi.org/10.1145/2747303.

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34

Knight, Thomas F. "Technologies for low latency interconnection switches." ACM SIGARCH Computer Architecture News 19, no. 1 (March 1991): 61–68. http://dx.doi.org/10.1145/121956.121963.

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35

Goel, Ashvin, Charles Krasic, and Jonathan Walpole. "Low-latency adaptive streaming over tcp." ACM Transactions on Multimedia Computing, Communications, and Applications 4, no. 3 (August 2008): 1–20. http://dx.doi.org/10.1145/1386109.1386113.

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36

K, Venkata Reddy, Simranjeet Singh C, Vivian Desalphine, and David Selvakumar. "A Low Latency Montgomery Modular Exponentiation." Procedia Computer Science 171 (2020): 800–809. http://dx.doi.org/10.1016/j.procs.2020.04.087.

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37

Bos, Joppe W. "Low-Latency Elliptic Curve Scalar Multiplication." International Journal of Parallel Programming 40, no. 5 (May 26, 2012): 532–50. http://dx.doi.org/10.1007/s10766-012-0198-5.

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38

Horbach, Ulrich. "REDUCED LATENCY LOW FREQUENCY EQUALIZATION SYSTEM." Journal of the Acoustical Society of America 134, no. 2 (2013): 1433. http://dx.doi.org/10.1121/1.4817601.

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39

Pekmestzi, K. Z., and C. Caraiscos. "Low-latency bit-parallel systolic multiplier." Electronics Letters 29, no. 4 (1993): 367. http://dx.doi.org/10.1049/el:19930247.

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40

Yakovlev, A., A. Petrov, and L. Lavagno. "A low latency asynchronous arbitration circuit." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, no. 3 (September 1994): 372–77. http://dx.doi.org/10.1109/92.311648.

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41

Pu, Qifan, Ganesh Ananthanarayanan, Peter Bodik, Srikanth Kandula, Aditya Akella, Paramvir Bahl, and Ion Stoica. "Low Latency Geo-distributed Data Analytics." ACM SIGCOMM Computer Communication Review 45, no. 4 (September 22, 2015): 421–34. http://dx.doi.org/10.1145/2829988.2787505.

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42

Rezaei, Hossein, Nandana Rajatheva, and Matti Latva-Aho. "Low-Latency Multi-Kernel Polar Decoders." IEEE Access 10 (2022): 119460–74. http://dx.doi.org/10.1109/access.2022.3221742.

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43

Hildinger, Rainer, and Marco Breiling. "The DVB-SH low-latency extension." International Journal of Satellite Communications and Networking 32, no. 6 (November 8, 2013): 475–84. http://dx.doi.org/10.1002/sat.1051.

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44

Wang, Jingxian, Vaishnavi Ranganathan, Jonathan Lester, and Swarun Kumar. "Ultra Low-Latency Backscatter for Fast-Moving Location Tracking." Proceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies 6, no. 1 (March 29, 2022): 1–22. http://dx.doi.org/10.1145/3517242.

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This paper explores building an ultra-low latency and high-accuracy location tracking solution using battery-free tags. While there is rich prior work on location tracking with battery-free RFID tags and backscatter devices, these systems typically face tradeoffs with accuracy, power consumption, and latency. Such limitations make these existing solutions unsuitable for emerging applications like industrial augmented reality which requires tracking fast-moving machinery; monitoring indoor sports activities that require real-time tracking of fast-moving objects with high precision and under stringent latency constraints. We propose and demonstrate FastLoc, a precision tracking system that locates tiny, battery-free analog backscatter tags at sub-millisecond latency and sub-centimeter accuracy. FastLoc is a hybrid system that simultaneously uses RF and optical signals to track tiny tags that can be attached to everyday objects. FastLoc leverages the RF channel responses from tags for estimating the coarse region where the tags may be located. It simultaneously uses the sensed optical information modulated on the backscatter signals to enable fine-grained location estimation within the coarse region. To achieve this, we design and fabricate a custom analog tag that consumes less than 150 uW and instantaneously converts incident optical signals to one-shot wideband harmonic RF responses at nanosecond latency. We then develop a static high-density distributed-frequency structured light pattern that can localize tags in the area of interest at a sub-centimeter accuracy and microsecond-scale latency. A detailed experimental evaluation of FastLoc shows a median accuracy of 0.7 cm in tag localization with a 0.51 ms effective localization latency.
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Rosing, Matt, and Joel Saltz. "Low Latency Messages on Distributed Memory Multiprocessors." Scientific Programming 4, no. 1 (1995): 35–43. http://dx.doi.org/10.1155/1995/531941.

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This article describes many of the issues in developing an efficient interface for communication on distributed memory machines. Although the hardware component of message latency is less than 1 ws on many distributed memory machines, the software latency associated with sending and receiving typed messages is on the order of 50 μs. The reason for this imbalance is that the software interface does not match the hardware. By changing the interface to match the hardware more closely, applications with fine grained communication can be put on these machines. This article describes several tests performed and many of the issues involved in supporting low latency messages on distributed memory machines.
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46

Heimfarth, Tales, João Carlos Giacomin, Edison Pignaton de Freitas, Gustavo Figueiredo Araujo, and João Paulo de Araujo. "PAX-MAC: A Low Latency Anycast Protocol with Advanced Preamble." Sensors 20, no. 1 (January 1, 2020): 250. http://dx.doi.org/10.3390/s20010250.

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Wireless sensor networks employ duty-cycles to save energy, with the cost of enlargement of end-to-end latency. Cross-layer protocols that use anycast medium access control achieve latency reduction in asynchronous duty-cycled wireless sensor networks (WSNs). A series of strobed preambles is sent in order to achieve rendezvous with the next relay, selected from a forwarding candidate set (FCS). This paper proposes PAX-MAC: Pramble Ahead Cross-layer Medium Access Control. It is a novel anycast protocol for low latency packet propagation in duty-cycled WSNs. In PAX-MAC, preambles propagate ahead of data packet, prospecting the route towards sink node, while the message is sent some hops later. Simultaneous propagation of preambles and data packets provides latency reduction. The cardinality of FCS determines the average preamble propagation speed, which is lower bounded by data packet propagation speed. Differently from other approaches, our protocol takes the data packet size into account in order to maintain an optimal distance between preamble and data to minimize latency. For determining this distance, a detailed mathematical model is introduced. The performance of several state-of-the-art asynchronous protocols was appraised and compared with PAX-MAC. Our protocol outperforms in latency all other protocols for the simulated scenarios. Its energy expenditure was compatible with the best result among the other protocols. In the worst case, PAX-MAC spent 6 % more energy than the best one for a gain of 20 % in latency.
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47

Xia, Jincheng, Wenjia Fu, Ming Liu, and Mingjiang Wang. "Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division." Applied Sciences 11, no. 11 (May 28, 2021): 4988. http://dx.doi.org/10.3390/app11114988.

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Floating-point division is indispensable and becoming increasingly important in many modern applications. To improve speed performance of floating-point division in actual microprocessors, this paper proposes a low-latency architecture with a multi-precision architecture for floating-point division which will meet the IEEE-754 standard. There are three parts in the floating-point division design: pre-configuration, mantissa division, and quotient normalization. In the part of mantissa division, based on the fast division algorithm, a Predict–Correct algorithm is employed which brings about more partial quotient bits per cycle without consuming too much circuit area. Detailed analysis is presented to support the guaranteed accuracy per cycle with no restriction to specific parameters. In the synthesis using TSMC, 90 nm standard cell library, the results show that the proposed architecture has ≈63.6% latency, ≈30.23% total time (latency × period), ≈31.8% total energy (power × latency × period), and ≈44.6% efficient average energy (power × latency × period/efficient length) overhead over the latest floating-point division structure. In terms of latency, the proposed division architecture is much faster than several classic processors.
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48

Virgin, Herbert W., Rachel M. Presti, Xi-Yang Li, Carl Liu, and Samuel H. Speck. "Three Distinct Regions of the Murine Gammaherpesvirus 68 Genome Are Transcriptionally Active in Latently Infected Mice." Journal of Virology 73, no. 3 (March 1, 1999): 2321–32. http://dx.doi.org/10.1128/jvi.73.3.2321-2332.1999.

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ABSTRACT The program(s) of gene expression operating during murine gammaherpesvirus 68 (γHV68) latency is undefined, as is the relationship between γHV68 latency and latency of primate gammaherpesviruses. We used a nested reverse transcriptase PCR strategy (sensitive to approximately one copy of γHV68 genome for each genomic region tested) to screen for the presence of viral transcripts in latently infected mice. Based on the positions of known latency-associated genes in other gammaherpesviruses, we screened for the presence of transcripts corresponding to 11 open reading frames (ORFs) in the γHV68 genome in RNA from spleens and peritoneal cells of latently infected B-cell-deficient (MuMT) mice which have been shown contain high levels of reactivable latent γHV68 (K. E. Weck, M. L. Barkon, L. I. Yoo, S. H. Speck, and H. W. Virgin, J. Virol. 70:6775–6780, 1996). To control for the possible presence of viral lytic activity, we determined that RNA from latently infected peritoneal and spleen cells contained few or no detectable transcripts corresponding to seven ORFs known to encode viral gene products associated with lytic replication. However, we did detect low-level expression of transcripts arising from the region of gene 50 (encoding the putative homolog of the Epstein-Barr virus BRLF1 transactivator) in peritoneal but not spleen cells. Latently infected peritoneal cells consistently scored for expression of RNA derived from 4 of the 11 candidate latency-associated ORFs examined, including the regions of ORF M2, ORF M11 (encoding v-bcl-2), gene 73 (a homolog of the Kaposi’s sarcoma-associated herpesvirus [human herpesvirus 8] gene encoding latency-associated nuclear antigen), and gene 74 (encoding a G-protein coupled receptor homolog, v-GCR). Latently infected spleen cells consistently scored positive for RNA derived from 3 of the 11 candidate latency-associated ORFs examined, including ORF M2, ORF M3, and ORF M9. To further characterize transcription of these candidate latency-associated ORFs, we examined their transcription in lytically infected fibroblasts by Northern analysis. We detected abundant transcription from regions of the genome containing ORF M3 and ORF M9, as well as the known lytic-cycle genes. However, transcription of ORF M2, ORF M11, gene 73, and gene 74 was barely detectable in lytically infected fibroblasts, consistent with a role of these viral genes during latent infection. We conclude that (i) we have identified several candidate latency genes of murine γHV68, (ii) expression of genes during latency may be different in different organs, consistent with multiple latency programs and/or multiple cellular sites of latency, and (iii) regions of the viral genome (v-bcl-2 gene, v-GCR gene, and gene 73) are transcribed during latency with both γHV68 and primate gammaherpesviruses. The implications of these findings for replacing previous operational definitions of γHV68 latency with a molecular definition are discussed.
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49

Zheng, Chengshi, Wenzhe Liu, Andong Li, Yuxuan Ke, and Xiaodong Li. "Low-latency monaural speech enhancement with deep filter-bank equalizer." Journal of the Acoustical Society of America 151, no. 5 (May 2022): 3291–304. http://dx.doi.org/10.1121/10.0011396.

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It is highly desirable that speech enhancement algorithms can achieve good performance while keeping low latency for many applications, such as digital hearing aids, mobile phones, acoustically transparent hearing devices, and public address systems. To improve the performance of traditional low-latency speech enhancement algorithms, a deep filter-bank equalizer (FBE) framework was proposed that integrated a deep learning-based subband noise reduction network with a deep learning-based shortened digital filter mapping network. In the first network, a deep learning model was trained with a controllable small frame shift to satisfy the low-latency demand, i.e., no greater than 4 ms, so as to obtain (complex) subband gains that could be regarded as an adaptive digital filter in each frame. In the second network, to reduce the latency, this adaptive digital filter was implicitly shortened by a deep learning-based framework and was then applied to noisy speech to reconstruct the enhanced speech without the overlap-add method. Experimental results on the WSJ0-SI84 corpus indicated that the proposed DeepFBE with only 4-ms latency achieved much better performance than traditional low-latency speech enhancement algorithms across several objective metrics. Listening test results further confirmed that our approach achieved higher speech quality than other methods.
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50

Yamakawa, Yuji, Yugo Katsuki, Yoshihiro Watanabe, and Masatoshi Ishikawa. "Development of a High-Speed, Low-Latency Telemanipulated Robot Hand System." Robotics 10, no. 1 (March 3, 2021): 41. http://dx.doi.org/10.3390/robotics10010041.

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This paper focuses on development of a high-speed, low-latency telemanipulated robot hand system, evaluation of the system, and demonstration of the system. The characteristics of the developed system are the followings: non-contact, high-speed 3D visual sensing of the human hand, intuitive motion mapping between human hands and robot hands, and low-latency, fast responsiveness to human hand motion. Such a high-speed, low-latency telemanipulated robot hand system can be considered to be more effective from the viewpoint of usability. The developed system consists of a high-speed vision system, a high-speed robot hand, and a real-time controller. For the developed system, we propose new methods of 3D sensing, mapping between the human hand and the robot hand, and the robot hand control. We evaluated the performance (latency and responsiveness) of the developed system. As a result, the latency of the developed system is so small that humans cannot recognize the latency. In addition, we conducted experiments of opening/closing motion, object grasping, and moving object grasping as demonstrations. Finally, we confirmed the validity and effectiveness of the developed system and proposed method.
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