To see the other types of publications on this topic, follow the link: Low effective mass channel material transistors.
Journal articles on the topic 'Low effective mass channel material transistors'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 34 journal articles for your research on the topic 'Low effective mass channel material transistors.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.
1
van Fraassen, Niels C. A., Sanggil Han, Kham Niang, and Andrew J. John Flewitt. "(Invited) Achieving Lower Power Logic Using P-Type Metal Oxide Thin Film Transistors." ECS Meeting Abstracts MA2022-02, no. 35 (October 9, 2022): 1267. http://dx.doi.org/10.1149/ma2022-02351267mtgabs.
Full textAbstract:
Thin film transistors (TFTs) have enabled the active matrix displays that are a ubiquitous part of everyday life, from mobile phones and tablets through to desktop monitors and home televisions. They are used in the circuit at each pixel over the display as they can be fabricated for relatively low cost with excellent uniformity at low temperatures over large areas on glass substrates. These pixel circuits only require either n-channel or p-channel enhancement mode TFTs. However, there has long been a desire to integrate the display driver electronics onto the display panel as an alternative to connecting silicon-based integrated circuits using complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) to displays. More recently, there has been an increasing interest in producing other logic circuits using TFTs on glass and plastic substrates as this could enable a new generation of products with embedded electronics. However, both of these applications need low power logic circuits. CMOS is an inherently low power technology, but it requires both n-channel and p-channel transistors. Whilst this can be realised in silicon CMOS FETs, it has not yet been achieved using TFTs because it has proved difficult to realise both n-channel and p-channel devices using one material system at low cost. For example, hydrogenated amorphous silicon can be used to make reasonable n-type material but not p-type. Thin film oxide semiconductors such as amorphous indium gallium zinc oxide have been successfully commercialised in the pixel circuits of active matrix displays as they possess high field effect mobility, low threshold voltage, low off-state current and a high switching ratio. There is therefore a lot of interest in finding a suitable complementary p-type metal oxide thin film material to allow CMOS-type logic to be realised using this material system. Cuprous oxide is one such promising candidate material as the top of the valence band is dominated by states which form as a result of hybridisation of the completely filled Cu 3d orbitals and the O 2p orbitals. These hybridised states are less localised and have a higher dispersion with a resulting decrease in the effective mass of holes in these states and a higher carrier mobility. The results of an extensive study of this material shows that the grain structure is of critical importance with [100] oriented films resulting in a higher mobility. Furthermore, the impact of grain boundaries on conduction must be controlled. Although this allows TFTs with reasonable on-state current to be fabricated, it is found that there is a significant residual off-state current which is a result of electron accumulation in the channel. This is consistent with the high off-state current that has been observed widely in TFTs using p-type metal oxide thin film materials. The low off-state current in silicon MOSFETs means that the geometric transistor design in low power CMOS logic circuits only needs to focus on the effect of the on-state current in the p-channel and n-channel transistors. However, in TFTs, the much larger off-state current also becomes important as it can end up being a significant parameter when calculating the power consumption of CMOS logic circuits. An alternative geometric design parameter for TFT logic circuits is presented. This compares the maximum switching current with the static currents allowing optimisation based on both the noise margin and static power consumption. The result is improved performance of TFT-based CMOS logic circuits using the n- and p-type thin film oxide semiconductors that are currently available.
2
Yen, Te Jui, Albert Chin, Weng Kent Chan, Hsin-Yi Tiffany Chen, and Vladimir Gritsenko. "Remarkably High-Performance Nanosheet GeSn Thin-Film Transistor." Nanomaterials 12, no. 2 (January 14, 2022): 261. http://dx.doi.org/10.3390/nano12020261.
Full textAbstract:
High-performance p-type thin-film transistors (pTFTs) are crucial for realizing low-power display-on-panel and monolithic three-dimensional integrated circuits. Unfortunately, it is difficult to achieve a high hole mobility of greater than 10 cm2/V·s, even for SnO TFTs with a unique single-hole band and a small hole effective mass. In this paper, we demonstrate a high-performance GeSn pTFT with a high field-effect hole mobility (μFE), of 41.8 cm2/V·s; a sharp turn-on subthreshold slope (SS), of 311 mV/dec, for low-voltage operation; and a large on-current/off-current (ION/IOFF) value, of 8.9 × 106. This remarkably high ION/IOFF is achieved using an ultra-thin nanosheet GeSn, with a thickness of only 7 nm. Although an even higher hole mobility (103.8 cm2/V·s) was obtained with a thicker GeSn channel, the IOFF increased rapidly and the poor ION/IOFF (75) was unsuitable for transistor applications. The high mobility is due to the small hole effective mass of GeSn, which is supported by first-principles electronic structure calculations.
3
Pooja, Pheiroijam, Chun Che Chien, and Albert Chin. "Superior High Transistor’s Effective Mobility of 325 cm2/V-s by 5 nm Quasi-Two-Dimensional SnON nFET." Nanomaterials 13, no. 12 (June 20, 2023): 1892. http://dx.doi.org/10.3390/nano13121892.
Full textAbstract:
This work reports the first nanocrystalline SnON (7.6% nitrogen content) nanosheet n-type Field-Effect Transistor (nFET) with the transistor’s effective mobility (µeff) as high as 357 and 325 cm2/V-s at electron density (Qe) of 5 × 1012 cm−2 and an ultra-thin body thickness (Tbody) of 7 nm and 5 nm, respectively. At the same Tbody and Qe, these µeff values are significantly higher than those of single-crystalline Si, InGaAs, thin-body Si-on-Insulator (SOI), two-dimensional (2D) MoS2 and WS2. The new discovery of a slower µeff decay rate at high Qe than that of the SiO2/bulk-Si universal curve was found, owing to a one order of magnitude lower effective field (Eeff) by more than 10 times higher dielectric constant (κ) in the channel material, which keeps the electron wave-function away from the gate-oxide/semiconductor interface and lowers the gate-oxide surface scattering. In addition, the high µeff is also due to the overlapped large radius s-orbitals, low 0.29 mo effective mass (me*) and low polar optical phonon scattering. SnON nFETs with record-breaking µeff and quasi-2D thickness enable a potential monolithic three-dimensional (3D) integrated circuit (IC) and embedded memory for 3D biological brain-mimicking structures.
4
Lee, Dong Hun, Yuxuan Zhang, Kwangsoo No, Han Wook Song, and Sunghwan Lee. "(Digital Presentation) Multimodal Encapsulation of p-SnOx to Engineer the Carrier Density for Thin Film Transistor Applications." ECS Meeting Abstracts MA2022-02, no. 15 (October 9, 2022): 821. http://dx.doi.org/10.1149/ma2022-0215821mtgabs.
Full textAbstract:
It has been challenging to synthesize p-type SnOx (1≤x<2) and engineer the electrical properties such as carrier density and mobility due to the narrow processing window and the localized oxygen 2p orbitals near the valence band. We recently reported on the processing of p-type SnOx and an oxide-based p-n heterostructures, demonstrating high on/off rectification ratio (>103), small turn-on voltage (<0.5 V), and low saturation current (~1×10-10 A)1. In order to further understand the p-type oxide and engineer the properties for various electronic device applications, it is important to identify (or establish) the dominating doping and transport mechanisms. The low dopability in p-type SnOx, of which the causation is also closely related to the narrow processing window, needs to be mitigated so that the electrical properties of the material are to be adequately engineered 2, 3. Herein, we report on the multifunctional encapsulation of p-SnOx to limit the surface adsorption of oxygen and selectively permeate hydrogen into the p-SnOx channel for thin film transistor (TFT) applications. Time-of-flight secondary ion mass spectrometry measurements identified that ultra-thin SiO2 as a multifunctional encapsulation layer effectively suppressed the oxygen adsorption on the back channel surface of p-SnOx and augmented hydrogen density across the entire thickness of the channel. Encapsulated p-SnOx-based TFTs demonstrated much-enhanced channel conductance modulation in response to the gate bias applied, featuring higher on-state current and lower off-state current. The relevance between the TFT performance and the effects of oxygen suppression and hydrogen permeation is discussed in regard to the intrinsic and extrinsic doping mechanisms. These results are supported by density-functional-theory calculations. Acknowledgement This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS. K.N. was supported by Basic Science Research Program (NRF-2021R11A1A01051246) through the NRF Korea funded by the Ministry of Education. References Lee, D. H.; Park, H.; Clevenger, M.; Kim, H.; Kim, C. S.; Liu, M.; Kim, G.; Song, H. W.; No, K.; Kim, S. Y.; Ko, D.-K.; Lucietto, A.; Park, H.; Lee, S., High-Performance Oxide-Based p–n Heterojunctions Integrating p-SnOx and n-InGaZnO. ACS Applied Materials & Interfaces 2021, 13 (46), 55676-55686. Hautier, G.; Miglio, A.; Ceder, G.; Rignanese, G.-M.; Gonze, X., Identification and design principles of low hole effective mass p-type transparent conducting oxides. Nat Commun 2013, 4. Yim, K.; Youn, Y.; Lee, M.; Yoo, D.; Lee, J.; Cho, S. H.; Han, S., Computational discovery of p-type transparent oxide semiconductors using hydrogen descriptor. npj Computational Materials 2018, 4 (1), 17. Figure 1
5
Tong, Shi Wun, and Man-Fai Ng. "(Digital Presentation) Scalable Growth of Transition Metal Dichalcogenides for Next-Generation Nanoelectronics." ECS Meeting Abstracts MA2022-02, no. 36 (October 9, 2022): 1343. http://dx.doi.org/10.1149/ma2022-02361343mtgabs.
Full textAbstract:
Alternative channel materials for future ultra-scaled electronic devices have been intensively pursued nowadays since the feature size of silicon-based transistors has been scaled down to their physical limit. Atomically-thin semiconducting transitional metal dichalcogenides (TMDCs) including WS2, MoS2, WSe2, MoSe2, e. have shown a lot of unique properties compared to their bulk crystals, such as indirect-to-direct bandgap transitions, strong spin-orbit coupling and valley polarization. In particular, monolayer WS2 has shown the highest theoretical room temperature electron mobility among other semiconducting TMDCs as a result of its low effective mass. Combined with the large exciton/trion binding energy with high photoluminescence quantum yield, monolayer WS2 is a strong candidate as a potential channel material for high-efficiency optoelectronic applications. However, it is still challenging to grow wafer-sized, highly uniform and strictly monolayer TMDCs continuous film through the conventional chemical vapor deposition (CVD) due to the uncontrollable growth kinetics. The evaporation rates and amounts of the heated precursors are uncontrollable because the saturation vapor pressure of the precursor is exponentially dependent on the temperature inside the furnace. The sulfurized film is thus consisted of a mixture of monolayer, bilayer and multiple layers of TMDCs. The film with such unreproducible quality is not applicable for real industrial applications. In this work, we provide a self-limiting growth strategy based on modified CVD process to prepare the wafer-sized monolayer TMDCs. Theoretical simulations were performed to understand the fundamental thermodynamically mechanism of the strictly monolayer growth. The property-variation in TMDCs due to difference in electronic structure between different layers of TMDCs can be significantly reduced based on this new approach. The following figure indicates that the PL spectra detected from different spots (spot 1 to 5) of the WS2 film. All spectra measured from the 4'' wafer-sized sample show characteristics unique to monolayer WS2. This poses a reliable route for the growth of large-area monolayer TMDCs, which is essential for their reliable and robust applications in nanoelectronic devices. Figure 1
6
Choy, JUN-HO, Valeriy Sukharev, Armen Kteyan, Stephane Moreau, and Catherine Brunet-Manquat. "(Invited, Digital Presentation) Advanced Methodology for Assessing Chip Package Interaction Induced Stress Effects on Chip Performance and Reliability." ECS Meeting Abstracts MA2022-02, no. 17 (October 9, 2022): 846. http://dx.doi.org/10.1149/ma2022-0217846mtgabs.
Full textAbstract:
In IC industry, the use of multiple die stack packaging has emerged to meet the increasing demand in miniaturization and improved functionality of mobile devices. During chip operation, transistor power dissipation raises temperature unevenly across a die. The generated thermal hotspots negatively impact reliability and degrade performance. In mechanical aspects, dies become thinner, and bumps and pitch become smaller, which makes heat dissipation more difficult, and lead to increase in mechanical stress. Such stress may cause carrier mobility degradation for transistors and could lead to parametric circuit failure. In the back-end-of-line (BEoL) interconnects, the employed ultra-low k materials prone to damage interconnects when mechanical stress is present, due to its brittle nature and poor adhesion to the barrier materials. These stresses originated at the die packaging step due to thermal mismatch between die and package materials, which is termed as chip package interaction (CPI). We call mechanical CPI (mCPI) when such stress affects reliability of the whole chip, i.e., BEoL, RDL (redistribution layer), bump, or TSVs (through silicon vias). When such stress affects device performance, we call electrical CPI (eCPI). To analyze CPI effects on a feature scale, i.e., in transistor channel or in the individual metal line or ILD (inter layer dielectric) /IMD (inter metal dielectric) gap, an analysis tool must generate accurate feature-scale stress variation across a die. Finite element analysis (FEA) is widely used for analyzing CPI induced problems. However, the traditional FEA cannot effectively handle feature-scale geometries due to huge memory consumption, and instead, treats a die as a uniform material block. Therefore, this approach cannot describe stress distribution caused by local non-uniformity of metal line distribution and fail to provide the needed accuracy for feature-scale analysis. [1] Here, we present an advanced physics-based EDA tool that overcomes the above-mentioned problems by introducing the novel methodology of extracting effective anisotropic thermal-mechanical properties (EMP), as well as employing FEA-based multi-scale simulation procedure. Prior to running FEA, the tool extracts EMP that accurately represent non-uniformities at different scales within a simulation domain. Here, each metal layer in a die is considered a binary system that consists of metal inclusions embedded in an insulator matrix. By dividing the die area into bins, metal density dependent effective properties for each bin are calculated according to theory of anisotropic composite materials. Anisotropy of properties can be obtained by taking routing direction of metal lines into account [2, 3]. EMP can adjust to multi-scale by varying bin size as shown in Fig.1. Here, Young’s modulus is extracted globally with coarse grid, and on sub-modeling region with very fine grid, which shows the corresponding property variation with much finer scale. Since EMP constructs no actual geometrical objects, the methodology can efficiently handle feature-scale objects on a large layout region. When a user selects a circuit block, or a region to be analyzed in detail, the automated tool flow enables two step stress simulation procedure, which is schematically shown in Fig. 2. First, the global-scale stress simulation is performed with coarse both the simulation mesh and EMP bin and extracts the boundary displacements for the circuit block. These boundary displacements are employed in the sub-modeling, with employed fine mesh and EMP bin. Figure 3 demonstrates the importance of EMP for accurate resolution of stress field. The 2D color maps show the x-component of stress distributions in a circuit block as a result of sub-modeling. Here, die BEoL is represented by EMP in (a), while in (b), the entire die including BEoL is represented by silicon, which is employed in traditional FEA. The stress pattern due to interconnect layout details are visible only when EMP is employed. The difference is even more pronounced when 1D stress profile is compared. By back annotating the obtained stress components in a SPICE netlist, the tool enables a user to perform accurate circuit simulation with accounted CPI effects. In eCPI analysis, the tool has been validated by employing measurements of different types of devices [4]. The additional tool capabilities that will be presented are mCPI analysis and thermomechanical stress analysis during chip operating conditions. [1] R. Radojcic, More-than-Moore 2.5D and 3D SiP Integration, Springer, 2017. [2] V. Sukharev et al. J. Electron Test, vol. 28, pp. 63-72, 2012 [3] V. Sukharev et al., Proc. Int. 3D Systems Integration Conference, 2019 [4]. A. Kteyan, et al. Proc. ISPD 2022 Figure 1
7
Wulf, Ulrich, and Hans Richter. "Scaling in Quantum Transport in Silicon Nano-Transistors." Solid State Phenomena 156-158 (October 2009): 517–21. http://dx.doi.org/10.4028/www.scientific.net/ssp.156-158.517.
Full textAbstract:
We develop a theory for scaling properties of quantum transport in nano-field effect transistors. Our starting point is a one-dimensional effective expression for the drain current in the Landauer-Büttiker formalism. Assuming a relatively simple total potential acting on the electrons the effective theory can be reduced to a scale-invariant form yielding a set of dimensionless control parameters. Among these control parameters are the characteristic length l and -width w of the electron channel which are its physical length and -width in units of the scaling length . Here is the Fermi energy in the source contact and is the effective mass in the electron channel. In the limit of wide transistors and low temperatures we evaluate the scale-invariant i-v characteristics as a function of the characteristic length. In the strong barrier regime, i. e. for long-channel behavior is found. At weaker barriers source-drain tunneling leads to increasingly significant deviations from the long-channel behavior.
8
Zhu, Yan, and Mantu K. Hudait. "Low-power tunnel field effect transistors using mixed As and Sb based heterostructures." Nanotechnology Reviews 2, no. 6 (December 1, 2013): 637–78. http://dx.doi.org/10.1515/ntrev-2012-0082.
Full textAbstract:
AbstractReducing supply voltage is a promising way to address the power dissipation in nano-electronic circuits. However, the fundamental lower limit of subthreshold slope (SS) within metal oxide semiconductor field effect transistors (MOSFETs) is a major obstacle to further scaling the operation voltage without degrading ON/OFF ratio in current integrated circuits. Tunnel field-effect transistors (TFETs) benefit from steep switching characteristics due to the quantum-mechanical tunneling injection of carriers from source to channel, rather than by conventional thermionic emission in MOSFETs. TFETs based on group III-V compound semiconductor materials further improve the ON-state current and reduce SS due to the low band gap energies and smaller carrier tunneling mass. The mixed arsenide/antimonide (As/Sb) InxGa1-xAs/GaAsySb1-y heterostructures allow a wide range of band gap energies and various staggered band alignments depending on the alloy compositions in the source and channel materials. Band alignments at source/channel heterointerface can be well modulated by carefully controlling the compositions of the mixed As/Sb material system. In particular, this review introduces and summarizes the progress in the development and optimization of low-power TFETs using mixed As/Sb based heterostructures including basic working principles, design considerations, material growth, interface engineering, material characterization, device fabrication, device performance investigation, band alignment determination, and high temperature reliability. A review of TFETs using mixed As/Sb based heterostructures shows superior structural properties and distinguished device performance, both of which indicate the mixed As/Sb staggered gap TFET as a promising option for high-performance, low-standby power, and energy-efficient logic circuit application.
9
Pakmehr, Mehdi, B. D. McCombe, Olivio Chiatti, S. F. Fischer, Ch Heyn, and W. Hansen. "Characterization of High Mobility InAs/InGaAs/InAlAs Composite Channels by THz Magneto-Photoresponse Spectroscopy." International Journal of High Speed Electronics and Systems 24, no. 01n02 (March 2015): 1520004. http://dx.doi.org/10.1142/s0129156415200049.
Full textAbstract:
Inserted narrow InAs quantum wells in InAs/InGaAs/InAlAs heterostructures have been used to achieve higher mobility for high-electron-mobility transistors (HEMTs) with ultra-low-power and low-noise amplification characteristics and for spin-based devices. Due to the large nonparabolicity of the conduction band of InAs and the penetration of the confined electronic envelope function into the adjacent layer(s), accurate calculations of effective mass and g-factor of charge carriers can be problematic. Methods of making precise determinations of the mass and other electronic parameters are thus of interest. We have applied magneto-photoresponse and -transmissions measurements at several THz laser frequencies in concert with dc magnetotransport measurements at low temperature (T = 1.6 K) to determine various electronic parameters (effective mass, carrier density, g-factor, mobility and the quantum scattering time) of the 2DEG in an InAs/In0.75Ga0.25As/In0.75Al0.25As inserted channel structure. This characterization method can also be used to probe the effect of strain, Rashba field, etc on the properties of charge carriers in such structures.
10
John Chelliah, Cyril R. A., and Rajesh Swaminathan. "Current trends in changing the channel in MOSFETs by III–V semiconducting nanostructures." Nanotechnology Reviews 6, no. 6 (November 27, 2017): 613–23. http://dx.doi.org/10.1515/ntrev-2017-0155.
Full textAbstract:
AbstractThe quest for high device density in advanced technology nodes makes strain engineering increasingly difficult in the last few decades. The mechanical strain and performance gain has also started to diminish due to aggressive transistor pitch scaling. In order to continue Moore’s law of scaling, it is necessary to find an effective way to enhance carrier transport in scaled dimensions. In this regard, the use of alternative nanomaterials that have superior transport properties for metal-oxide-semiconductor field-effect transistor (MOSFET) channel would be advantageous. Because of the extraordinary electron transport properties of certain III–V compound semiconductors, III–Vs are considered a promising candidate as a channel material for future channel metal-oxide-semiconductor transistors and complementary metal-oxide-semiconductor devices. In this review, the importance of the III–V semiconductor nanostructured channel in MOSFET is highlighted with a proposed III–V GaN nanostructured channel (thickness of 10 nm); Al2O3 dielectric gate oxide based MOSFET is reported with a very low threshold voltage of 0.1 V and faster switching of the device.
11
Shikoh, Ali Sehpar, Gi Sang Choi, Sungmin Hong, Kwang Seob Jeong, and Jaekyun Kim. "High-sensitivity hybrid PbSe/ITZO thin film-based phototransistor detecting from 2100 to 2500 nm near-infrared illumination." Nanotechnology 33, no. 16 (January 24, 2022): 165501. http://dx.doi.org/10.1088/1361-6528/ac47d3.
Full textAbstract:
Abstract We report that high absorption PbSe colloidal quantum dots (QDs) having a peak absorbance beyond 2100 nm were synthesized and incorporated into InSnZnO (ITZO) channel layer-based thin film transistors (TFTs). It was intended that PbSe QDs with proportionally less photocurrent modulation can be remedied by semiconducting and low off-current ITZO-based TFT configuration. Multiple deposition scheme of PbSe QDs on ITZO metal oxide thin film gave rise to nearly linear increase of film thickness with acceptably uniform and smooth surface (less than 10 nm). Hybrid PbSe/ITZO thin film-based phototransistor exhibited the best performance of near infrared (NIR) detection in terms of response time, sensitivity and detectivity as high as 0.38 s, 3.91 and 4.55 × 107 Jones at room temperature, respectively. This is indebted mainly from the effective diffusion of photogenerated carrier from the PbSe surface to ITZO channel layer as well as from the conduction band alignment between them. Therefore, we believe that our hybrid PbSe/ITZO material platform can be widely used to be in favour of incorporation of solution-processed colloidal light absorbing material into the high-performance metal oxide thin film transistor configuration.
12
Bermundo, Juan Paolo, Dianne Corsino, Umu Hanifah, and Yukiharu Uraoka. "(Invited) High Performance Fully Solution Processed Transistors Towards Flexible Sustainable Electronics." ECS Meeting Abstracts MA2022-02, no. 35 (October 9, 2022): 1279. http://dx.doi.org/10.1149/ma2022-02351279mtgabs.
Full textAbstract:
The shift towards a human-centered society promotes greater interconnectedness between people and the digital space. Modern devices such as displays and sensors in which thin-film transistors (TFT) are key materials have crucial roles in the next-generation society because displays are used as both information terminals and interface for human-device interactions while sensors gather data. Furthermore, there is growing interest in neuromorphic devices which aim to mimic the human brain’s efficiency in simultaneously processing and memorizing information to address the von Neumann bottleneck pervasive in modern computing architecture [1]. Amorphous oxide semiconductors (AOS) have gained attention as excellent materials for TFT [2], memory [3], sensing [4], and neuromorphic [5] applications for their superb combination of electrical performance and transparency. Currently, AOS devices are still mainly fabricated using vacuum process. To achieve high throughput and cost-effective production of numerous ubiquitous devices necessary in the next-generation society, an alternative fabrication process is needed. Solution process is an exceptional candidate because of its: (i) efficient production with cost-effective equipment, (ii) large material utilization (low waste) since it can be an additive process compared to vacuum process (high waste), and (iii) low temperature processability for flexible applications in healthcare, energy, and electronics. However, solution process still has major issues such as inferior performance and reliability compared with vacuum process. Several processes have been developed to address these issues but are mostly focused on improving performance and usually limited to a single solution processed device layer – the channel or gate insulator [6]. Thus, many still opt for vacuum process or a single solution processed layer as a compromise. For truly high throughput fabrication, all device layers should be fabricated by solution process. In reality, fully solution-processed TFTs are challenging to fabricate, have dismal performance (mobility (μ) < 1 cm2/Vs), and poor reliability. Therefore, high temperature (>400 °C) process and exotic materials are required for decent μ <10 cm2/Vs which precludes their use in high performance flexible device applications [7]. Here, we present how photo-assisted methods through UV treatment and excimer laser annealing (ELA) can selectively transform AOS regions at low substrate temperatures [8]. Consequently, a single AOS film acts as both the semiconductor channel and conducting electrode to realize fully solution processed TFTs with μ of ~40 cm2/Vs (see Fig. 1) [9]. We also show how alternative methods can be used to enhance the performance and stability of fully solution processed TFTs on rigid/flexible substrates. In particular, how low temperature processes such as light, plasma, and material design of functional materials enable high throughput solution processing of flexible electronic devices. Acknowledgment This research was supported by JSPS Kakenhi Grant no. 22K14291. References [1] J. von Neumann, IEEE Ann. Hist. Comput. 15, 27 (1993). [2] K. Nomura et al. Nature 432, 488–492 (2004). [3] C. H. Kim et al Appl. Phys. Lett. 97, 062109 (2010) [4] R. Jaisutti et al ACS Appl. Mater. Interfaces 8, 20192–20199 (2016) [5] M. Lee et al Adv. Mater. 29, 1700951 (2017) [6] J. W. Park et al Adv. Funct. Mater. 30, 1904632 (2020). [7] S. J. Lee et al ACS Appl. Mater. Interfaces 8, 12894 (2016) [8] J. P. Bermundo et al ACS Appl. Mater. Interfaces 10, 24590 (2018) [9] D. Corsino et al ACS Appl. Electron. Mater., 2, 2398 (2020) Figure 1
13
Kuo, Chil-Chyuan, and Yi-Jun Zhu. "Characterization of Epoxy-Based Rapid Mold with Profiled Conformal Cooling Channel." Polymers 14, no. 15 (July 26, 2022): 3017. http://dx.doi.org/10.3390/polym14153017.
Full textAbstract:
Based on the experience of the foundry industry, reducing the demolding time is the key for mass production of wax patterns with sophisticated geometries. Integration of numerical simulation and rapid tooling technology for decreasing the time to market is essential in advanced manufacturing technology. However, characterization of epoxy-based rapid molds with a profiled conformal cooling channel (PCCC) using computer-aided engineering simulation of the epoxy-based rapid mold with PCCC was not found in the literature. In this study, epoxy-based rapid molds with PCCC were characterized numerically and experimentally. The cooling performance of wax injection molds with two different kinds of cross-sections of the cooling channel was investigated. Four pairs of injection molds with PCCC were implemented using four different kinds of material formulations. It was found that the cooling performance of the PCCC was better than a circular conformal cooling channel (CCCC) since the PCCC maintained a more uniform and steady cooling performance of injection-molded product than CCCC. Epoxy resin added with 41 vol.% Cu powder seems to be a cost-effective empirical material formulation in terms of cooling time and material costs. This empirical material formulation provided an injection mold with low material cost and good cooling performance simultaneously compared to an injection mold fabricated with commercial material. The cooling performance could reach 88% of that of the injection mold fabricated with commercial material. The material cost of making the injection mold was only about 60% of that of the injection mold fabricated with commercial material. The coolant flow rate had no significant effect on the cooling time, whereas the cooling time of the wax pattern was affected by coolant temperature significantly.
14
Gadzhiev, M. Kh, A. S. Tyuftyaev, Yu M. Kulikov, M. A. Sargsyan, D. I. Yusupov, N. A. Demirov, and E. E. Son. "Lowtemperature plasma generator for effective processing of materials." Ferrous Metallurgy. Bulletin of Scientific , Technical and Economic Information 77, no. 5 (May 26, 2021): 587–92. http://dx.doi.org/10.32339/0135-5910-2021-5-587-592.
Full textAbstract:
Low-temperature plasma is used in metallurgy for steel alloying by nitrogen, deoxidization of magnetic alloys, obtaining of steels with particularly low carbon content, metal cleaning of nonmetallic inclusions, desulfurization and other refining processes. The wide application of those technologies is restrained by absence of reliable generators of low-temperature plasma (GLP) with sufficient resource of continuous operation. As a result of studies, a universal generator of high-enthalpy plasma jet of various working gases was created. The generator has expanding channel of the output electrode with an efficiency of ~60 % for argon working gas and ~80% for nitrogen and air. It was shown that the developed generator of low-temperature plasma ensures formation of a weakly diverging (2α = 12°) plasma jet with a diameter D = 5–12 mm, an enthalpy of 5–50 kJ/g and a mass average temperature of 5–10 kK, at a full electric power of the arc discharge of 5–50 kW and a plasma-forming gas flow rate of 1–3 g/s. Results of the study of propane additions to the plasma-forming gas effect on the state of cathodes with inserts made of pure tungsten, lanthanum tungsten, and hafnium presented. It was shown that a small propane addition (1%) to the plasma-forming gas, results in reducing effect of the insert material. Study of the GLP operation at arc current 100A with addition to the working gas nitrogen maximum possible volume of propane, which don’t disturb stability of arc showed that for the developed plasma generator at the nitrogen flow rate ~0,45 g/s, the propane flow rate was ~0,33 g/s (not more than ~73 % of the plasma-forming gas). The created high-resource GLP with changeable electrodes enables to obtain at the exit a high-enthalpy plasma flow of various gases (argon, nitrogen, air) and can be a prototype of more powerful plasmotrons of various technological application, in particular for plasma metallurgy.
15
Ito, Kosuke, Noah Utsumi, and Masashi Yoshida. "Development of Forming Method for Aluminum Alloy Channel with Curvature and Modified Cross-Section Shape in Rotary Draw Bending." Advanced Materials Research 1110 (June 2015): 130–35. http://dx.doi.org/10.4028/www.scientific.net/amr.1110.130.
Full textAbstract:
In the manufacturing industry, metal cross-sections and profiles are manufactured by using extrusion as the primary process. Subsequently, the products are generally subjected to bending in a secondary process. However, long products with the same cross-sections are typically mass-produced by one extrusion. In industries that manufacture such products, there have been increasing demands for flexible manufacturing systems that can be used for low-volume diverse products. However, it is difficult to adapt traditional manufacturing systems to this requirement. In this study, we aimed to develop a new bending method that can be used to deform the cross-sections of existing versatile extruded sections, such as channel materials and rectangular tubes, to several types of cross-sectional shapes and to simultaneously impose a desired curvature on them. The rotary draw bending process for an aluminum alloy channel material without tensile flanges was investigated by using the finite element method and experiments. The effects of the bend angle and thickness ratio on the cross-sectional deformation were examined. Furthermore, the influence of additional axial tension on the channel materials was studied. Additional axial tension can be used to control the outward and inward deformations of the webs. In addition, it was confirmed that the axial tension is very effective in preventing wrinkling and folding.
16
Hamlin, Andrew Bradford, Youxiong Ye, Julia Elizabeth Huddy, and William Joseph Scheideler. "Modulation Doped 2D InOx/GaOx Heterostructure Tfts Via Liquid Metal Printing." ECS Meeting Abstracts MA2022-01, no. 31 (July 7, 2022): 1326. http://dx.doi.org/10.1149/ma2022-01311326mtgabs.
Full textAbstract:
Indium gallium zinc oxide (IGZO) and similar wide bandgap metal oxides are among the most widely used channel materials for drive transistors in displays due to their excellent electronic mobility and their ultra-high transparency1. However, industry-standard processing involves expensive vacuum deposition and elevated activation temperatures to produce semiconducting thin films. Liquid metal printing (LMP) is an emerging technique for oxide semiconductor fabrication poised to overcome these drawbacks via scalable vacuum-free transfer of the native oxide layers formed by spontaneous surface oxidation of molten metals2–4. Heterostructures of these 1-4 nm 2D oxide layers provide unprecedented opportunities for engineering electrostatic control of multilayers in thin film transistors, leading to improved mobility, Ion/Ioff ratios, and faster switching capabilities. Likewise, the backchannel is of high importance to these devices, as selection of an appropriate capping layer can enhance performance via remote doping while also mitigating bias stress effects. Herein, we compare the results of heterostructure InOx/GaOx with pure InOx TFTs, which demonstrates the mobility enhancement provided by GaOx modulation doping. Bottom gate thin film transistors (TFTs) (Figures 1a and 1b) were fabricated on Si substrates with 100 nm of thermally grown SiO2. 4 nm thick InOx and GaOx were deposited at 240 ˚C and 180 ˚C, respectively, using a linear printing speed of 8 cm/s. InOx and GaOx were printed in less than 10 s, with no post annealing necessary. Figure 1c illustrates the proposed mechanism for electron donation from GaOx at the heterointerface with InOx. The conduction band offset between these materials results in band bending at the interface and an increased carrier concentration in the InOx layer. The substoichiometric, defective GaOx is expected to further enhance this effect. Figure 1d demonstrates the transfer characteristics of heterostructure InOx/GaOx in comparison with pure InOx. The improved mobility for the heterostructure (7.8 cm2/Vs) vs pure InOx (3.8 cm2/Vs) channels can be attributed to modulation doping provided by GaOx and can be analyzed by extracting the electronic density of states (eDOS). These results illustrate a unique capability of LMP, which is to engineer the electronic structure of highly conductive 2D oxides while maintaining electrostatic control. This work also investigates the material properties of these 2D oxide heterostructures by UV-vis, XRD and XPS characterization. UV-Vis analysis revealed that the GaOx capping layer induces band gap widening and enhanced transparency, which can be explained by the Burstein-Moss effect from modulation doping. Unique to this LMP process is also the low temperature crystallization of the InOx films. XRD showed that even with low deposition temperatures (200 – 240 ˚C), these InOx films are highly crystalline with grain sizes substantially larger than the film thickness. Finally, XPS analysis of the O1s peak was utilized to understand the stoichiometry and interactions between the InOx and GaOx layers. This work demonstrates an effective pathway to enhance electronic transport in semiconducting metal oxides through liquid metal printed 2D heterostructures. The ultrathin films produced by LMP are well suited for thin film devices requiring nm-scale electrostatic control for effective gating. Combining this 2D nature of LMP InOx with a 2D GaOx backchannel capping layer is shown to yield high-performance printed transistors. This approach demonstrates a rapid, open-air compatible and low temperature manufacturing method, elucidating the broad impact of this technology in display fabrication, low-cost and flexible electronics. H. Hosono, Nat Electron, 1, 428–428 (2018). K. A. Messalea et al., ACS Nano, 15, 16067–16075 (2021). R. S. Datta et al., Nat Electron, 3, 51–58 (2020). A. Jannat et al., ACS Nano, 15, 4045–4053 (2021). A. Goff et al., Dalton Transactions, 50, 7513–7526 (2021). C.-H. Choi, Y.-W. Su, L.-Y. Lin, C.-C. Cheng, and C. Chang, RSC Advances, 5, 93779–93785 (2015). Figure 1
17
Liao, Chun-Da, Andrea Capasso, Tiago Queirós, Telma Domingues, Fatima Cerqueira, Nicoleta Nicoara, Jérôme Borme, Paulo Freitas, and Pedro Alpuim. "Optimizing PMMA solutions to suppress contamination in the transfer of CVD graphene for batch production." Beilstein Journal of Nanotechnology 13 (August 18, 2022): 796–806. http://dx.doi.org/10.3762/bjnano.13.70.
Full textAbstract:
Mass production and commercial adoption of graphene-based devices are held back by a few crucial technical challenges related to quality control. In the case of graphene produced by chemical vapor deposition, the transfer process represents a delicate step that can compromise device performance and reliability, thus hindering industrial production. In this context, the impact of poly(methyl methacrylate) (PMMA), the most common support material for transferring graphene from the Cu substrate to any target surface, can be decisive in obtaining reproducible sample batches. Although effective in mechanically supporting graphene during the transfer, PMMA solutions needs to be efficiently designed, deposited, and post-treated to serve their purpose while minimizing potential contaminations. Here, we prepared and tested PMMA solutions with different average molecular weight (AMW) and weight concentration in anisole, to be deposited by spin coating. Optical microscopy and Raman spectroscopy showed that the amount of PMMA residues on transferred graphene is proportional to the AMW and concentration in the solvent. At the same time, the mechanical strength of the PMMA layer is proportional to the AMW. These tests served to design an optimized PMMA solution made of a mixture of 550,000 (550k) and 15,000 (15k) AMW PMMA in anisole at 3% concentration. In this design, PMMA-550k provided suitable mechanical strength against breakage during the transfer cycles, while PMMA-15k promoted depolymerization, which allowed for a complete removal of PMMA residues without the need for any post-treatment. An XPS analysis confirmed the cleanness of the optimized process. We validated the impact of the optimized PMMA solution on the mass fabrication of arrays of electrolyte-gated graphene field-effect transistors operating as biosensors. On average, the transistor channel resistance decreased from 1860 to 690 Ω when using the optimized PMMA. Even more importantly, the vast majority of these resistance values are distributed within a narrow range (only ca. 300 Ω wide), in evident contrast with the scattered values obtained in non-optimized devices (about 30% of which showed values above 1 MΩ). These results prove that the optimized PMMA solution unlock the production of reproducible electronic devices at the batch scale, which is the key to industrial production.
18
Liu, Cheewee, Chien-Te Tu, Bo-Wei Huang, and Chun-Yi Cheng. "(Digital Presentation) Stacked Nanosheet FETs and Beyond." ECS Meeting Abstracts MA2022-02, no. 32 (October 9, 2022): 1193. http://dx.doi.org/10.1149/ma2022-02321193mtgabs.
Full textAbstract:
Si FinFETs have been used in the industry for mass production of advanced technology nodes [1-3]. Recently, the horizontal gate-all-around (GAA) transistors are considered as promising candidates to replace FinFETs due to the excellent electrostatics and short channel control [4-6]. The GAA architecture with vertically channel stacking can further enhance the drive current for a given footprint to achieve high performance and area scaling [7]. Moreover, high mobility channel is an attractive option to boost the drive current thanks to its intrinsic higher mobility as compared with Si [8]. Furthermore, a novel TreeFET architecture [9] as a combination of stacked nanosheets and additional fin interbridges (IBs) between nanosheets can enhance ION per footprint. In this work, we demonstrate the 8 stacked Ge0.75Si0.25 nanosheets with high inter-channel uniformity and the 7 stacked Ge0.95Si0.05 nanowires with record ION per channel footprint for nFETs [10, 11]. The highly stacked 8 Ge0.9Sn0.1 nanosheet pFET with ultrathin bodies and thick bodies are demonstrated for low power and high performance [12, 13], respectively. Furthermore, TreeFETs can increase Weff per footprint for high performance devices beyond FinFETs and nanosheets. The epilayers with 8 undoped and fully strained Ge0.75Si0.25 layers sandwiched by 9 P-doped Ge sacrificial layers (SL) were grown on the Ge buffer by CVD epitaxy. The S/D and channels of the 8 stacked Ge0.75Si0.25 nanosheets are fabricated by the same epilayer structures without S/D regrowth. The doping of S/D is obtained by the heavily P-doped Ge SLs by annealing, while the channel is undoped to reduce the impurity scattering. H2O2 wet etching was used to etch the Ge SLs in channel region. The etching selectivity of Ge over Ge0.75Si0.25 is attributed to the Si content in GeSi layers and the enhanced etching rate of Ge SLs by heavily doped phosphorus [14]. To further improve the drive current, [Si] in GeSi channels is decreased to 5% to ensure the electrons populated in L4 valleys with small mt. In addition to channel stacking, TreeFET combining with FinFETs and stacked nanosheets is demonstrated to enhance Weff per footprint. IBs of TreeFETs were formed by well-controlled H2O2 wet etching. With adequate etching selectivity and optimized etching time, the SLs were partially removed to form the IBs between the nanosheets for extra conduction channels. Strained GeSn has higher hole mobility than Ge to increase ION for pFET [15] due to the hole effective mass reduction under compressive strain. Recently, the radical-based highly selective isotropic dry etching (HiSIDE) was reported to form the stacked GeSn nanosheets [16-18]. However, the challenge of Ge-based channel is the large IOFF due to the small bandgap [15-20]. Ultrathin body device can effectively reduce the IOFF [21], but the mobility degradation is observed as the channel thickness decrease below 5nm due to surface roughness scattering [22]. However, the high mobility GeSn can afford some mobility loss due to the ultrathin body. By combining the high mobility channel and the large number of stacked nanosheets, the ION can be further improved with the suppression of IOFF by the ultrathin body. The 11nm Ge0.9Sn0.1 channel layers sandwiched by 8nm Ge0.97Sn0.03 caps, 3nm Ge caps, and 24nm Ge:B SLs were grown repeatedly on the Ge buffer. The thin double Ge0.97Sn0.03 caps can provide sufficient etching selectivity and prevent the channel bending. The heavily B-doped Ge SLs are used to reduce the S/D resistance. The significant IOFF reduction of the GeSn ultrathin bodies is attributed to the quantum confinement effects. The quantum confinement energy of 170meV in 3nm Ge0.9Sn0.1 ultrathin body is simulated by TCAD. The enlarged bandgap results in the suppression of IOFF and yields the record high ION/IOFF~107 of 8 stacked GeSn ultrathin bodies among GeSn/Ge 3D pFETs. Simple wet etching can reach the sufficient selectivity to fabricate the highly uniform Ge0.75Si0.25 nanosheets and the Ge0.95Si0.05 nanowires. The 3nm Ge0.9Sn0.1 ultrathin bodies with high inter-channel uniformity are demonstrated to reduce the IOFF. Highly stacked Ge0.9Sn0.1 thick nanosheets can improve the ION. TreeFET with the process flow similar to stacked nanosheets are the promising candidates for technology node scaling. Even higher number of stacked channels (>8) and extremely scaled ultrathin bodies (<3nm) are expected to further enhance the ION and to increase the ION/IOFF for advanced CMOS scaling. Acknowledgements- This work is supported by MOST (110-2218-E-002-030-, 110-2622-8-002-014-, 110-2218-E-002-034-MBK, and 110-2218-E-002-042-MBK) and MOE (NTU-CC-111L892001), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated. Figure 1
19
Andricek, Ladislav. "All-silicon multi-chip modules based on ultra-thin active pixel radiation sensors." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (January 1, 2014): 000960–83. http://dx.doi.org/10.4071/2014dpc-tp31.
Full textAbstract:
The Semiconductor Laboratory of the Max Planck Society is designing and producing cutting edge radiation and particle sensors for experiments in basic science conducted by institutes of the German Max Planck Society and other international partners. One of the most challenging projects is the construction of so-called vertex detectors for experiments at high energy particle colliders like KEKB in Japan and the future International Linear Collider (ILC) as the next big international high energy physics project after the LHC at CERN, Geneva, Switzerland. Modern vertex detectors are pixelated position sensitive particle sensors based on highly specialized silicon technology similar to CMOS or CCD sensors for commercial optical applications. The goal is to measure the track of a secondary particle and extrapolate to the point of its origin. One of the main challenges for up-to-date vertex detectors is the requirement of low mass to minimize the effect of scattering of the traversing particle in the sensor material itself and the sensor support structures. We are developing ultra-low-mass sensors based on the DEPFET (DEpleted P-channel FET) pixel technology. DEPFETs are MOS transistors made on fully depleted detector grade silicon and combine the sensing and first signal amplification element in the same device. The thickness of the sensor is minimized and optimized for the best vertexing performance of the detector arrangement as whole. The detector is a cylindrical arrangement of sensor modules around the primary beam interaction point. The sensor module is a silicon based multi-chip module with the module substrate being the sensor wafer itself. There are three functional regions on the MCM: the 50 μm thin sensitive active pixel area with the DEPFETs in a two metal and two poly-silicon layer technology, the ‘end of stave’ with three metal layers (two Al and one Cu) where the read-out electronic is placed and the narrow frame in the same interconnect technology with the steering ASICs. Three types of ASICs are used: a mixed-signal ASICs as the analogue front-end and ADC, a digital data handling chip and a steering chip in HV-MOS technology for the row-wise addressing and clearing of the pixel matrix. There are 12 chips in total on the module, all bump-bonded to the substrate, about 3000 area array bumps in total. The finished module has 250 kPixels and is read out at a frame rate of 50 kHz via a wire-bonded flex cable. Our paper will describe the technology for the production of ultra-thin DEPFET sensors and the monolithically integrated support, testing challenges during production and their solutions as well as electrical, thermal, and mechanical properties of the assembled MCMs. An outlook will be given on how micro-channels for active cooling will be integrated in the current MCM concept.
20
Glasser, Neil F., and Matthew R. Bennett. "Glacial erosional landforms: origins and significance for palaeoglaciology." Progress in Physical Geography: Earth and Environment 28, no. 1 (March 2004): 43–75. http://dx.doi.org/10.1191/0309133304pp401ra.
Full textAbstract:
Glacial inversion modelling of continental-scale palaeo-ice sheets is now recognized as an important tool in palaeoglaciology. Existing palaeoglaciological reconstructions of the dimensions, geometry and dynamics of former ice sheets are based mainly on glacial depositional, as opposed to glacial erosional, landforms. Part of the reason for this is a lack of detailed understanding of the origin and significance of glacial erosional landforms. Here we review recent developments in our understanding of the processes and landforms of glacial erosion and consider their value in palaeoglaciology. Glacial erosion involves the removal and transport of bedrock and/or sediment by glacial quarrying, glacial abrasion and glacial meltwater. These processes combine to create a suite of landforms that are frequently observed in areas formerly occupied by ice sheets and glaciers, and which can be used in palaeoglaciological reconstructions. For example, all landforms of glacial erosion provide evidence for the release of subglacial meltwater and the existence of warm-based ice. Landforms of glacial quarrying such as roches moutonnées, rock basins and zones of areal scouring are created when cavities form between an ice sheet and its bed and therefore are indicative of low effective basal pressures (0.1-1 MPa) and high sliding velocities that are necessary for ice-bed separation. Fluctuations in basal water pressure also play an important role in the formation of glacially quarried landforms. Landforms of glacial abrasion include streamlined bedrock features (‘whalebacks’), some ‘p-forms’, striae, grooves, micro-crag and tails, bedrock gouges and cracks. Abrasion can be achieved by bodies of subglacial sediment sliding over bedrock or by individual clasts contained within ice. Although abrasion models depend critically on whether clasts are treated as dependent or independent of subglacial water pressure, it appears that abrasion is favoured in situations where effective basal pressures are greater than 1 MPa and where there are low sliding velocities. Consequently, landforms dominated by glacial abrasion are created when there is no ice-bed separation. Landforms of glacial meltwater erosion include both subglacial and ice-marginal meltwater channels. Investigations of the relationship between glacial meltwater channels and other aspects of the subglacial drainage system, such as areas of ice-bed contact, areas of ice-bed separation and precipitate-filled depressions, enable inferences to be made concerning former subglacial water pressure-drainage relationships, effective pressures and glacier velocities. Meltwater palaeovelocity and palaeodischarge can also be calculated from measurements of channel shape, channel width and the size of material transported within former glacial meltwater channels. We surmize that glacial erosional landforms offer insight into former glacio-logical conditions at both the landform- and landscape-scale within palaeoglaciology. Exposure-age dating techniques, including cosmogenic isotope dating of bedrock surfaces, will be important in increasing our understanding of the age and chronological significance of landforms of glacial erosion. We conclude that landforms of glacial erosion are of great value in ice mass reconstruction and speculate that these landforms will achieve greater recognition within palaeoglaciology in line with improvements in exposure-age dating techniques.
21
Quino, Candell Grace Paredes, Juan Paolo Bermundo, Mutsunori Uenuma, and Yukiharu Uraoka. "Performance Enhancement of Solution-Processed SixSnyO TFTs using Solution Combustion Synthesis." ECS Meeting Abstracts MA2022-02, no. 35 (October 9, 2022): 1280. http://dx.doi.org/10.1149/ma2022-02351280mtgabs.
Full textAbstract:
Amorphous oxide semiconductors thin-film transistors (AOs TFTs) have gained interest over the years because of their advantages over a-Si and poly-Si transistors.In particular, tin oxide is used as a semiconductor material because of its abundance, low toxicity, and high intrinsic mobility. Performance-wise, tin oxide TFTs need improvement because the reported average mobility remains < 10 cm2/Vs.1 Previous research used silicon doping to reduce tin oxide’s oxygen vacancies and improve its performance as a semiconductor channel.Currently, SixSnyO TFTs are fabricated using vacuum process, but solution processing is important to realize large-scale and high-throughput electronics. Sol-gel method is one of the conventional routes to produce solution-processed metal oxides. However, it requires high temperature (≤500°C) to facilitate film densification which is not compatible with flexible substrates having low degradation temperatures. Among the approaches for low-temperature TFT fabrication, solution combustion synthesis (SCS) has garnered significant attention because of its simplicity and versatility.2 SCS uses the energy released by combustion to help the formation of more M-O-M networks in the film. Thus, there is no need to use high temperature to condense and densify the film. This study attempts to produce SixSnyO TFTs through solution processing for the first time. We investigated the effect of solution combustion synthesis to the quality of SixSnyO films. Next, we optimized the aging time and oxidizer to fuel ratio (ammonium nitrate to urea) to determine the films with better quality. For aging time optimization, SixSnyO precursors were stirred at RT for 24-h, 48-h, and 72-h. Lastly, we compared the TFT performance in terms transfer characteristics of SixSnyO TFTs fabricated by sol-gel and SCS annealed at the same temperature. Secondary ion mass spectrometry (SIMS) analysis was used to compare the carbon impurities present in both SixSnyO films. The sol-gel film contained higher amounts of carbon impurities, about an order of magnitude higher as shown in Figure 1. This proves that SCS provides extra energy to help degrade the carbon-containing compounds in the film. Carbon atoms are considered impurities that can introduce defects in the SixSnyO film. These defects are detrimental to the performance characteristics of the fabricated TFT device. In addition, the thickness of the films was determined using X-ray reflectivity. The SCS film is 15.70 nm-thick while the sol-gel film is 18.88-nm thick. Furthermore, optimization of the SixSnyO films via SCS revealed that oxidizer to fuel ratio affects the roughness and amount of M-O bonds formed in the film. The 3:1 ratio failed to produce a film while other ratios were successful in producing films. Although the film with 1:1 ratio has root mean square roughness (Rq) value of 0.380 nm, it contains depressions and voids. On the other hand, the film using a 1:3 ratio showed a uniform and even surface with Rq value of 0.377 nm. In addition, characterization of the two films through X-ray photoelectron spectroscopy (XPS) showed higher percentage of M-O bonds in the O1s spectrum (530.5 eV) for the film with 1:3 ratio. The values are 45.9% and 59.3% for 1:1 and 1:3 ratios, respectively. The amount of oxygen vacancy and H- containing compounds also decreased in the 1:3 film. SixSnyO TFTs were fabricated from both SCS and sol-gel methods. Both TFTs showed high off-current and highly negative Vth, as shown in Figure 1. Therefore, both TFTs still contain several defects which suggests that 3% Si doping may be insufficient and must be increased to produce a significant effect. The sol-gel fabricated TFT also showed lower drain current. Therefore, the low annealing temperature at 300 ˚C is insufficient to densify the film and reduce impurities. On the other hand, SCS-assisted fabrication showed higher mobility at 3.14 cm2/Vs – confirming that SCS provided additional energy to degrade impurities and improve the M-O network in the SixSnyO channel. In conclusion, we were able to produce SixSnyO TFTs with improved mobility using solution combustion synthesis. However, the high V th and high off-current issues need to be addressed by increasing silicon dopant addition and exploring other fuel options. But overall, we can confirm that SCS is beneficial in improving the quality of SixSnyO films annealed at 300 ˚C. In the future, this low temperature fabrication is important to realize flexible SixSnyO TFT devices. Acknowledgements This research was supported by NAIST foundation grant. References Chang, H., et al. ACS Applied Electronic Materials, 3(11), 4943–4949. Carlos, E., et al. Chemistry - A European Journal, 26(42), 9099–9125. Figure 1
22
Akkili, Viswanath G., and Viranjay M. Srivastava. "Design and Performance Analysis of Low Sub-Threshold Swing p-Channel Cylindrical Thin-Film Transistors." Micro and Nanosystems 14 (May 18, 2022). http://dx.doi.org/10.2174/1876402914666220518141705.
Full textAbstract:
Background: Tin monoxide (SnO) attracts considerable interest for p-channel Cylindrical Thin Film Transistors (CTFTs) applications due to their merits, including low hole effective mass, Sn s and O p orbital hybridization at the valance band maxima, and ambipolar nature, among other p-type oxide semiconductors. Objective: This article analyses the influence of channel radius and the impact of dielectric materials on the performance of SnO based CTFT devices through 3D numerical simulations. Methods: The radius of the active layer in the CTFT was varied in the range from 10 nm to 30 nm, and it has been observed that an increase of channel radius reduces the switching behavior of the devices. Results: The 10 nm thick CTFT exhibited superior results with a lower threshold voltage of 1.5 V and higher field-effect mobility of 13.12 cm2/V-s over other simulated CTFTs. Conclusion: The obtained mobility values are superior to the existing planar TFTs reports. To improve the device performance further, the CTFTs with various dielectric materials have been simulated and optimized with high field-effect mobility and low sub-threshold swing values.
23
Wager, John F. "Single‐layer thin‐film transistor analysis and design." Journal of the Society for Information Display, August 24, 2023. http://dx.doi.org/10.1002/jsid.1257.
Full textAbstract:
AbstractA set of direct current (DC) analytical equations is formulated for the analysis and design of a single‐layer thin‐film transistor (TFT). For a specified TFT structure, drain current is calculated as a function of drain and gate voltage (taking the source as ground) according to the Enz, Krummenacher, Vittoz (EKV) compact model. One model parameter function is required to implement this EKV‐based equation, that is, drift mobility as a function of gate voltage. Drift mobility is evaluated as a consequence of accumulation layer electrostatics assessment of the TFT structure specified. In order to implement the model, three semiconductor properties (low‐frequency (static) relative dielectric constant, free electron concentration, and maximum (no trapping) mobility), two structure properties (insulator capacitance density and TFT width‐to‐length ratio), and one physical operating parameter (temperature) must be specified. Optimal TFT mobility performance is achieved when the thickness of the semiconductor channel layer is constrained to be less than 2.22 times the channel layer Debye length such that “short‐base” TFT operation obtains. Additionally, higher mobility TFT performance is obtained by selecting a channel layer with a small electron effective mass, reducing channel layer trap density, reducing channel layer thickness, reducing the free electron concentration, and/or increasing gate capacitance density.
24
Alam, Khairul. "Transport and performance study of double-walled black phosphorus nanotube transistors." Semiconductor Science and Technology, June 9, 2022. http://dx.doi.org/10.1088/1361-6641/ac773e.
Full textAbstract:
Abstract Monolayer- and a few layers-Black Phosphorus is an emerging two-dimensional material for the post-silicon era. We study the transport mechanism and performance metrics of double-walled black phosphorus n-channel and p-channel gate-all-around nanotube transistors using a k·p Hamiltonian and a non-equilibrium Green’s function quantum simulation. We effectively use the anisotropic effective masses along the zigzag and armchair directions of black phosphorus for high performance nanotube field-effect transistors. The heavy mass along the zigzag direction is used for quantization to increase the carrier density, while the lighter mass along the armchair direction is used for transport to maximize the carrier injection velocity. The on-state current is governed by the thermionic transport mechanism over the top of the potential barrier, while the off-state current is predominantly governed by intra-band tunneling current. Although the lighter mass in transport direction initiates intra-band tunneling current, the device can be successfully turned on and off with a high on/off current ratio of 1.4×105. The n-channel transistor has an on-state current of 724 µA/µm, a subthreshold slope of 63 mV/dec, a transconductance of 7.97 mS/µm, a switching delay time of 3.92 ps, a cut-off frequency of 0.201 THz, and a dynamic power loss of 0.64 fJ/µm, respectively. The corresponding performance metrics for the p-channel are 726 µA/µm, 64 mV/dec, 8.20 mS/µm, 3.96 ps, 0.205 THz, and 0.65 fJ/µm. Both the transistors are potential candidates for the ITRS 2026 LOP devices.
25
Nupur Navlakha, Leonard F. Register, and Sanjay K. Banerjee. "Emerging 2D materials for tunneling field effect transistors." Revista Tecnología en Marcha, June 29, 2023. http://dx.doi.org/10.18845/tm.v36i6.6768.
Full textAbstract:
This work focuses on understanding the electronic properties of materials to enhance the performance of Tunnel Field Effect Transistor (TFET) through Density Functional Theory (DFT) simulations. Material selection prefers a p-type material with in-plane high density of state (DOS) (and low out-of-plane effective mass, m*, where defined for many layer systems), and high valence band maxima (VBM) energy stacked with an n-type material with low conduction band minimum (CBM) energy (large electron affinity (EA)) that creates a broken or nearly broken band alignment and has low lattice mismatch. SnSe2 is well-suited for an n-type 2D material due to high EA, while WSe2, Black phosphorous (BP) and SnSe are explored for p-type materials. Bilayers consisting of monolayers of WSe2 and SnSe2 show a staggered but nearly broken band alignment (gap of 24 meV) and a high valence band DOS for WSe2. BP-SnSe2 shows a broken band alignment and benefits from a low lattice mismatch. SnSe-SnSe2 shows the highest chemical stability, an optimal performance in terms of DOS of SnSe, tunability with an external field, and high VBM that also leads to a broken band alignment.
26
"Germanane: A Low Effective Mass and High Bandgap 2-D Channel Material for Future FETs." IEEE Transactions on Electron Devices 61, no. 7 (July 2014): 2309–15. http://dx.doi.org/10.1109/ted.2014.2325136.
Full text
27
Huang, Chunhui, Zeyi Yan, Chengwei Hu, Xiong Xiong, and Yanqing Wu. "Performance and stability improvement of CVD monolayer MoS2 transistors through HfO2 dielectrics engineering." Applied Physics Letters 123, no. 7 (August 14, 2023). http://dx.doi.org/10.1063/5.0157416.
Full textAbstract:
Monolayer molybdenum disulfide (MoS2) is a promising semiconductor channel material for future electronics due to its atomic thickness and high mobility. However, conventional back-gate MoS2 transistors suffer from substantial scattering caused by substrate and surface adsorbates, which impair carrier mobility and device reliability. In this work, we demonstrate an exemplary dielectric engineering approach that uses atomic-layer-deposited hafnium oxide (HfO2) as the gate dielectric and channel passivation layer to improve device performance and positive bias instability. The large-single-crystal monolayer MoS2 film was directly synthesized on SiO2/Si substrates by a low-pressure chemical vapor deposition method. MoS2 transistors with various dielectrics were fabricated and characterized for a fair comparison. The mobility increased from 4.2 to 19.9 cm2/V·s by suppressing charged impurities and phonon scattering when transferring the MoS2 channel from 100 nm SiO2 substrates to 20 nm HfO2 substrates. Passivation of another 10 nm HfO2 on the back-gate transistors further increased the mobility to 36.4 cm2/V·s with a high drive current of 107 μA/μm. Moreover, the threshold voltage shift of the passivated transistor was reduced by about 58% from 1.9 to 0.8 V under positive bias stress. This is due to the fact that channel passivation with HfO2 effectively eliminated charge trapping of adsorbed substances. These results reveal that HfO2 gate dielectric and passivation by atomic-layer deposition are effective methods to improve the performance and stability of MoS2 devices.
28
zhang, wei, Ruohao Hong, Wenjing Qin, Yawei Lv, Jianmin Ma, Lei Liao, Kenli Li, and Changzhong Jiang. "Enhanced performance of p-type SnOx thin film transistors through defect compensation." Journal of Physics: Condensed Matter, July 26, 2022. http://dx.doi.org/10.1088/1361-648x/ac8464.
Full textAbstract:
Abstract Due to the unique outermost orbitals of Sn, hole carriers in tin monoxide (SnO) possess small effective mass and high mobility among oxide semiconductors, making it a promising p-channel material for thin film field-effect transistors (TFTs). However, the Sn vacancy induced field-effect mobility deterioration and threshold voltage (Vth) shift in experiments greatly limit its application in complementary metal-oxide-semiconductor transistors (CMOS). In this study, the internal mechanism of vacancy defect compensation by aluminium (Al) doping in SnOx film is studied combining experiments with the density functional theory (DFT). The doping is achieved by an argon (Ar) plasma treatment of Al2O3 deposited onto the SnOx film, in which the Al2O3 provides both the surface passivation and Al doping source. Experimental results show a wide Vth modulation range (6.08 to −19.77 V) and notable mobility enhancement (11.56 cm2V-1s-1) in the SnOx TFTs after the Al doping by Ar plasma. DFT results reveal that the most possible positions of Al in SnO and SnO2 segments are the compensation to Sn vacancy and interstitial. The compensation will create an n-type doping effect and improve the hole carrier transport by reducing the hole effective mass (mh*), which is responsible for the device performance variation, while the interstitial in the SnO2 segment can hardly affect the valence transport of the film. The defect compensation is suitable for the electronic property modulation of SnO towards the high-performance CMOS application.
29
Jiang, Guanggang, Wei Dou, Xiaomin Gan, Liuhui Lei, Xing Yuan, Wei Hou, Jia Yang, Weichang Zhou, and Dongsheng Tang. "Low-voltage solution-processed P-type Mg-doped CuI thin film transistors with NAND logic function." Applied Physics Letters 122, no. 21 (May 22, 2023). http://dx.doi.org/10.1063/5.0152445.
Full textAbstract:
Low-voltage electric-double-layer (EDL) p-channel Mg-doped CuI thin-film-transistors (TFTs) have been fabricated on glass substrates at low temperatures. Electrical properties of the solution-processed CuI TFTs with different Mg doping concentrations were investigated. It is observed that compared to undoped CuI TFTs and Mg0.1Cu0.9Ix TFTs, Mg0.05Cu0.95Ix TFTs exhibit an excellent current on/off ratio of 1.1 × 105, a steep subthreshold swing of 21.78 mV/dec, a higher saturation field-effect mobility of 0.95 cm2 V−1 s−1, and the threshold voltage of 1.81 V. The high specific capacitance of 4.7 μF/cm2 is obtained in solution-processed chitosan dielectrics; when it was used as the gate dielectric instead of traditional SiO2, the operating voltage of TFTs can be reduced to 2.5 V. It is noteworthy that the NAND logic function has been realized on the dual in-plane-gate structure of such Mg0.05Cu0.95Ix-based TFTs. Finally, the effects of laser (λ = 638 nm) and negative bias stress (NBS) were observed on Mg0.05Cu0.95Ix TFTs. The transfer curves of the TFT drifted positively as the power of the laser progressively increased; the OFF-state current gradually increased as the NBS time became longer. This paper provides an effective way to improve the performance of p-channel CuI TFTs and indicates that Mg0.05Cu0.95Ix as a promising p-type material for next-generation high-performance low-power-consumption logic circuit applications.
30
Song, Okin, Dongjoon Rhee, Jihyun Kim, Youngseo Jeon, Vlastimil Mazánek, Aljoscha Söll, Yonghyun Albert Kwon, et al. "All inkjet-printed electronics based on electrochemically exfoliated two-dimensional metal, semiconductor, and dielectric." npj 2D Materials and Applications 6, no. 1 (September 9, 2022). http://dx.doi.org/10.1038/s41699-022-00337-1.
Full textAbstract:
AbstractInkjet printing is a cost-effective and scalable way to assemble colloidal materials into desired patterns in a vacuum- and lithography-free manner. Two-dimensional (2D) nanosheets are a promising material category for printed electronics because of their compatibility with solution processing for stable ink formulations as well as a wide range of electronic types from metal, semiconductor to insulator. Furthermore, their dangling bond-free surface enables atomically thin, electronically-active thin films with van der Waals contacts which significantly reduce the junction resistance. Here, we demonstrate all inkjet-printed thin-film transistors consisting of electrochemically exfoliated graphene, MoS2, and HfO2 as metallic electrodes, a semiconducting channel, and a high-k dielectric layer, respectively. In particular, the HfO2 dielectric layer is prepared via two-step; electrochemical exfoliation of semiconducting HfS2 followed by a thermal oxidation process to overcome the incompatibility of electrochemical exfoliation with insulating crystals. Consequently, all inkjet-printed 2D nanosheets with various electronic types enable high-performance, thin-film transistors which demonstrate field-effect mobilities and current on/off ratios of ~10 cm2 V−1 s−1 and >105, respectively, at low operating voltage.
31
Proano, R. E., and R. J. Soave. "Fabrication and Properties of Single, Double, and Triple Gate Polycrystalline-Silicon Thin Film Transistors." MRS Proceedings 106 (1987). http://dx.doi.org/10.1557/proc-106-317.
Full textAbstract:
ABSTRACTPolysilicon based Thin Film Transistors (poly-Si TFT's) with superior electrical performance can be achieved by maximizing the number of intrinsic point defect injected into the material during high temperature processing. These point defects will migrate to grain boundaries (GB's), enhance their mobility by facilitating climb, and allow the boundary to achieve a low energy configuration with a minimum of electrically active broken bonds. Proper processing of poly-Si TFT's therefore requires a redesign of the conventional processing cycle where, working with single crystal silicon, one minimizes the concentration of intrinsic point defects which otherwise precipitate out as Oxidation induced Stacking Faults (OSF's).TFT's were fabricated under nine different processing cycles to study the relationship between device performance and fabrication conditions. Device performance increased with higher gate oxidation temperature, elimination of HCI flow during gate oxidation, post hydrogenation, and multiple gates. Using conventional MOS processing steps only, n-type (p-type) devices were fabricated, which were capable of handling 40 volts VDS with a leakage current of 2×10−11 (6×10−12) A/μm and effective electron (hole) channel mobilities of 130 (50) cm2/Vs.
32
Lee, Hyun Jung, Andrei Sazonov, and Arokia Nathan. "Evolution of Structural and Electronic Properties in Boron-doped Nanocrystalline Silicon Thin Films." MRS Proceedings 989 (2007). http://dx.doi.org/10.1557/proc-0989-a21-07.
Full textAbstract:
AbstractWe report on the boron-doping dependence of the structural and electronic properties in nanocrystalline silicon (nc-Si:H) films directly deposited by plasma- enhanced chemical vapor deposition (PECVD). The crystallinity, micro-structure, and dark conductivity of the films were investigated by gradually varying the ratio of trimethylboron [B(CH3)3 or TMB] to silane (SiH4) from 0.1 to 2 %. It was found that the low level of boron doping (< 0.2 %) first compensated the nc-Si:H material which demonstrates slightly n-type properties. As the doping increased up to 0.5 %, the maximum dark conductivity (ód) of 1.11 S/cm was obtained while high crystalline fraction (Xc) of the films (over 70 %) was maintained. However, further increase in a TMB-to-SiH4 ratio reduced ód to the order of 10-7 S/cm due to a phase transition of the films from nanocrystalline to amorphous, which was indicated by Raman spectra measurements.P-channel nc-Si:H thin film transistors (TFTs) with top gate and staggered source/drain contacts were fabricated using the developed p+ nc-Si:H layer. The fabricated TFT exhibits a threshold voltage (VTp) of -26.2 V and field effective mobility of holes (μp) of 0.24 cm2/V·s.
33
Birkhahn, Ronald, David Gotthold, Nathan Cauffman, Boris Peres, and Seikoh Yoshida. "AlGaN/GaN HFETs for Automotive Applications." MRS Proceedings 743 (2002). http://dx.doi.org/10.1557/proc-743-l11.45.
Full textAbstract:
ABSTRACTAlGaN/GaN heterojunction field effect transistors (HFET) on sapphire substrates have demonstrated ability as power devices operating with high current densities and high breakdown voltages. Additionally, AlGaN/GaN HFET devices have a very low on-state resistance. This makes these devices ideal for automotive applications such as switching relays, DC-DC converters, and power inverters. By 2006, switching devices using GaN-based FETs are anticipated to be employed in luxury automobiles and transitioned to the mass market by 2009.In this presentation, data from AlGaN/GaN HFET's grown in an Emcore D180 MOCVD system will be presented. Typical production-scale material results (on 2” sapphire substrates) for these wafers were: μ ∼ 1000 cm2/Vs, Ns = 1.0×1013 cm−2, and Rs ∼ 450 Ω/square with <3% variation across the wafer. These wafers were then processed into devices using Pt/Au gate contacts with 2 μm gate length, 200 μm gate width, and a source to drain spacing of 13 μm. A total of 1000 FETs were combined in parallel for an effective gate width of 20 cm for high current operation (10A). These devices have a lower on-state resistance (<0.01 Ω-cm2) and higher Schottky breakdown voltages (400 V) than the theoretical limit of Si MOSFET devices. These devices demonstrate suitability for insertion in automotive electrical harnesses.
34
Li, Jiangdan, Christopher A. Onken, Christian Wolf, Péter Németh, Mike Bessell, Zhenwei Li, Xiaobin Zhang, et al. "A Roche Lobe-filling hot Subdwarf and White Dwarf Binary: Possible detection of an ejected common envelope?" Monthly Notices of the Royal Astronomical Society, July 7, 2022. http://dx.doi.org/10.1093/mnras/stac1768.
Full textAbstract:
Abstract Binaries consisting of a hot subdwarf star and an accreting white dwarf (WD) are sources of gravitational wave radiation at low frequencies and possible progenitors of type Ia supernovae if the WD mass is large enough. Here, we report the discovery of the third binary known of this kind: it consists of a hot subdwarf O (sdO) star and a WD with an orbital period of 3.495 hours and an orbital shrinkage of 0.1 s in 6 yr. The sdO star overfills its Roche lobe and likely transfers mass to the WD via an accretion disk. From spectroscopy, we obtain an effective temperature of Teff = 54 240 ± 1 840 K and a surface gravity of log g = 4.841 ± 0.108 for the sdO star. From the light curve analysis, we obtain a sdO mass of MsdO = 0.55 M⊙ and a mass ratio of q = MWD/MsdO = 0.738 ± 0.001. Also, we estimate that the disk has a radius of ∼0.41 R⊙ and a thickness of ∼0.18 R⊙. The origin of this binary is probably a common envelope ejection channel, where the progenitor of the sdO star is either an RGB star or, more likely, an early AGB star; the sdO star will subsequently evolve into a WD and merge with its WD companion, likely resulting in an R CrB star. The outstanding feature in the spectrum of this object is strong Ca H&K lines, which are blueshifted by ∼200 km s−1 and likely originate from the recently ejected common envelope, and we estimated that the remnant CE material in the binary system has a density ∼6 × 10−10 g cm−3.